Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment includes: a build-up insulating layer including a plurality of insulating layers stacked in a vertical direction; a wiring part including a plurality of via electrodes respectively arranged in the plurality of insulating layers of the build-up insulating layer; and a through-via electrode penetrating the build-up insulating layer. The through-via electrode includes: a first portion having a horizontal-direction width increasing in a direction from the top surface of the build-up insulating layer toward the bottom surface of the build-up insulating layer; a second portion arranged on the first portion and having a horizontal-direction width decreasing in a direction from the top surface of the build-up insulating layer toward the bottom surface of the build-up insulating layer; and a base portion arranged between the first portion and the second portion. At least one of the plurality of via electrodes of the wiring part is connected to the base portion.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies for arranging a greater number of semiconductor devices on semiconductor package substrates are being proposed and researched. However, because conventional semiconductor packages are based on mounting a single semiconductor device, achieving desired performance is limited.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] As the number of semiconductor devices and / or semiconductor chiplets mounted in a semiconductor package increases, the area of ​​the semiconductor package is increasing.

[0006] Accordingly, as the area of ​​a semiconductor package increases, the semiconductor package suffers from greater warpage. Furthermore, as the number of semiconductor devices and / or semiconductor chiplets increases, heat generation becomes more severe, necessitating further improvements in heat dissipation characteristics.

[0007] Meanwhile, circuit boards used in conventional semiconductor packages typically include a heat-dissipating member that functions as a heat sink. The heat-dissipating member may be a structure inserted into the circuit board, such as a heat-dissipating coin. However, the inclusion of a heat-dissipating member, such as a heat-dissipating coin, on a circuit board imposes design constraints, increases the unit price, and limits improvements in heat-dissipation characteristics.

[0008] In addition, the heat dissipation member described above may be one of the via electrodes provided on the circuit board. For example, conventionally, at least one via electrode among a plurality of via electrodes penetrating at least a portion of a circuit board is configured to perform a heat dissipation function. However, the via electrode having a heat dissipation function has a larger width in the horizontal direction and / or a larger thickness in the vertical direction than a via electrode that transmits a general signal. Accordingly, conventionally, there is a problem that the process of forming the via electrode having a heat dissipation function is complicated, and the product yield is reduced accordingly. For example, conventionally, a process of forming a chemical copper plating layer in a via hole and a process of forming an electrolytic plating layer using the chemical copper plating layer are performed. At this time, the chemical copper plating layer is disposed on the sidewall of the via hole and the bottom surface of the via hole (preferably, the upper surface of the pad exposed through the via hole). Accordingly, when electrolytic plating is performed to form an electrolytic plating layer, electrolytic plating is performed on the sidewalls and bottom surface of the via hole, and the height of the upper surface of the via electrode may not be uniform due to the resulting isotropic plating. For example, a conventional via electrode may be provided with a convex portion such as a burr, and a planarization process is required to uniformize the height of the upper surface of the via electrode due to this.

[0009] Accordingly, a new method is required to further improve the heat dissipation characteristics of circuit boards, simplify the circuit board manufacturing process, and improve product yield.

[0010] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0011] Additionally, the embodiment provides a circuit board with improved heat dissipation characteristics and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board with improved bending characteristics and a semiconductor package including the same.

[0013] Additionally, the embodiment provides a circuit board including a via electrode having a uniform height of the upper surface and a semiconductor package including the same.

[0014] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0015] A circuit board according to an embodiment comprises a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction; a wiring portion including a plurality of via electrodes respectively disposed within the plurality of insulating layers of the build-up insulating layer; and a through-via electrode penetrating the build-up insulating layer, wherein the through-via electrode includes a first portion having a horizontal width widening along a direction from an upper surface of the build-up insulating layer toward a lower surface of the build-up insulating layer, a second portion disposed on the first portion and having a horizontal width narrowing along a direction from an upper surface of the build-up insulating layer toward a lower surface of the build-up insulating layer, and a base portion disposed between the first portion and the second portion, wherein at least one of the plurality of via electrodes of the wiring portion is connected to the base portion.

[0016] In addition, the build-up insulating layer includes an upper build-up insulating layer including a plurality of upper insulating layers arranged on an upper surface of the base portion and stacked along the vertical direction, and a lower build-up insulating layer including a plurality of lower insulating layers arranged on a lower surface of the base portion and stacked along the vertical direction.

[0017] Additionally, the first portion of the through-via electrode integrally penetrates the plurality of lower insulating layers of the lower build-up insulating layer along the vertical direction, and the second portion of the through-via electrode integrally penetrates the plurality of upper insulating layers of the upper build-up insulating layer along the vertical direction.

[0018] In addition, the wiring portion further includes a plurality of intermediate pad portions arranged between the plurality of via electrodes, and the wiring portion includes a first wiring portion including the via electrodes connected to the base portion and the plurality of via electrodes and the plurality of intermediate pad portions electrically connected to the first portion and the second portion of the through-via electrode through the base portion.

[0019] Additionally, the wiring portion further includes a second wiring portion that is further away from the through-via electrode than the first wiring portion, the first wiring portion being disposed between the second wiring portion and the through-via electrode in a horizontal direction, and the second wiring portion being electrically spaced apart from the first wiring portion and the through-via electrode.

[0020] Additionally, the crystal grains of the first or second portion of the through via electrode and the crystal grains of the base portion are different from each other.

[0021] Additionally, the size of the crystal grains of at least one region of the base portion is smaller than the size of the crystal grains of the first portion or the second portion of the through via electrode.

[0022] In addition, the first portion or the second portion of the through via electrode includes a first region in contact with the inner wall of the through hole of the build-up insulating layer, and a second region located on the inner side of the through hole further from the inner wall than the first region, and the size of the crystal grains in the first region is the same as the size of the crystal grains in the second region.

[0023] Additionally, the boundary between the first portion of the through-via electrode and the build-up insulating layer is located between the lower surface of the lower build-up insulating layer and the lower surface of the base portion, and the boundary between the second portion of the through-via electrode and the upper build-up insulating layer is located between the upper surface of the upper build-up insulating layer and the upper surface of the base portion.

[0024] In addition, the first wiring portion includes a lower wiring portion arranged on a lower surface of the base portion and arranged along a circumferential direction of the first portion of the through-via electrode, and an upper wiring portion arranged on a lower surface of the base portion and arranged along a circumferential direction of the second portion of the through-via electrode.

[0025] In addition, the plurality of via electrodes of the lower wiring portion include a plurality of lower via electrodes arranged in each of the plurality of lower insulating layers and spaced apart from each other along the circumferential direction of the first portion of the through-via electrode, and the plurality of via electrodes of the upper wiring portion include a plurality of upper via electrodes arranged in each of the plurality of upper insulating layers and spaced apart from each other along the circumferential direction of the second portion of the through-via electrode.

[0026] Additionally, the width in the horizontal direction of at least one of the plurality of via electrodes of the upper wiring portion and the plurality of via electrodes of the lower wiring portion is greater than the width in the horizontal direction of at least one of the plurality of via electrodes of the second wiring portion.

[0027] Additionally, at least one of the plurality of via electrodes of the lower wiring portion and the plurality of via electrodes of the upper wiring portion has a closed loop shape surrounding the first portion or the second portion of the through via electrode.

[0028] In addition, the lower wiring portion includes a lower pad portion arranged on a lower surface of the lower build-up insulating layer, the upper wiring portion includes an upper pad portion arranged on an upper surface of the upper build-up insulating layer, and the through-via electrode includes a lower through-electrode pad portion arranged on a lower surface of the first portion and an upper through-electrode pad portion arranged on an upper surface of the second portion, and the lower pad portion and the lower through-electrode pad portion, or the upper pad portion and the upper through-electrode pad portion, are formed integrally.

[0029] Additionally, a plurality of intermediate pad portions of each of the upper wiring portion and the lower wiring portion are spaced apart from the first portion and the second portion of the through-via electrode in the horizontal direction.

[0030] Additionally, the first portion and the second portion of the through via electrode have a symmetrical shape with respect to the base portion.

[0031] In addition, at least one of the first portion and the second portion of the through-via electrode includes a first-first portion and a first-second portion spaced apart along a horizontal direction, and the first wiring portion includes a first-first wiring portion arranged along a circumferential direction of the first-first portion, and a first-second wiring portion arranged along a circumferential direction of the first-second portion.

[0032] Additionally, the horizontal central axis of the first portion of the through via electrode and the horizontal central axis of the second portion are misaligned.

[0033] In addition, the lower wiring portion is disposed on one side of the first portion of the through-via electrode, the upper wiring portion is disposed on the other side of the second portion of the through-via electrode, and the upper wiring portion and the lower wiring portion do not overlap each other along the vertical direction.

[0034] The circuit board of the embodiment includes a plurality of insulating layers stacked along a vertical direction, wiring portions arranged in the plurality of insulating layers, and through-via electrodes integrally penetrating the plurality of insulating layers. At this time, the wiring portions include a plurality of via electrodes respectively arranged in the plurality of insulating layers, and a plurality of pad portions connected to the plurality of via electrodes. At this time, the embodiment can electroplating the through-via electrodes using a portion of the wiring portion including the via electrodes and the pad portions. For example, the wiring portion can include a first wiring portion arranged adjacent to the through-via electrode, and the plurality of pad portions of the first wiring portion can include a base portion connected to the through-via electrode, and a second pad portion spaced apart from the through-via electrode. Here, the plurality of pad portions of the first wiring portion including the base portion connected to the through-via electrode means that the pad portion and the via electrode of the first wiring portion can be utilized as seed layers for electroplating the through-via electrode.

[0035] That is, the current for electroplating the through-via electrode can be uniformly provided in the vertical direction through the base portion. Therefore, in the embodiment, plating can be performed with a uniform height in the vertical direction based on the upper surface of the base portion, and the flatness of the through-via electrode can be improved accordingly. Therefore, in the embodiment, the process for manufacturing the through-via electrode can be simplified. For example, in the embodiment, the through hole corresponding to the through-via electrode can be completely filled while the upper surface is flat through a single plating process. Therefore, in the embodiment, a polishing process, etc. can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, in the embodiment, the polishing process, etc. can be omitted, so that the electrodes provided on the circuit board can be prevented from being damaged by the polishing process. Therefore, in the embodiment, the product yield can be further improved.

[0036] In addition, the grain size of the through-via electrode may be different from the grain size of the wiring portion. For example, the grain size of the through-via electrode may be different from the grain size of at least a region of the base portion. That is, the base portion may include a chemical copper plating layer and an electrolytic plating layer. In contrast, the through-via electrode may be provided with only an electrolytic plating layer. Through this, the embodiment can ensure that uniform plating growth of the upper through-via electrode is achieved in the vertical direction with respect to the base portion because the through-via electrode includes only an electrolytic plating layer, and can further improve the flatness of the surface of the through-via electrode. In addition, the embodiment can ensure that the through-via electrode includes only an electrolytic plating layer with dense grains, thereby having high thermal conductivity characteristics and more efficiently dissipating heat generated through the semiconductor device.

[0037] Accordingly, the through-via electrode can have a uniform grain size throughout the entire area. For example, the through-via electrode can include a first area in contact with the inner wall of a through-hole that integrally penetrates a plurality of insulating layers, and a second area on the inner side of the through-via electrode that is further away from the inner wall of the through-hole than the first area. In addition, the grain sizes in each of the first area and the second area of ​​the through-via electrode can be the same. That is, in the comparative example, the through-via electrode can be formed by performing electroplating, but for this purpose, a chemical copper plating layer must be necessarily disposed on the inner wall of the through-hole, and accordingly, the grain sizes in the first area and the second area of ​​the through-via electrode in the comparative example are different. In contrast, the embodiment can have a uniform grain size in the first area and the second area of ​​the through-via electrode, thereby improving the flatness of the through-via electrode while providing high heat dissipation characteristics.

[0038] In addition, the inclination angle of the through-via electrode may be different from the inclination angle of the via electrode of the wiring portion. For example, the inclination angle of the through-via electrode with respect to the upper surface of the build-up insulating layer may be closer to 90 degrees than the inclination of the via electrode of the wiring portion with respect to the upper surface of the build-up insulating layer. Through this, the volume of the through-via electrode in the build-up insulating layer can be increased. Accordingly, the effect according to the function of the through-via electrode can be maximized. For example, when the through-via electrode is used as a heat dissipation electrode with a heat dissipation function, the heat dissipation characteristics can be further improved by maximizing the volume of the through-via electrode. Through this, the semiconductor device can be operated more stably, and the product reliability can be further improved accordingly.

[0039] Additionally, at least two of the plurality of side portions of the through-via electrode may be provided with a single sub-via electrode that is interconnected. Through this, the embodiment can ensure that the current for plating the upper through-via electrode is uniformly applied, thereby further securing the flatness of the upper through-via electrode. Furthermore, the embodiment can further improve the heat dissipation function by increasing the area of ​​the first wiring portion, thereby enabling the circuit board and semiconductor package to operate more stably.

[0040] In addition, the upper through-via electrode and the lower through-via electrode may have an asymmetrical shape with respect to the base portion. For example, the horizontal width and / or the vertical thickness of the upper through-via electrode may be different from the horizontal width and / or the vertical thickness of the lower through-via electrode. For example, the horizontal width of the upper through-via electrode may be different from the horizontal width of the lower through-via electrode. For example, the horizontal width of the upper through-via electrode may be smaller than the horizontal width of the lower through-via electrode. Through this, the embodiment can allow heat to be transferred from the upper through-via electrode having a relatively smaller horizontal width to the lower through-via electrode having a relatively larger horizontal width. That is, the embodiment can control the direction of heat transfer by making the widths of the upper through-via electrode and the lower through-via electrode different, thereby providing a more efficient heat dissipation function.

[0041] In addition, the upper through-via electrodes may be provided in multiple numbers and spaced apart from each other in the horizontal direction. For example, the upper through-via electrodes may include a first upper through-via electrode that integrally penetrates multiple insulating layers of the upper insulating layer, and a second upper through-via electrode that integrally penetrates multiple insulating layers of the upper insulating layer and is spaced apart from the first upper through-via electrode in the horizontal direction. Through this, the first upper through-via electrode and the second upper through-via electrode may transfer heat through mutually branched paths. Through this, the embodiment may enable heat dissipation to be performed through multiple paths rather than a single path, thereby further improving heat dissipation characteristics. In addition, a plurality of semiconductor devices may be arranged on the circuit board, and the first upper through-via electrode may be provided in an area where the first semiconductor device is arranged. In addition, the second upper through-via electrode may be provided in an area where the second semiconductor device is arranged. That is, the embodiment may provide an upper through-via electrode corresponding to each of the multiple semiconductor devices arranged on the circuit board. Through this, the embodiment can further maximize the heat dissipation characteristics in a semiconductor package equipped with a plurality of semiconductor elements.

[0042] Additionally, the first wiring portion may include an upper wiring portion provided only on one side of the upper through-via. Additionally, the first wiring portion may include a lower wiring portion provided only on the other side of the lower through-via. Accordingly, the embodiment may further increase the volume of the upper through-via electrode and / or the lower through-via electrode within the same area as the area of ​​the circuit board. Through this, the embodiment may further improve heat dissipation characteristics.

[0043] Figure 1 is a cross-sectional view illustrating a circuit board according to the first embodiment.

[0044] FIG. 2a is a drawing for explaining a problem in a method for manufacturing a through-via electrode of a circuit board according to a comparative example.

[0045] FIGS. 2b and 2c are drawings for explaining a through-via electrode according to an embodiment compared to FIG. 2a.

[0046] Figure 3 is an enlarged view of the upper part of the base in Figure 1.

[0047] Figure 4 is a plan view of the area where the third base part is placed.

[0048] Figure 5 is a cross-sectional view along the AA' direction of Figure 3.

[0049] Fig. 6 is a drawing showing the shape of a via electrode of a first wiring section according to the first embodiment.

[0050] Fig. 7 is a drawing showing the shape of a via electrode of a first wiring section according to the second embodiment.

[0051] Fig. 8 is a drawing showing the shape of a via electrode of a first wiring section according to a third embodiment.

[0052] Figure 9 is a cross-sectional view showing a circuit board according to the second embodiment.

[0053] Fig. 10 is a cross-sectional view showing a circuit board according to the third embodiment.

[0054] Fig. 11 is a cross-sectional view showing a circuit board according to the fourth embodiment.

[0055] Fig. 12 is a cross-sectional view showing a circuit board according to the fifth embodiment.

[0056] Fig. 13 is a cross-sectional view showing a circuit board according to the sixth embodiment.

[0057] Fig. 14 is a drawing showing a semiconductor package according to the first embodiment.

[0058] Fig. 15 is a drawing showing a semiconductor package according to the second embodiment.

[0059] Figures 16 to 20 are cross-sectional views showing a method for manufacturing a circuit board according to one embodiment in process order.

[0060] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0061] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0062] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0063] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0064] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0065] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0066] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0067] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0068]

[0069] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing symbols, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0070]

[0071] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0072] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be electrically connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor element, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0073] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0074] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0075]

[0076] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment, FIG. 2a is a drawing for explaining a problem in a method for manufacturing a through-via electrode of a circuit board according to a comparative example, FIGS. 2b and 2c are drawings for explaining a through-via electrode according to an embodiment compared to FIG. 2a, FIG. 3 is an enlarged view of an upper portion of a base portion in FIG. 1, FIG. 4 is a plan view in an area where a third base portion is arranged, FIG. 5 is a cross-sectional view along the AA' direction of FIG. 3, FIG. 6 is a drawing showing a shape of a via electrode of a first wiring portion according to the first embodiment, FIG. 7 is a drawing showing a shape of a via electrode of a first wiring portion according to the second embodiment, FIG. 8 is a drawing showing a shape of a via electrode of a first wiring portion according to the third embodiment, FIG. 9 is a cross-sectional view showing a circuit board according to the second embodiment, FIG. 10 is a cross-sectional view showing a circuit board according to the third embodiment, and FIG. 11 is a cross-sectional view showing a circuit board according to the fourth embodiment, FIG. 12 is a cross-sectional view showing a circuit board according to the fifth embodiment, FIG. 13 is a cross-sectional view showing a circuit board according to the sixth embodiment, FIG. 14 is a drawing showing a semiconductor package according to the first embodiment, and FIG. 15 is a drawing showing a semiconductor package according to the second embodiment.

[0077] Hereinafter, a circuit board and a semiconductor package including the same according to an embodiment will be specifically described with reference to FIGS. 1 to 15.

[0078] Referring to FIG. 1, the circuit board (100) includes a build-up insulating layer (110), a first protective layer (120), a second protective layer (130), a wiring portion (140), and a through via electrode (170). The build-up insulating layer (110) includes a plurality of insulating layers stacked along a vertical direction. The first protective layer (120) may be disposed on one surface of the build-up insulating layer (110). The second protective layer (130) may be disposed on the other surface of the build-up insulating layer (110). Here, the meaning of being disposed on one surface and the other surface should not be understood only as a configuration in direct contact with the one surface and the other surface, but should be understood to mean that there are other configurations between one surface of the build-up insulating layer (110) and the first protective layer (120), and between the other surface of the build-up insulating layer (110) and the second protective layer (130). The wiring portion (140) may include a plurality of via electrodes (160) arranged within a plurality of insulating layers of the build-up insulating layer (110) and a plurality of pad portions (150) arranged between the plurality of via electrodes (160). The through-via electrode (170) may be provided so as to integrally penetrate at least two insulating layers among the plurality of insulating layers of the build-up insulating layer (110). At this time, the via electrode (160) and the through-via electrode (170) may be similar in that they are provided so as to penetrate at least a portion of the build-up insulating layer (110) along the vertical direction. However, the via electrode (160) and the through-via electrode (170) may be distinguished based on at least one of a width in the horizontal direction, a thickness in the vertical direction, a planar area, and a volume. For example, the width in the horizontal direction of the via electrode (160) may be smaller than the width in the horizontal direction of the through-via electrode (170). Alternatively, the vertical thickness of the via electrode (160) may be smaller than the vertical thickness of the through via electrode (170). Alternatively, the planar area of ​​the via electrode (160) may be smaller than the planar area of ​​the through via electrode (170). Alternatively, the volume of the via electrode (160) may be smaller than the volume of the through via electrode (170).For example, the through-via electrode (170) may be larger than the via electrode (160) in at least one of a width in the horizontal direction, a thickness in the vertical direction, a planar area, and a volume. For example, the through-via electrode (170) may mean a via electrode having a relatively large area.

[0079] Specifically, the build-up insulation layer (110) may have a structure in which multiple insulation layers are laminated along the vertical direction.

[0080] The build-up insulating layer (110) may include an upper build-up insulating layer (111) including a plurality of insulating layers (113, 114, 115) stacked along a vertical direction, and a lower build-up insulating layer (112) including a plurality of insulating layers (116, 117, 118) stacked along a vertical direction and positioned below the upper build-up insulating layer (111). The upper build-up insulating layer (111) and the lower build-up insulating layer (112) may be distinguished based on the position of a pad that serves as a reference for forming a through-via electrode (170).

[0081] For example, the upper build-up insulating layer (111) and the lower build-up insulating layer (112) can be distinguished based on the through-via electrode (170). The through-via electrode (170) can include a first portion (171), a second portion (172), and a base portion (173) between the first portion (171) and the second portion (172). The base portion (173) can mean a base pad that serves as a reference for forming the through-via electrode (170). In addition, the first portion (171) of the through-via electrode (170) can be a through-via electrode positioned below the base portion (173), and the second portion (172) of the through-via electrode (170) can be a through-via electrode positioned above the base portion (173).

[0082] Accordingly, the upper build-up insulating layer (111) may refer to insulating layers located above the base portion (173) that serves as a reference, and the lower build-up insulating layer (112) may refer to insulating layers located below the base portion (173). The upper build-up insulating layer (111) may refer to insulating layers that are integrally penetrated through the second portion (172) of the through-via electrode (170), and the lower build-up insulating layer (112) may refer to insulating layers that are integrally penetrated through the first portion (171) of the through-via electrode (170).

[0083] The build-up insulating layer (110) as described above may not include a core layer. For example, the circuit board (100) including the build-up insulating layer (110) may be a coreless board. However, the embodiment is not limited thereto, and the circuit board (100) may be a core board including a core layer. In this case, the build-up insulating layer (110) may be disposed on each of the upper and lower surfaces of the core layer. Specifically, when the circuit board (100) is a core board including a core layer, the upper build-up insulating layer (111) of the build-up insulating layer (110) may be disposed on the upper surface of the core layer, and the lower build-up insulating layer (112) of the build-up insulating layer (110) may be disposed on the lower surface of the core layer.

[0084] The upper build-up insulating layer (111) may include a first insulating layer (113) that is closest to the first protective layer (120) along the vertical direction, a second insulating layer (114) that is further away from the first protective layer (120) along the vertical direction than the first insulating layer (113), and a third insulating layer (115) that is further away from the first protective layer (120) along the vertical direction than the second insulating layer (114).

[0085] The lower build-up insulating layer (112) may include a fourth insulating layer (116) that is closest to the first protective layer (120) and / or the upper build-up insulating layer (111) along the vertical direction, a fifth insulating layer (117) that is further away from the first protective layer (120) and / or the upper build-up insulating layer (111) along the vertical direction than the fourth insulating layer (116), and a sixth insulating layer (118) that is further away from the first protective layer (120) and / or the upper build-up insulating layer (111) along the vertical direction than the fifth insulating layer (117).

[0086] At this time, the upper build-up insulation layer (111) and the lower build-up insulation layer (112) are described as each including three insulation layers, but are not limited thereto. For example, the upper build-up insulation layer (111) and / or the lower build-up insulation layer (112) may have a structure in which two or fewer insulation layers are laminated. As another example, the upper build-up insulation layer (111) and / or the lower build-up insulation layer (112) may have a structure in which four or more insulation layers are laminated.

[0087] In addition, although it has been described that the upper build-up insulation layer (111) and the lower build-up insulation layer (112) have the same number of layers, it is not limited thereto. For example, the upper build-up insulation layer (111) and the lower build-up insulation layer (112) may have an asymmetrical structure. For example, the number of layers of at least one insulation layer among the upper build-up insulation layer (111) and the lower build-up insulation layer (112) may be greater than or less than the number of layers of the other insulation layer among the upper build-up insulation layer (111) and the lower build-up insulation layer (112).

[0088] The first to sixth insulating layers (113, 114, 115, 116, 117, 118) of the upper build-up insulating layer (111) and the lower build-up insulating layer (112) are arranged to vertically insulate between the pad portions (150) of the wiring portion (140) to be described later. For example, the first to sixth insulating layers (113, 114, 115, 116, 117, 118) may be formed of a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0089] At least one of the first to sixth insulating layers (113, 114, 115, 116, 117, 118) may include an insulating material different from at least one other. For example, at least one of the first to sixth insulating layers (113, 114, 115, 116, 117, 118) may include a reinforcing member (not shown). In one embodiment, the reinforcing member may mean glass fiber. In another embodiment, the reinforcing member may mean GCP (Glass Core Primer). The reinforcing member may be provided in at least one of the first to sixth insulating layers (113, 114, 115, 116, 117, 118) to improve the rigidity of the circuit board (100). The reinforcing member can prevent the circuit board (100) from being significantly bent in a specific direction, thereby improving the vertical positional alignment between the pad portion (150) and the via electrode (160), thereby improving the electrical reliability and / or mechanical reliability of the circuit board (100) and the semiconductor package. In addition, the reinforcing member can improve the rigidity of the circuit board (100), thereby improving the processability in the process of mounting a semiconductor device on the circuit board (100), and improving the product yield. Therefore, the reinforcing member can enable the semiconductor device to be stably mounted on the circuit board (100) and can enable the semiconductor device to operate stably. Through this, the operating reliability can be improved by enabling the stable operation of electronic products such as servers to which the semiconductor package is applied. For example, the reinforcing members can be alternately arranged in the vertical direction within the first to sixth insulating layers (113, 114, 115, 116, 117, 118). For example, the reinforcing member may be provided in an odd-numbered insulation layer among the first to sixth insulation layers (113, 114, 115, 116, 117, 118), or may be provided in an even-numbered insulation layer.

[0090] The wiring portion (140) may include a pad portion (150) and a via electrode (160). The pad portion (150) may be disposed on the upper surface and / or lower surface of the first to sixth insulating layers (113, 114, 115, 116, 117, 118), respectively. The via electrode (160) may be disposed between a plurality of pad portions (150) and may electrically connect between a plurality of pad portions disposed in different layers. The pad portion (150) may be divided into an upper pad portion provided in the upper build-up insulating layer (111) and a lower pad portion provided in the lower build-up insulating layer (112).

[0091] The upper pad portion of the pad portion (150) may include a first upper pad portion (151) that is closest to the first protective layer (120) in the vertical direction, a second upper pad portion (152) that is further away from the first protective layer (120) than the first upper pad portion (151), a third upper pad portion (153) that is further away from the first protective layer (120) than the second upper pad portion (152), and a fourth upper pad portion (154) that is further away from the first protective layer (120) than the third upper pad portion (153).

[0092] In addition, the lower pad portion of the pad portion (150) may include a first lower pad portion (155) that is further away from the first protective layer (120) than the fourth upper pad portion (154), a second lower pad portion (156) that is further away from the first protective layer (120) than the first lower pad portion (155), and a third lower pad portion (157) that is further away from the first protective layer (120) than the second lower pad portion (156). Here, the pad portion (150) may mean a wiring that overlaps with the via electrode (160) of the wiring portion (140) in a vertical direction or is physically directly connected to the via electrode (160). At this time, although not shown in the drawing, the wiring portion (140) may further include a trace that overlaps with at least one pad portion among the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157) in the horizontal direction. The trace may mean a wiring line that electrically connects between a plurality of pads that overlap in the horizontal direction. Here, the pad portion and the via electrode may be distinguished based on a width in the horizontal direction, a thickness in the vertical direction, and a slope of the side surface. For example, the width of the pad portion in the horizontal direction may be greater than the width of the via electrode in the horizontal direction. Alternatively, the thickness of the pad portion in the vertical direction may be less than the thickness of the via electrode in the vertical direction. Alternatively, the slope of the side surface of the pad portion may be closer to perpendicular to the upper or lower surface of the build-up insulating layer (110) than the slope of the side surface of the via electrode. Accordingly, the pad portion and the via electrode can be distinguished by using at least one of the width in the horizontal direction, the thickness in the vertical direction, and the slope of the side surface. In addition, the trace may refer to a signal line that electrically connects between a plurality of pad portions. In this case, the trace and the pad portion can be formed based on the width in the horizontal direction. For example, the width of the trace in the horizontal direction may be smaller than the width of the pad portion in the horizontal direction.Additionally, traces and pads can be distinguished by whether they overlap vertically with the via electrode. For example, the pad can overlap the via electrode along the vertical direction and be physically and / or electrically directly connected to the via electrode, and the trace can not overlap the via electrode along the vertical direction. The trace can electrically connect a plurality of pads along the horizontal direction.

[0093] In addition, the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157) can function to electrically connect with semiconductor elements placed on the circuit board (100). Each of the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157) can be freely designed in consideration of impedance.

[0094] Among the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157), the fourth upper pad portion (154) is positioned between the upper build-up insulating layer (111) and the lower build-up insulating layer (112). At this time, the base portion (173) of the through via electrode (170) described later may be a part of the fourth upper pad portion (154).

[0095] That is, the fourth upper pad portions (154) may be arranged in multiple numbers while being spaced apart from each other in the horizontal direction. In addition, among the fourth upper pad portions (154), the pad portions that are physically and / or electrically connected to the first portion (172) and the second portion (171) of the through-via electrode (170) may be referred to as a base portion (173) that electrically connects a portion of the wiring portion (140) described above with the through-via electrode (170). The base portion (173) may electrically connect the other upper pad portions / via electrodes of the wiring portion (140) and the second portion (171) of the through-via electrode in order to simplify the manufacturing process and further improve the product yield while improving the physical reliability and / or electrical reliability of the first portion (172) and the second portion (171) of the through-via electrode (170) described later. Furthermore, the base portion (173) can electrically connect the other lower pad portion / via electrode of the wiring portion (140) and the first portion (172) of the through-via electrode. For example, the wiring portion (140) can include a plurality of pad portions (150) and a plurality of via electrodes (160) as described above. And, at least some of the plurality of pad portions (150) and the plurality of via electrodes (160) can be used as signal wiring for signal transmission. In addition, the remaining portions of the plurality of pad portions (150) and the plurality of via electrodes (160) can be electrically connected to the first portion (172) and the second portion (171) of the through-via electrode (170), thereby performing the same function as the function performed by the first portion (172) and the second portion (171). For example, when the first part (172) and the second part (171) of the through-via electrode (170) perform a heat dissipation function, at least some of the plurality of pad parts (150) and the plurality of via electrodes (160) of the wiring part (140) can be physically and electrically connected to the first part (172) and / or the second part (171) of the through-via electrode to perform the heat dissipation function.Furthermore, the pad portion (150) and the via electrode (160) of the wiring portion (140) electrically connected to the first portion (172) and the second portion (171) of the through-via electrode can be used as a seed layer for easy electroplating of the first portion (172) and / or the second portion (171) of the through-via electrode. The detailed structure thereof will be described later.

[0096] The via electrode (160) may be arranged to electrically connect the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157) to each other. The via electrode (160) may include the first to sixth via electrodes (161, 162, 163, 164, 165, 166).

[0097] The first via electrode (161) may be disposed between the first upper pad portion (151) and the second upper pad portion (152). The second via electrode (162) may be disposed between the second upper pad portion (152) and the third upper pad portion (152). The third via electrode (163) may be disposed between the third upper pad portion (153) and the fourth upper pad portion (154). The fourth via electrode (164) may be disposed between the fourth upper pad portion (154) and the first lower pad portion (155). The fifth via electrode (165) may be disposed between the first lower pad portion (155) and the second lower pad portion (156). The sixth via electrode (166) may be disposed between the second lower pad portion (156) and the third lower pad portion (157).

[0098] The first to sixth via electrodes (161, 162, 163, 164, 165, 166) can be formed simultaneously in the process of arranging the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157). For example, in the process of arranging the first upper pad portion (151), a through hole can be formed in the first insulating layer (113) to expose a portion of the second upper pad portion (152), thereby forming the first upper pad portion (151) together with the first via electrode (161) filling the through hole of the first insulating layer (113). Therefore, the first via electrode (161) can be distinguished as a protrusion of the first upper pad portion (151).

[0099] Since the first to fourth upper pad portions (151, 152, 153, 154) are sequentially stacked along the vertical direction on the lower build-up insulating layer (112), the inclination directions of each of the first to third via electrodes (161, 162, 163) may be the same. For example, each of the first to third via electrodes (161, 162, 163) may have an inclination that becomes wider as it approaches the second protective layer (130).

[0100] Since the first to third lower pad portions (155, 156, 157) are sequentially stacked in a vertical direction under the upper build-up insulating layer (111), the inclination directions of the fourth to sixth via electrodes (164, 165, 166) may be the same. For example, the fourth to sixth via electrodes (164, 165, 166) may each have an inclination that becomes wider as they move toward the first protective layer (120).

[0101] The inclination directions of the first to third via electrodes (161, 162, 163) may be different from the inclination directions of the fourth to sixth via electrodes (164, 165, 166). For example, the inclination directions of the fourth to sixth via electrodes (164, 165, 166) may be opposite to the inclination directions of the first to third via electrodes (161, 162, 163). For example, the first to third via electrodes (161, 162, 163) may have shapes that are symmetrical to each other with respect to the fourth to sixth via electrodes (164, 165, 166).

[0102] The through-via electrode (170) is provided to penetrate the upper build-up insulating layer (111) and the lower build-up insulating layer (112). The through-via electrode (170) includes a base portion (173) and may include a first portion (172) disposed under the base portion (173) and a second portion (171) disposed on the base portion (173). Accordingly, for convenience of explanation, the first portion (172) of the through-via electrode (170) is referred to as a lower through-via electrode (172) of the through-via electrode (170) disposed on the lower surface of the base portion (173), and the second portion (171) of the through-via electrode (170) is referred to as an upper through-via electrode (171) of the through-via electrode (170) disposed on the upper surface of the base portion (173).

[0103] That is, the through-via electrode (170) may include an upper through-via electrode (171) penetrating the upper build-up insulating layer (111) along the vertical direction, a lower through-via electrode (172) penetrating the lower build-up insulating layer (112) along the vertical direction, and a base portion (173) disposed between the upper through-via electrode (171) and the lower through-via electrode (172).

[0104] The upper through-via electrode (171) may be provided to integrally penetrate the upper build-up insulating layer (111). For example, the upper through-via electrode (171) may integrally penetrate the first to third insulating layers (113, 114, 115) of the upper build-up insulating layer (111).

[0105] For example, the upper through-via electrode (171) may have a width that is narrowed horizontally from the upper surface of the build-up insulating layer (110) toward the lower surface of the build-up insulating layer (110).

[0106] The inclination direction of the upper through-via electrode (171) may be the same as the inclination direction of the first to third via electrodes (161, 162, 163). That is, the width of each of the upper through-via electrode (171) and the first to third via electrodes (161, 162, 163) in the horizontal direction may be narrowed along the direction from the upper surface of the build-up insulating layer (110) toward the lower surface of the build-up insulating layer (110).

[0107] At this time, the inclination angle of the upper through-via electrode (171) may be different from the inclination angles of the first to third via electrodes (161, 162, 163). For example, the upper through-via electrode (171) may be provided so as to integrally penetrate the first to third insulating layers (113, 114, 115) while having a relatively large horizontal width, and the first to third via electrodes (161, 162, 163) may be provided so as to penetrate the first to third insulating layers (113, 114, 115) respectively while having a relatively small horizontal width. Therefore, the inclination angle of the upper through-via electrode (171) may be closer to vertical than the inclination angles of each of the first to third via electrodes (161, 162, 163). For example, the inclination angle of the side surface of the upper through-via electrode (171) with respect to the upper surface of the upper build-up insulating layer (111) may be closer to vertical than the inclination angle of the side surface of each of the first to third via electrodes (161, 162, 163) with respect to the upper surface of the upper build-up insulating layer (111). Through this, the volume of the upper through-via electrode (171) in the upper build-up insulating layer (111) can be increased. Accordingly, the effect according to the function of the upper through-via electrode (171) can be maximized. For example, when the upper through-via electrode (171) is used as a heat dissipation electrode having a heat dissipation function, the heat dissipation characteristics can be further improved by maximizing the volume of the upper through-via electrode (171). Through this, the semiconductor device can be operated more stably, and thus the product reliability can be further improved.

[0108] The lower through-hole via electrode (172) may be provided to integrally penetrate the lower build-up insulating layer (112). For example, the lower through-hole via electrode (172) may integrally penetrate the fourth to sixth insulating layers (116, 117, 118) of the lower build-up insulating layer (112).

[0109] For example, the lower through-via electrode (172) may have a width that increases horizontally from the upper surface of the build-up insulating layer (110) toward the lower surface of the build-up insulating layer (110).

[0110] The inclination direction of the lower through-hole via electrode (172) may be the same as the inclination direction of the fourth to sixth via electrodes (164, 165, 166). That is, the width of each of the lower through-hole via electrode (172) and the fourth to sixth via electrodes (164, 165, 166) in the horizontal direction may increase along the direction from the upper surface of the build-up insulating layer (110) toward the lower surface of the build-up insulating layer (110).

[0111] The inclination angle of the lower through-via electrode (172) may be different from the inclination angles of the fourth to sixth via electrodes (164, 165, 166). For example, the lower through-via electrode (172) may be provided so as to integrally penetrate the fourth to sixth insulating layers (116, 117, 118) while having a relatively large horizontal width, and the fourth to sixth via electrodes (164, 165, 166) may be provided so as to penetrate the fourth to sixth insulating layers (116, 117, 118) respectively while having a relatively small horizontal width. Therefore, the inclination angle of the lower through-via electrode (172) may be closer to vertical than the inclination angles of each of the fourth to sixth via electrodes (164, 165, 166). For example, the inclination angle of the side surface of the lower through-via electrode (172) with respect to the lower surface of the lower build-up insulating layer (112) may be closer to vertical than the inclination angle of the side surface of each of the fourth to sixth via electrodes (164, 165, 166) with respect to the lower surface of the lower build-up insulating layer (112). Through this, the volume of the lower through-via electrode (172) in the lower build-up insulating layer (112) can be increased. Accordingly, the effect according to the function of the lower through-via electrode (172) can be maximized. For example, when the lower through-via electrode (172) is used as a heat dissipation electrode having a heat dissipation function, the heat dissipation characteristics can be further improved by maximizing the volume of the lower through-via electrode (172). Through this, the semiconductor device can be operated more stably, and thus the product reliability can be further improved.

[0112] The first protective layer (120) may be disposed on the upper surface of the upper build-up insulating layer (111), and the second protective layer (130) may be disposed on the lower surface of the lower build-up insulating layer (112). The first protective layer (120) and the second protective layer (130) may protect the upper surface of the first upper pad portion (151) and / or the upper build-up insulating layer (111) from external moisture or contaminants. In addition, when a semiconductor element is disposed on the circuit board (100) using a material such as solder, the first protective layer (120) functions to prevent short circuits between solders due to low wettability with the solder. The first protective layer (120) may use a photocurable insulating material, and for example, a solder resist may be used. However, the embodiment is not limited thereto, and the first protective layer (120) may include a thermocurable insulating material that is the same insulating material as the build-up insulating layer (110). The first protective layer (120) may have the same insulating material as the build-up insulating layer (110), and may be provided as, for example, ABF (Ajinomoto Build-up Film) from Ajinomoto Corporation.

[0113] The circuit board (100) requires a heat dissipation function for stable operation of semiconductor elements. Here, the heat dissipation function may mean easily dissipating heat generated from semiconductor elements placed on the circuit board (100) to the outside of the circuit board.

[0114] For example, the embodiment can discharge heat generated from a semiconductor element placed on a circuit board toward the lower side of the circuit board by using an upper through-via electrode (171) and a lower through-via electrode (172) provided in an upper build-up insulating layer (111) and a lower build-up insulating layer (112).

[0115] At this time, the wiring section (140) of the present invention may have a structure that can simplify the manufacturing process of the upper through-via electrode (171) and / or the lower through-via electrode (172), while improving the electrical characteristics of the upper through-via electrode (171) and / or the lower through-via electrode (172), and further improving the product yield. To this end, the wiring section (140) may include a wiring section that is electrically connected to the upper through-via electrode (171) and / or the lower through-via electrode (172) and that functions as a heat dissipation section together with the upper through-via electrode (171) and / or the lower through-via electrode (172). That is, the wiring section (140) may include a wiring section that is electrically connected to the upper through-via electrode (171) and / or the lower through-via electrode (172) and that applies current for electrolytic plating the upper through-via electrode (171) and / or the lower through-via electrode (172).

[0116] Before describing the embodiment, a through via electrode formed through electrolytic plating according to a comparative example is described.

[0117] Referring to Fig. 2a, a circuit board according to a comparative example includes a build-up insulating layer (10). The build-up insulating layer (10) includes a through hole (TH). The build-up insulating layer (10) includes a plurality of insulating layers stacked along a vertical direction, and the through hole (TH) is provided to integrally penetrate the plurality of insulating layers.

[0118] At this time, a comparative example is a process in which a mask (20) having a through hole (TH) and an opening vertically overlapping each other is formed on a build-up insulating layer (10), and then a process of plating a first metal layer (30) and a second metal layer (40) is performed. At this time, the first metal layer (30) is a seed layer for forming the second metal layer (40), and may be, for example, a chemical copper plating layer. The second metal layer (40) is an electrolytic plating layer formed by electrolytic plating the first metal layer (30) as a seed layer.

[0119] The first metal layer (30) is formed on the inner wall of the through hole (TH) and the bottom surface of the through hole (TH) (preferably, the upper surface of the lower pad exposed through the through hole). Accordingly, when the second metal layer (40) is formed by electroplating, plating is performed on the inner wall of the through hole (TH) and the upper surface of the lower pad. For example, in a comparative example, isotropic plating of the second metal layer (40) is performed as electroplating is performed using the first metal layer (30) as a seed layer. At this time, the second metal layer (40) is formed to fill the through hole (TH) and the opening of the mask (20). At this time, the portion of the second metal layer (40) provided in the opening of the mask (20) may exceed the target thickness before the second metal layer (40) is completely filled within the through hole (TH).

[0120] Therefore, the comparative example must perform multiple plating processes to completely fill the through hole (TH) with the second metal layer (40). For example, the comparative example performs a process of forming a primary second metal layer (40) in the through hole (TH) and the opening of the mask (20). Thereafter, the comparative example performs a process of removing a portion of the second metal layer (30) that protrudes excessively above the opening of the mask (20) by polishing. Thereafter, the comparative example performs a process of forming a secondary second metal layer (40) in the second through hole (TH) and the opening of the mask (20). At this time, the plating process as described above may be performed repeatedly, and the number of plating processes may increase depending on the depth of the through hole (TH) in the vertical direction.

[0121] Accordingly, the comparative example has the problem that the time required to completely fill the via hole (TH) with the second metal layer (40) increases and the manufacturing process becomes complicated.

[0122] In addition, the upper surface of the second metal layer (40) that is finally formed is not flat but has a curve. For example, the upper surface of the second metal layer (40) includes a convex portion (40T1) that is convex toward the upper direction and a concave portion (40T2) that is concave toward the lower direction. Through this, in the conventional technology, a process of finally flattening the upper surface of the second metal layer (40) is performed. Through this, in the conventional technology, there is a problem that the manufacturing process according to the polishing process is complicated, the manufacturing cost increases during the polishing process, and the product yield decreases accordingly.

[0123] In particular, in the comparative example, isotropic plating is performed using the first metal layer (30) formed on the side wall of the via hole (TH) as a seed layer, and accordingly, there is a problem that the difference in flatness between the convex portion (40T1) and the concave portion (40T2) becomes larger. In particular, in the comparative example, there is a problem that the height difference between the convex portion (40T1) and the concave portion (40T2) exceeds 150 um, or exceeds 180 um, or exceeds 200 um. Therefore, in the comparative example, in order to match the flatness between the convex portion (40T1) and the concave portion (40T2), a polishing process of at least 150 um must be performed.

[0124] In contrast, referring to FIGS. 2b and 2c, the embodiment forms the upper through-via electrode (171) and the lower through-via electrode (172) without forming a separate seed layer such as a chemical copper plating layer. At this time, the upper through-via electrode (171) and the lower through-via electrode (172) may be formed by filling a material such as a conductive paste, but in this case, since they have relatively low heat transfer characteristics, the heat dissipation characteristics of the circuit board and the semiconductor package may be deteriorated.

[0125] Accordingly, the embodiment forms an upper through-via electrode (171) and a lower through-via electrode (172) having excellent heat dissipation characteristics by performing electrolytic plating. Furthermore, the embodiment enables electrolytic plating of the upper through-via electrode (171) and the lower through-via electrode (172) without forming a seed layer, such as a separate chemical copper plating layer, for electrolytic plating of the upper through-via electrode (171) and the lower through-via electrode (172). For example, the upper through-via electrode (171) and the lower through-via electrode (172) may include only an electrolytic plating layer, and the electrolytic plating layer of the upper through-via electrode (171) and the lower through-via electrode (172) may allow the build-up insulating layer (110) to directly contact the inner wall of the through hole.

[0126] Preferably, the embodiment utilizes a portion of the pad portion (150) and the via electrode (160) constituting the wiring portion (140) as a seed layer for electrolytic plating of the upper through-via electrode (171) and the lower through-via electrode (172). Through this, the embodiment can form the upper through-via electrode (171) and the lower through-via electrode (172) by electrolytic plating, while allowing the upper through-via electrode (171) and the lower through-via electrode (172) to include only an electrolytic plating layer, and further, can prevent a chemical copper plating layer from being provided between the electrolytic plating layers of the upper through-via electrode (171) and the lower through-via electrode (172) and the inner wall of the through hole of the build-up insulating layer (110).

[0127] However, even if the anisotropic plating method using the first wiring portion (140A) described later is applied without forming a separate seed layer on the inner wall of the through hole as shown in FIG. 2b, which is different from the comparative example, a protruding portion (A) may exist on the upper through-via electrode (171) and / or the lower through-via electrode (172). However, it can be confirmed that the thickness of the protruding portion (A) according to the embodiment is significantly reduced compared to the comparative example of FIG. 2a, and in particular, it can be confirmed that the difference in flatness is 100 um or less, 80 um or less, or 50 um or less, which is a level that can be removed by a general, simple polishing process.

[0128] Furthermore, as illustrated in FIG. 2c, the structure has no separate seed layer disposed between the inner wall of the upper build-up insulating layer (111) and the upper through-via electrode (171), and accordingly, it can be confirmed that the interface (IS) between the inner wall of the upper build-up insulating layer (111) and the upper through-via electrode (171) is clearly distinguishable compared to the comparative example. Furthermore, the embodiment may have a small gap provided at the interface (IS) between the inner wall of the upper build-up insulating layer (111) and the upper through-via electrode (171), through which heat transferred through the upper through-via electrode (171) can be minimized from being transferred to the upper build-up insulating layer (111), and thereby, electrical reliability and / or physical reliability of the circuit board can be further improved.

[0129] Hereinafter, the structure of the wiring portion (140) and the through-via electrode (170) of the embodiment will be described in more detail. For convenience of explanation, the wiring portion (140) and the upper through-via electrode (171) provided in the upper build-up insulating layer (111) based on the build-up insulating layer (110) will be described below. However, corresponding to the wiring portion (140) and the upper through-via electrode (171) described below, the wiring portion (140) and the lower through-via electrode (172) may also be arranged in the lower insulating layer (112).

[0130] Referring to FIGS. 3 to 5, the circuit board of the embodiment includes an upper build-up insulating layer (111). The upper build-up insulating layer (111) includes a plurality of insulating layers (113, 114, 115) stacked along a vertical direction.

[0131] Additionally, a wiring portion (140) including a pad portion (150) and a via electrode (160) may be provided on a plurality of insulating layers (113, 114, 115) of the upper build-up insulating layer (111). Additionally, an upper through-via electrode (171) may be provided by integrally penetrating the plurality of insulating layers (113, 114, 115).

[0132] At this time, the wiring section (140) includes a first wiring section (140A) and a second wiring section (140B). In addition, each of the first wiring section (140A) and the second wiring section (140B) may include a pad section (151, 152, 153, 154) and a via electrode (161, 162, 163). In addition, in the embodiment, the pad portions (151, 152, 153, 154) and via electrodes (161, 162, 163) of the first wiring portion (140A) are connected to the upper through-via electrode (171) and the lower through-via electrode (172) through the base portion (173), and the pad portions (151, 152, 153, 154) and via electrodes (161, 162, 163) of the second wiring portion (140B) can be electrically separated from the first wiring portion (140A), the upper through-via electrode (171), the lower through-via electrode (172), and the base portion (173).

[0133] The first wiring portion (140A) may refer to a wiring portion that is arranged closest to the upper through-via electrode (171). For example, the first wiring portion (140A) may refer to a wiring portion that is closest to the upper through-via electrode (171) along the horizontal direction. For example, the first wiring portion (140A) may refer to a wiring portion that is arranged closer to the upper through-via electrode (171) than the second wiring portion (140B). The first wiring portion (140A) may be electrically connected to the upper through-via electrode (171). The second wiring portion (140B) may be electrically spaced from the upper through-via electrode (171). The second wiring portion (140B) may be electrically spaced from the first wiring portion (140A). For example, the second wiring portion (140B) may refer to a wiring portion that is spaced further away from the upper through-via electrode (171) than the first wiring portion (140A). That is, the first wiring portion (140A) may be positioned between the second wiring portion (140B) and the upper through-via electrode (171).

[0134] The second wiring section (140B) may be a wiring section that has a different function from the first wiring section (140A).

[0135] The second wiring unit (140B) may be a signal transmission electrode that transmits a signal. For example, the second wiring unit (140B) may be a communication line that transmits a signal to a semiconductor element placed on a circuit board or receives and transmits a signal transmitted from a semiconductor element. In contrast, the first wiring unit (140A) may function as a line other than a signal transmission line. For example, the first wiring unit (140A) may be utilized as a heat transfer path that transfers heat. For example, the first wiring unit (140A) may be an electrode that functions as a heat dissipation electrode together with the upper through-via electrode (171), but is not limited thereto.

[0136] For example, the upper through-via electrode (171) may perform a function other than a heat dissipation function, and accordingly, the first wiring portion (140A) may perform a function corresponding to the other function of the upper through-via electrode (171). However, the first wiring portion (140A) is electrically connected to the upper through-via electrode (171) and may be utilized as a current transmission path for transmitting a plating current applied to electrolytically plate the upper through-via electrode (171). For example, the upper through-via electrode (171) may be an electrolytically plated layer electrolytically plated through a current flowing through the first wiring portion (140A).

[0137] Specifically, in the manufacturing process of forming the upper through-via electrode (171) and the lower through-via electrode (172), the first wiring portion (140A) can be used as a power line for applying a plating current for electrolytic plating the upper through-via electrode (171) and the lower through-via electrode (172). In addition, after the manufacturing of the circuit board (100) is completed, the first wiring portion (140A) can be used as a ground electrode for grounding together with the upper through-via electrode (171), the lower through-via electrode (172), and the base portion (173), or can be used as a heat dissipation line for heat dissipation.

[0138] The first wiring section (140A) includes a plurality of via electrodes (160A1) each arranged within a plurality of insulating layers (113, 114, 115) along the vertical direction, and pad sections (150A2, 150A3) each arranged between the plurality of via electrodes (160A1).

[0139] In response to this, the second wiring portion (140B) includes a plurality of via electrodes (160B) each arranged within a plurality of insulating layers (113, 114, 115) along the vertical direction, and a pad portion (150B) each arranged between the plurality of via electrodes (160B).

[0140] Here, the plurality of via electrodes (160A1) and pad portions (150A2, 150A3) of the first wiring portion (140A) may have substantially the same shape and / or structure as the plurality of via electrodes (160B) and pad portions (150B) of the second wiring portion (140B). However, the plurality of via electrodes (160A1) and pad portions (150A2, 150A3) of the first wiring portion (140A) have a structure electrically connected to the upper through-via electrode (171). In contrast, the plurality of via electrodes (160B) and pad portions (150B) of the second wiring portion (140B) have a structure electrically spaced apart from the first wiring portion (140A) and the upper through-via electrode (171). For example, a plurality of via electrodes (160A1) and pad portions (150A2, 150A3) of the first wiring portion (140A) are electrically connected to the upper through-via electrode (171), and can function as a seed layer that supplies plating current in a process of electroplating the upper through-via electrode (171). In contrast, a plurality of via electrodes (160B) and pad portions (150B) of the second wiring portion (140B) are electrically spaced apart from the first wiring portion (140A) and the upper through-via electrode (171), and can function as signal wiring that transmits a practical electrically effective signal through this.

[0141] At this time, the base portion (173) of the through-via electrode (170) may mean one of the pad portions of the first wiring portion (140A), and preferably, may mean a base pad that electrically connects the through-via electrode (170) and the first wiring portion (140A).

[0142] The base portion (173) can electrically connect between the plurality of via electrodes (160A1) of the first wiring portion (140A) and the upper through-via electrode (171).

[0143] That is, the base portion (173) can be electrically and physically connected to the plurality of via electrodes (160A1) of the first wiring portion (140) while being electrically and physically connected to the upper through-via electrode (171). In addition, the base portion (173) can be electrically and physically connected to the plurality of via electrodes (160A1) of the first wiring portion (140) while being electrically and physically connected to the lower through-via electrode (172).

[0144] For example, the base portion (173) may include a first overlapping portion overlapping a plurality of via electrodes (160A) along the vertical direction, and a second overlapping portion overlapping an upper through-via electrode (171) along the vertical direction.

[0145] That is, the width of the base portion (173) in the horizontal direction may be greater than the width of the upper through-via electrode (171) in the horizontal direction. In addition, the width of the base portion (173) in the horizontal direction may be greater than the width of the lower through-via electrode (172) in the horizontal direction. For example, the width of the base portion (173) in the horizontal direction may be greater than the sum of the widths of the upper through-via electrode (171) and the via electrode (160A1) in the horizontal direction.

[0146] The base portion (173) may refer to a pad portion that is closest to the lower surface of the upper through-via electrode (171). For example, the base portion (173) may be a pad portion that is in contact with the lower surface of the upper through-via electrode (171). For example, the base portion (173) may be a pad portion that is in contact with the via electrode located at the lowest position among the plurality of via electrodes (160A1) of the first wiring portion (140A). In addition, the base portion (173) may be in direct contact with the via electrode (160A1) of the first wiring portion (140A) and may also be in direct contact with the upper through-via electrode (171). Here, direct contact may refer to direct contact with the lower surface of the via electrode located at the lowest position among the upper via electrodes (160A1) of the base portion (173) and the lower surface of the upper through-via electrode (171). Through this, the base portion (173) can electrically connect between the via electrode (160A1) of the first wiring portion (140A) and the upper through-via electrode (171). The planar area of ​​the base portion (173) can be larger than the planar area of ​​the upper through-via electrode (171). For example, as illustrated in FIG. 4, the base portion (173) can vertically overlap with each of the plurality of via electrodes (160A1) and the upper through-via electrode (171) of the first wiring portion (140A). The base portion (173) electrically connects the first wiring portion (140A) and the upper through-via electrode (171), thereby enabling electrolytic plating of the upper through-via electrode (171) using the first wiring portion (140A). That is, the first wiring portion (140A) can function as a seed layer used for electroplating the upper through-via electrode (171), and further can function as a heat dissipation electrode that releases heat together with the upper through-via electrode.

[0147] The base portion (173) may overlap with the upper through-via electrode (171) in the vertical direction, but may not overlap with the upper through-via electrode (171) in the horizontal direction. This may mean that the upper through-via electrode (171) is placed on the base portion (173) in a state where the lower surface of the upper through-via electrode (171) is in direct contact with the upper surface of the base portion (173) based on the position where the base portion (173) is placed.

[0148] The upper surface of the base portion (173) may include a first upper surface that contacts the lower surface of the upper through-via electrode (171) along the vertical direction, and a second upper surface that contacts a plurality of via electrodes (160A1) of the first wiring portion (140A) along the vertical direction. At this time, the plurality of via electrodes (160A1) may be provided in plurality and spaced apart from each other along the horizontal direction. Accordingly, the second upper surface may be divided into a plurality of sub-parts that are spaced apart from each other along the circumferential direction of the first upper surface.

[0149] The base portion (173) may be a reference pad that distinguishes the upper insulating layer from the lower insulating layer. In addition, the upper surface of the base portion (173) is in direct contact with the lower surface of the upper through-via electrode (171), and the lower surface of the base portion (173) is in direct contact with the upper surface of the lower through-via electrode (172).

[0150] To summarize, the base portion (173) is a plate-shaped single pad, and a plurality of via electrodes (160A1) and an upper through-via electrode (171) of the first wiring portion (140A) are arranged on the upper portion. In addition, the base portion (173) can electrically connect a plurality of middle pad portions (150A2), a plurality of upper pad portions (150A3), and a plurality of via electrodes (160A1) of the first wiring portion (140A) that are overlapped with the upper through-via electrodes (171) that are overlapped in the horizontal direction. In addition, the base portion (173) can electrically connect the first wiring portion (140A) and the upper through-via electrode (171) described above.

[0151] For example, the via electrode (160A1) of the first wiring portion (140A) is provided in each of the plurality of insulating layers of the upper build-up insulating layer (111). For example, the via electrodes (160A1) of the first wiring portion (140A) are provided in plurality in the first insulating layer (114) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) are provided in plurality in the second insulating layer (115) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) are provided in plurality in the third insulating layer (116) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171). In addition, the middle pad portion (150A2) of the first wiring portion (140A) can electrically and / or physically connect the via electrodes (160A1) of the first wiring portion (140A) arranged on different layers to each other. At this time, it can be spaced apart from the via electrode (160A1) and the middle pad portion (150A2) of the first wiring portion (140) in the horizontal direction. Through this, in a state where the via electrode (160A1) and the middle pad portion (150A2) of the first wiring portion (140) are formed, a through hole corresponding to the upper through via electrode (171) can be easily processed, and thus the process characteristics for forming the upper through via electrode (171) can be further improved.

[0152] Through this, the via electrodes (160A1) of the first wiring portion (140A) arranged on different layers are electrically connected to each other through the intermediate pad portion (150A2), and these can be electrically connected to the upper through-via electrode (171) through the base portion (173). Accordingly, the plurality of via electrodes (160A1) and the plurality of intermediate pad portions (150A2) of the first wiring portion (140A) can be electrically connected to the upper through-via electrode (171) through the base portion (173).

[0153] Through this, the first wiring portion (140) can be utilized as a seed layer for electroplating the upper through-via electrode (171), thereby allowing anisotropic plating of the upper through-via electrode (171) to proceed. Here, the anisotropic plating may mean that plating is not performed on the inner wall of the through-hole and the bottom surface of the through-hole, but rather in a vertical direction on the bottom surface of the through-hole. Specifically, a chemical copper plating layer is not provided on the inner wall of the through-hole corresponding to the upper through-via electrode (171). In addition, a part of the base portion (173) may be exposed through the through-hole corresponding to the upper through-via electrode (171). Therefore, when electroplating is performed using the first wiring portion (140A), plating growth may occur upward from the upper surface of the base portion (173). Accordingly, the embodiment can utilize the current flowing through the first wiring portion (140A) to perform electroplating for forming the upper through-via electrode (171), thereby omitting the process for forming a separate chemical copper plating layer. Accordingly, the embodiment can provide the current for electroplating the upper through-via electrode (171) using the first wiring portion (140A). Furthermore, the embodiment can provide a uniform current for electroplating the upper through-via electrode (171) using the first wiring portion (140A), thereby enabling the plating to be uniformly formed along the vertical direction during the plating process of the upper through-via electrode (171).

[0154] The current for electroplating the upper through-via electrode (171) can be uniformly provided in the vertical direction through the base portion (173). Therefore, in the embodiment, plating can be performed with a uniform height in the vertical direction based on the upper surface of the base portion (173), thereby improving the flatness of the upper through-via electrode (171). Therefore, the embodiment can simplify the process of manufacturing the upper through-via electrode (171). For example, in the embodiment, the through hole corresponding to the upper through-via electrode (171) can be completely filled with a flat upper surface through a single plating process. Therefore, the embodiment can omit a polishing process, etc., thereby simplifying the manufacturing process and reducing the manufacturing cost. Furthermore, the embodiment can prevent electrodes provided on the circuit board from being damaged by the polishing process by omitting the polishing process, etc. Therefore, the embodiment can further improve the product yield.

[0155] Accordingly, the boundary between the upper through-via electrode (171) and the upper build-up insulating layer (111) may be located between the upper surface of the base portion (173) and the upper surface of the upper build-up insulating layer (111). This may be because the upper through-via electrode (171) is formed by performing electrolytic plating within the through hole penetrating the upper build-up insulating layer (111) using the current flowing between the upper pad portion (150A3) disposed on the upper surface of the upper build-up insulating layer (111) and the base portion (173).

[0156] In addition, the boundary between the lower through-via electrode (172) and the lower build-up insulating layer (112) may be located between the lower surface of the base portion (173) and the lower surface of the lower build-up insulating layer (112). This may be because the lower through-via electrode (172) is formed by performing electrolytic plating within the through-hole penetrating the lower insulating layer (111) using a current flowing between the base portion (173) and the pad portion (not shown) disposed on the upper surface of the lower build-up insulating layer (112).

[0157] The crystal grains of the upper through-via electrode (171) may be different from the crystal grains of the wiring portion (140). In addition, the crystal grains of the upper through-via electrode (171) may be different from the crystal grains of the base portion (173). Correspondingly, the crystal grains of the lower through-via electrode (172) may be different from the crystal grains of the wiring portion (140). In addition, the crystal grains of the lower through-via electrode (172) may be different from the crystal grains of the base portion (173). At this time, the crystal grains of the upper through-via electrode (171) may be the same as the crystal grains of the lower through-via electrode (172). At this time, the above-described crystal grains may mean the crystal grain size.

[0158] That is, the size of the crystal grains of the upper through-via electrode (171) may be different from the size of the crystal grains of the wiring portion (140). For example, the size of the crystal grains of the upper through-via electrode (171) may be different from the size of the crystal grains of at least one region of the wiring portion (140). The size of the crystal grains of the upper through-via electrode (171) may be different from the size of the crystal grains of at least one region of the base portion (173). That is, the base portion (173) may include a chemical copper plating layer and an electrolytic plating layer. In contrast, the upper through-via electrode (171) may be provided with only an electrolytic plating layer. Through this, the embodiment can ensure that uniform plating growth of the upper through-via electrode (171) is achieved along the vertical direction based on the base portion (173) since the upper through-via electrode (171) includes only an electrolytic plating layer, and can further improve the flatness of the surface of the upper through-via electrode (171). Additionally, the embodiment can be configured to include only a dense electrolytic plating layer of crystal grains of the upper through-via electrode (171), thereby providing high thermal conductivity characteristics and more efficiently dissipating heat generated through the semiconductor element.

[0159] Therefore, the upper through-via electrode (171) can have a uniform grain size over the entire area.

[0160] For example, the upper through-via electrode (171) may include a first region that contacts the inner wall of a through-hole that integrally penetrates the upper insulating layer, and a second region on the inner side of the upper through-via electrode (171) that is further away from the inner wall of the through-hole than the first region. In addition, the sizes of the crystal grains in each of the first region and the second region of the upper through-via electrode (171) may be the same. That is, in the comparative example, the through-via electrode may be formed by performing electrolytic plating, but for this purpose, a chemical copper plating layer must be necessarily disposed on the inner wall of the through-hole, and accordingly, the sizes of the crystal grains in the first region and the second region of the through-via electrode in the comparative example are different. In contrast, the embodiment may have uniform crystal grain sizes in the first region and the second region of the upper through-via electrode (171), thereby improving the flatness of the upper through-via electrode (171) while providing high heat dissipation characteristics.

[0161] In addition, the size of the crystal grains of the lower through-via electrode (172) may be different from the size of the crystal grains of the wiring portion (140). For example, the size of the crystal grains of the lower through-via electrode (172) may be different from the size of the crystal grains of at least one region of the wiring portion (140). The size of the crystal grains of the lower through-via electrode (172) may be different from the size of the crystal grains of at least one region of the base portion (173). That is, the base portion (173) may include a chemical copper plating layer and an electrolytic plating layer. In contrast, the lower through-via electrode (172) may be provided with only an electrolytic plating layer. Through this, the embodiment can ensure that uniform plating growth of the lower through-via electrode (172) is achieved along the vertical direction based on the base portion (173) since the lower through-via electrode (172) includes only an electrolytic plating layer, and can further improve the flatness of the surface of the lower through-via electrode (172). Additionally, the embodiment can be configured to include only a dense electrolytic plating layer of crystal grains of the lower through-via electrode (172), thereby providing high thermal conductivity characteristics and more efficiently dissipating heat generated through the semiconductor element.

[0162] Therefore, the lower through-via electrode (172) can have a uniform grain size over the entire area.

[0163] For example, the lower through-via electrode (172) may include a first region that contacts the inner wall of a through-hole that integrally penetrates the lower insulating layer, and a second region on the inner side of the lower through-via electrode (172) that is further away from the inner wall of the through-hole than the first region. In addition, the sizes of the crystal grains in each of the first region and the second region of the lower through-via electrode (172) may be the same. That is, in the comparative example, the through-via electrode may be formed by performing electrolytic plating, but for this purpose, a chemical copper plating layer must be necessarily disposed on the inner wall of the through-hole, and accordingly, the sizes of the crystal grains in the first region and the second region of the through-via electrode in the comparative example are different. In contrast, the embodiment may have uniform crystal grain sizes in the first region and the second region of the lower through-via electrode (172), thereby improving the flatness of the lower through-via electrode (172) while providing high heat dissipation characteristics.

[0164] The first wiring portion (140A) further includes an upper pad portion (150A3). The upper pad portion (150A3) may refer to the pad portion closest to the first protective layer (120) among the pad portions of the first wiring portion (140A). The upper pad portion (150A3) may function as a plating lead pad to which a current is applied for electrolytic plating of the upper through-via electrode (171).

[0165] Additionally, a through-via electrode pad (171P) may be placed on the upper through-via electrode (171). The through-via electrode pad (171P) may be formed together with the upper through-via electrode (171) in the process of forming the upper through-via electrode (171).

[0166] At this time, the upper pad portion (150A3) may be physically spaced apart from the through-via electrode pad (171P) without being directly connected to it. In this case, the upper pad portion (150A3) and the through-via electrode pad (171P) may be spaced apart from each other without being in direct contact with each other in the horizontal direction on the upper surface of the upper build-up insulating layer (111). In this case, the upper pad portion (150A3) and the through-via electrode pad (171P) may be electrically connected to each other through the via electrode (160A1), the base portion (173), the middle pad portion (150A2) and the upper through-via electrode (171) of the first wiring portion (140A). In addition, when the upper pad portion (150A3) and the through-via electrode pad (171P) are spaced apart from each other in the horizontal direction, the heat dissipation path can be branched into multiple paths, thereby further improving the heat dissipation characteristics.

[0167] Meanwhile, as illustrated in FIG. 1, the first wiring portion (140A) described above may be provided at the lower portion of the base portion (173) together with the lower through-via electrode (172). For example, the first wiring portion and the upper through-via electrode arranged at the upper portion of the base portion (173) may have a symmetrical shape with respect to the first wiring portion and the lower through-via electrode arranged at the lower portion of the base portion (173).

[0168] In addition, according to the embodiment of FIG. 5, the via electrodes (160A1) of the first wiring portion (140A) may be provided in plurality while being spaced apart from each other along the circumferential direction of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) may be provided in plurality while being spaced apart from each other along the circumferential direction of the upper through-via electrode (171) within each insulating layer (113, 114, 114) of the upper build-up insulating layer (111).

[0169] Specifically, the via electrodes (160A1) of the first wiring portion (140A) may include a plurality of first via electrodes that are arranged in the first insulating layer (113) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171). In addition, the via electrodes (160A1) of the first wiring portion (140A) may include a plurality of second via electrodes that are arranged in the second insulating layer (114) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171). In addition, the via electrodes (160A1) of the first wiring portion (140A) may include a plurality of third via electrodes that are arranged in the third insulating layer (115) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171).

[0170] At this time, the via electrodes (160A1) of the first wiring section (140A) may have a circular planar shape and be arranged in multiple numbers along the circumferential direction of the upper through via electrode (171).

[0171] In addition, according to the embodiment of FIG. 6, the via electrodes (160A1) of the first wiring portion (140A) may be provided in multiple numbers while being spaced apart from each other along the circumferential direction of the upper through-via electrode (171). At this time, the via electrodes (160A1) of the first wiring portion (140A) may have a rectangular planar shape and may be arranged in multiple numbers along the circumferential direction of the upper through-via electrode (171).

[0172] At this time, according to the embodiments of FIGS. 5 and 6, the via electrodes (160A1) of the first wiring portion (140A) may be provided so as to be spaced apart from each other in the horizontal direction within each insulating layer of the upper build-up insulating layer (111). At this time, the upper through-via electrode (171) may have a plurality of side portions from a planar perspective. For example, the upper through-via electrode (171) may include a first side portion and a second side portion that face each other. In addition, the upper through-via electrode (171) may include a third side portion and a fourth side portion between the first side portion and the second side portion that face each other. At this time, the via electrodes (160A1) of the first wiring portion (140A) may be provided so as to be spaced apart from each other in a plurality of adjacent regions of each of the first side portion, the second side portion, the third side portion, and the fourth side portion of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) may be provided in multiple numbers and spaced apart from each other on the first side of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) may be provided in multiple numbers and spaced apart from each other on the second side of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) may be provided in multiple numbers and spaced apart from each other on the third side of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) may be provided in multiple numbers and spaced apart from each other on the fourth side of the upper through-via electrode (171). Specifically, the via electrodes (160A1) of the first wiring portion (140A) may be provided in plurality in each insulating layer (113, 114, 115) of the upper build-up insulating layer (111) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171). For example, the via electrodes (160A1) of the first wiring portion (140A) may include a plurality of first sub-via electrodes that are arranged on the first side of the upper through-via electrode (171) and spaced apart from each other.In addition, the via electrode (160A1) of the first wiring portion (140A) may include a plurality of second sub-via electrodes that are arranged on the second side of the upper through-via electrode (171) and spaced apart from each other. In addition, the via electrode (160A1) of the first wiring portion (140A) may include a plurality of third sub-via electrodes that are arranged on the third side of the upper through-via electrode (171) and spaced apart from each other. In addition, the via electrode (160A1) of the first wiring portion (140A) may include a plurality of fourth sub-via electrodes that are arranged on the fourth side of the upper through-via electrode (171) and spaced apart from each other. And, the plurality of first sub-via electrodes, the plurality of second sub-via electrodes, the plurality of third sub-via electrodes, and the plurality of fourth sub-via electrodes of the via electrode (160A1) of the first wiring portion (140A) are electrically connected to the upper through-via electrode (171) through the base portion (173) and the middle pad portion (150A2). Through this, the embodiment can uniformly provide a plating current for electrolytic plating the upper through-via electrode (171) through the plurality of plating lines through the plurality of first sub-via electrodes, the plurality of second sub-via electrodes, the plurality of third sub-via electrodes, and the plurality of fourth sub-via electrodes.

[0173] Furthermore, the via electrode (160A1) of the first wiring portion (140A) is disposed within each of the plurality of insulating layers (113, 114, 115) of the upper build-up insulating layer (111), and the via electrode (160A1) of the first wiring portion (140A) disposed within each of the plurality of insulating layers (113, 114, 115) may include the plurality of first sub-via electrodes, the plurality of second sub-via electrodes, the plurality of third sub-via electrodes, and the plurality of fourth sub-via electrodes described above.

[0174] According to the embodiment of FIG. 7, unlike the embodiments of FIGS. 5 and 6, the via electrode (160A1) of the first wiring portion (140A) may be provided with only one via electrode extending in the circumferential direction on each side of the upper through via electrode (171).

[0175] For example, the via electrode (160A1) of the first wiring portion (140A) may include one first sub-via electrode (160A11) disposed on the first side of the upper through-via electrode (171). For example, the first sub-via electrode (160A11) may have a structure in which a plurality of first sub-via electrodes according to the embodiment of FIG. 6 are integrally formed.

[0176] The first sub-via electrode (160A11) may have a bar shape that extends long in the horizontal direction. In this case, the first sub-via electrode (160A11) is illustrated in the drawing as having a square shape in the planar shape, but is not limited thereto. For example, the planar shape of the first sub-via electrode (160A11) may have a circular or oval shape and may be provided to extend long in a specific horizontal direction.

[0177] For example, the via electrode (160A1) of the first wiring portion (140A) may include one second sub-via electrode (160A12) disposed on the second side of the upper through-via electrode (171). For example, the second sub-via electrode (160A12) may have a structure in which a plurality of second sub-via electrodes according to the embodiment of FIG. 6 are integrally formed. The second sub-via electrode (160A12) may have a bar shape that is elongated in the horizontal direction. At this time, the second sub-via electrode (160A12) is illustrated in the drawing as having a square shape in the planar shape, but is not limited thereto. For example, the planar shape of the second sub-via electrode (160A12) may be provided to be elongated in a specific horizontal direction while having a circular or oval shape.

[0178] For example, the via electrode (160A1) of the first wiring portion (140A) may include a third sub-via electrode (160A13) disposed on the third side of the upper through-via electrode (171). For example, the third sub-via electrode (160A13) may have a structure in which a plurality of third sub-via electrodes according to the embodiment of FIG. 6 are integrally formed. The third sub-via electrode (160A13) may have a bar shape that is elongated in the horizontal direction. In this case, the third sub-via electrode (160A13) is illustrated in the drawing as having a square shape in the planar shape, but is not limited thereto. For example, the planar shape of the third sub-via electrode (160A13) may be provided to be elongated in a specific horizontal direction while having a circular or oval shape.

[0179] For example, the via electrode (160A1) of the first wiring portion (140A) may include a fourth sub-via electrode (160A14) disposed on the fourth side of the upper through-via electrode (171). For example, the fourth sub-via electrode (160A14) may have a structure in which a plurality of fourth sub-via electrodes according to the embodiment of FIG. 6 are integrally formed. The fourth sub-via electrode (160A14) may have a bar shape that is elongated in the horizontal direction. In this case, the fourth sub-via electrode (160A14) is illustrated in the drawing as having a square shape in the planar shape, but is not limited thereto. For example, the planar shape of the fourth sub-via electrode (160A14) may be provided to be elongated in a specific horizontal direction while having a circular or oval shape.

[0180] Accordingly, according to the embodiment of FIG. 7, the via electrodes of the first wiring portion (140A) can uniformly provide a plating current for electrolytic plating the upper through-via electrode (171) through a plating line through one first sub-via electrode, one second sub-via electrode, one third sub-via electrode, and one fourth sub-via electrode.

[0181] In addition, at least two of the plurality of side portions of the upper through-via electrode (171) may be provided with a single sub-via electrode that is physically directly connected to each other. For example, the first sub-via electrode (160A11) and the third sub-via electrode (160A13) may have an integral structure that is connected to each other, and the second sub-via electrode (160A12) and the fourth sub-via electrode (160A14) may have an integral structure that is connected to each other. Through this, the embodiment can ensure that the current for plating the upper through-via electrode (171) is uniformly applied, thereby further securing the flatness of the upper through-via electrode (171). In addition, the embodiment can further improve the heat dissipation function by increasing the area of ​​the first wiring portion (140A), thereby allowing the circuit board and the semiconductor package to operate more stably.

[0182] However, in Fig. 6, four sub-via electrodes spaced apart along the circumferential direction are provided on the side of the upper through-via electrode (171), but this is not limited thereto.

[0183] Additionally, the via electrode (160A1) of the first wiring section (140A) of the embodiment can also be implemented by a combination of the via electrodes illustrated in FIGS. 4 to 6.

[0184] For example, the first insulating layer (113) of the upper build-up insulating layer (111) may be provided with a via electrode (160A1) illustrated in any one of FIGS. 5 to 7, and the second insulating layer (114) may be provided with a via electrode of a different drawing from the via electrode provided in the first insulating layer (113) of FIGS. 5 to 7.

[0185] In addition, according to the embodiment of FIG. 8, the via electrode (160A1) of the first wiring portion (140A) may be provided with a closed loop shape along the circumferential direction of the upper through-via electrode (171). For example, the via electrode (160A1) of the first wiring portion (140) may be provided with a ring shape along the circumferential direction of the upper through-via electrode (171) in one insulating layer. In this case, the intermediate pad portion (150A2) physically directly connected to the via electrode (160A1) of the first wiring portion (140) may be provided with a closed loop shape rather than a structure in which the via electrodes (160A1) are connected to each other. In this case, the embodiment can further increase the volume of the first wiring portion (140A), thereby further improving the heat dissipation characteristics.

[0186] Additionally, the via electrode (160A1) of the first wiring section (140A) of the embodiment can also be implemented by a combination of the via electrodes illustrated in FIGS. 5 to 8.

[0187] For example, the first insulating layer (113) of the upper build-up insulating layer (111) may be provided with a via electrode as shown in one of the drawings in FIGS. 5 to 8, the second insulating layer (114) of the upper build-up insulating layer (111) may be provided with a via electrode as shown in another drawing in FIGS. 5 to 8, and the third insulating layer (115) of the upper build-up insulating layer (111) may be provided with a via electrode as shown in another drawing in FIGS. 5 to 8.

[0188] Additionally, according to the embodiment of FIG. 9, a through-via electrode pad (171P1) may be placed on the upper through-via electrode (171). The through-via electrode pad (171P) may be formed together with the upper through-via electrode (171) in the process of forming the upper through-via electrode (171).

[0189] At this time, the upper pad portion (150A3) may be physically and / or electrically connected to the through-via electrode pad (171P1). For example, the upper pad portion (150A3) and the through-via electrode pad (171P1) may be physically directly connected to each other to form a single pad. For example, the upper pad portion (150A3) and the through-via electrode pad (171P1) may be formed integrally. This may be implemented by adjusting the size of the opening of the mask disposed on the upper build-up insulating layer (111) in the process of forming the upper through-via electrode (171).

[0190] Through this, the embodiment can further improve the heat dissipation characteristics of the semiconductor element placed on the upper pad portion (150A3) and the through via electrode pad (171P1), thereby enabling the semiconductor element to operate more stably.

[0191] Below, various embodiments of the first wiring section and the through via electrode of the embodiment are described.

[0192] Before describing various embodiments of the first wiring section and the through via electrode, the structure of the previous embodiment is briefly described as follows.

[0193] A circuit board includes a wiring portion and a through-via electrode. The wiring portion includes a first wiring portion connected to the through-via electrode, and a second wiring portion spaced apart from the through-via electrode. The first wiring portion includes a plurality of via electrodes each disposed within a plurality of insulating layers stacked in a vertical direction, and a plurality of pad portions disposed between the plurality of via electrodes. At this time, the circuit board may include a base portion. The base portion may be a component of the through-via electrode and a component of the first wiring portion. Preferably, the base portion may be a base pad electrically connecting the first portion and / or the second portion of the through-via electrode and the first wiring portion. The base portion is electrically connected to the plurality of via electrodes and is also connected to the through-via electrode. Through this, the first wiring portion and the through-via electrode are electrically connected. At this time, the through-via electrode includes an upper through-via electrode disposed on the base portion, and a lower through-via electrode disposed under the base portion. In addition, the first wiring portion includes an upper wiring portion provided along the circumferential direction of the upper through-via electrode, and a lower wiring portion provided along the circumferential direction of the lower through-via electrode. At this time, the upper through-via electrode and the lower through-via electrode in the previous embodiment have shapes that are symmetrical with respect to the base portion. Furthermore, the upper wiring portion and the lower wiring portion have shapes that are symmetrical with respect to the base portion.

[0194] A circuit board according to an embodiment of FIG. 10 includes an upper build-up insulating layer (211) including a plurality of insulating layers stacked along a vertical direction, and a lower build-up insulating layer (212) including a plurality of insulating layers stacked along a vertical direction. A first protective layer (220) is disposed on the upper build-up insulating layer (211). In addition, a second protective layer (230) is disposed under the lower build-up insulating layer (212).

[0195] In addition, an upper through-via electrode (250) is arranged to integrally penetrate the upper build-up insulating layer (211) on which multiple insulating layers are laminated. In addition, a lower through-via electrode (260) is arranged to integrally penetrate the lower build-up insulating layer (212) on which multiple insulating layers are laminated.

[0196] In addition, the wiring portion of the circuit board has a plurality of via electrodes and pad portions. At this time, the wiring portion includes a first wiring portion (242, 243) electrically connected to an upper through-via electrode (250) and / or a lower through-via electrode (260). In addition, the wiring portion includes a second wiring portion (244) electrically and physically spaced from the upper through-via electrode (250) and the lower through-via electrode (260).

[0197] The first wiring portion (242, 243) includes an upper wiring portion (242) provided along the circumferential direction of the upper through-via electrode (250). The first wiring portion (242, 243) includes a lower wiring portion (243) provided along the circumferential direction of the lower through-via electrode (260).

[0198] At this time, the upper through-via electrode (171) and the lower through-via electrode (172) in the previous embodiment had shapes that were symmetrical to each other.

[0199] In contrast, the upper through-via electrode (250) and the lower through-via electrode (260) may have an asymmetrical shape with respect to the base portion (241). For example, the width in the horizontal direction and / or the thickness in the vertical direction of the upper through-via electrode (250) may be different from the width in the horizontal direction and / or the thickness in the vertical direction of the lower through-via electrode (260). For example, the width in the horizontal direction of the upper through-via electrode (250) may be different from the width in the horizontal direction of the lower through-via electrode (260). For example, the width in the horizontal direction of the upper through-via electrode (250) may be smaller than the width in the horizontal direction of the lower through-via electrode (260). Through this, the embodiment may allow heat to be transferred from the upper through-via electrode (250) having a relatively small width in the horizontal direction to the lower through-via electrode (260) having a relatively large width in the horizontal direction. That is, the embodiment can control the heat transfer direction by varying the width of the upper through-via electrode (250) and the lower through-via electrode (260), thereby providing a more efficient heat dissipation function.

[0200]

[0201] A circuit board according to an embodiment of FIG. 11 includes an upper build-up insulating layer (311) including a plurality of insulating layers stacked along a vertical direction, and a lower build-up insulating layer (312) including a plurality of insulating layers stacked along a vertical direction. A first protective layer (320) is disposed on the upper build-up insulating layer (311). In addition, a second protective layer (330) is disposed under the lower build-up insulating layer (312).

[0202] Additionally, an upper through-via electrode (350) is arranged to integrally penetrate the upper build-up insulating layer (311) on which multiple insulating layers are laminated. Additionally, a lower through-via electrode (360) is arranged to integrally penetrate the lower build-up insulating layer (312) on which multiple insulating layers are laminated.

[0203] At this time, the upper through-via electrode (350) may be provided in multiple pieces spaced apart along the horizontal direction.

[0204] For example, the upper through-via electrode (350) may include a first upper through-via electrode (351) that integrally penetrates multiple insulating layers of the upper insulating layer (311), and a second upper through-via electrode (352) that integrally penetrates multiple insulating layers of the upper insulating layer (311) and is spaced apart from the first upper through-via electrode (351) in the horizontal direction. The first upper through-via electrode (351) and the second upper through-via electrode (352) may be referred to as a first sub-through-via electrode and a second sub-through-via electrode of the upper through-via electrode (350) that are spaced apart from each other in the horizontal direction.

[0205] For example, the first upper through-via electrode (351) and the second upper through-via electrode (352) can transfer heat through mutually branched paths. This allows the embodiment to dissipate heat through multiple paths rather than a single path, thereby further improving heat dissipation characteristics.

[0206] At this time, a plurality of semiconductor elements may be arranged on the circuit board. For example, first and second semiconductor elements spaced apart horizontally may be arranged on the circuit board.

[0207] In addition, the first upper through-via electrode (351) may be provided in an area where the first semiconductor element is arranged. In addition, the second upper through-via electrode (352) may be provided in an area where the second semiconductor element is arranged. That is, the embodiment may provide an upper through-via electrode corresponding to each of a plurality of semiconductor elements arranged on the circuit board. Through this, the embodiment may further maximize the heat dissipation characteristics in a semiconductor package in which a plurality of semiconductor elements are arranged.

[0208] In addition, the wiring portion of the circuit board has a plurality of via electrodes and pad portions. At this time, the wiring portion includes a first wiring portion (342, 343) electrically connected to an upper through-via electrode (350) and / or a lower through-via electrode (360). In addition, the wiring portion includes a second wiring portion (344) spaced apart from the upper through-via electrode (350) and the lower through-via electrode (360).

[0209] The first wiring portion (342, 343) includes an upper wiring portion (342) provided along the circumferential direction of the upper through-via electrode (350). The first wiring portion (342, 343) includes a lower wiring portion (343) provided along the circumferential direction of the lower through-via electrode (360).

[0210] The upper wiring portion (342) may include a first upper wiring portion (342a) provided along the circumferential direction of the first upper through-via electrode (351). In addition, the upper wiring portion (342) may include a second upper wiring portion (342b) provided along the circumferential direction of the second upper through-via electrode (352). That is, the embodiment may allow the upper through-via electrode (350) to include a first upper through-via electrode (351) and a second upper through-via electrode (352) spaced apart from each other in the horizontal direction, and the upper wiring portion (342) to include a first upper wiring portion (342a) and a second upper wiring portion (342b) provided along the circumferential direction of each of the upper through-via electrodes. Through this, the embodiment may allow uniform plating of each of the first upper through-via electrode (351) and the second upper through-via electrode (352).

[0211] A circuit board according to an embodiment of FIG. 12 includes an upper build-up insulating layer (411) including a plurality of insulating layers stacked along a vertical direction, and a lower build-up insulating layer (412) including a plurality of insulating layers stacked along a vertical direction. A first protective layer (420) is disposed on the upper build-up insulating layer (411). In addition, a second protective layer (430) is disposed under the lower build-up insulating layer (412).

[0212] Additionally, an upper through-via electrode (450) is disposed that integrally penetrates the upper build-up insulating layer (411) on which multiple insulating layers are laminated. Additionally, a lower through-via electrode (460) is disposed that integrally penetrates the lower build-up insulating layer (412) on which multiple insulating layers are laminated.

[0213] In addition, the wiring portion of the circuit board has a plurality of via electrodes and pad portions. At this time, the wiring portion includes a first wiring portion (442, 443) electrically connected to an upper through-via electrode (450) and / or a lower through-via electrode (460). In addition, the wiring portion includes a second wiring portion (444) spaced apart from the upper through-via electrode (450) and the lower through-via electrode (460).

[0214] The first wiring portion (442, 443) includes an upper wiring portion (442) provided on one side of the periphery of the upper through-via electrode (450). The first wiring portion (442, 443) includes a lower wiring portion (443) provided on the other side of the periphery of the lower through-via electrode (460).

[0215] At this time, each of the upper wiring portion and the lower wiring portion in the previous embodiment was provided to surround the periphery of the upper through-via electrode or the lower through-via electrode.

[0216] Alternatively, the upper wiring portion (442) may be provided on one side of the upper through-via electrode (450), and the lower wiring portion (443) may be provided on the other side of the lower through-via electrode (460). In this case, the current for plating the upper through-via electrode (450) and the lower through-via electrode (460) may flow through a path formed by the upper wiring portion (442), the base portion (441), and the lower wiring portion (443). Therefore, the embodiment can further increase the volume of the upper through-via electrode (450) and / or the lower through-via electrode (450) in an area equal to the area of ​​the circuit board of the previous embodiment. Through this, the embodiment can further improve the heat dissipation characteristics. In this case, at least a portion of the upper through-via electrode (450) may overlap with the lower wiring portion (443) in a vertical direction, and at least a portion of the lower through-via electrode (460) may overlap with the upper wiring portion (442) in a vertical direction.

[0217] Furthermore, the horizontal central axis of the lower through-via electrode (460) and the horizontal central axis of the upper through-via electrode (450) may be misaligned with each other.

[0218] Meanwhile, in the previous embodiment, the via electrodes of each of the upper wiring portion and the lower wiring portion were positioned to overlap each other in the vertical direction. Alternatively, the via electrodes of each of the upper wiring portion and the lower wiring portion may be positioned to be offset from each other in the vertical direction.

[0219] According to the embodiment of Fig. 13, the circuit board may have an upper wiring portion (542) and a lower wiring portion (543) that are arranged at positions that are offset from each other along the vertical direction. Fig. 13 is a cross-sectional view taken along the BB' direction in Fig. 1, and specifically, is a cross-sectional view in the vertical direction at the positions where the upper wiring portion and the lower wiring portion are arranged.

[0220] The circuit board includes an upper build-up insulating layer (511) including a plurality of insulating layers stacked along a vertical direction, and a lower build-up insulating layer (512) including a plurality of insulating layers stacked along a vertical direction. A first protective layer (520) is disposed on the upper insulating layer (511). In addition, a second protective layer (530) is disposed under the lower build-up insulating layer (512).

[0221] Additionally, an upper through-via electrode (not shown) is disposed that integrally penetrates the upper build-up insulating layer (511) on which multiple insulating layers are laminated. Additionally, a lower through-via electrode (560) is disposed that integrally penetrates the lower build-up insulating layer (512) on which multiple insulating layers are laminated.

[0222] In addition, the wiring portion of the circuit board has a plurality of via electrodes and pad portions. At this time, the wiring portion includes a first wiring portion (542, 543) electrically connected to an upper through-via electrode and / or a lower through-via electrode. In addition, the wiring portion includes a second wiring portion (not shown) spaced apart from the upper through-via electrode and the lower through-via electrode.

[0223] The first wiring portion (542, 543) includes an upper wiring portion (542) provided along the circumference direction of the upper through-via electrode. The first wiring portion (542, 543) includes a lower wiring portion (543) provided on the other side of the circumference of the lower through-via electrode.

[0224] At this time, the upper wiring portion (542) has via electrodes arranged in a plurality of insulating layers of the upper build-up insulating layer (511), and these may be arranged at positions that are offset from each other along the vertical direction. In addition, the lower wiring portion (543) has via electrodes arranged in a plurality of insulating layers of the lower build-up insulating layer (512), and these may be arranged at positions that are offset from each other along the vertical direction. Through this, the embodiment can allow the current supplied for electrolytic plating of the upper through-via electrode and the lower through-via electrode to flow along a zigzag path along the vertical direction rather than along a path along a single vertical line. Through this, the embodiment can allow the current to be supplied more uniformly along the circumferential direction of the through-via electrode, and thus the flatness of the surface of the through-via electrode can be further improved.

[0225]

[0226] According to the embodiment of FIG. 14, the semiconductor package may include at least one circuit board among the circuit boards illustrated in FIGS. 1 to 13. As an example, the semiconductor package may include a circuit board (600) as illustrated in FIG. 3.

[0227] A first connection portion (610) and a second connection portion (620) may be provided on the circuit board (600). The first connection portion (610) may overlap a through-via electrode provided on the circuit board (600) in a vertical direction. Preferably, the first connection portion (610) may be provided on an upper surface of a pad portion provided on an upper portion of the through-via electrode provided on the circuit board (600). In addition, the second connection portion (620) may be provided on a pad portion provided on an uppermost portion of a second wiring portion provided on the circuit board (600).

[0228] A semiconductor element (630) may be placed on the first connection portion (610) and the second connection portion (620). The semiconductor element (630) may be electrically connected to the circuit board (600) through the first connection portion (610) and the second connection portion (620). For example, the semiconductor element (630) may be thermally connected to a through-via electrode of the circuit board (600) through the first connection portion (610). Through this, heat generated in the semiconductor element (630) may be dissipated through the through-via electrode of the circuit board (600) through the first connection portion (610).

[0229] In addition, the semiconductor element (630) has a terminal (640), and the terminal (640) of the semiconductor element (630) can be electrically connected to a pad portion of a second wiring portion of the circuit board through a second connection portion (620).

[0230]

[0231] According to the embodiment of FIG. 15, the semiconductor package may include at least one circuit board among the circuit boards illustrated in FIGS. 1 to 13. As an example, the semiconductor package may include a circuit board (700) as illustrated in FIG. 3.

[0232] A connection portion (710) may be provided on the circuit board (700). The connection portion (710) may overlap a through-via electrode provided on the circuit board (700) in a vertical direction. Preferably, the connection portion (710) may be provided on an upper surface of a pad portion provided on an upper portion of the through-via electrode provided on the circuit board (700). For example, the semiconductor element (730) may be thermally connected to the through-via electrode of the circuit board (700) through the connection portion (710). Through this, heat generated in the semiconductor element (730) may be dissipated through the through-via electrode of the circuit board (700) through the connection portion (710).

[0233] In addition, the semiconductor element (730) may be provided with a terminal (740) on the upper surface, and a connecting member (720) such as a wire may electrically connect the terminal (740) of the semiconductor element (730) and the pad portion of the second wiring portion of the circuit board.

[0234]

[0235] Below, a method for manufacturing a circuit board according to an embodiment will be described.

[0236] Figures 16 to 20 are cross-sectional views showing a method for manufacturing a circuit board according to one embodiment in process order.

[0237] Referring to FIG. 16, the embodiment may perform a process of forming a build-up insulating layer (110) in which an upper build-up insulating layer (111) and a lower build-up insulating layer (112) are stacked along a vertical direction, and a wiring portion (140) including a plurality of via electrodes and a plurality of pad portions within the build-up insulating layer (110). At this time, the wiring portion (140) may include a first wiring portion (140A) and a second wiring portion (140B). The first wiring portion (140) may include a base portion (173) which is a part of a through-via electrode (170).

[0238] Next, referring to FIG. 17, the embodiment may perform a process of forming an upper through hole (VH1) integrally penetrating the upper build-up insulating layer (111). At this time, the embodiment may perform a process of forming the upper through hole (VH1) using the base portion (173) as a stopper. Therefore, as the upper through hole (VH1) is formed, the upper surface of the base portion (173) may be exposed. In addition, the embodiment may perform a process of forming a lower through hole (VH2) integrally penetrating the lower build-up insulating layer (112). At this time, the embodiment may perform a process of forming the lower through hole (VH2) using the base portion (173) as a stopper. Therefore, as the lower through hole (VH2) is formed, the lower surface of the base portion (173) may be exposed.

[0239] Next, referring to FIG. 18, the embodiment may perform a process of forming a first mask (M1) on the upper build-up insulating layer (111). At this time, the first mask (M1) may include an opening that overlaps the upper through hole (VH1) in a vertical direction. In addition, the opening of the first mask (M1) may expose a side surface of the uppermost pad portion of the first wiring portion (140A). Through this, the upper pad portion of the upper through via electrode and the upper pad portion of the first wiring portion (140A) may be physically directly connected to each other later. In addition, the embodiment may perform a process of forming a second mask (M2) on the lower build-up insulating layer (112). At this time, the second mask (M2) may include an opening that overlaps the lower through hole (VH2) in a vertical direction. In addition, the opening of the second mask (M2) may expose a side surface of the lowermost pad portion of the first wiring portion (140A). Through this, the lower pad portion of the lower through-via electrode and the lower pad portion of the first wiring portion (140A) can be physically directly connected to each other in the future. Thereafter, the embodiment may perform a process of forming an electrolytic plating layer (171A) on the upper surface of the base portion (173) by performing electrolytic plating on the first wiring portion (140A) as a seed layer. At this time, the embodiment may form the electrolytic plating layer (171A) using the first wiring portion (140A), and thus, plating growth to a uniform height along the vertical direction may be achieved. The embodiment may perform a process of forming an electrolytic plating layer (172A) on the lower surface of the base portion (173) by performing electrolytic plating on the first wiring portion (140A) as a seed layer. At this time, the embodiment may form the electrolytic plating layer (172A) using the first wiring portion (140A), and thus, plating growth to a uniform height along the vertical direction may be achieved.

[0240] Next, referring to FIG. 19, the embodiment may perform a process of forming an upper through-via electrode (171) and an upper pad portion of the upper through-via electrode (171). In addition, the embodiment may perform a process of forming a lower through-via electrode (172) and a lower pad portion of the lower through-via electrode (172). Next, the embodiment may perform a process of removing the first mask (M1) and the second mask (M2).

[0241] Next, referring to FIG. 20, the embodiment can proceed with a process of forming a first protective layer (120) and a second protective layer (130).

[0242]

[0243] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0244] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0245] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0246] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up insulation layer comprising a plurality of insulation layers laminated along a vertical direction; A wiring section including a plurality of via electrodes each arranged within the plurality of insulating layers of the above build-up insulating layer; and Includes a through via electrode penetrating the above build-up insulating layer, The above-mentioned through via electrode includes a first portion having a horizontal width that increases in a direction from the upper surface of the build-up insulating layer toward the lower surface of the build-up insulating layer, a second portion disposed on the first portion and having a horizontal width that decreases in a direction from the upper surface of the build-up insulating layer toward the lower surface of the build-up insulating layer, and a base portion disposed between the first portion and the second portion. A circuit board in which at least one of the plurality of via electrodes of the wiring portion is connected to the base portion.

2. In paragraph 1, The above build-up insulation layer is, An upper build-up insulating layer including a plurality of upper insulating layers arranged on the upper surface of the base portion and stacked along the vertical direction, and A circuit board comprising a lower build-up insulating layer disposed on the lower surface of the base portion and including a plurality of lower insulating layers stacked along the vertical direction.

3. In paragraph 2, The first portion of the above through-via electrode integrally penetrates the plurality of lower insulating layers of the lower build-up insulating layer along the vertical direction, A circuit board, wherein the second portion of the above-mentioned through via electrode integrally penetrates the plurality of upper insulating layers of the upper build-up insulating layer along the vertical direction.

4. In paragraph 3, The wiring portion further includes a plurality of intermediate pad portions arranged between the plurality of via electrodes, The above wiring section, A circuit board comprising a first wiring portion including a plurality of via electrodes and a plurality of intermediate pad portions, the first wiring portion including the via electrode connected to the base portion and the second portion of the through-via electrode electrically connected through the base portion.

5. In paragraph 4, The above wiring portion further includes a second wiring portion that is further away from the through via electrode than the first wiring portion, The first wiring portion is arranged between the second wiring portion and the through via electrode along the horizontal direction, A circuit board, wherein the second wiring portion is electrically separated from the first wiring portion and the through via electrode.

6. In paragraph 1, A circuit board wherein the crystal grains of the first or second portion of the through via electrode and the crystal grains of the base portion are different from each other.

7. In paragraph 6, A circuit board, wherein the size of the crystal grains in at least one area of ​​the base portion is smaller than the size of the crystal grains in the first portion or the second portion of the through via electrode.

8. In paragraph 6, The first part or the second part of the above through via electrode, A first region in contact with the inner wall of the through hole of the above-mentioned build-up insulating layer, and a second region located on the inner side of the through hole further from the inner wall than the first region, A circuit board, wherein the size of the crystal grains in the first region is the same as the size of the crystal grains in the second region.

9. In paragraph 4, The boundary between the first portion of the above-mentioned through via electrode and the above-mentioned build-up insulating layer is located between the lower surface of the lower build-up insulating layer and the lower surface of the base portion, A circuit board, wherein the interface between the second portion of the through via electrode and the upper build-up insulating layer is located between the upper surface of the upper build-up insulating layer and the upper surface of the base portion.

10. In paragraph 5, A circuit board, wherein the first wiring portion includes a lower wiring portion arranged on a lower surface of the base portion and arranged along a circumferential direction of the first portion of the through-via electrode, and an upper wiring portion arranged on a lower surface of the base portion and arranged along a circumferential direction of the second portion of the through-via electrode.

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