Circuit board, and semiconductor package comprising same

Abstract

An embodiment of the present invention provides a circuit board comprising: a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via land disposed between the first insulating layer and the second insulating layer; and a capacitor structure including the first via land, a dielectric layer, and a second via land sequentially stacked on the first insulating layer, wherein the area of the bottom surface of the second via land is different from the area of the top surface of the dielectric layer in contact with the second via land, and the outer surface of the dielectric layer includes an inwardly concave groove.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, to eliminate power transmission noise and droop phenomena, it is required to form a capacitor layer within the substrate. Furthermore, in forming the capacitor layer, there is a problem in that capacitance errors occur due to the etching of some components of the capacitor structure as multiple development, etching, and peeling processes are performed to form the desired capacitance.

[0007] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which a groove is formed only on an outer surface of a dielectric layer in a capacitor structure, and an outer surface of a second via land on the upper side has a different angle (e.g., vertical) with respect to a plane with respect to the dielectric layer, thereby minimizing an error in target capacitance during etching to form a dielectric layer or a first via land, thereby improving circuit performance, power efficiency and stability, and component matching.

[0008] In addition, the embodiment suppresses the formation of a via electrode penetrating the multi-layer insulating layers by forming a capacitor structure on the upper surface of the boundary of adjacent insulating layers, thereby suppressing the occurrence of voids or gaps at the boundary of adjacent insulating layers and implementing a circuit board and a semiconductor package including the same with improved electrical performance.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved integration, increased input / output count, and reduced signal loss through an embedded capacitor structure.

[0010] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which the capacitor layer is formed within a desired insulating layer to reduce an electrical connection path for the capacitor layer and suppress droop and power transmission noise.

[0011] In addition, the embodiment can implement a miniaturized circuit board and a semiconductor package including the same by placing a portion of a capacitor structure under the interface of adjacent insulating layers.

[0012] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0013] A circuit board according to an embodiment of the present invention includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via land disposed between the first insulating layer and the second insulating layer; and a capacitor structure including the first via land, a dielectric layer, and a second via land sequentially stacked on the first insulating layer; wherein an area on a lower surface of the second via land is different from an area on an upper surface of the dielectric layer in contact with the second via land, and an outer surface of the dielectric layer includes an inwardly concave groove.

[0014] The area on the upper surface of the first via land may be greater than the area on the lower surface of the dielectric layer.

[0015] The area on the lower surface of the second vialand may be greater than the area on the upper surface of the dielectric layer.

[0016] The area on the lower surface of the second vialand may be greater than the area on the lower surface of the dielectric layer.

[0017] The above dielectric layer may include an intermediate surface having a minimum area in the stacking direction between the upper surface and the lower surface.

[0018] In the above dielectric layer, the length between the intermediate surface and the upper surface may be the same as the length between the intermediate surface and the lower surface.

[0019] The outer surface of the second via land may be located in the outer region of the edge of the dielectric layer.

[0020] The above first via land may be located above the interface between the first insulating layer and the second insulating layer.

[0021] The area of ​​the second vialand may be smaller than the area of ​​the dielectric layer.

[0022] The upper surface of the above dielectric layer may have a step structure.

[0023] The groove of the above dielectric layer may not overlap with the second via land in the stacking direction.

[0024] The outer surface of the above dielectric layer may be located in a region between the outer surface of the first via land and the outer surface of the second via land.

[0025] The above first via land may be located below the interface between the first insulating layer and the second insulating layer.

[0026] The above second vialand may include a land home located at the edge of the upper surface.

[0027] The above land home may partially overlap with the above home in the stacking direction.

[0028] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which a groove is formed only on an outer surface of a dielectric layer in a capacitor structure, and an outer surface of a second via land on the upper side has a different angle (e.g., vertical) with respect to a plane with respect to the dielectric layer, thereby minimizing an error in target capacitance during etching to form a dielectric layer or a first via land, thereby improving circuit performance, power efficiency and stability, and component matching.

[0029] In addition, the embodiment suppresses the formation of a via electrode penetrating the multi-layer insulating layers by forming a capacitor structure on the upper surface of the boundary surface of adjacent insulating layers, thereby suppressing the occurrence of voids or gaps at the boundary surface of adjacent insulating layers and providing a circuit board and a semiconductor package including the same with improved electrical performance.

[0030] Additionally, the embodiment can provide a circuit board and a semiconductor package including the same with improved integration, increased input / output count, and reduced signal loss through an embedded capacitor structure.

[0031] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which a capacitor layer is formed within a desired insulating layer to reduce an electrical connection path for the capacitor layer and suppress droop and power transmission noise.

[0032] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which miniaturization is realized by placing a portion of a capacitor structure below the interface of adjacent insulating layers.

[0033] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0034] Figure 1 is a plan view of a circuit board according to an embodiment of the present invention;

[0035] Figure 2 is a perspective view of a circuit board according to an embodiment of the present invention;

[0036] Figure 3 is a cross-sectional view of a circuit board according to the first embodiment of the present invention.

[0037] Figure 4 is an enlarged view of K1 in Figure 3,

[0038] Fig. 5 is a plan view of a capacitor structure in a circuit board according to the first embodiment;

[0039] Figure 6 is a drawing taken along the line KK' in Figure 5.

[0040] Fig. 7 is another example of Fig. 5,

[0041] Figure 8 is a drawing taken along the line LL' in Figure 7.

[0042] Figure 9 is an enlarged view of K2 in Figure 3,

[0043] Figures 10a to 10r are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0044] Fig. 11 is a cross-sectional view of a circuit board according to the second embodiment,

[0045] Figure 12 is an enlarged view of K3 in Figure 11,

[0046] Fig. 13 is a plan view of a capacitor structure in a circuit board according to the second embodiment.

[0047] Figure 14 is a drawing taken along the line MM' in Figure 13,

[0048] Figures 15a to 15r are drawings explaining a method for manufacturing a circuit board according to the second embodiment.

[0049] Fig. 16 is a cross-sectional view of a circuit board according to the third embodiment,

[0050] Figure 17 is an enlarged view of K4 in Figure 16,

[0051] Fig. 18 is a plan view of a capacitor structure in a circuit board according to the third embodiment.

[0052] Figure 19 is a drawing taken along the line NN' of Figure 18,

[0053] FIGS. 20A to 20Y are drawings explaining a method for manufacturing a circuit board according to a third embodiment.

[0054] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0055] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0056] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0057] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0058] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0059] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0060] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0061] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0062] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0063] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0064] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0065] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0066] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0067] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0068] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0069] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0070] FIG. 1 is a plan view of a circuit board according to an embodiment of the present invention, FIG. 2 is a perspective view of a circuit board according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 4 is an enlarged view of K1 in FIG. 3, FIG. 5 is a plan view of a capacitor structure in a circuit board according to the first embodiment, FIG. 6 is a view taken along line KK' in FIG. 5, FIG. 7 is another example of FIG. 5, FIG. 8 is a view taken along line LL' in FIG. 7, and FIG. 9 is an enlarged view of K2 in FIG. 3.

[0071] Referring to FIG. 1, a circuit board (100) according to an embodiment may include an insulating layer (110), an electrode portion (120), a protective layer (SR), and a capacitor structure (CAS). Furthermore, the circuit board (100) may include a core layer as a part of the insulating layer (110).

[0072] The insulating layer (110) may be composed of multiple layers. The insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113).

[0073] The third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) may be sequentially positioned along the stacking direction or the vertical direction (Y-axis direction). In other words, the third insulating layer (113) may be positioned at the bottom, the first insulating layer (111) may be positioned on the third insulating layer (113), and the second insulating layer (112) may be sequentially positioned on the first insulating layer (111).

[0074] In addition, the insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0075] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF. In addition, each insulating layer may be composed of the same or different materials.

[0076] Additionally, a protective layer (SR) may be further disposed on the uppermost or lowermost portion of the insulating layer (110). The protective layer (SR) may include a first protective layer (SR2) on the upper portion and a second protective layer (SR1) on the lower portion. The protective layer (SR) may function to protect the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between a semiconductor element and / or a main board and a circuit board, the protective layer (SR) may be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals to be connected to the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist having poor wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (SR) may be formed of a material having insulating properties for electrical connection.

[0077] For example, the protective layer (SR) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0078] And the insulating layer or protective layer (SR) located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it can be electrically connected to other semiconductor elements, the circuit board, etc.

[0079] The electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0080] In an embodiment, the electrode portion (120) may include a wiring electrode (or wiring portion) and a via electrode (or via portion). The embryonic via electrode may include a wiring (or circuit pattern, pattern) and a pad arranged in an insulating layer. The via electrode may be positioned within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Through the via electrode, an electrical connection may be implemented within the insulating layer or above or below the insulating layer.

[0081] The electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123). Each electrode portion may include a wiring portion and a via electrode.

[0082] The first electrode portion (121) may be positioned on the first insulating layer (111). The second electrode portion (122) may be positioned on the second insulating layer (112). The third electrode portion (123) may be positioned on the third insulating layer (113). A portion of each electrode portion may be positioned on an insulating layer adjacent to the corresponding insulating layer. A detailed description thereof will be provided later.

[0083] Furthermore, the first electrode portion (121) may include a first via electrode (121a) and a first wiring portion (121b). In addition, the second electrode portion (122) may include a second-first via electrode (122a), a second wiring portion (122b), and a second-second via electrode (122c). The second-first via electrode (122a) may penetrate the second insulating layer (112) and be connected to a capacitor structure (CAS). The second-second via electrode (122c) may penetrate the second insulating layer (112) and be connected to an electrode located on an upper surface (US1) of the first insulating layer (111) (e.g., an electrode that horizontally overlaps the first via land). And the third electrode portion (123) may include a second-second via electrode (122c) and a third wiring portion (123b).

[0084] In addition, the outer pad of the electrode portion (120) can be bonded to a semiconductor element, substrate, board, etc. using solder, wire, conductive adhesive, etc., and can be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and can have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process.

[0085] And the pads arranged on the inside have the function of connecting the via electrode and the circuit pattern. When the via electrode is arranged with a wider width than the circuit pattern, a pad with a wider width than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is located on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is located on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0086] Additionally, semiconductor devices may be mounted within or on the circuit board. The semiconductor devices may be logic chips, memory chips, etc. The logic chips may be central processing units (CPUs), graphics processors (GPUs), etc.

[0087] Additionally, a capacitor structure (CAS) may be positioned within the insulating layer (110) of the circuit board (100). The capacitor structure (CAS) may be positioned in the first insulating layer (111) or the second insulating layer (112). Alternatively, the capacitor structure (CAS) may be positioned between the first insulating layer (111) and the second insulating layer (112). The capacitor structure (CAS) may be positioned between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). Additionally, the capacitor structure (CAS) may be covered by the second insulating layer (112).

[0088] A capacitor structure (CAS) according to an embodiment may include a first via land (VL1), a dielectric layer (DL), and a second via land (VL2). In the capacitor structure (CAS), the first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may be sequentially stacked or positioned along a vertical direction (Y-axis direction). The first and second via lands (VL1, VL2) may be directly connected to a via electrode. Through the first and second via lands (VL1, VL2), a function for securing positional alignment of the via electrode and a function of a circuit electrically connected to the via electrode may be implemented. In addition, a via land here may mean an electrode, for example, one electrode (layer) and another electrode (layer) of a capacitor structure that performs a capacitor function. Furthermore, although the via electrodes connected to the first via land and the second via land of the capacitor are illustrated as a single via electrode, they may be connected in a single or multiple number depending on the circuit connection.

[0089] Furthermore, as the processor of an electronic device or package substrate continues to draw more power, first droop and power transmission noise can be obstacles. Specifically, first droop can occur when the circuitry within the die or semiconductor device pulls power. To improve this first droop, a capacitor can be added to the circuit substrate on which the die or semiconductor device is provided, as in the embodiment. In particular, it may be desirable to add the capacitor near the die or semiconductor device, which is the source of the droop. In this case, when the capacitor is placed on the die side or the side land of the substrate, the electrical path between the capacitor on the die and the land side (or the die side) becomes longer, which may reduce the additional effect of the capacitor due to added parasitic inductance, etc. In addition, the capacitor on the land side may cause interference with the interface of the circuit substrate or package substrate.

[0090] Therefore, by embedding the capacitor structure in the circuit board under the die as in the embodiment, droop and power transmission noise can be suppressed. In addition, a high-k dielectric layer (DL) can be applied to form a large capacitance capacity. Furthermore, in the embodiment, the capacitor structure can have any suitable shape and dimension. For example, the capacitor structure can have a rectangular or circular shape in plan view. Furthermore, the capacitor structure can be arranged at any position within the circuit board. For example, in order to reduce the electrical path, the capacitor structure can be positioned in a layer adjacent to the upper die within the circuit board. That is, the capacitor structure is positioned in an area adjacent to the die in the insulating layer, so that electrical performance degradation can be suppressed.

[0091] In addition, as an example, the first insulating layer (111) may include an upper surface (US1) and a lower surface (BS1). The second insulating layer (112) may include an upper surface (US2) and a lower surface (BS2). The upper surface (US1) of the first insulating layer (111) may be in contact with the lower surface (BS2) of the second insulating layer (112). For example, the upper surface (US1) of the first insulating layer (111) and the lower surface (BS2) of the second insulating layer (112) may form the same surface.

[0092] And the first via electrode (121a) may be arranged between the lower surface (BS1) of the first insulating layer (111) and the first via land (VL1). In addition, the first via electrode (121a) may be positioned between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US1) of the first insulating layer (111). In addition, the first via electrode (121a) may be positioned between the lower surface (BS1) of the first insulating layer (111) and the second via land (VL2). The first via electrode (121a) may penetrate at least a portion of the first insulating layer (111).

[0093] The second-first via electrode (122a) may be arranged between the first via land (VL1) and the upper surface (US2) of the second insulating layer (112). In addition, the second-first via electrode (122a) may be positioned between the upper surface (US1) of the first insulating layer (111) (or the lower surface, BS2, of the second insulating layer (112)) and the upper surface (US2) of the second insulating layer (112). The second-first via electrode (122a) may penetrate at least a portion of the second insulating layer (112).

[0094] The second-second via electrode (122c) may be disposed between the upper surface (US1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). In addition, the second-second via electrode (122c) may be disposed between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). In addition, the second-second via electrode (122c) may be positioned between the first via land (VL1) and the upper surface (US2) of the second insulating layer (112). And, the second-second via electrode (122c) may penetrate the second insulating layer (112). The second-second via electrode (122c) may penetrate the upper surface (US2) and the lower surface (BS2) of the second insulating layer (112).

[0095] In this specification, the via electrode may be located within a via hole formed in each insulating layer, etc. This corresponds to the via electrode penetrating each insulating layer, etc. This is described based on this.

[0096] Referring further to FIG. 4, in a circuit board (100) according to an embodiment, a capacitor structure (CAS) is disposed between a first insulating layer (111) and a second insulating layer (112), and a first via land (VL1) of the capacitor structure (CAS) may also be located between the first insulating layer (111) and the second insulating layer (112). For example, the first via land (VL1) may be located on the upper surface (US1) of the first insulating layer (111) or the lower surface (BS2) of the second insulating layer (112). That is, the first via land (VL1) may be located above the boundary between the first insulating layer (111) and the second insulating layer (112). Accordingly, the capacitor structure (CAS) may also be located above the boundary between the first insulating layer (111) and the second insulating layer (112). By this configuration, even if a via electrode is created for electrical connection with the first via land (VL1), it may not penetrate the boundary between the first insulating layer (111) and the second insulating layer (112). Accordingly, phenomena such as interface peeling between insulating layers can be prevented due to penetration of the boundary between adjacent insulating layers. In other words, a decrease in the reliability of the circuit board can be prevented.

[0097] Additionally, as an example, a dielectric layer (DL) within a capacitor structure (CAS) is positioned between a first via land (VL1) and a second via land (VL2), and may have a different area compared to the first via land (VL1) or the second via land (VL2).

[0098] For example, the area of ​​the dielectric layer (DL) may be different from the area of ​​the first via land (VL1). For example, the area of ​​the dielectric layer (DL) may be smaller than the area of ​​the first via land (VL1). Furthermore, the area of ​​the first via land (VL1) may be larger than the area of ​​the second via land (VL2).

[0099] Accordingly, the capacitance can be easily controlled by the capacitor structure (CAS) by simply controlling the area (or width) of the second via land (VL2) and the dielectric layer (DL).

[0100] And in the circuit board (100) according to the embodiment, the outer surface (ES1) of the dielectric layer (DL) may include an inwardly concave groove (GV). Due to the groove (GV) of the dielectric layer (DL), the area of ​​the dielectric layer (DL) may decrease and then increase along the stacking direction (Y-axis direction).

[0101] And, in the capacitor structure (CAS) of the circuit board (100), the outer surface or outer side (ES2) of the second via land (VL2) and the outer surface or side (OS1) of the dielectric layer (DL) may extend in different directions. For example, the first inclination angle of the outer surface (ES2) of the second via land (VL2) and the second inclination angle of the outer surface (ES1) of the dielectric layer (DL) may be different from each other. In an embodiment, the outer surface (ES1) of the dielectric layer (DL) may be convex toward the inside or center of the dielectric layer (DL). Alternatively, the outer surface (ES1) of the dielectric layer (DL) may be concave toward the outside or may have a concave recess / groove. Accordingly, the edge or outer side (ES1) of the dielectric layer (DL) having a high dielectric constant (High Dk) may have a shape that is concave inward. The groove (GV) (or recess) located on the side surface (ES1) of the dielectric layer (DL) may overlap with the second via land (VL2) in a vertical direction. In addition, the groove (GV) (or recess) located on the side surface (ES1) of the dielectric layer (DL) may overlap with the first via land (VL1) in a vertical direction. Furthermore, the outer surface (ES2) of the second via land (VL2) may be perpendicular to a plane (a plane perpendicular to the Y-axis direction). In addition, the outer surface (ES2) of the second via land (VL2) may be closer to being perpendicular to the plane than the groove (GV) located on the side surface (ES1) of the dielectric layer (DL).

[0102] And even if a groove is formed through some etching on the outer surface of the dielectric layer (DL), since the groove (GV) is located on the inner side of the outer surface of the second via land (VL2), a change in capacitance due to etching of the second via land (VL2) can be prevented. Accordingly, a change in capacitance due to etching, etc. is suppressed when forming the capacitor structure, and the circuit board can include a capacitor structure having a desired capacitance. Accordingly, a circuit board with improved signal integrity and improved reliability and power efficiency can be provided.

[0103] Referring further to FIGS. 5 and 6, the outer surfaces of each layer in the capacitor structure (CAS) may be spaced apart from each other in the stacking direction (Y-axis direction). Additionally, the outer surfaces of each layer may be spaced apart from each other in the horizontal direction (X-axis direction).

[0104] In an embodiment, the outer surface (ES1) of the dielectric layer (DL) may be located inside the outer surface (ES2) of the second via land (VL2). In other words, a distance from the center of the dielectric layer (DL) to the outer surface (ES1) of the dielectric layer (DL) may be smaller than a distance from the outer surface (ES2) of the second via land (VL2). In addition, the outer surface (ES2) of the second via land (VL2) may be located in an outer region of an edge (or an edge of a plane) of the dielectric layer (DL). In addition, the outer surface (ES1) of the dielectric layer (DL) may be spaced apart from the outer surface (ES2) of the second via land (VL2) by a predetermined distance (gap1, gap2).

[0105] Additionally, the outer surface (ES2) of the second via land (VL2) may be located on the inner side of the outer surface (ES3) of the first via land (VL1). In addition, the outer surface (ES2) of the second via land (VL2) and the outer surface (ES3) of the first via land (VL1) may be spaced apart from each other by a distance (gap3, gap4) in the horizontal direction (X-axis direction).

[0106] And, a predetermined separation distance (gap1, gap2) between the outer surface (ES1) of the dielectric layer (DL) and the outer surface (ES2) of the second via land (VL2) may be smaller than a separation distance (gap3, gap4) between the outer surface (ES2) of the second via land (VL2) and the outer surface (ES3) of the first via land (VL1). Accordingly, a capacitor structure having a desired capacitance can be easily manufactured by adjusting the area of ​​the second via land (VL2) based on the first via land (VL1). Accordingly, impedance matching within the circuit board (100) can be easily and more accurately performed.

[0107] Additionally, in the embodiment, the first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may have different areas for their upper and lower surfaces, respectively.

[0108] For example, the upper surface (S4) and the lower surface (S3) of the first via land (VL1) may be larger than the area of ​​the dielectric layer (DL) or the second via land (VL2). The upper surface (S4) of the first via land (VL1) may have a larger area than the lower surface (S2) of the dielectric layer (DL) that is in contact with the upper surface (S4).

[0109] And the upper surface (S1) and the lower surface (S2) of the dielectric layer (DL) may have different or identical areas. For example, the dielectric layer (DL) may include an intermediate surface (CH) having a minimum area in the stacking direction (Y-axis direction) between the upper surface (S1) and the lower surface (S2). The intermediate surface (CH) may be located at the center of the dielectric layer (DL) along the stacking direction (Y-axis direction) or at a side other than the center.

[0110] For example, the intermediate plane (CH) may be located at the center of the dielectric layer (DL) along the stacking direction (Y-axis direction). Accordingly, the length between the intermediate plane (CH) and the upper surface (S1) of the dielectric layer (DL) may be equal to the length between the intermediate plane (CH) and the lower surface (S2) of the dielectric layer (DL).

[0111] In addition, when the etching of the dielectric layer (DL) is performed isotropically, the intermediate plane (CH) may not be located at the center of the dielectric layer (DL). For example, the intermediate plane (CH) may be located adjacent to the upper surface (S1). In addition, the upper surface (S1) and the lower surface (S2) of the dielectric layer (DL) may have different areas. For example, the upper surface (S1) of the dielectric layer (DL) may have a smaller area than the lower surface (S2). In addition, the outer surface (IS1) of the dielectric layer (DL) may have a curved surface by having a groove (GV). In this way, by having the edge of the outer surface of the dielectric layer (DL) curved or having a curvature, the contact resistance may be reduced, thereby improving the capacitance performance.

[0112] In addition, as an example, the second via land (VL2) may have a different area from the dielectric layer in contact with the second via land (VL2). That is, the area of ​​the second via land (VL2) may be different from the area of ​​the dielectric layer (DL) under the second via land (VL2). The area of ​​the second via land (VL2) may be larger than the area of ​​the dielectric layer (DL). Furthermore, the area of ​​the lower surface (S5) of the second via land (VL2) may be larger than the area of ​​the upper surface (S1) of the dielectric layer (DL) in contact with the lower surface (S5). As a result, over-etching of the dielectric layer can be prevented.

[0113] Furthermore, the area of ​​the lower surface (S5) of the second via land (VL2) may be different from the area of ​​the lower surface (S2) of the dielectric layer (DL). For example, the area of ​​the lower surface (S5) of the second via land (VL2) may be larger than the area of ​​the lower surface (S2) of the dielectric layer (DL). Accordingly, the dielectric layer may be etched to an area less than or equal to the area of ​​the second via land, corresponding to the area of ​​the second via land.

[0114] In addition, in the embodiment, the distance between the outer surface (ES1) of the dielectric layer (DL) and the outer surface (ES2) of the second via land (VL2) may be maintained the same on a plane. For example, the distance to the outer surface (ES1) of the dielectric layer (DL) with respect to the center (on a plane perpendicular to the Y-axis) of the dielectric layer (DL) may be the same with respect to the axis. In addition, the distance to the outer surface (ES2) of the second via land (VL2) with respect to the center (on a plane perpendicular to the Y-axis) of the dielectric layer (DL) may also be the same. Accordingly, since the second via land (VL2) and the dielectric layer (DL) are arranged symmetrically with respect to the central axis, the capacitor structure may have a desired capacitance.

[0115] And the second-first via electrode (122a) and the second wiring portion (122b) may be positioned on the second via land (VL2). For example, the second via land (VL2) may overlap the second-first via electrode (122a) in the stacking direction (Y-axis direction). And the second via land (VL2) may have a larger area than the second-first via electrode (122a). The dielectric layer (DL) and the first via land (VL1) may overlap the second-first via electrode (122a) in the stacking direction (Y-axis direction). In addition, the dielectric layer (DL) and the first via land (VL1) may have a larger area than the second-first via electrode (122a).

[0116] And the 2-1 via electrode (122a) is placed on the upper part of the capacitor structure (CAS) and may not overlap with the capacitor structure (CAS) in the horizontal direction (X-axis direction).

[0117] The second-second via electrode (122c) may be horizontally spaced apart from the capacitor structure (CAS). And the second-second via electrode (122c) may overlap with the capacitor structure (CAS) in the horizontal direction (X-axis direction). And as described above, since the first via land (VL1) is positioned above the boundary surface between the first insulating layer (111) and the second insulating layer (112), the second-second via electrode (122c) may overlap with the first via land (VL1), the second via land (VL2), and the dielectric layer (DL) in the horizontal direction (X-axis direction). However, when the wiring portion or wiring electrode in contact with the 2-2 via electrode (122c) is placed on the upper surface (US1) of the first insulating layer (111), the 2-2 via electrode (122c) may overlap with the dielectric layer (DL) and the second via land (VL2) in the horizontal direction.

[0118] In addition, when the wiring portion in contact with the 2nd via electrode (122c) has a smaller thickness than the 1st via land (VL1), the 2nd via electrode (122c) may overlap a portion of the 1st via land (VL1) in the horizontal direction (X-axis direction).

[0119] Additionally, the outer surface (ES2) of the second via land (VL2) may be located on the inner side of the outer surface (ES3) of the first via land (VL1). In addition, the outer surface (ES2) of the second via land (VL2) and the outer surface (ES3) of the first via land (VL1) may be spaced apart from each other by a distance (gap3, gap4) in the horizontal direction (X-axis direction).

[0120] Referring to FIGS. 7 and 8, as another example, the outer surface (ES1) of the dielectric layer (DL) may be spaced apart from the outer surface (ES2) of the second via land (VL2) by a predetermined distance (gap1, gap2).

[0121] Additionally, the outer surface (ES2) of the second via land (VL2) may be located on the inner side of the outer surface (ES3) of the first via land (VL1). In addition, the outer surface (ES2) of the second via land (VL2) and the outer surface (ES3) of the first via land (VL1) may be spaced apart from each other in the horizontal direction (X-axis direction) by a distance (gap3, gap4).

[0122] However, the distance between the outer surface (ES1) of the dielectric layer (DL) and the outer surface (ES2) of the second via land (VL2) may be different from each other on a plane. For example, the distance (gap1') to the outer surface (ES1) of the dielectric layer (DL) on one side based on the center of the dielectric layer (DL) (on a plane perpendicular to the Y-axis) may be different from the distance (gap2') to the outer surface (ES) of the dielectric layer (DL) on the other side.

[0123] In addition, the distance from the center of the dielectric layer (DL) (on a plane perpendicular to the Y-axis) to the outer surface (ES2) of the second via land (VL2) may also be different. Accordingly, the second via land (VL2) and the dielectric layer (DL) may be arranged asymmetrically with respect to the central axis. For example, the distance (gap3') from the center of the dielectric layer (DL) to the outer surface (ES2) of the second via land (VL2) on one side may be different from the distance (gap4') from the outer surface (ES2) of the second via land (VL2) on the other side.

[0124] Referring further to FIG. 9, the circuit board may include a plurality of capacitor structures (CAS). For example, the circuit board may include a first capacitor structure (CAS1) and a second capacitor structure (CAS2). The first capacitor structure (CAS1) and the second capacitor structure (CAS2) may be spaced apart from each other in the horizontal direction (X-axis direction). Accordingly, the first via land, the dielectric layer, and the second via land of each capacitor structure may overlap each other in the horizontal direction (X-axis direction).

[0125] And, in each capacitor structure, the horizontal length of the groove located on the outer surface of the dielectric layer (DL) may be the same or different. For example, the horizontal length of the groove of the dielectric layer (DL) in the first capacitor structure (CAS1) may be the same or different from the horizontal length of the groove of the dielectric layer (DL) in the second capacitor structure (CAS2).

[0126] In addition, the distance between the upper surface of the dielectric layer (DL) and the outer surface of the second via land (VL2) in each capacitor structure may be different. For example, the distance between the upper surface (S1) of the dielectric layer (DL) and the outer surface of the second via land (VL2) in the first capacitor structure (CAS1) may be the same as or different from the distance between the upper surface (S1') of the dielectric layer (DL) and the outer surface of the second via land (VL2) in the second capacitor structure (CAS2). Accordingly, the manufacturing of a capacitor structure having a desired capacitance can be easily achieved.

[0127] FIGS. 10A to 10R are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0128] Referring to FIG. 10a, in an embodiment, a basic material for manufacturing a circuit board or a semiconductor package including the same can be prepared.

[0129] For example, in the embodiment, a carrier board (310) may be provided. The carrier board (310) may be a copper clad laminate (CCL). Accordingly, the carrier board (310) may include a carrier insulating layer (311) and a copper foil layer (312) disposed on both sides of the carrier insulating layer (311). The carrier insulating layer (311) may be made of PPG.

[0130] Additionally, an additional insulating layer (320) may be placed on both sides or one side of the carrier board (310). The structure in which each layer is placed on both sides will be described below.

[0131] In addition, a base dielectric layer (DLL), a first base layer (LL1), and a second base layer (LL2) for a capacitor layer, which will be described later, may be arranged on both sides or one side of the carrier board (310). The base dielectric layer (DLL) may correspond to the above-described dielectric layer. The first base layer (LL1) may correspond to the above-described first layer or the first via land. The second base layer (LL2) may correspond to the above-described second layer or the second via land.

[0132] And a separation layer (330) for separation may be arranged on the first base layer (LL1) and the second base layer (LL2). The separation layer (330) may be a copper foil. Accordingly, the bonding strength between the dielectric layer and the first base layer (LL1) and the second base layer (LL2) may be greater than the bonding strength between the dielectric layer and the separation layer (330).

[0133] Referring to FIG. 10b, a carrier board (310), an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a base dielectric layer (DLL), and a first base layer (LL1) can be laminated and pressed. At this time, pressing can be performed with the outermost separation layer (330) removed. Accordingly, an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a base dielectric layer (DLL), and a first base layer (LL1) can be sequentially laminated on both sides of the carrier board (310).

[0134] Referring to Fig. 10c, a mask (e.g., a dry film) may be formed on the first base layer (LL1). Furthermore, a first insulating layer (111) and a third insulating layer (113) may be laminated. After each insulating layer is laminated, etching, plating, etc. may be sequentially performed. In addition, an etching method such as a laser may be applied to form a via electrode, etc. For example, a via hole may be formed using a carbon dioxide (CO2) laser drill, etc.

[0135] Furthermore, a protective layer (SR1) etc. may be additionally formed, and mask formation, etching, etc. may be additionally performed on the protective layer.

[0136] Referring to FIG. 10d, the second base layer (LL2) and the layer above the second base layer (LL2) can be separated from the aforementioned carrier board (310) and additional insulating layer (320).

[0137] Additionally, a mask (350'') can be formed on the second base layer (LL2). The mask (350'') can form an open area through exposure and development, etc., i.e., patterning can be performed. The mask (350'') can be formed corresponding to the position of the desired dielectric layer and the second via electrode.

[0138] Referring to FIG. 10e, etching (e.g., flash etching) may be performed. That is, a portion of the second base layer (LL2) may be removed by etching. By this configuration, a second via land (VL2) may be formed.

[0139] Referring to FIG. 10f, the mask (350'') can be peeled off.

[0140] Referring to FIG. 10g, etching may be performed to form a desired dielectric layer. For example, plasma etching may be performed. By etching, a dielectric layer (DL) may be formed under the second via land (VL2).

[0141] Referring to FIG. 10h, a mask (350') may be formed on the first base layer (LL1). The mask (350') may cover the dielectric layer (DL) and the second via land (VL2). Accordingly, the mask (350') may prevent etching of the dielectric layer (DL) and the second via land (VL2). Accordingly, it is possible to suppress subsequent etching of the dielectric layer (DL) and the second via land (VL2) from changing the capacitance to a value other than the desired capacitance.

[0142] Referring to FIG. 10i, the mask (350') can be patterned into a desired shape by exposure and development, etc. The mask (350') can be positioned to correspond to a desired first via land. And a portion of the first base layer can be removed by etching. For example, a first via land (VL1) can be formed by flash etching. The first via land (VL1) can remain on the first insulating layer (111) under the mask (350').

[0143] Referring to FIG. 10j, the mask (350') can be removed. As described above, a capacitor structure (CAS) including a first via land (VL1), a dielectric layer (DL), and a second via land (VL2) can be formed.

[0144] Referring to FIG. 10k, a second insulating layer (112) may be laminated on a first insulating layer (111).

[0145] And a plating layer (EE) can be formed on the second insulating layer (112).

[0146] Referring to FIG. 10l, a via (V3) may be formed in the second insulating layer (112). The via (V3) may correspond to a second via electrode. For example, the via (V3) may expose the upper surface of the capacitor structure (CAS). Accordingly, the via (V3) may correspond to the second-first via electrode. In addition, a portion of the plating layer (EE) may be removed by the via (V3).

[0147] Furthermore, as described above, a via corresponding to the second-second via electrode may be formed. The upper surface of the first insulating layer (111) may be exposed by the via.

[0148] Referring to FIG. 10m, a mask (350) may be formed on a partially removed plating layer (EE'). The mask (350) may be patterned by exposure or the like. The mask (350) may be a dry film or the like. In addition, the mask (350) may be positioned in an area excluding the second wiring portion.

[0149] Referring to FIG. 10n, plating may be performed in an area opened by a mask (350). For example, electroplating may be performed to form a wiring electrode (122') connected by a plating layer (EE').

[0150] Referring to FIG. 10o, etching can be performed corresponding to the mask. Accordingly, the connected wiring electrode (122') can be separated.

[0151] Referring to FIG. 10p, a second electrode portion (122) can be formed by the aforementioned etching. In particular, a second wiring portion can be formed.

[0152] Referring to FIG. 10q, a second protective layer (SR2') may be laminated on the first insulating layer. The protective layer (SR2`) may be formed on the second electrode portion (122).

[0153] Referring to FIG. 10r, an opening area may be formed in the protective layer (SR2) for electrical connection with a chip or substrate, etc. Additionally, a bump portion or a metal layer may be further formed in the opening area of ​​the protective layer (SR2).

[0154] Fig. 11 is a cross-sectional view of a circuit board according to a second embodiment, Fig. 12 is an enlarged view of K3 in Fig. 11, Fig. 13 is a plan view of a capacitor structure in a circuit board according to the second embodiment, and Fig. 14 is a view taken along line MM' in Fig. 13.

[0155] Referring to FIGS. 11 to 14, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100A) may also include a protective layer (SR) disposed on the electrode portion (120). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0156] In the capacitor structure (CAS) according to the present example, the areas of each layer may be different from each other. For example, the area of ​​the second via land (VL2) may be smaller than the area of ​​the dielectric layer (DL). Additionally, the area of ​​the first via land (VL1) may be larger than the area of ​​the dielectric layer (DL) or the area of ​​the second via land (VL2). In this way, in the capacitor structure (CAS), the area of ​​the second via land (VL2) may be smaller than that of the other layers, and the area of ​​the first via land (VL1) may be larger than that of the other layers.

[0157] Furthermore, the outer surface (ES1) of the dielectric layer (DL) may include a groove (GV). And the groove (GV) located on the outer surface (ES1) of the dielectric layer (DL) may not overlap with the second via land (VL2) in the vertical direction (Y-axis direction). Furthermore, the groove (GV) of the dielectric layer (DL) may be spaced apart from the second via land (VL2) in the horizontal direction (X-axis direction).

[0158] Accordingly, the upper surface of the dielectric layer (DL) can be exposed in an area misaligned in the vertical direction (Y-axis direction) with respect to the second via land (VL2).

[0159] Furthermore, the upper surface of the dielectric layer (DL) may have a step structure. For example, a land groove (GV1) may be formed on the upper surface of the dielectric layer (DL). That is, the dielectric layer (DL) may include the land groove (GV1). The land groove (GV1) may be a groove having a convex structure directed downward from the upper surface of the dielectric layer (DL). This land groove (GV1) may overlap at least partially with the groove (GV) of the outer surface (ES1) in the lamination direction. That is, the upper surface of the exposed dielectric layer (DL) and the outer surface (ES1) of the dielectric layer (DL) may be positioned adjacent to each other. In addition, this land groove (GV1) may be spaced apart from the outer surface (ES2) of the second via land (VL2) in the horizontal direction (X-axis direction). Additionally, the home (GV) can also be spaced horizontally (X-axis direction) from the outer surface (ES2) of the second via land (VL2).

[0160] And the outer surface (ES2) of the second via land (VL2) may be perpendicular to the plane (plane perpendicular to the Y-axis direction). In addition, the outer surface (ES2) of the second via land (VL2) may be closer to the vertical than the groove (GV) located on the side surface (ES1) of the dielectric layer (DL) with respect to the plane. And the outer surface (ES1) of the dielectric layer (DL) may have a predetermined inclination angle with respect to the plane (plane perpendicular to the Y-axis direction). For example, the inclination angle between the outer surface (ES1) of the dielectric layer (DL) and the plane may be smaller than the inclination angle formed by the outer surface (ES2) of the second via land (VL2) and the plane. For example, the inclination angle formed by the outer surface (ES2) of the second via land (VL2) and the plane may be vertical. And the inclination angle formed by the outer surface (ES2) of the second via land (VL2) and the plane may be smaller than 90 degrees. there is.

[0161] By this configuration, when the area of ​​the dielectric layer (DL) is larger than the second via land (VL2), etching can be performed only on the outer surface and a part of the upper surface of the dielectric layer (DL). That is, in the formation of the dielectric layer (DL), etching can be performed on the outer surface and the upper surface of the dielectric layer (DL) without etching the second via land (VL2). Accordingly, except for the formation of the second via land (VL2), a reduction in the area of ​​the second via land (VL2) may not occur due to the etching of other layers. That is, the second via land (VL2) can have a designed area. Accordingly, the capacitance of the capacitor structure (CAS) can also form a designed value. Accordingly, the capacitor structure within the circuit board can perform an accurate electrical function.

[0162] In addition, in this example, the outer surface (ES1) of the dielectric layer (DL) may be located outside the outer surface (ES2) of the second via land (VL2). In other words, the distance between the center of the dielectric layer (DL) and the outer surface (ES1) of the dielectric layer (DL) may be greater than the distance between the center of the dielectric layer (DL) and the outer surface (ES2) of the second via land (VL2). In addition, the outer surface (ES2) of the second via land (VL2) may be located in an inner region of an edge (or an edge of a plane) of the dielectric layer (DL). In addition, the outer surface (ES1) of the dielectric layer (DL) may be spaced apart from the outer surface (ES2) of the second via land (VL2) by a predetermined distance (gap1, gap2).

[0163] Additionally, the outer surface (ES2) of the second via land (VL2) may be located on the inner side of the outer surface (ES3) of the first via land (VL1). In addition, the outer surface (ES2) of the second via land (VL2) and the outer surface (ES3) of the first via land (VL1) may be spaced apart from each other by a distance (gap3, gap4) in the horizontal direction (X-axis direction).

[0164] In this way, in the embodiment, the outer surface (ES1) of the dielectric layer (DL) may be located between the outer surface (ES3) of the first via land (VL1) and the outer surface (ES2) of the second via land (VL2).

[0165] Additionally, in the embodiment, the first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may have different areas for their upper and lower surfaces, respectively.

[0166] Figures 15a to 15r are drawings explaining a method for manufacturing a circuit board according to a second embodiment.

[0167] Referring to FIG. 15a, in an embodiment, a basic material for manufacturing a circuit board or a semiconductor package including the same can be prepared.

[0168] For example, in the embodiment, a carrier board (310) may be provided. The carrier board (310) may be a copper clad laminate (CCL). Accordingly, the carrier board (310) may include a carrier insulating layer (311) and a copper foil layer (312) disposed on both sides of the carrier insulating layer (311). The carrier insulating layer (311) may be made of PPG.

[0169] Additionally, an additional insulating layer (320) may be placed on both sides or one side of the carrier board (310). The structure in which each layer is placed on both sides will be described below.

[0170] In addition, a base dielectric layer (DLL), a first base layer (LL1), and a second base layer (LL2) for a capacitor layer, which will be described later, may be arranged on both sides or one side of the carrier board (310). The base dielectric layer (DLL) may correspond to the above-described dielectric layer. The first base layer (LL1) may correspond to the above-described first layer or the first via land. The second base layer (LL2) may correspond to the above-described second layer or the second via land.

[0171] And a separation layer (330) for separation may be arranged on the first base layer (LL1) and the second base layer (LL2). The separation layer (330) may be a copper foil. Accordingly, the bonding strength between the dielectric layer and the first base layer (LL1) and the second base layer (LL2) may be greater than the bonding strength between the dielectric layer and the separation layer (330).

[0172] Referring to FIG. 15b, a carrier board (310), an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a base dielectric layer (DLL), and a first base layer (LL1) can be laminated and pressed. At this time, pressing can be performed with the outermost separation layer (330) removed. Accordingly, an additional insulating layer (320), a separation layer (330), a second base layer (LL2), a base dielectric layer (DLL), and a first base layer (LL1) can be sequentially laminated on both sides of the carrier board (310).

[0173] Referring to Fig. 15c, a mask (e.g., a dry film) may be formed on the first base layer (LL1). Furthermore, a first insulating layer (111) and a third insulating layer (113) may be laminated. After each insulating layer is laminated, etching, plating, etc. may be sequentially performed. In addition, an etching method such as a laser may be applied to form a via electrode, etc. For example, a via hole may be formed using a carbon dioxide (CO2) laser drill, etc.

[0174] Furthermore, a protective layer (SR1) etc. may be additionally formed, and mask formation, etching, etc. may be additionally performed on the protective layer.

[0175] Referring to FIG. 15d, the second base layer (LL2) and the layer above the second base layer (LL2) can be separated from the aforementioned carrier board (310) and additional insulating layer (320).

[0176] Additionally, a mask (350'') can be formed on the second base layer (LL2). The mask (350'') can form an open area through exposure and development, etc., i.e., patterning can be performed. The mask (350'') can be formed corresponding to the position of the desired dielectric layer and the second via electrode.

[0177] Referring to FIG. 15e, etching (e.g., flash etching) may be performed. That is, a portion of the second base layer (LL2) may be removed by etching. By this configuration, a second via land (VL2) may be formed.

[0178] Referring to FIG. 15f, the mask (350'') can be peeled off.

[0179] Referring to FIG. 15g, etching may be performed to form a desired dielectric layer. For example, plasma etching may be performed. By etching, a dielectric layer (DL) may be formed under the second via land (VL2).

[0180] Referring to FIGS. 10h15h, a mask (350') may be formed on the first base layer (LL1). The mask (350') may be disposed on the second via land (VL2). The mask (350') may prevent etching of a portion of the second via land (VL2). The mask (350') may also overlap with the underlying dielectric layer (DL) in the stacking direction. The area of ​​the mask (350') may be smaller than the areas of the second via land (VL2) and the dielectric layer (DL). Accordingly, etching suppression of the second via land (VL2) may be implemented by subsequent etching. In addition, even if a portion of the dielectric layer (DL) is etched, the etching of the second via land (VL2) is suppressed by the mask (350'), thereby suppressing the capacitor structure described below from changing to a value other than a desired capacitance.

[0181] Referring to FIG. 15i, the mask (350') can be patterned into a desired shape by exposure and development, etc. The mask (350') can be positioned to correspond to a desired first via land. And a portion of the first base layer can be removed by etching. For example, a first via land (VL1) can be formed by flash etching. The first via land (VL1) can remain on the first insulating layer (111) under the mask (350').

[0182] Referring to FIG. 15j, the mask (350') can be removed. As described above, a capacitor structure (CAS) including a first via land (VL1), a dielectric layer (DL), and a second via land (VL2) can be formed.

[0183] Referring to FIG. 15k, a second insulating layer (112) can be laminated on a first insulating layer (111).

[0184] And a plating layer (EE) can be formed on the second insulating layer (112).

[0185] Referring to FIG. 15l, a via (V3) may be formed in the second insulating layer (112). The via (V3) may correspond to a second via electrode. For example, the via (V3) may expose the upper surface of the capacitor structure (CAS). Accordingly, the via (V3) may correspond to the second-first via electrode. In addition, a portion of the plating layer (EE) may be removed by the via (V3).

[0186] Furthermore, as described above, a via corresponding to the second-second via electrode may be formed. The upper surface of the first insulating layer (111) may be exposed by the via.

[0187] Referring to FIG. 15m, a mask (350) may be formed on a partially removed plating layer (EE'). The mask (350) may be patterned by exposure or the like. The mask (350) may be a dry film or the like. In addition, the mask (350) may be positioned in an area excluding the second wiring portion.

[0188] Referring to FIG. 15n, plating may be performed in an area opened by a mask (350). For example, electroplating may be performed to form a wiring electrode (122') connected by a plating layer (EE').

[0189] Referring to FIG. 15o, etching can be performed corresponding to the mask. Accordingly, the connected wiring electrode (122') can be separated.

[0190] Referring to FIG. 15p, a second electrode portion (122) can be formed by the aforementioned etching. In particular, a second wiring portion can be formed.

[0191] Referring to FIG. 15q, a second protective layer (SR2') may be laminated on the first insulating layer. The protective layer (SR2) may be formed on the second electrode portion (122).

[0192] Referring to FIG. 15r, an opening area may be formed in the protective layer (SR2) for electrical connection with a chip or substrate, etc. Additionally, a bump portion or a metal layer may be further formed in the opening area of ​​the protective layer (SR2).

[0193] Fig. 16 is a cross-sectional view of a circuit board according to a third embodiment, Fig. 17 is an enlarged view of K4 in Fig. 16, Fig. 18 is a plan view of a capacitor structure in a circuit board according to the third embodiment, and Fig. 19 is a view taken along line NN' of Fig. 18.

[0194] Referring to FIGS. 16 to 19, a circuit board (100B) according to a third embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100B) may also include a protective layer (SR) disposed on the electrode portion (120). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0195] In a capacitor structure (CAS), the outer surfaces of each layer may be spaced apart from each other in the stacking direction (Y-axis direction). Additionally, the outer surfaces of each layer may be spaced apart from each other in the horizontal direction (X-axis direction).

[0196] In an embodiment, the outer surface (ES1) of the dielectric layer (DL) may be located inward relative to the outer surface (ES2) of the second via land (VL2). In other words, a distance relative to the center of the dielectric layer (DL) with respect to the outer surface (ES1) of the dielectric layer (DL) may be smaller than a distance relative to the outer surface (ES2) of the second via land (VL2). In addition, the outer surface (ES2) of the second via land (VL2) may be located in an outer region of an edge (or an edge of a plane) of the dielectric layer (DL).

[0197] Additionally, the outer surface (ES2) of the second via land (VL2) may be located on the inner side of the outer surface (ES3) of the first via land (VL1).

[0198] And the above-mentioned contents can be applied to each separation distance, etc.

[0199] Additionally, in this example, the first via land (VL1) may be located below the boundary surface of the first insulating layer (111) and the second insulating layer (112). That is, the first via land (VL1) may be located below the upper surface (US1) of the first insulating layer (111) or the lower surface (BS2) of the second insulating layer (112).

[0200] Accordingly, in the capacitor structure (CAS), the first via land (VL1) may overlap with the first insulating layer (111) in the horizontal direction. In the capacitor structure (CAS), the first via land (VL1) may not overlap with the second insulating layer (112) in the horizontal direction but may be misaligned. In addition, the first via electrode penetrating the first insulating layer (111) and the first via land (VL1) may overlap in the horizontal direction (X-axis direction).

[0201] And in the capacitor structure (CAS), the dielectric layer (DL) and the second via land (VL2) may overlap with the second insulating layer (112) in the horizontal direction (X-axis direction). In the capacitor structure (CAS), the dielectric layer (DL) and the second via land (VL2) may not overlap with the first insulating layer (111) in the horizontal direction but may be misaligned.

[0202] By this configuration, miniaturization of the circuit board can be realized even if the capacitor structure (CAS) is embedded within the circuit board.

[0203] FIGS. 20A to 20Y are drawings explaining a method for manufacturing a circuit board according to a third embodiment.

[0204] Referring to FIG. 20a, in an embodiment, a basic material for manufacturing a circuit board or a semiconductor package including the same can be prepared.

[0205] For example, in the embodiment, a carrier board (310) may be provided. The carrier board (310) may be a copper clad laminate (CCL). Accordingly, the carrier board (310) may include a carrier insulating layer (311) and a copper foil layer (312) disposed on both sides of the carrier insulating layer (311). The carrier insulating layer (311) may be made of PPG.

[0206] Additionally, an additional insulating layer (320) may be placed on both sides or one side of the carrier board (310). The structure in which each layer is placed on both sides will be described below.

[0207] In addition, a base dielectric layer (DLL), a first base layer (LL1), and a second base layer (LL2) for a capacitor layer, which will be described later, may be arranged on both sides or one side of the carrier board (310). The base dielectric layer (DLL) may correspond to the above-described dielectric layer. The first base layer (LL1) may correspond to the above-described first layer or the first via land. The second base layer (LL2) may correspond to the above-described second layer or the second via land.

[0208] And a separation layer (330) for separation may be arranged on the first base layer (LL1) and the second base layer (LL2). The separation layer (330) may be a copper foil. Accordingly, the bonding strength between the dielectric layer and the first base layer (LL1) and the second base layer (LL2) may be greater than the bonding strength between the dielectric layer and the separation layer (330).

[0209] Referring to Fig. 20b, a carrier board, an additional insulating layer, a separation layer, a second base layer (LL2), a dielectric layer, and a first base layer () can be laminated and pressed. At this time, the pressing can be performed with the outermost separation layer removed. The above-described content can be applied to this, and the underlying structure is omitted and described below.

[0210] Referring to FIG. 20c, a mask (350a) can be formed on the first base layer (LL1). For example, the mask (350a) may be a dry film. Then, exposure and development, etc., can be performed on the mask (350a).

[0211] Exposure and development of the mask (350a) may form an open area in the mask (350) on the first base layer (LL1). In other words, patterning of the dry film may be performed. The mask (350) may be positioned in an area other than a location where the first via land is formed. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure or the like. This mask formation may be applied to other mask formations in the same manner.

[0212] Referring to FIG. 20d, etching (e.g., flash etching) may be performed. As a result, a first via land (VL1) may be formed.

[0213] Referring to FIGS. 20E and 20F, the mask (350a) can be removed. Then, a first insulating layer (111) can be formed on the first via land (VL1). A plating layer (EE1) can be formed on the first insulating layer (111).

[0214] And a via (V1) can be formed in the first insulating layer (111) by etching or the like. That is, a via (V1) in which a first via electrode is provided can be formed. In addition, a first via land (VL1) can be exposed by the via (V1). In addition to the via (V1), various vias penetrating at least one insulating layer can be formed. This can be equally applied to other embodiments and when forming vias. And the vias can be formed by various methods. For example, via formation can be performed by a laser.

[0215] Referring to FIG. 20g, a plating layer (EE2) may be formed on the via (V1) and the first insulating layer (111). The plating layer (EE2) may be formed by various plating methods.

[0216] Referring to FIG. 20h, a mask (350a') may be formed on the plating layer (EE2). The mask (350a') may be patterned as described above. In addition, the mask (350a') may be positioned in an area other than the first electrode portion.

[0217] Referring to FIG. 20i, a plating process can be performed on an open area of ​​a patterned mask (350a'). Then, a plating layer (EE3) connected by plating can be formed.

[0218] Referring to FIGS. 20j and 20k, the mask (350a') can be removed, and etching can be performed corresponding to the first electrode portion. Thus, the first electrode portion (121) can be formed.

[0219] Referring to FIGS. 20l and 20m, pressing can be performed on each layer as described above, and the second base layer (LL2) and the arranged layer on top of the second base layer (LL2) can be separated from the carrier board and the additional insulating layer.

[0220] Referring to FIG. 20n, a mask (350b) may be formed on the second base layer (LL2). The mask (350b) may form an open area through exposure and development, etc., i.e., patterning may be performed. The mask (350b) may be formed corresponding to the position of a desired dielectric layer and a second via electrode. Furthermore, a protective layer or the like may be additionally formed, and mask formation, etching, etc. may be additionally performed on the protective layer.

[0221] Referring to FIGS. 20o and 20p, etching (e.g., flash etching) may be performed. That is, a portion of the base dielectric layer (DLL) may be removed by etching. Thus, a dielectric layer (DL) of the capacitor structure may be formed. Then, the mask (350b) may be removed.

[0222] Referring to FIG. 20q, a second insulating layer (112) may be laminated on a first insulating layer (111). And a plating layer (EE) may be formed on the second insulating layer (112).

[0223] Referring to FIG. 20r, a via (V3) may be formed in the second insulating layer (112). The via (V3) may correspond to a second via electrode. For example, the via (V3) may expose the upper surface of the capacitor structure (CAS). Accordingly, the via (V3) may correspond to the second-first via electrode. In addition, a portion of the plating layer (EE) may be removed by the via (V3).

[0224] Furthermore, as described above, a via corresponding to the second-second via electrode may be formed. The upper surface of the first insulating layer (111) may be exposed by the via.

[0225] Referring to FIGS. 20s and 20t, plating may be performed on the plating layer (EE'). A mask (350c) may be formed on the plating layer (EE''). The mask (350c) may be patterned by exposure or the like. The mask (350c) may be a dry film or the like. The mask (350c) may be positioned in an area excluding the second wiring portion.

[0226] Referring to FIG. 20u, plating may be performed in an area opened by a mask (350c). For example, electroplating may be performed to form a wiring electrode (122') connected by a plating layer (EE'').

[0227] Referring to FIG. 20v, the mask can be removed and etching can be performed corresponding to the position of the mask. Accordingly, the connected wiring electrode (122') can be separated.

[0228] Referring to FIG. 20w, a second electrode portion (122) can be formed by the aforementioned etching. In particular, a second wiring portion can be formed.

[0229] Referring to FIG. 20x, a second protective layer (SR2') may be laminated on the first insulating layer. The protective layer (SR2`) may be formed on the second electrode portion (122).

[0230] Referring to FIG. 20y, an opening area may be formed in the protective layer (SR2) for electrical connection with a chip or substrate, etc. Additionally, a bump portion or a metal layer may be further formed in the opening area of ​​the protective layer (SR2).

[0231] Furthermore, the circuit board according to the embodiment can be divided into a package substrate and an interposer corresponding to the lower substrate according to the function of the circuit board, and applied thereto. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the area of ​​the circuit board increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of a circuit board with a high number of laminated layers, the yield of the circuit board can be improved by separating it into an interposer and a package substrate. In addition, as the density of terminals of semiconductor devices increases, it may be difficult to implement pads of the package substrate having an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0232] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0233] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0234] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying power to semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0235] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0236] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0237] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A second insulating layer disposed on the first insulating layer; A first via land disposed between the first insulating layer and the second insulating layer; and A capacitor structure including the first via land, the dielectric layer, and the second via land sequentially stacked on the first insulating layer; The area on the lower surface of the second via land is different from the area on the upper surface of the dielectric layer in contact with the second via land, A circuit board having an outer surface of the dielectric layer including an inwardly concave groove.

2. In paragraph 1, A circuit board in which the area on the upper surface of the first via land is larger than the area on the lower surface of the dielectric layer.

3. In paragraph 1, A circuit board in which the area on the lower surface of the second via land is larger than the area on the upper surface of the dielectric layer.

4. In paragraph 1, A circuit board in which the area on the lower surface of the second via land is larger than the area on the lower surface of the dielectric layer.

5. In paragraph 1, A circuit board in which the dielectric layer includes an intermediate surface having a minimum area in the stacking direction between the upper surface and the lower surface.

6. In paragraph 5, A circuit board in which the length between the intermediate surface and the upper surface in the dielectric layer is the same as the length between the intermediate surface and the lower surface.

7. In paragraph 1, A circuit board in which the outer surface of the second via land is located in the outer region of the edge of the dielectric layer.

8. In paragraph 1, A circuit board in which the first via land is located above the boundary between the first insulating layer and the second insulating layer.

9. In paragraph 1, A circuit board in which the area of ​​the second via land is smaller than the area of ​​the dielectric layer.

10. In paragraph 9, A circuit board having a stepped structure on the upper surface of the dielectric layer.

Images