Circuit board and semiconductor package comprising same

Abstract

One embodiment of the present invention discloses a circuit board comprising: a glass core layer; an insulating substrate spaced apart from the glass core layer and comprising a hole for receiving the glass core layer therein; and a build-up insulating portion comprising an upper build-up layer and a lower build-up layer disposed on the glass core layer and the insulating substrate, wherein the build-up insulating portion comprises a connection build-up layer disposed between the outermost surface of the glass core layer and the inner surface of the hole of the insulating substrate, and connected to the upper build-up layer and the lower build-up layer.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package containing a processor chip and a memory package containing memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing chip mounting area and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing need for separate processor chips for each function, and for circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, as circuit boards become increasingly thinner, deformations such as warping and twisting that occur during circuit board manufacturing are increasing. To prevent this, a glass core structure, in which a glass plate is formed in the core portion of the circuit board, has been proposed.

[0007] However, the reliability of these glass substrates is weak, and when manufacturing individual circuit boards from panels into units, the glass substrates are prone to breakage, further weakening the reliability of the circuit boards. Furthermore, manufacturing individual glass units presents challenges, such as additional damage to components due to cutting and other factors, as well as separation between the insulating layer and the glass plates.

[0008] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, which suppresses a breakage phenomenon occurring on the outermost surface of the glass core layer during a cutting process by arranging a separate insulating substrate on the outer side of the glass core layer, and which has improved reliability and suppresses crack occurrence and crack propagation through a build-up insulating portion covering the glass core layer.

[0009] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by controlling the width of the insulating substrate arranged on the outside of the glass core layer and the width between the outermost surface of the glass core layer and the inner surface of the insulating substrate, thereby suppressing warpage.

[0010] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by increasing the bonding area with the build-up insulation portion by forming a step structure on the glass core layer and the insulation substrate.

[0011] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which have reduced electrical resistance and delay rate and improved mechanical strength, by placing a build-up insulation between a glass core layer and an insulating substrate.

[0012] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which warpage is suppressed through a glass core layer having high rigidity and a small coefficient of thermal expansion.

[0013] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0014] A circuit board according to an embodiment of the present invention includes a glass core layer; an insulating substrate spaced apart from the glass core layer and including a hole for accommodating the glass core layer; and a spaced apart space between the glass core layer and the insulating substrate and a build-up insulating portion disposed on the glass core layer and the insulating substrate.

[0015] The outermost surface of the above glass core layer may be spaced apart from the inner surface of the above insulating substrate.

[0016] The above-mentioned build-up insulation portion can be in contact with the upper surface, lower surface, and inner surface of the above-mentioned insulating substrate.

[0017] The above-mentioned build-up insulation can be in contact with the upper surface, lower surface and outer surface of the glass core layer.

[0018] The outermost surface of the glass core layer may include a first outer surface and a second outer surface spaced apart from the first outer surface.

[0019] The first distance may be different from the second distance, and the first distance may be a separation distance between the first outer surface and the first inner surface of the insulating substrate facing the first outer surface, and the second distance may be a separation distance between the second outer surface and the second inner surface of the insulating substrate facing the second outer surface.

[0020] In the insulating substrate, the thickness in the horizontal direction in the region facing the first outer surface may be different from the thickness in the horizontal direction in the region facing the second outer surface.

[0021] The above-mentioned build-up insulation includes a connecting build-up layer positioned between the inner surface of the insulating substrate and the outermost surface of the glass core layer; and the connecting build-up layer may have a closed-loop structure on the outer side of the glass core layer.

[0022] The horizontal length of the insulating substrate may be less than the horizontal length of the connecting build-up layer.

[0023] It may further include a dummy electrode disposed on the upper surface of the insulating substrate.

[0024] The glass core layer may include a first lower region; and a first upper region having a larger area than the first lower region and disposed on the first lower region.

[0025] The first lower region may include a first surface which is an outer surface; the first upper region may include a second surface which does not overlap with the first lower region; and a third surface which is an outer surface.

[0026] The third side may be positioned outside the first side.

[0027] The second side can be in contact with the first side and the third side.

[0028] The insulating substrate may include a second upper region; and a second lower region having a larger area than the second upper region and positioned below the second upper region.

[0029] The first upper region may at least partially overlap the second lower region in the vertical direction.

[0030] It may further include a bonding member disposed between the first upper region and the second lower region.

[0031] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which a breakage phenomenon occurring on the outermost surface of the glass core layer during a cutting process is suppressed by placing a separate insulating substrate on the outer side of the glass core layer, and a build-up insulating portion covering the glass core layer is used to improve reliability and suppress crack occurrence and crack propagation.

[0032] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by controlling the width of the insulating substrate arranged on the outside of the glass core layer and the width between the outermost surface of the glass core layer and the inner surface of the insulating substrate, thereby suppressing warpage.

[0033] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by increasing the bonding area with the build-up insulation part by forming a step structure on the glass core layer and the insulation substrate.

[0034] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with reduced electrical resistance and delay rate and improved mechanical strength by placing a build-up insulation between a glass core layer and an insulating substrate.

[0035] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which warpage is suppressed through a glass core layer having high rigidity and a small coefficient of thermal expansion.

[0036] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0037] Figure 1 is a plan view of a circuit board according to a first embodiment of the present invention.

[0038] Figure 2 is a drawing taken along line AA' in Figure 1,

[0039] Figure 3 is an enlarged view of part K1 in Figure 2,

[0040] Figure 4 is an enlarged view of part K2 in Figure 1,

[0041] Figures 5 to 14 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0042] Fig. 15 is a cross-sectional view of a circuit board according to the second embodiment,

[0043] Figure 16 is an enlarged view of part K3 in Figure 15,

[0044] Figures 17 to 19 are drawings explaining a method for manufacturing a circuit board according to the second embodiment.

[0045] Fig. 20 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0046] Fig. 21 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0047] Fig. 22 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0048] Fig. 23 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0049] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0050] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0051] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0052] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0053] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0054] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0055] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0056] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0057] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0058] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0059] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0060] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0061] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0062] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0063] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0064] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0065] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0066] The semiconductor device may include active components and / or passive components.

[0067] Additionally, the memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0068] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0069] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0070] FIG. 1 is a plan view of a circuit board according to a first embodiment of the present invention, FIG. 2 is a view taken along line AA' in FIG. 1, FIG. 3 is an enlarged view of a portion K1 in FIG. 2, and FIG. 4 is an enlarged view of a portion K2 in FIG. 1.

[0071] Referring to FIGS. 1 and 2, a circuit board (100) according to the first embodiment may include an insulating portion (110) and an electrode portion (120). In the embodiment, the insulating portion (110) may be provided in a structure in which a plurality of build-up insulating portions are laminated. The electrode portion (120) may be disposed by being embedded in each build-up insulating portion of the plurality of insulating portions (110), thereby performing a function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0072] In addition, the circuit board (100) may include a protective layer (SR) and a build-up structure. The build-up structure may include a build-up insulating portion and a build-up wiring portion. In addition, the build-up structure may include a core portion including a glass core layer (111) and a core electrode portion (121). In this case, the build-up insulating portion may be formed of a plurality of build-up layers. For example, when the circuit board includes a core layer, the build-up insulating portion may include a first build-up insulating portion (112), a second build-up insulating portion (113), and a connection build-up layer (PA), as in the embodiment. Specifically, in the embodiment, the circuit board may include a first build-up insulating portion (112) disposed on an upper surface of the core layer and a second build-up insulating portion (113) disposed on a lower surface of the core layer. In addition, the connection build-up layer (PA) may be located between the glass core layer (111) and the insulation substrate (DS).

[0073] And as illustrated, the circuit board (100) according to the embodiment may include a glass core layer (111), a build-up insulating portion (112, 113, PA), a core electrode portion (121), a build-up electrode portion (122, 123), and an insulating substrate (DS). Furthermore, the circuit board (100) may further include a protective layer (SR) disposed on the upper surface of the first build-up insulating portion and / or the lower surface of the second build-up insulating portion. In addition, in the following embodiments of the present invention, the upper portion and / or the build-up insulating portion (112, 113) may include a plurality of build-up insulating portions stacked along the vertical direction (Y-axis direction). In the embodiment, the horizontal direction may be the first direction or the X-axis direction, and the vertical direction (or stacking direction) may be the second direction or the Y-axis direction. The horizontal direction and the vertical direction may be perpendicular to each other. The build-up electrode portions (122, 123) are disposed in a manner embedded in each layer (e.g., build-up insulation portion) of the build-up insulation portions (112, 113, PA), thereby transmitting signals and / or power from a main board (not shown) to semiconductor elements. The build-up electrode portions (122, 123) may include a circuit layer and a via electrode. The circuit layer is disposed on one surface of each of a plurality of build-up insulation portions included in the upper and / or second build-up insulation portions, thereby transmitting signals and / or power, and the via electrode may penetrate at least a portion of each of the plurality of build-up insulation portions to electrically connect each circuit layer. In addition, the circuit layer may include a bump portion (BP) disposed on the build-up insulation portion, thereby electrically connecting the semiconductor element and / or the electronic element with the circuit board.

[0074] The insulating substrate (DS) may include a hole therein. The insulating substrate (DS) may have a glass core layer (111) positioned in the hole. Accordingly, the insulating substrate (DS) may overlap the glass core layer (111) in a horizontal direction (X-axis direction). In addition, the insulating substrate (DS) may surround the glass core layer (111). Furthermore, the insulating substrate (DS) may have a closed-loop structure in a plane perpendicular to the lamination direction (Y-axis direction). Accordingly, the insulating substrate (DS) may be separated from the glass core layer (111) without being in contact with it.

[0075] The insulating portion (110) of the circuit board or each build-up insulating portion constituting the insulating portion (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating portion (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating portion (110) of the circuit board may include sapphire. For example, the insulating portion (110) of the circuit board may include an optically isotropic film. For example, the insulating portion (110) of the circuit board may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA). For example, the insulating portion (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating portion (110) of the circuit board may have a structure in which a filler such as silica or alumina is arranged in a thermosetting resin or a thermoplastic resin. The insulating portion (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0076] In one embodiment, the insulation (110) may include a glass core layer (111) including a reinforcing member.

[0077] The glass core layer (111) may be formed of a glass material. For example, the glass core layer (111) may include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., but is not limited to silicon-based glass compositions, and alternative glass materials such as fluorine glass, phosphate glass, chalcogen glass, etc. may also be used. In addition, the glass core layer (111) may further include other additives to form a glass having specific physical properties. These additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these and other elements. In addition, the glass core layer (111) may include an insulating material.

[0078] The glass core layer (111) can suppress warpage that occurs due to thinning of the circuit board. In other words, warpage can be reduced by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the glass core layer (111) can have high rigidity and a low coefficient of thermal expansion compared to other build-up insulating parts or protective layers.

[0079] And the first build-up insulating part (112) or the second build-up insulating part (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin can be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and can include an inorganic filler such as silica. When the insulating resin is used as a core, it can include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating portion (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating portion (110) can be provided by laminating ABF without a core layer.

[0080] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0081] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the build-up insulation portion. Hereinafter, the wiring portion will be described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the build-up insulation portion. Accordingly, in the embodiment, the electrode portion (120) will be described below as including a wiring portion (circuit pattern) and a via electrode in each build-up insulation portion. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from semiconductor elements, and may be arranged in each build-up insulation portion of the stacked build-up insulation portions (112, 113, PA).

[0082] In the electrode section (120), a via electrode (or via section) is positioned to penetrate at least a portion of each build-up insulation section (112, 113, PA) for vertical connection between circuit patterns positioned in each build-up insulation section. The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the build-up insulation section may include a via hole for positioning the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0083] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each build-up insulation portion. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the build-up insulation portions in the build-up insulation portions (112, 113, PA) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (build-up insulation portion) of the glass core layer (111), the first build-up insulation portion (112), and the second build-up insulation portion (113).

[0084] Specifically, in the embodiment, the electrode portion (120) may include a core electrode portion (121) and build-up electrode portions (122, 123). The build-up electrode portions (122, 123) may include a first electrode portion (122) and a second electrode portion (123). The first electrode portion (122) may be an 'upper electrode portion'. The second electrode portion (123) may be a 'lower electrode portion'. And the first electrode portion (122) and the second electrode portion (123) may be build-up wiring portions. And the first electrode portion (122) is disposed in each build-up insulation portion in the first build-up insulation portion (112) and may be an 'upper build-up wiring portion'. And the second electrode portion (123) is disposed in each build-up insulation portion in the second build-up insulation portion (113) and may be a 'lower build-up layer electrode portion'. Alternatively, the electrode portion may include a build-up wiring portion, a build-up via electrode (via portion).

[0085] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the glass core layer (111) and a core via electrode (121b) penetrating the glass core layer (111).

[0086] The first electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each build-up insulation portion of the first build-up insulation portion (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each build-up insulation portion of the first build-up insulation portion (112).

[0087] Furthermore, the second electrode portion (123) may include a lower wiring portion (123a) which is a wiring portion arranged on the upper and lower surfaces of the second build-up insulation portion (113) and a lower via electrode (123b) which is a via electrode. In addition, the lower via electrode (123b) may penetrate each build-up insulation portion of the second build-up insulation portion (113).

[0088] And in the embodiment, the wiring portion of the first electrode portion (and / or the second electrode portion) may include a wiring portion (second wiring portion) having a fine pitch and a wiring portion (first wiring portion) having a pitch larger than the second wiring portion.

[0089] The protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material that has insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0090] A protective layer (SR) may be disposed on the build-up insulation portion (112, 113, PA). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on the first build-up insulation portion (112) and a second protective layer (SR2) disposed under the second build-up insulation portion (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along the lamination direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0091] Furthermore, the circuit board (100) includes a bump portion (BP) positioned on the outer surface, and the bump portion (BP) may be disposed on the protective layer (SR). For example, the bump portion (BP) may be disposed on the upper surface of the protective layer (SR). The bump portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the first build-up insulating portion (112), the bump portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bump portion (BP) may include a protrusion disposed on the upper surface of the protective layer (SR) and a via region penetrating the protective layer (SR). In an embodiment, the via region and the protrusion may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via region and the protrusion may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0092] Furthermore, the bump portion (BP) may include a plurality of metal layers, or additional metal layers may be disposed on the bump portion (BP). The durability and reliability of the bump portion (BP) can be further improved. For example, the bump portion (BP) or the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. As a result, the bonding strength between the metal layer and the bump portion (BP) is improved, the corrosion resistance and durability of the bump portion (BP) are improved, and the loss of electrical signals can be minimized. The metal layer may be formed on the bump portion (BP) by deposition, electroplating, or the like of various metals.

[0093] The semiconductor device (SD) may be mounted on the upper portion of the circuit board (100). The semiconductor device (SD) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of those listed so far. And the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0094] Additionally, a semiconductor element (SD) may be placed on the first build-up insulating portion (112). The semiconductor element may be electrically connected to the aforementioned bump portion (BP) and electrode portion (120). The circuit board may be placed so as to have a high wiring density for connecting the semiconductor element and signals.

[0095] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of stacked build-up insulation layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high stacked layer count, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0096] The package substrate and interposer described above can be divided into core substrates and coreless substrates, respectively, depending on the configuration of the build-up insulation. In the case of the core substrate, the build-up insulation may include a core layer, and the core layer may refer to a layer of laminated build-up insulation including a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have a function of preventing warpage of the circuit board during the process by being arranged thicker than other build-up insulation members. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the build-up insulation of the circuit board may use a coreless substrate that does not include a core layer.

[0097] Referring further to FIGS. 3 and 4, in an embodiment, a glass core layer (111) may be positioned in a hole of an insulating substrate (DS). In addition, the glass core layer (111) may be positioned in a hole of a closed-loop insulating substrate (DS), such that the glass core layer (111) and the insulating substrate (DS) may not be in contact. For example, the glass core layer (111) may be spaced apart from and surrounded by the insulating substrate (DS) in a plane perpendicular to the lamination direction.

[0098] And the insulating substrate (DS) is an insulating substrate and may be formed of an insulating material. For example, the insulating substrate (DS) may include a copper clad laminate (CCL).

[0099] In addition, the glass core layer (111) may overlap with the insulating substrate (DS) in the horizontal direction (X-axis direction). And the glass core layer (111) may be spaced apart from the insulating substrate (DS) in the horizontal direction (X-axis direction) by a distance (gap). The outermost surface (OS) of the glass core layer (111) may be spaced apart from the inner surface of the insulating substrate (DS). In an embodiment, the outer surface of the glass core layer (111) may mean the outermost surface (OS). In addition, the glass core layer (111) and the insulating substrate (DS) may be arranged to be misaligned in the lamination direction. By this configuration, the outermost surface (OS) of the glass core layer (111) may be in contact with the connecting build-up layer (PA) of the build-up insulation and may be surrounded by the connecting build-up layer (PA). Furthermore, the insulating substrate (DS) may also be arranged on the outside of the outermost surface (OS) of the glass core layer (111). As a result, chipping can be suppressed on the outermost surface (OS) of the glass core layer (111). Accordingly, the reliability of the circuit board can be significantly improved.

[0100] In addition, as the insulating substrate (DS) is arranged on the outside of the glass core layer (111), the insulating substrate (DS) can overlap with the first build-up insulating portion (112), the second build-up insulating portion (113), and the protective layer (SR) in the lamination direction. Furthermore, the insulating substrate (DS) is arranged on the outside, and the build-up wiring portion can be arranged in an area overlapping with the insulating substrate (DS) in the lamination direction. Accordingly, the dummy electrode (DE) described below can overlap with the build-up wiring portion in the lamination direction. In this way, the reliability of the circuit board is improved through the insulating substrate, and at the same time, more space for forming an electrode portion (e.g., a build-up wiring portion) on the insulating substrate (DS) can be secured. Accordingly, the input / output (I / O) count can be increased.

[0101] In addition, the thickness of the glass core layer (111) may correspond to the thickness of the insulating substrate (DS). For example, the thickness of the glass core layer (111) may be the same as the thickness of the insulating substrate (DS). Accordingly, the build-up insulating portion (112, 113, PA) can be positioned without bending on the upper surface (US1) and the lower surface (BS1) of the glass core layer (111) to the upper surface (US2) and the lower surface (BS2) of the insulating substrate (DS). That is, problems such as step formation or peeling due to the height difference between the upper surface (US2) (or lower surface, BS2) of the insulating substrate (DS) and the upper surface (US1) (or lower surface, BS1) of the glass core layer (111) can be resolved.

[0102] In addition, the build-up insulating member can be in contact with the upper surface (US2), the outermost surface (OS), the lower surface (BS1) of the glass core layer (111) and the upper surface (US2), the lower surface (BS2) and the inner surface (IS) of the insulating substrate (DS). In particular, the build-up insulating member can be arranged in a separation region between the glass core layer (111) and the insulating substrate (DS). Specifically, the first build-up insulating member (112) can be in contact with the upper surface (US2) of the glass core layer (111) and the upper surface (US1) of the insulating substrate (DS). And the second build-up insulating member (113) can be in contact with the lower surface (BS2) of the glass core layer (111) and the lower surface (BS1) of the insulating substrate (DS). And the connecting build-up layer (PA) can be in contact with the outermost surface (OS) of the glass core layer (111) and the inner surface (IS) of the insulating substrate (DS). As a result, the build-up insulation can penetrate the area between the glass core layer (111) and the insulating substrate (DS). In addition, the build-up insulation can be formed to connect the upper and lower portions of the glass core layer (111). That is, one surface of the connecting build-up layer (PA) can be in contact with the first build-up insulation (112), and the other surface can be in contact with the second build-up insulation (113). With this configuration, a circuit board with reduced electrical resistance and delay and improved mechanical strength can be provided.

[0103] Additionally, the connection build-up layer (PA) may overlap with the glass core layer (111) and the insulating substrate (DS) in the horizontal direction (X-axis direction). Furthermore, the connection build-up layer (PA) may not overlap with the core wiring portion (121a) in the horizontal direction (X-axis direction).

[0104] Additionally, the connection build-up layer (PA) can have a closed loop structure because it is placed in a hole of the insulating substrate (DS).

[0105] The glass core layer (111) may include a plurality of outer surfaces. The glass core layer (111) may have a rectangular shape in plan view. For example, the glass core layer (111) may include a first outer surface (OS1), a second outer surface (OS2), a third outer surface, and a fourth outer surface.

[0106] The first outer side (OS1) and the second outer side (OS2) may be positioned opposite each other in the glass core layer (111). For example, the first outer side (OS1) and the second outer side (OS2) may be spaced apart from each other in the horizontal direction (X-axis direction). In addition, the third outer side and the fourth outer side may also be positioned opposite each other in the glass core layer (111). The third outer side and the fourth outer side may be positioned between the first outer side (OS1) and the second outer side (OS2).

[0107] And the first distance (gap1) may be different from the second distance (gap2). For example, the first distance (gap1) may be a separation distance between the first outer surface (OS1) and the inner surface (IS1) of the insulating substrate (DS) facing the first outer surface (OS1).

[0108] Additionally, the second distance (gap2) may be a separation distance between the second outer surface (OS2) and the inner surface (IS2) of the insulating substrate (DS) facing the second outer surface (OS2).

[0109] In this way, the first distance (gap1) and the second distance (gap2) may be different from each other depending on the arrangement of the electrode portion on the circuit board. As a result, the warpage phenomenon of the circuit board can be easily improved.

[0110] Additionally, in the embodiment, the length of the insulating substrate (DS) in the horizontal direction (X-axis direction) may be greater than 50 um. By this configuration, the insulating substrate (DS) can be prevented from being detached during the cutting process.

[0111] Additionally, the insulating substrate (DS) may vary in length in the horizontal direction (X-axis direction) depending on the region. For example, the insulating substrate (DS) may vary in length in the horizontal direction (X-axis direction) depending on the region adjacent to each outer surface of the glass core layer (111).

[0112] In the insulating substrate (DS), the thickness (T1) in the region facing the first outer surface (OS1) may be different from the thickness (T2) in the region facing the second outer surface (OS2). For example, when the number of electrode portions adjacent to the first outer surface (OS1) is greater than that of electrode portions adjacent to the second outer surface (OS2) (e.g., when the area is large), the thickness (T1) in the region facing the first outer surface (OS1) may be greater than the thickness (T2) in the region facing the second outer surface (OS2) in order to reduce the relatively large stress on the first outer surface (OS1). Accordingly, the structural stress of the circuit board may not be concentrated in one region, thereby improving reliability.

[0113] In addition, the length (T1, T2) in the horizontal direction (X-axis direction) of the insulating substrate (DS) can be smaller than the length (gap1, gap2) in the horizontal direction (X-axis direction) of the connecting build-up layer (PA). This allows for easy miniaturization of the circuit board.

[0114] In addition, the length in the horizontal direction (X-axis direction) of the insulating substrate (DS) may be smaller than the hole in the glass core layer (111) or the thickness of the glass core layer (111). In addition, the length (gap1, gap2) in the horizontal direction (X-axis direction) of the connecting build-up layer (PA) may be smaller than the hole in the glass core layer (111) or the thickness of the glass core layer (111). By this configuration, the length in the horizontal direction of the build-up insulating portion and the insulating substrate (DS) can be minimized while protecting the glass core layer (111).

[0115] In addition, the circuit board (100) may further include a dummy electrode (DE). The dummy electrode (DE) may be positioned on the upper surface (US2) or the lower surface (BS2) of the insulating substrate (DS). The thickness (Ta) of the dummy electrode (DE) may be different from the thickness (Tb) of the core wiring portion (121a). For example, the thickness (Ta) of the dummy electrode (DE) may be smaller than the thickness (Tb) of the core wiring portion (121a). By this configuration, the minimum width (length in the horizontal direction) of the insulating substrate (DS) can be easily preserved after the cutting (e.g., sawing) described below. That is, the phenomenon of the insulating substrate (DS) being separated or detached from the build-up insulating portion can be suppressed.

[0116] These dummy electrodes (DE) can be partially or completely positioned on the upper surface (US2) or lower surface (BS2) of the insulating substrate (DS). This allows the residual portion of the insulating substrate (DS) to be more easily implemented.

[0117] Figures 5 to 14 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0118] A circuit board according to a first embodiment may include a step of preparing an insulating substrate, a step of forming a hole in the insulating substrate, a step of arranging a glass core layer in the hole of the insulating substrate, a step of forming a hole in the glass core layer, a step of arranging a build-up insulating portion and an electrode portion in the glass core layer, a step of forming a protective layer, and a step of performing a cutting process.

[0119] In the present invention, a circuit board according to an embodiment may correspond to a unit circuit board. That is, during the manufacturing process, a mother circuit board may be composed of a plurality of unit circuit boards. The mother circuit board may be separated into a plurality of unit circuit boards along a sawing line. That is, a plurality of unit circuit boards may form a large board in the form of a panel. The large board in the form of a panel may be cut as described below to produce a unit circuit board.

[0120] First, as shown in Fig. 5, a panel-unit insulating substrate (DSU) can be prepared. The panel-unit insulating substrate (DSU) can be a large substrate larger than the insulating substrate of the circuit board according to the embodiment.

[0121] And as shown in Fig. 6, a hole (DSh) can be formed in the insulating substrate (DSU) of the panel unit. The number of holes (DSh) of the insulating substrate (DSU) can be multiple. In addition, the holes (DSh) in the insulating substrate (DSU) of the panel unit can be formed corresponding to each glass core layer of each unit circuit board.

[0122] And as in Fig. 7, a glass core layer (111) can be placed in a hole (DSh) formed in an insulating substrate (DSU) of a panel unit. A glass core layer (111) can be placed in each hole (DSh). In this step, the glass core layer (111) can be formed of a plurality of unit glass core layers (111). And, a film (PI) or the like can be placed underneath each hole (DSh) of the glass core layer (111) to accommodate the glass core layer (111). That is, a panel unit insulating substrate (DSU) and a plurality of glass core layers (111) can be placed on the film (PI).

[0123] And as in Fig. 8, each hole (111h) can be formed in the glass core layer (111). Hereinafter, the film will be omitted and described. Each hole (111h) in the glass core layer (111) can be formed corresponding to a core via electrode.

[0124] Referring to FIGS. 9 to 12, a build-up insulation part and an electrode part can be placed on a glass core layer, and a protective layer can be formed.

[0125] The glass core layer (111) may be formed with a through hole for arranging a through electrode (via electrode), a hole for connecting adjacent unit glass core layers, a core via electrode arranged within the hole, and a core wiring portion arranged on the upper and lower surfaces of the glass core layer. The holes of the glass core layer (111) may be formed by various etching methods, such as mechanical or chemical.

[0126] In addition, a build-up insulation portion and an electrode portion may be arranged on the glass core layer (111). For example, a via electrode may be formed in a via hole or a through hole of the glass core layer. In the electrode portion, a circuit pattern layer may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), a semi-additive process (SAP), or the like, which are manufacturing processes for printed circuit boards. In addition, the pattern may be formed by a dry film, etc.

[0127] Additionally, a second build-up insulating portion may be arranged on the outer side of the glass core layer (111). An electrode portion may also be arranged on the second build-up insulating portion.

[0128] Furthermore, a protective layer may be formed on the build-up insulation portion. Additionally, conductive members or semiconductor elements may be further arranged on the build-up insulation portion. However, cutting may be performed first without arranging the conductive members or semiconductor elements. Furthermore, the cutting process may be performed prior to the formation of the protective layer or bump portion.

[0129] Referring to Fig. 13, a cutting process can be performed. That is, a circuit board of a panel unit can be separated into unit circuit boards through a cutting process.

[0130] As an example, a panel unit circuit board can be cut along a sawing line. A plurality of unit circuit boards can be manufactured by cutting.

[0131] A sawing line can be applied to the insulating substrate. Therefore, during cutting, the build-up insulation and the insulating substrate can be cut. In other words, the glass core layer may not be cut during the cutting process. With this configuration, cracks generated by cutting in the unit circuit board may not propagate into the glass core layer. Furthermore, since the glass core layer is not cut, cracks, etc., may not occur on the outer surface.

[0132] In addition, the thickness of the insulating substrate adjacent to the outer surface of the glass core layer (111) may vary in the horizontal direction depending on the position of the sawing line. Furthermore, the distance between the inner surface of the insulating substrate adjacent to the outermost surface of the glass core layer may vary depending on the position of the glass core layer in the hole of the insulating substrate of the unit panel. Accordingly, the distance between the outermost surface of the glass core layer and the inner surface of the insulating substrate in the unit circuit board may differ depending on the region. By this configuration, the warpage phenomenon of the unit circuit board, i.e., the circuit board according to the embodiment, may be suppressed, thereby improving reliability.

[0133] Fig. 15 is a cross-sectional view of a circuit board according to the second embodiment, and Fig. 16 is an enlarged view of part K3 in Fig. 15.

[0134] Referring to FIGS. 15 and 16, a circuit board (100A) according to the second embodiment may include a glass core layer (111), a build-up insulating portion (112, 113, PA), an electrode portion (120), an insulating substrate (DS), and a protective layer (SR). In addition, the circuit board (100A) may further include a semiconductor element (SD) and a conductive member positioned on one side (e.g., the upper side). Except for the contents described below, the contents described in various embodiments may be applied.

[0135] In this embodiment, the glass core layer (111) may include a first lower region (BA1) and an upper region (UA1). The first upper region (UA1) may be laminated on the first lower region (BA1).

[0136] In addition, the first upper region (UA1) may have a larger area than the first lower region (BA1) on the first lower region (BA1). That is, the area (plane perpendicular to the stacking direction) of the first upper region (UA1) may be larger than the area of ​​the first lower region (BA1). In addition, the first lower region (BA1) may overlap with the first upper region (UA1) in the stacking direction (Y-axis direction). However, the first upper region (UA1) may not overlap with the first lower region (BA1) at least partially in the stacking direction (Y-axis direction). In addition, at least a portion of the first upper region (UA1) may be located outside the first lower region (BA1). The outside may correspond to a direction from the glass core layer toward the insulating substrate with respect to the center of the circuit board.

[0137] And the first sub-area (BA1) may include a first side (S1), a second side (S2), and a third side (S3). The first side (S1), the second side (S2), and the third side (S3) may be the outermost side of the glass core layer of the circuit board. The first side (S1) may be the outer side of the glass core layer (111) in the first sub-area (BA1). The second side (S2) may be located on the upper side of the first sub-area (BA1).

[0138] The third side (S3) may be an outer side disposed further outward than the first side (S1). In particular, the third side (S3) may be an outer side in the first upper region (UA1) of the glass core layer (111). The second side (S2) may be a side in the first upper region (UA1) that does not contact the first lower region (BA1).

[0139] The second surface (S2) may be in contact with the first surface (S1) and the third surface (S3). For example, one side of the second surface (S2) may be in contact with the first surface (S1), and the other side (outer side than the first side) of the second surface (S2) may be in contact with the third surface (S3). In addition, the second surface (S2) may be located in an area between the first surface (S1) and the third surface (S3).

[0140] Furthermore, in the embodiment, the insulating substrate (DS) may include a second lower region (BA2) and a second upper region (UA2). The second upper region (UA2) may have a smaller area than the second lower region (BA2). That is, the area (plane perpendicular to the stacking direction) of the second upper region (UA2) may be smaller than the area of ​​the second lower region (BA2). In addition, the second lower region (BA2) may overlap with the second upper region (UA2) in the stacking direction (Y-axis direction). In addition, at least a portion of the second lower region (BA2) may not overlap with the second upper region (UA2) in the stacking direction (Y-axis direction). However, the second upper region (UA2) may overlap with the second lower region (BA2) in the stacking direction (Y-axis direction). In addition, at least a portion of the second lower region (BA2) may be located outside the second upper region (UA2).

[0141] Accordingly, both the glass core layer (111) and the insulating substrate (DS) may have a step structure. In particular, the glass core layer (111) and the insulating substrate (DS) may have a step structure formed on surfaces adjacent to each other. For example, a step structure may be formed on the outer surface of the glass core layer (111), and a step structure may be formed on the inner surface of the insulating substrate (DS). By this configuration, the bonding or joining area between the glass core layer (111) and the insulating substrate (DS) through the build-up insulating portion may be improved. Accordingly, the bonding strength between the glass core layer (111), the build-up insulating portion, and the insulating substrate (DS) may be improved, thereby improving the reliability of the circuit board.

[0142] And the first upper region (UA1) can overlap at least partially with the second lower region (BA2) in the stacking direction (Y-axis direction).

[0143] Furthermore, the circuit board (100A) may further include a bonding member (BM) disposed in an overlapping area (OA) where the first upper area (UA1) and the second lower area (BA2) overlap each other. The bonding member (BM) may be positioned between the outer surface of the glass core layer (111) and the inner surface of the insulating substrate (DS). In particular, the bonding member (BM) may be in contact with the second surface (S2). In addition, the bonding member (BM) is disposed in the above-described overlapping area (OA) and may be in contact with the outer surface of the glass core layer (111) and the inner surface of the insulating substrate (DS). By this configuration, the detachment or separation of the insulating substrate (DS) can be easily prevented. In the cutting process, warping or tilting of the insulating substrate (DS) can be suppressed, so that the manufacturing accuracy of the circuit board can be improved.

[0144] Figures 17 to 19 are drawings explaining a method for manufacturing a circuit board according to the second embodiment.

[0145] Except for the contents described below, the contents of the manufacturing method described above may be applied equally.

[0146] Referring to Fig. 17, a panel-unit insulating substrate (DSU) can be prepared as described in Fig. 5. The panel-unit insulating substrate (DSU) can be a large substrate larger than the insulating substrate of the circuit board according to the embodiment.

[0147] Referring to Fig. 18, holes (DSh) may be formed in the insulating substrate (DSU) of the panel unit as in Fig. 6. The number of holes (DSh) of the insulating substrate (DSU) may be multiple. In addition, the holes (DSh) in the insulating substrate (DSU) of the panel unit may be formed corresponding to each glass core layer of each unit circuit board.

[0148] In this example, the insulating substrate (DS) may have a step. For example, the insulating substrate (DS) may be formed so that the area of ​​the hole (DSh) decreases as it faces downward.

[0149] Accordingly, the insulating substrate (DS) may have a second lower area (BA2) and an upper area (UA2) having a larger area than the second lower area (BA2).

[0150] And as in FIG. 7, a glass core layer (111) may be placed in a hole (DSh) formed in an insulating substrate (DSU) of a panel unit. A glass core layer (111) may be placed in each hole (DSh). In this step, the glass core layer (111) may be formed of a plurality of unit glass core layers (111). And, a film (PI) or the like may be placed below each hole (DSh) of the glass core layer (111) to accommodate the glass core layer (111). That is, the insulating substrate (DSU) of a panel unit and a plurality of glass core layers (111) may be settled on the film (PI). However, each glass core layer (111) may have a step structure. For example, the glass core layer (111) may include a first lower region (BA1) and a first upper region (UA1) having a larger area than the first lower region (BA1).

[0151] Afterwards, as described above, a hole is formed in the glass core layer, a build-up insulation part and an electrode part are placed on the glass core layer, and a protective layer is formed, after which a cutting process can be performed.

[0152] Fig. 20 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 21 is a cross-sectional view showing a semiconductor package according to the second embodiment, Fig. 22 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 23 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0153] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0154] Referring to FIG. 20, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0155] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0156] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0157] The first substrate (1100) may include at least one build-up insulating portion and an electrode portion disposed on at least one build-up insulating portion.

[0158] A second substrate (1200) may be placed on the first substrate (1100).

[0159] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0160] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0161] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0162] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate (1100).

[0163] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0164] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0165] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0166] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0167] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0168] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0169] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0170] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a solder layer formed between the plurality of components by recrystallization.

[0171] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0172] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the build-up insulation portion of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0173] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0174] Additionally, looking further into FIG. 20, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0175] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0176] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0177] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0178] Referring to FIG. 21, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0179] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0180] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0181] Referring to FIG. 22, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0182] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0183] That is, the first substrate (1100) of the third embodiment can function as a package substrate while also connecting a semiconductor element (1300) and a main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting a plurality of semiconductor elements.

[0184] Referring to FIG. 23, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0185] In this way, the semiconductor package of the fourth embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0186] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0187] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0188] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0189] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0190] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0191] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0192] The semiconductor package of the fourth embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive coupling portion (1450).

[0193] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0194] Meanwhile, the third semiconductor element (1330) in the fourth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0195] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0196] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying power to semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integrity or technical interoperability with each other.

[0197] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuits between terminals, or electrical open circuits of terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0198] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuits between terminals, or electrical open circuits of terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0199] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0200] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Glass core layer; An insulating substrate spaced apart from the glass core layer and including a hole in which the glass core layer is received; and A build-up insulating member including an upper build-up layer and a lower build-up layer disposed on the glass core layer and the insulating substrate; A circuit board including a connecting build-up layer disposed between the outermost surface of the glass core layer and the inner surface of the hole of the insulating substrate, and connected to the upper build-up layer and the lower build-up layer; 2. In paragraph 1, A circuit board in which the outermost surface of the glass core layer is spaced apart from the inner surface of the insulating substrate.

3. In paragraph 1, The above-mentioned build-up insulation part is a circuit board in contact with the upper surface, lower surface, and inner surface of the above-mentioned insulation substrate.

4. In paragraph 1, The above-mentioned build-up insulation is a circuit board in contact with the upper surface, lower surface and outer surface of the glass core layer.

5. In paragraph 1, A circuit board wherein the outermost surface of the glass core layer includes a first outer surface and a second outer surface spaced apart from the first outer surface.

6. In paragraph 5, The first distance is different from the second distance, The first distance is a distance between the first outer surface and the first inner surface of the insulating substrate facing the first outer surface, A circuit board in which the second distance is a distance between the second outer surface and the second inner surface of the insulating substrate facing the second outer surface.

7. In paragraph 5, A circuit board having a thickness in the horizontal direction in a region facing the first outer surface of the insulating substrate and a thickness in the horizontal direction in a region facing the second outer surface.

8. In paragraph 5, The above-mentioned connection build-up layer is a circuit board having a closed-loop structure on the outside of the above-mentioned glass core layer.

9. In paragraph 8, A circuit board in which the horizontal length of the insulating substrate is shorter than the horizontal length of the connecting build-up layer.

10. In paragraph 1, A circuit board further comprising a dummy electrode disposed on the upper surface of the insulating substrate.

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