Scaled alscn ferroelectric diodes with optimized performance

Abstract

Described herein are BEOL-compatible, high-performance FE-diodes scaled to 5, 10, and 20 nm FE Al0.72Sc0.28N films. Through interlayer (IL) engineering, substantial improvements in the ON / OFF ratios (>590 times) and rectification ratios (>251 times) in these scaled devices are shown. The superlative characteristics also enables 5-bit multi-state operation with a stable retention. Also provided herein are experimental and theoretical demonstrations of counterintuitive results that the inclusion of an IL can lead to a decrease in the ferroelectric switching voltage of the device. An in-depth analysis into the device transport mechanisms is performed, and the compact model aligns seamlessly with the experimental results. The results suggest the possibility of using scaled AlxSc1-xN FE-diodes for high performance, low-power, embedded NVM.

Description

SCALED ALSCN FERROELECTRIC DIODES WITH OPTIMIZED PERFORMANCERELATED APPLICATIONS

[0001] The present application claims priority to and the benefit of United States patent application no. 63 / 601,920, “Scaled AlScN Ferroelectric Diodes with Optimized Performance” (filed November 22, 2023). All foregoing applications are incorporated herein by reference in their entireties for any and all purposes.GOVERNMENT RIGHTS

[0002] This invention was made with government support under 1542153, and 1720530 awarded by the National Science Foundation and FA9550-23-1-0391 awarded by the Air Force Office of Scientific Research, W91 INF-19- 2-0119 awarded by the Army Research Laboratory - Army Research Office. The government has certain rights in the invention.TECHNICAL FIELD

[0003] The disclosed technology relates to the field of ferroelectric diodes.BACKGROUND

[0004] The expansion in data generation via a range of ubiquitously connected devices has intensified the need for highly efficient and rapid data processing technologies that can overcome the von Neumann bottleneck. Recent research suggests the use of memory- driven computing by integrating emerging non-volatile memory (NVM) devices with the processing transistors in a dense monolithic 3D stack. For this application, a CMOS BEOL-compatible FE-diode is particularly attractive, as it is a two-terminal device with rectifying I-V characteristics, enabling selector-free and high-density crossbar array memory technology.

[0005] The ferroelectric material Ali.xScxN (AlScN) is promising for application in FE- diodes due to its unique ferroelectric properties, such as a high remnant polarization (Pr) of > 125 pC / cm2, coercive field (Ec) of 3 - 6 MV / cm, and square-shaped polarization-electric field (P-E) loop. Moreover, Ali.xScxN (x < 0.43) is highly CMOS BEOL-compatible with a low process temperature (< 400 °C), and has a single, stable wurtzite ferroelectric phase,24-10543 / 103241.007431 unlike HfOxpolymorphisms exhibiting its ferroelectricity only in metastable phases. As a result, ferroelectric AlScN can offer uniform and reliable device performances without any additional post-annealing or other phase stabilization procedures.

[0006] Despite the remarkable attributes of FE AlScN such as large Prand moderate 8, scaling of FE-diodes to low-voltages concurrently with high rectification and ON / OFF ratios remains unachieved. The majority of existing studies predominantly focus on the ferroelectric tunneling junction (FTJ), which shows a marginal rectification ratio, necessitating the addition of a selector. While some recent demonstrations have shown AlScN FE-diodes, the thickness of the AlScN films used typically range over 20 - 45 nm. To lower the operating voltage of an AlScN FE-diode, a reduction in AlScN thickness is essential. Encouragingly, recent research have shown that AlScN can be scaled down to sub- 10 nm dimensions without compromising its outstanding ferroelectric properties. However, the ON / OFF current ratios and rectification characteristics of the scaled devices are far from desirable values.

[0007] One approach to enhancing the performance of FE-diodes is the introduction of an interlayer (IL) in the device stack, resulting in a metal -ferroelectric-insulator-metal (MFIM) structure. The inclusion of an IL can enhance the FE polarization-induced electrostatic modulation of the tunneling barrier in FE-diodes, thereby improving ON / OFF and rectification characteristics. Therefore, IL engineering becomes a key aspect of AlScN FE-diode optimization at these scaled thicknesses to improve performances which we have thoroughly explored.SUMMARY

[0008] Ferroelectric diodes with optimized performance are described herein. In one aspect, a ferroelectric diode can include: a first electrode layer; a second electrode layer; a ferroelectric layer disposed between the first electrode layer and the second electrode layer; and a non-ferroelectric interlayer disposed between either the first electrode layer and the ferroelectric layer, or between the ferroelectric layer and the second electrode layer.BRIEF DESCRIPTION OF THE DRAWINGS24-10543 / 103241.007431

[0009] For the purpose of illustrating the invention, there is shown in the drawings a form that is presently preferred; it being understood, however, that this invention is not limited to the precise arrangements and instrumentalities shown.

[0010] FIG. 1 depicts a general structure of the AI0 / 72SC0.28N ferroelectric diode devices. Panel (a): Cross-sectional bright field STEM and Panel (b): high-resolution TEM image of the device. Panel (c): Schematic diagram of the MFIM Alo.72Sco.28N ferroelectric diode. Panel (d): Optical image of the device array. The darker contrast circles represent the top metal electrodes of 20 pm radii.

[0011] FIG. 2 depicts I-V curves and extracted performance characteristics of 20 nm AI0 / 72SC0.28N ferroelectric diodes. I-V curves of 20 nm AI0 / 72SC0.28N ferroelectric diodes with an A1OXthickness of Panel (a) 0 nm, Panel (b) 1 nm, Panel (c) 2 nm, Panel (d) 3 nm, Panel (e) 4nm, and Panel (f) 5 nm are shown. For all devices, Al is the bottom electrode, and Ti (shown in red) or Cr (shown in purple) is the top electrode. Panel (g): Extracted IL- thickness dependent ON / OFF ratio of the devices. Panel (h): IL-thickness dependent rectification ratio extracted at the point of the maximum ON / OFF ratio.

[0012] FIG. 3 depicts theoretical analysis of carrier transport through the device and compact model fitting. Energy band diagram and active transport mechanisms of the ferroelectric diode for Panel (a) LRS and Panel (b) HRS. The diagrams highlight the relative importance of various tunneling mechanisms. They also show the modulation of local electric fields and the emission barrier by the polarization state of the ferroelectric. Panel (c): Fitting of the Poole-Frenkel (P-F) and thermionic emission (TI) models to the 20 nm device with no IL. Panel (d): Fitting of the two carrier transport models to the 20 nm device with 4 nm A1OXIL. This demonstrates the suppression of current in the HRS that induces an enhanced ON / OFF ratio.

[0013] FIG. 4 depicts IL-induced switching voltage reduction and electrostatic analysis of the device structure. Panel (a): Ferroelectric switching voltages of 20 nm AlScN FE- diodes extracted from quasi-DC I-V curves as shown in figure 2. Panel (b): PUND measurement results using 200 kHz pulses of the 20 nm device with A1OXthicknesses from 1 to 5 nm. Voltage is applied in 1 V steps until the point of device breakdown. Panel (c): Applied voltage (Va) extracted from the PUND measurements needed to reach a 2Prvalue of 6 pC / cm2for various IL thicknesses.24-10543 / 103241.007431

[0014] FIG. 5 depicts Two-state retention, and multistate retention characteristics of 20 nm AlScN FE-diode devices. Panel (a): LRS / HRS retention measurement of 20 nm AlScN FE-diode with 4 nm A1OXIL up to 50,000 seconds. Panel (b): Simulated IL thicknessdependent P-E hysteresis loop using a multidomain Preisach ferroelectric model. Panel(c): 32-state I-V curves of the 20 nm AlScN FE-diode with 5 nm A1OXIL FE-diode obtained after gradual switching by applying 0.25 V stepwise voltage amplitude. Panel(d): 32 multi-states retention of FE-diode up to 300 s.

[0015] FIG. 6 depicts I-V characteristics of 10 and 5 nm Alo.72Sco.28N FE-diode. 10 nm Alo.72Sco.28N FE-diode with A1OXIL thickness of Panel (a) 0 nm, Panel (b) 2 nm, and Panel (c) 4 nm; 5 nm Alo.72Sco.28N FE-diode with A1OXthickness of Panel (d) 0 nm, Panel(e) 2 nm, and Panel (f) 4 nm. Each plot includes I-V curves obtained from three different devices to confirm the device-to-device variation. Except for the 5 nm AI0.72SC0.28N / 4 nm A1OXFE-diode, they show uniform I-V characteristics. The insertion of a 4 nm IL into a 10 nm AlScN FE-diode results in a substantial enhancement in the ON / OFF ratio, increasing from 175 to 2177, as well as an improvement in the rectification ratio from 7 to 644 compared to the control sample (without IL). Similarly, for the 5 nm AlScN FE-diode, the introduction of the 4 nm IL leads to substantial improvements in the ON / OFF and rectification ratios, which increase from 2 to 1149 and 3 to 186 respectively. These results for scaled 10 and 5 nm devices follow the trend observed in 20 nm FE-diodes (Figure S2).

[0016] FIG. 7 depicts retention measurements of 5 and 10 nm FE-diodes. Panel (a): Retention measurement of the 10 nm AlScN / 4 nm A1OXIL FE-diode up to 5 x 104s and Panel (b) the 5 nm AlScN / 2 nm A1OXIL FE-diode up until the point of retention loss.

[0017] FIG. 8 depicts STEM and EDX images of an AlScN FE-diode. STEM Spectrum image and corresponding energy-dispersive X-ray spectroscopy maps of the device.

[0018] FIG. 9, Panels (a)-(d) depict extracted On-Off ratio graphs, and rectification ratio graphs at the point of maximum On-Off ratio from I-V curves of FE-diodes with (a, b) 10 nm, and (c, d) 5 nm AlScN and various A1OXIL thicknesses (0-4 nm).

[0019] FIG. 10 depicts a fitting of the Poole-Frenkel (P-F) and thermionic emission (TI) models to Panel (a) 10 nm AlScN / no IL, Panel (b) 10 nm AlScN / 2 nm A1OXIL, Panel (c) 5 nm AlScN / no IL, and Panel (d) 5 nm AlScN / 4 nm A1OXIL FE-diodes. The dotted lines are experimental results, and solids lines are fitting models. Upon the introduction of the24-10543 / 103241.007431IL, the relatively flat region of HRS described by the TI model is extended, resulting in an enhanced On-Off ratio.

[0020] FIG. 11 depicts I-V characteristics of 10 nm Alo.72Sco.28N FE-diode with HfOxIL thickness of Panel (a) 0 nm, Panel (b) 2 nm, and Panel (c) 4 nm. Inserting HfOxalso results in a multitude (e.g., 10 times) higher On-Off ratio compared to no IL.

[0021] FIG. 12 depicts retention measurements of 10 nm FE-diodes. Left panel: Retention measurement of the 10 nm AlScN / 4 nm A1OXIL FE-diode up to 5 x 104s; and Right panel: retention measurement of the 10 nm AlScN / 4 nm HfOxIL FE-diode up to 5 x 104s.

[0022] FIG. 13 depicts retention measurements of 5 and 10 nm FE-diodes. Panel (a): Retention measurement of the 10 nm AlScN / 4 nm A1OXIL FE-diode up to 5 x 104s and Panel (b) the 5 nm AlScN / 2 nm A1OXIL FE-diode up until the point of retention loss.

[0023] FIG. 14 depicts retention measurements of 10 nm FE-diodes. Left panel: Retention measurement of the 10 nm AlScN / 0 nm HfOxIL FE-diode up to 5 x 104s; Middle panel: retention measurement of the 10 nm AlScN / 2 nm HfOxIL FE-diode up to 5 x 104s; and Right panel: retention measurement of the 10 nm AlScN / 4 nm HfOxIL FE- diode up to 5 x 104s.

[0024] FIG. 15 depicts Two-state retention, and multistate retention characteristics of 20 nm AlScN FE-diode devices. Left panel LRS / HRS retention measurement of 10 nm AlScN FE-diode with 4 nm A1OXIL up to 50,000 seconds. Reft panel LRS / HRS retention measurement of 10 nm AlScN FE-diode with 4 nm HfOxIL up to 50,000 seconds.

[0025] FIG. 16A provides a cross-sectional view of an exemplary device according to the present disclosure. As shown, the device includes a Pt electrode superposed on a Si substate (Pt / Si), with a layer of Alo.64Sco.36N atop the Pt. An Al Ox interlayer is disposed on the AlScN layer; in this non-limiting instance, the interlayer has a thickness of about 6 nm. Ni electrode material is disposed on the interlayer; in this non-limiting instance, the Ni electrodes are about 150 nm in thickness.

[0026] FIG. 16B provides example voltage v. current data for a device according to FIG. 16A across a range of temperatures. As shown, the difference in current at a given voltage is greater at lower temperatures; for example, the current difference at 5 V at 25 °C is greater than at 600 °C.24-10543 / 103241.007431

[0027] FIG. 16C provides example temperature vs. current data for on and off current for a device according to FIG. 16 A. As shown, there are differences between on and off currents across the range of provided temperatures.

[0028] FIG. 16D provides example temperature vs. Ec data for a device according to FIG. 16 A. As shown, there are differences between the positive and negative coercive fields across the range of provided temperatures.

[0029] FIG. 16E provides example temperature vs. rectification ratio data for a device according to FIG. 16 A. As shown, there are differences in the rectification ratios in the on and off states across the range of provided temperatures.

[0030] FIG. 16F provides example temperature vs. on-off ratio data for a device according to FIG. 16 A.

[0031] FIG. 16G provides example E vs. J data for a device according to FIG. 16A.

[0032] FIG. 16H provides example time vs. J data for a device according to FIG. 16A.

[0033] FIG. 161 provides example temperature vs. Ec data for a device according to FIG. 16 A. As shown, there are differences in the Ec values for positive and negative coercive fields across the range of provided temperatures.

[0034] FIG. 16J provides example time vs. current data for a device according to FIG.16 A.

[0035] FIG. 16K provides example voltage vs. 2PR (P-U and N-D) data for a device according to FIG. 16 A.

[0036] FIG. 16L provides example temperature vs. PR data for a device according to FIG. 16 A.

[0037] FIG. 17A provides a cross-sectional view of an exemplary device according to the present disclosure. As shown, the device includes a Pt electrode superposed on a Si substate (Pt / Si), with a layer of Alo.64Sco.36N atop the Pt. An Al Ox interlayer is disposed on the AlScN layer; in this non-limiting instance, the interlayer has a thickness of about 10 nm. Ni electrode material is disposed on the interlayer; in this non-limiting instance, the Ni electrodes are about 150 nm in thickness.

[0038] FIG. 17B provides example voltage v. current data for a device according to FIG. 17B across a range of temperatures. As shown, the difference in current at a given voltage is greater at lower temperatures; for example, the current difference at 5 V at 25 °C is greater than at 600 °C.24-10543 / 103241.007431

[0039] FIG. 17C provides example temperature vs. current data for on and off current for a device according to FIG. 17 A.

[0040] FIG. 17D provides example temperature vs. rectification ratio data for a device according to FIG. 17 A.

[0041] FIG. 17E provides example temperature vs. Ec data for a device according to FIG. 17 A.

[0042] FIG. 17F provides example temperature vs. on-off ratio data for a device according to FIG. 17 A.

[0043] FIG. 17G provides example E vs. J data for a device according to FIG. 17A.

[0044] FIG. 17H provides example time vs. J data for a device according to FIG. 17A.

[0045] FIG. 171 provides example temperature vs. Ec data for a device according to FIG. 17 A.

[0046] FIG. 17K provides example voltage vs. 2PR (P-U and N-D) data for a device according to FIG. 17 A.

[0047] FIG. 17K provides example temperature vs. PR data for a device according to FIG. 17 A.

[0048] FIG. 17L provides example time vs. current data for a device according to FIG.17 A.

[0049] FIG. 18A provides a view of an exemplary device according to the present disclosure. As shown, a layer of AlScN (for example, AISC0.32N) can be placed on a SiC substrate. Electrodes (in this instance, Ni) can be placed on the SiC substrate and on the AlScN layer.

[0050] FIG. 18B provides example roughness data for a device according to FIG. 18 A.

[0051] FIG. 18C provides example room temperature data for a device according to FIG.18 A.

[0052] FIG. 18D provides example AC-IV PUND data for a device according to FIG.18 A.

[0053] FIG. 18E provides example electric field vs. current density and voltage vs. current density data for a device according to FIG. 18A at a range of temperatures.

[0054] FIG. 18F provides example electric field vs. current density and voltage vs. current density data for a device according to FIG. 18A at a range of temperatures.24-10543 / 103241.007431

[0055] FIG. 18G provides example temperature vs. coercive field data for a device according to FIG. 18A at a range of temperatures.

[0056] FIG. 18H provides example electric field vs. current density and voltage vs. current density data for a device according to FIG. 18A at a range of temperatures.

[0057] FIG. 181 provides example temperature vs. coercive field data for a device according to FIG. 18A at a range of temperatures.

[0058] FIG. 18J provides example time vs. current data for a device according to FIG. 18A at a range of temperatures.

[0059] FIG. 18K provides example temperature vs. 2PR data for a device according to FIG. 18 A.

[0060] FIG. 18L provides example cycle number vs. 2PR data for a device according to FIG. 18 A.

[0061] FIG. 18M provides time vs. 2PR data for a device according to FIG. 18 A.DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0062] The present disclosure may be understood more readily by reference to the following detailed description taken in connection with the accompanying figures and examples, which form a part of this disclosure. It is to be understood that this invention is not limited to the specific devices, methods, applications, conditions or parameters described and / or shown herein, and that the terminology used herein is for the purpose of describing particular embodiments by way of example only and is not intended to be limiting of the claimed invention. Also, as used in the specification including the appended claims, the singular forms “a,” “an,” and “the” include the plural, and reference to a particular numerical value includes at least that particular value, unless the context clearly dictates otherwise. The term “plurality”, as used herein, means more than one. When a range of values is expressed, another embodiment includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another embodiment. All ranges are inclusive and combinable, and it should be understood that steps may be performed in any order. Any documents cited herein are incorporated by reference in their entireties for any and all purposes.24-10543 / 103241.007431

[0063] It is to be appreciated that certain features of the invention which are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, reference to values stated in ranges include each and every value within that range. In addition, the term “comprising” should be understood as having its standard, open-ended meaning, but also as encompassing “consisting” as well. For example, a device that comprises Part A and Part B may include parts in addition to Part A and Part B, but may also be formed only from Part A and Part B.

[0064] Ferroelectric (FE) diodes are described herein. The disclosure provides a successful demonstration of BEOL-compatible FE-diodes using Alo.72Sco.28N films with thicknesses of 5 nm, 10 nm, and 20 nm. With the inclusion of an A1OXIL, the scaled AlScN FE-diodes show a substantial enhancement in both the ON / OFF and rectification ratios. Notably, the 10 nm AlScN FE-diode exhibits a remarkable increase in the ON / OFF ratio from 211 to 2177 and an improvement in the rectification ratio from 7 to 644. For the 5 nm AlScN FE-diodes, these values jump from 2 to 1149 and 3 to 754 for the ON / OFF and rectification ratios, respectively. In addition to these performance enhancements, also presented is a counterintuitive benefit of IL integration to be a reduction in ferroelectric switching voltage. This effect is verified through two experimental methods of switching voltage extraction as well as theoretical electrostatics analysis. Ferroelectric systems exhibiting high Pr, low 8, and square-like hysteresis, such as AlScN, are ideal for exploiting this effect. The use of thicker ILs (>3nm) also stabilizes intermediate Prstates, allowing for 32 stable memory states with a maximum ON / OFF ratio separation of 1175. Each of these states show robust retention for up to 300 seconds, with two states among these demonstrating remarkably stable retention beyond 50,000 seconds maintaining an ON / OFF ratio exceeding 700. Further, a comprehensive analysis of the FE-diode operation, corroborated by a well-fitted compact device model that is based on thermionic emission and the Poole-Frenkel effect, is provided.General Structure of the AlScN FE-diodes

[0065] The FE-diode examples can include 50 nm Al bottom electrodes grown on a sapphire wafer. The ferroelectric layer can include sputter-deposited 5, 10, or 20 nm24-10543 / 103241.007431Alo.72Sco.28N. The IL can include ALD-deposited A1OXwith thickness ranging from 0 (no IL) to 5 nm. The top electrode arrays can include 20 pm-radius pads of Ti or Cr metal with an Au capping layer. The detailed information of fabrication processes is described in the method section below. TEM images of the devices are shown in FIGS. 1(a) and (b). A detailed compositional analysis is presented in FIG. 8. TEM images were taken of the thinnest AlScN FE-diode devices and the AlScN thickness is confirmed to be 5 nm in this case. The schematic of the fabricated FE-diode is shown in FIG. 1(c), and an optical image of the device arrays is shown in FIG. 1(d).I-V Characterization of 20 nm AlScN FE-diode s

[0066] The results on FE-diodes built on 20 nm thick AlScN layer are first described, and then comparisons are made with thinner devices. FIG. 2(a-f) presents the experimental I-V characteristics of FE-diodes that includes a 20 nm AlScN layer, an A1OXIL with thicknesses varying from 0 to 5 nm, an Al bottom electrode, and a Cr or Ti top electrode. The driving voltage is applied to the bottom electrode while the top electrode is grounded. The devices display an ON / OFF ratio and asymmetric I-V characteristics between the positive and negative side in devices with both Cr and Ti top electrodes. The inclusion of Cr allows verification for the resistive switching is triggered by the ferroelectric switching and is not due to Ti atom diffusion forming a current path as is the case in conductive bridge oxide memristors.

[0067] The ON / OFF and rectification ratios of the 20 nm AlScN FE-diodes are extracted from the I-V characteristics and plotted against IL thickness in FIG. 2(g-h). The rectification ratio is extracted for the devices at the point of the maximum ON / OFF ratio. This is because it is preferable to apply the read voltage at the point of largest ON / OFF ratio, and a large rectification ratio at this point enhances self-rectification characteristics that suppress sneak current paths in crossbar arrays. A significant increase is observed in both ON / OFF ratio and rectification ratio vis-a-vis control samples at large (>3 nm) IL thicknesses. To interpret these results, a precise physical model for the I-V characteristic is presented, which is described in the following section.Compact Modeling of AlScN FE-diode I-V Characteristics

[0068] To understand the I-V characteristics of our FE-diodes in detail, a ID compact model is developed, that accounts for all electrostatics as well as band and defect induced transport within the band-gap. Due to neutral-level traps in AlScN created by nitrogen24-10543 / 103241.007431 vacancies and the polarization-induced lowering of the tunneling barrier to these traps as illustrated in FIG. 3(a), the LRS I-V characteristics of the devices are well-described by the bulk-limited Poole-Frenkel (P-F) emission model.

[0069] In contrast, the HRS characteristics contain several distinct regions. Of particular interest is the low-bias, low-current regime that supports the largest ON / OFF ratio observed in the device. In this regime, the tunneling barrier to traps in AlScN is large. As such, the current is interface-limited, where direct tunneling (DT) to trap sites and thermionic emission (TI) over the barrier are two possible mechanisms for carrier injection into AlScN (FIG. 3(b)). For low biases or thick barriers, TI is the limiting mechanism for carrier transport as illustrated in FIG. 3(b). IL insertion introduces a thicker barrier and extends the active range of TI, facilitating a decrease in off-state current and an increase in the ON / OFF ratio. Furthermore, a thicker IL exponentially suppresses the effect of DT to trap sites, further lowering the off-state current. This results in the significantly superior ON / OFF ratios in thick (>2 nm) ILs compared to thinner ILs as shown in FIG. 2(g). Increasing the IL thickness also enhances the asymmetry of the device, leading to larger rectification ratios shown in FIG. 2(h).IL-induced Switchins Voltage Reduction in AlScN FE-diodes

[0070] An interesting and counterintuitive observation is made in the AlScN FE- diodes. Notably, the ferroelectric switching voltage (Vsw) of the FE-diodes can decrease with increasing IL thickness. This is counterintuitive since any non-ferroelectric insulating layer in a FE capacitor stack is expected to cause parasitic voltage drop across it, thereby increasing the Vsw. The counterintuitive observation is demonstrated through two methods of extracting Vswand then theoretically deriving the conditions of observing Vswreduction.

[0071] As described in the previous section, FE switching is accompanied by a modulation in the conduction mechanism that leads to an abrupt change of slope in the device’s HRS I-V characteristics. This enables the ability to extract the Vsw for devices of various IL thicknesses as shown in FIG.e 4(a). It can be seen that Vswdecreases up until an IL thickness of 2 nm before increasing again. To further confirm this effect, “positive up negative down” (PUND) measurements are conducted at 200 kHz across all IL thicknesses as seen FIG. 4(b). The applied voltage (Fa) necessary to get a 2Prof 6 pC / cm2was subsequently extracted and shown in FIG. 4(c). Confirming the earlier observations, an IL24-10543 / 103241.007431 thickness of 1 or 2 nm lowered the required Fa. However, an increase in IL thickness beyond 3 nm corresponded with a higher Fa than that in the control sample.

[0072] These observations can be explained by analyzing the electrostatics of the FE- diode using a single-domain Preisach model to describe the behavior of the ferroelectric layer. This simplifying assumption is made, and multidomain effects are neglected, because it allows an informative analytical solution and the tight Ecdistribution of AlScN means that its hysteresis behavior closely resembles a square P-E loop implied by the single-domain model. A more nuanced examination of multidomain effects is described in the following section.

[0073] In the single-domain model, the condition for switching is EFE = Ec, where EFE is the local electric field in the ferroelectric layer and Ecis the coercive field. By the principle of superposition, EFE = Ea+ Edep where Eais the electric field due to the applied bias and Edep is the depolarization field. The electric fields and the polarization state of the ferroelectric are shown graphically in FIG. 4 (d) without an applied bias and (e) with an applied bias. A convention is taken to have the +y direction to be positive. Solving thePoisson equation for the device yields the following expressions:

[0074] Where GSis the screening charge in metal electrode interfaces given by

[0075] Substituting into the expression for Vswgives us

[0076] As can be seen, the effect of changing IFF and SFE IS dependent on the sign of the term (Ec-PFE / SFE). If this term is positive, then decreasing IL capacitance (increasing tFE or decreasing SFE) will raise Vsw. However, if the term is negative, then decreasing IL capacitance will cause Vswto decrease. As such, the condition for achieving IL-induced Vswreduction is24-10543 / 103241.007431

[0077] From the above derivation, it can be seen that this effect is best demonstrated on materials with high Pr, low 8FE, and square-like hysteresis. AlScN satisfies these requirements well, but this result could apply to other ferroelectric systems such as Hf-xZryO, though square-like hysteresis have yet to be observed in such systems.

[0078] Further, the deviation from this theoretical result at large IL thicknesses where an increase in Vswis observed in FIG. 4(a) and FIG. 4(c). This is likely due to higher order effects like the increased suppression of PFE by the depolarization field and increased deviation from a square-shaped hysteresis loop as suggested by a multidomain simulation described later in FIG. 5(c). Nevertheless, there is only a modest increase in Vswcompared to the control sample even when the IL thickness reached a maximum of 5 nm.

[0079] This result enables the tuning of operation voltages for ferroelectric diodes and ferroelectric tunnel junctions using the MFIM structure, which could be of high relevance for the further scaling of these devices to operating at CMOS -compatible voltages.Retention and Multi-State programming in 20 nm AlScN FE-diodes

[0080] While the insertion of an IL brings multiple advantages, a thicker IL induces a higher Edep, which could lead to retention degradation. Nevertheless, the 20 nm AlScN / 4 nm A1OXFE-diode shows stable retention with an ON / OFF of 737 over 5* 104s as shown in FIG. 5(a). Due to the high Ecvalue of AlScN, even if Edepis significant in the 20 nm AlScN / 4 nm A1OXdevice, the ratio of EdepIEcremains low, ensuring good retention.

[0081] The introduction of a thicker IL in FE-diodes also makes these devices suitable for multi-state operation. This is due to their large ON / OFF ratios and their lower switching slope of P-E loop, as suggested by the self-consi stent device simulation program that implements a multi-domain Preisach FE model. A description of the model is included in the methods section. The simulated P-E loops are shown in FIG. 5(c). It is observed that IL insertion stabilizes low Prstates of the ferroelectric and sharply reduces the switching slope, enabling multi -state operation over a larger voltage range. The successful demonstration of multi-state FE-diode operation is depicted in FIG. 5(d). More importantly, it was confirmed that 32 states can be stably maintained with a significant ON / OFF ratio of 1175, even beyond 300 seconds (shown in FIG. 5(e)). This robust24-10543 / 103241.007431 performance in terms of maintaining multiple operational states indicates the considerable potential of these FE-diodes in advanced computational architectures and in-memory compute systems.FE-diodes based on 10 and 5 nm Alo.72Sco.28N

[0082] To achieve lower energy and lower voltage operation of the FE-diode, it is essential to further decrease the Esw. To this end, the thickness of AlScN can be reduced to 10 and 5 nm. FIG. 6 (a-f) presents representative I-V curves of the 10 and 5 nm AlScN FE- diodes with Ti top electrodes as a function of the IL thickness. I-V curves of three devices of the same type are shown to confirm that device-to-device variation remains minimal even as the thickness of AlScN is reduced. Remarkably, the I-V curve profiles from three different devices are highly similar, highlighting reliable device uniformity with the exception of AlScN 5 nm / IL 4 nm devices. Furthermore, both the ON / OFF and rectification ratios increase by 1-2 orders of magnitude when a thick A1OXIL was inserted for 10 and 5 nm AlScN FE-diodes (see FIG. 9 for more details).

[0083] The physical model developed for 20 nm AlScN FE-diodes still provides an excellent fit to these scaled devices (see FIG. 10 for additional details). The model offers insight into why the magnitude of the increase is more pronounced in the 5 nm AlScN compared to the 20 nm AlScN case. The enhancements in the ON / OFF ratio for the 5 nm AlScN FE-diodes exceed 570-fold, whereas the 20 nm AlScN FE-diodes exhibit an increase of approximately 17 times. This disparity likely arises due to the change in the relative proportions of IL thickness to AlScN thickness. Specifically, in the 5 nm AlScN / 4 nm IL configuration, the IL constitutes 80% of the combined thickness, while in the 20 nm AlScN / 5 nm IL device, the IL only accounts for 25%. This greater proportion of the IL thickness leads to much larger IL-induced modulation in the potential barrier as shown in FIG. 3(b). This results in a more pronounced suppression of thermionic emission and direct tunneling in the low voltage range. Consequently, a higher percentage of IL thickness relative to AlScN thickness appears beneficial for achieving a high ON / OFF ratio.

[0084] While a greater proportion of IL thickness to FE thickness can contribute to an enhanced ON / OFF ratio, theoretical predictions indicate that it also leads to an increased depolarization field as derived in equation (2) and (3). To confirm this, retention assessments are then conducted on the 10 and 5 nm AlScN FE-diodes with ILs. The 10 nm24-10543 / 103241.007431AlScN / 4 nm A10xdevice shows degradation in the ON / OFF ratio of 9 after 5* 104s (FIG. 7(a)), and the 5 nm AlScN / 2 nm A1OXsample lost its retention after 2.5* 103s (FIG. 7(b)). This is because the proportion of the IL to the FE layer is substantial (40%), leading to a significant Edep that significantly reduces the retention.

[0085] Further, the AlScN FE-diodes based on 5 and 10 nm AlScN can be compared to other two-terminal ferroelectric NVM devices reported (Table 1). The devices of the present disclosure not only exhibit BEOL-compatibility at significantly reduced FE layer thicknesses, but also demonstrate competitive ON / OFF and rectification ratios. This suggests promising potential for their practical application in future deployment as dense, self-selective, low-power embedded memory in Si CMOS processors.

[0086] Table 1: Benchmarking table. Comparison of the FE-diode in this work to other FE-diodes and ferroelectric tunneling junctions (FTJs) based on various ferroelectric materials. Maintaining CMOS BEOL-compatibility necessitates the ability to utilize existing CMOS processing equipment and to maintain a thermal budget under 400 °C. FE- diodes present self-rectifying I-V characteristics, thereby eliminating the need for a CMOS selector. In contrast, FTJs do not have this trait, potentially requiring a selector. Conclusion24-10543 / 103241.007431

[0087] In summary, scaled FE-diode NVM based on AlScN with an A1OXIL showing high ON / OFF and rectification ratios in an all BEOL -compatible process are disclosed. Furthermore, multi-state operation of the FE-diode is demonstrated, and retention is measured in all scaled devices. Presented herein is a comprehensive analysis on IL engineering with A1OXas an example, proving and emphasizing the need for higher quality and higher-k IL materials to improve retention, which constitute the most pressing challenges for further translation of AlScN FE-diodes for embedded memory applications. MethodsAl / Alo,72Sco.28N / Al deposition

[0088] Aluminum (46 nm) / Alo.72Sco.28N / Aluminum (46 nm) films were layered onto 100 mm c-axis oriented sapphire substrates with an inclination of 0.2° + / - 0.1° to the M-plane. This was done using a PVD technique, specifically using the Evatec CLUSTERLINEVR 200 II system, with a distance of 88.5 mm between the target and substrate without breaking the vacuum to avoid oxidation of Alo.72Sco.28N. The <111> Al was layered at 150 °C using an Al target power density of 12.7 W / cm2and an Ar flow rate of 20 seem, leading to a process pressure of 1.1 x 10'3mbar. This resulted in the Al being deposited at a rate of 1.3 nm / s. The Alo.72Sco.28N was deposited over the Al bottom layer by cosputtering. This process was carried out at 350 °C, with Al and Sc target power densities of 11.1 W / cm2and 7 ,07W / cm2, respectively. The N2 flow was set at 20 seem, resulting in a process pressure ranging between 8 * 10'4and 8.5 x 10'4mbar. The thickness of Alo.72Sco.28N was controlled by adjusting the deposition duration, with the layering rate set at 0.25 nm / s.Device fabrications

[0089] In the layered structure of AI / AI0.72SC0.28N / AI films, the top Al layer was stripped off by immersing the sample in a 1% Hydrofluoric (HF) solution for 80 seconds.Subsequently, an Atomic Layer Deposition (ALD) process was carried out to deposit an AI2O3 layer on Alo.72Sco.28N, utilizing the Cambridge Nanotech system from the USA. In this process, Trimethylaluminum (TMA) was employed as a metal-organic precursor, with water vapor introduced in each cycle. The top electrode patterns were intricately designed using electron-beam lithography. This was followed by the metal deposition process executed using electron-beam evaporation.Characterizations and device modeling / simulations of the FE-diodes24-10543 / 103241.007431

[0090] Transmission electron microscopy was performed on samples prepared using the focused ion beam and lift-out method. TEM was performed with a JEOL F200 instrument. The electrical measurements were performed in ambient air at room temperature using a Lakeshore probe station and a Keithley 4200A semiconductor analyzer.

[0091] The physical modeling of the device is based on the Poole-Frenkel emission and thermionic emission models with following two expressions for current density respectively:

[0092] The multidomain simulation is based on the Preisach model and implemented through a custom Python program. The c / a ratio and associated Ecand Psvalues of each domain are sampled from a Gaussian approximation to the Boltzmann distribution calculated by a previous report. Closed-form solutions of the Poisson equation for the FE- diode are used in the simulation, and the average polarization state of the ferroelectric layer is iteratively updated until convergence at each step of the applied voltage.Associated Content

[0093] Supporting information with FIGS. 8-10 showing additional STEM images with composition mapping, extracted ON / OFF and rectification ratios of various FE-diode devices as well as additional I-V characteristics with theoretical fits to them.EXEMPLARY EMBODIMENTS

[0094] The following embodiments are exemplary only and do not serve to limit the scope of the present disclosure of the appended claims. It should be understood that any part of any one or more Embodiments can be combined with any part of any other one or more Embodiments.Embodiment 1

[0095] A ferroelectric diode, comprising: a first electrode layer; a second electrode layer; a ferroelectric layer disposed between the first electrode layer and the second electrode layer; and a non-ferroelectric interlayer disposed (i) between the first electrode layer and the ferroelectric layer or (ii) between the ferroelectric layer and the second electrode layer.24-10543 / 103241.007431Embodiment 2

[0096] The ferroelectric diode of Embodiment 1, wherein the ferroelectric layer comprises Aluminum Scandium Nitride (AlScN).Embodiment 3

[0097] The ferroelectric diode of any of Embodiments 1 and 2, wherein the interlayer comprises Aluminum oxide (AlOx) or Hafnium oxide (HfOx).Embodiment 4

[0098] The ferroelectric diode of any of Embodiments 1 through 3, wherein the first electrode layer comprises Titanium (Ti) or Chromium (Cr).Embodiment 5

[0099] The ferroelectric diode of any of Embodiments 1 through 4, wherein the second electrode layer comprises Aluminum (Al) or Titanium Nitride (TiN).Embodiment 6

[0100] The ferroelectric diode of any of Embodiments 1 through 5, wherein the nonferroelectric interlayer has a thickness of 5 nm or less.Embodiment 7

[0101] The ferroelectric diode of any of Embodiments 1 through 6, wherein the ferroelectric diode comprises nonvolatile memory.Embodiment 8

[0102] The ferroelectric diode of any of Embodiments 1 through 7, wherein a switching voltage of the ferroelectric diode is less than 13 V.Embodiment 9

[0103] The ferroelectric diode of any of Embodiments 1 through 8, wherein the ferroelectric layer has a thickness of 20 nm or less.Embodiment 10

[0104] The ferroelectric diode of any of Embodiments 1 through 9, wherein anON / OFF ratio for the ferroelectric diode is greater than 3 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 1 nm. The ON / OFF ratio can be from greater than 3 up to about 1000, from greater than 3 up to about 500, from greater than 3 up to about 100, from greater than 3 up to about 50, or even from greater than 3 up to about 10.Embodiment 1124-10543 / 103241.007431

[0105] The ferroelectric diode of any of Embodiments 1 through 10, wherein an ON / OFF ratio for the ferroelectric diode is greater than 9 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 2 nm. The ON / OFF ratio can be from greater than 9 up to about 1000, from greater than 9 up to about 500, from greater than 9 up to about 100, from greater than 9 up to about 50, or even from greater than 9 up to about 10.Embodiment 12

[0106] The ferroelectric diode of any of Embodiments 1 through 11, wherein an ON / OFF ratio for the ferroelectric diode is greater than 3 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 3 nm. The ON / OFF ratio can be from greater than 3 up to about 1000, from greater than 3 up to about 500, from greater than 3 up to about 100, from greater than 3 up to about 50, or even from greater than 3 up to about 10.Embodiment 13

[0107] The ferroelectric diode of any of Embodiments 1 through 12, wherein an ON / OFF ratio for the ferroelectric diode is greater than 100 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 4 nm. The ON / OFF ratio can be from greater than 100 up to about 1000, from greater than 100 up to about 500, from greater than 100 up to about 200, or even from greater than 100 up to about 150.Embodiment 14

[0108] The ferroelectric diode of any of Embodiments 1 through 13, wherein an ON / OFF ratio for the ferroelectric diode is greater than 150 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 5 nm. The ON / OFF ratio can be from greater than 150 up to about 1000, from greater than 150 up to about 500, from greater than 150 up to about 200, or even from greater than 150 up to about 175.Embodiment 15

[0109] The ferroelectric diode of any of Embodiments 1 through 14, wherein the ferroelectric diode is configured with at least 32 multi-states having an ON / OFF ratio of greater than 1,100 over a 300 s time period.Embodiment 1624-10543 / 103241.007431

[0110] A device, the device comprising a ferroelectric diode according to any one of Embodiments 1-15.Embodiment 17

[0111] The device of Embodiment 16, wherein the device is characterized as a memory device.Embodiment 18

[0112] The device of Embodiment 17, wherein the device is comprised in a computing device.Embodiment 19

[0113] A method, the method comprising fabricating a ferroelectric diode according to any one of Embodiments 1-15.Embodiment 20

[0114] The method of Embodiment 19, wherein the method is performed at 400 °C or less, optionally at 150 °C or less.

Claims

24-10543 / 103241.007431What is Claimed:

1. A ferroelectric diode comprising: a first electrode layer; a second electrode layer; a ferroelectric layer disposed between the first electrode layer and the second electrode layer; and a non-ferroelectric interlayer disposed between (i) the first electrode layer and the ferroelectric layer or (ii) between the ferroelectric layer and the second electrode layer.

2. The ferroelectric diode of claim 1, wherein the ferroelectric layer comprises Aluminum Scandium Nitride (AlScN).

3. The ferroelectric diode of claim 1, wherein the interlayer comprises aluminum oxide (Al Ox) or hafnium oxide (HfOx).

4. The ferroelectric diode of claim 1, wherein the first electrode layer comprises titanium (Ti) or chromium (Cr).

5. The ferroelectric diode of claim 1, wherein the second electrode layer comprises aluminum (Al) or titanium nitride (TiN).

6. The ferroelectric diode of claim 1, wherein the non-ferroelectric interlayer has a thickness of 5 nm or less.

7. The ferroelectric diode of claim 1, wherein the ferroelectric diode comprises nonvolatile memory.

8. The ferroelectric diode of claim 1, wherein a switching voltage of the ferroelectric diode is less than 13 V.

9. The ferroelectric diode of claim 1, wherein the ferroelectric layer has a thickness of 20 nm or less.24-10543 / 103241.00743110. The ferroelectric diode of claim 1, wherein an ON / OFF ratio for the ferroelectric diode is greater than 3 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 1 nm.

11. The ferroelectric diode of claim 1, wherein an ON / OFF ratio for the ferroelectric diode is greater than 9 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 2 nm.

12. The ferroelectric diode of claim 1, wherein an ON / OFF ratio for the ferroelectric diode is greater than 3 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 3 nm.

13. The ferroelectric diode of claim 1, wherein an ON / OFF ratio for the ferroelectric diode is greater than 100 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 4 nm.

14. The ferroelectric diode of claim 1, wherein an ON / OFF ratio for the ferroelectric diode is greater than 150 over a 1,000 s time period when the non-ferroelectric interlayer has a thickness of approximately 5 nm.

15. The ferroelectric diode of claim 1, wherein the ferroelectric diode is configured with at least 32 multi-states having an ON / OFF ratio of greater than 1,100 over a 300 s time period.

16. A device, the device comprising a ferroelectric diode according to claim 1.

17. The device of claim 16, wherein the device is characterized as a memory device.

18. The device of claim 17, wherein the device is comprised in a computing device.24-10543 / 103241.00743119. A method, the method comprising fabricating a ferroelectric diode according to claim 1.

20. The method of claim 19, wherein the method is performed at 400 °C or less, optionally at 150 °C or less.

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