Vector combination instruction

Abstract

There is provided an apparatus, a method, and a computer program. The apparatus is provided with a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements. The apparatus is also provided with decoder circuitry responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying first and second input vector registers. The apparatus is also provided with processing circuitry responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements comprising at least a first element extracted from the first input vector register and a second element extracted from the second input vector register. The extremum calculating procedure comprises outputting an extremum value from a plurality of arithmetic results, each generated from a respective group of elements by combining, using an arithmetic operation, the first and second elements.

Description

[0001]VECTOR COMBINATION INSTRUCTION The present invention relates to data processing. Furthermore, the present invention relates to an apparatus, a method, and a computer program. Apparatuses for data processing may be provided with decoder circuitry arranged to receive instructions and, in response to receipt of those instructions, to generate control signals to control processing circuitry to perform operations. According to some configurations of the present techniques there is provided an apparatus comprising: a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements; decoder circuitry responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying a first input vector register and a second input vector register; and processing circuitry responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements, each of the plurality of groups of elements comprising at least a first element extracted from the first input vector register and a second element extracted from the second input vector register, and outputting an extremum value selected from a set comprising a plurality of arithmetic results, each of the arithmetic results generated from a respective group of elements of the plurality of groups of elements by combining, using an arithmetic operation, the first element and the second element of the respective group of elements. According to some configurations of the present techniques there is provided a method of operating an apparatus comprising a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements, the method comprising: in response to a fused extremum instruction, generating control signals, the fused extremum instruction specifying a first input vector register and a second input vector register; and in response to the control signals, performing an extremum calculation procedure comprising extracting a plurality of groups of elements, each of the plurality of groups of elements comprising at least a first element extracted from the first input vector register and a second element extracted from the second input vector register, and outputting an extremum value selected from a set comprising a plurality of arithmetic results, each of the arithmetic results generated from a respective group of elements of the plurality of groups of elements by combining, using an arithmetic operation, the first element and the second element of the respective group of elements. According to some configurations of the present techniques there is provided a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: a plurality of vector data structures, each of the plurality of vector data structures configured to store a plurality of elements; decoder program logic responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying a first input vector register and a second input vector register; and processing program logic responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements, each of the plurality of groups of elements comprising at least a first element extracted from the first input vector data structure and a second element extracted from the second input vector data structure, and outputting an extremum value selected from a set comprising a plurality of arithmetic results, each of the arithmetic results generated from a respective group of elements of the plurality of groups of elements by combining, using an arithmetic operation, the first element and the second element of the respective group of elements. According to some configurations of the present techniques the computer program may be recorded on a computer readable storage medium. According to some configurations of the present techniques the computer readable storage medium may be a non-transitory computer readable storage medium. The present techniques will be described further, by way of example only, with reference to configurations thereof as illustrated in the accompanying drawings, in which: Figure 1 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 2 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 3 schematically illustrates an example use case of an apparatus according to some configurations of the present techniques; Figure 4 schematically illustrates an example use case of an apparatus according to some configurations of the present techniques; Figure 5 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 6 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 7 schematically illustrates an extremum calculation according to some configurations of the present techniques; Figure 8 schematically illustrates an extremum calculation according to some configurations of the present techniques; Figure 9 schematically illustrates an example use case of an apparatus according to some configurations of the present techniques; Figure 10 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 11 schematically illustrates a sequence of steps carried out according to some configurations of the present techniques; and Figure 12 schematically illustrates a simulator implementation according to some configurations of the present techniques. Some apparatuses (for example, data processing apparatuses) are provided with decoder circuitry which is provided in combination with processing circuitry and is used to control the processing circuitry to perform processing operations. The decoder circuitry is responsive to instructions included in an Instruction Set Architecture (ISA). The ISA defines the set of instructions that can be used by a programmer or compiler to control the processing circuitry. Instructions included in the ISA are carefully chosen and are limited by the encoding space provided for the instructions. Often the inclusion of a new instruction may result in an existing instruction being removed and, as such, the designer of the ISA may require significant motivation to incorporate new instructions into the ISA. An apparatus implementing a given ISA has freedom to choose the precise circuitry arrangements that are provided for each instruction in the ISA and the manner in which instructions of the ISA are implemented may vary from system to system. In other words, the ISA defines the function that the apparatus should achieve in response to a given instruction, but provides freedom to the designer to implement the instruction in any way and according to particular design constraints associated with the apparatus. Provision of a carefully chosen instruction as part of an ISA provides advantages in terms of improved code density for workloads utilising the instruction which, in turn, improves the overall system efficiency. In some configurations of the present techniques there is provided an apparatus comprising: a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements. The apparatus is also provided with decoder circuitry responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying a first input vector register and a second input vector register. The apparatus is also provided with processing circuitry responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements. Each of the plurality of groups of elements comprises eat least a first element extracted from the first input vector register and a second element extracted from the second input vector register. The extremum calculation procedure also includes outputting an extremum value selected from a set comprising a plurality of arithmetic results, each of the arithmetic results generated from a respective group of elements of the plurality of groups of elements by combining, using an arithmetic operation, the first element and the second element of the respective group of elements. The inventors of the present techniques have recognised that there are some workloads, which are common in dynamic programming, which make use of a combination of arithmetic combination calculations, e.g., the combining of a group of elements through an arithmetic operation, and the calculation of an extremum of plural combined groups of elements. Whilst the summation of plural groups elements may be implemented as a vector operation in which the summation for each of the groups is performed in a lane of vector processing circuitry, and the extremum calculation may be implemented as a separate cross lane operation or as one or more scalar operations, this may take up multiple instructions and result in redundancies in terms of data manipulation and programming overheads. The decoder circuitry provided as part of the apparatus is therefore responsive to a fused extremum instruction which specifies first and second input vector registers. The decoder circuitry is responsive to receipt of such an instruction to perform an extremum calculation procedure. The extremum calculation procedure comprises extracting the groups of elements from the first and second input vector registers. The groups of elements include at least a pair of elements. In particular, each of the groups includes a first element extracted from the first vector register and a second element extracted from the second vector register. The first element and the second element are then combined for each of the groups to form arithmetic results. In other words, for each group of extracted elements, an arithmetic result is calculated from the first element and the second element belonging to that group. The extremum calculation procedure then calculates an extremum from the set comprising the arithmetic results. The fused extremum instruction is a single instruction and the extremum calculation procedure is carried out in response to that single instruction. The provision of the fused extremum instruction as a single instruction allows for efficient implementation of some dynamic programming algorithms. One example of such an algorithm is the matrix population stage of the Smith-Waterman algorithm which is used in the field of genomics. The Smith-Waterman algorithm comprises three stages: matrix creation, matrix population, and trace back. Of these stages, the matrix population stage requires an iterative application of arithmetic combination and extremum calculation and can take up to 50% of the total runtime required for the algorithm. The provision of the fused extremum instruction reduces the overall instruction count of the matrix population stage, reducing programing overhead and resulting in improved efficiency of the algorithm. In some configurations for each of the plurality of groups of elements the first element is extracted from an element position in the first input vector register and the second element is extracted from the element position in the second input vector register. In other words, for first and second input vector registers each comprising a plurality of element positions the first and second elements are extracted from the same element position in the first and second input vector registers respectively. Alternatively, the positions from which the first and second elements are extracted may be staggered or offset from one another by a predefined amount. Whilst the positions from which each of the plurality of groups of elements may be defined differently in different configurations, in some configurations each of the plurality of groups of elements are extracted from consecutive positions in the first input vector register and the second input vector register. The consecutive positions may be corresponding consecutive positions in each of the vector register, e.g., elements are extracted from the same set of corresponding positions of the first and second input vector registers. Alternatively, the consecutive positions of the first and second input vector registers may be a different set of consecutive positions in each of the first and second input vector registers. The consecutive positions may be consecutive positions at any point within the first and second vector registers. For example, the consecutive positions may be a most significant set of consecutive positions, a least significant set of consecutive positions, or a set of consecutive positions taken from a point in the vector register that excludes the most significant and least significant positions. In some configurations the processing circuitry is configured to perform processing in a plurality of vector processing lanes and the plurality of groups of elements comprises groups of elements from two or more of the plurality of vector processing lanes. For a vector processing apparatus arranged to perform processing in a plurality of lanes, elements within a given lane are typically combined with other elements in the same lane. Whilst there are advantages to restricting vector processing apparatuses in this way, for example, the separation of processing into separate processing lanes provides independence of the processing allowing reduced circuitry implementations in which different lanes of the vector processing can be performed sequentially using the same physical hardware, the provision of the fused extremum instruction capable of combining elements from two or more of the plurality of vector processing lanes results in an increased flexibility of the fused extremum operation. In addition to specifying the first and second input vector register, in some configurations the fused extremum instruction specifies an output register and the processing circuitry is configured to store the extremum value to the output register. The output register may be a scalar register or a vector register. Where the output register is a vector register the fused extremum instruction may specify a position of the output vector register into which the extremum value is to be stored. The output register may be specified explicitly in the fused extremum instruction. Alternatively, the output register may be implicitly defined in the fused extremum register and may be a particular (e.g., a predefined) position in one of the first or second input vector registers. Whilst in some configurations all elements of the first and second input vector register may be incorporated in the calculation of the arithmetic values, in some configurations the plurality of groups of elements comprises a subset of elements extracted from the first input vector register grouped with a corresponding subset of elements extracted from the second input vector register; and the subset of elements excludes at least one element of the first input vector register and the corresponding subset of elements excludes at least one element of the second input vector register. The at least one element that is excluded from the subset of elements may be predefined, e.g., hard coded into the instruction. Alternatively, the at least one element that is excluded from the subset may be specified in the fused extremum instruction. The at least one element may be specified explicitly, or may be implicit through omission of that element in a group of elements specified as being included in the subset. In some configurations the processing circuitry is configured to perform the extremum calculation procedure for a plurality of subsets of elements of the first input vector register and the second input vector register. The fused extremum instruction may specify the elements of the first and second input vectors to be included in the subset either implicitly, e.g., through the provision of a specific type of fused extremum instruction having an opcode that specifies the subsets, or explicitly, e.g., through provision of one or more parameters in the instruction to identify the subsets that can be specified by the programmer or compiler. Whilst overlapping subsets may be provided in some configurations, in some configurations the plurality of subsets of elements are non-overlapping subsets. The first and second input vector registers in such configurations are sufficiently wide (contain a sufficiently large number of elements) that plural instances of the extremum calculation procedure can fit within the width of the vector register. For example, if the extremum calculation procedure comprises extracting N groups of elements, where N is any integer greater than one, then the input vector registers have width of greater than or equal to K times N where K is any integer greater than one. In some configurations the processing circuitry is configured to output the extremum value for each of the plurality of subsets of elements in consecutive positions of an output vector register. Alternatively, the processing circuitry may be configured to output the extremum values in positions of the output vector register specified as part of the fused extremum instruction. In further configurations, the processing circuitry may be configured to output the extremum values into a plurality of different scalar registers or a plurality of different output vector registers. In some configurations the fused extremum instruction is a matrix population instruction for iterative population of elements of a matrix. As discussed, the fused extremum instruction may be beneficially used in the matrix population stage of the Smith-Waterman algorithm. It will be readily apparent to the skilled person that the fused extremum instruction is not limited to the Smith-Waterman algorithm and that the fused extremum instruction may find use in, for example, optimisation algorithms such as the Floyd-Warshall and Bellman-Ford algorithms for finding the shortest paths in weighted graphs and Viterbi decoding in telecommunications. Further applications may for example also be found in the Needleman-Wunsch algorithm for protein alignment, determining the longest common subsequence of two input strings, and pair hidden Markov models in variant callers. In some configurations the set comprises a zero value. In other words, the extremum value is calculated from the arithmetic results and the zero value. Such an approach can be used to prevent the extremum value being negative (e.g., in the case that the extremum value being calculated is a maximum) or from being positive (e.g., in the case that the extremum value being calculated is a minimum). In addition to the first and second input vector registers, in some configurations the fused extremum instruction specifies a third input register; and the processing circuitry is configured to predicate the set of elements from which the extremum value is selected based on values of respective third elements extracted from the third input register. The third input register may be a predicate register comprised in a set of predicate registers that are provided as part of the apparatus. The third input register acts as a mask to select which elements of the first input vector register and the second input vector register are used in the extremum calculation procedure. For example, where elements of the third input register take a first predefined value (e.g., one of a logical zero and a logical one) the corresponding elements of the first and second input vector registers may be included in the extremum calculation procedure. In addition, where elements of the third input vector register take a second predefined value (e.g., the other of the logical zero and the logical one) the corresponding elements of the first and second input vector registers may be excluded (omitted) from the extremum calculation procedure. In some configurations the arithmetic operation is an addition operation or a subtraction operation. The addition or subtraction may be a signed operation receiving signed input values. Alternatively, the addition or subtraction may receive non-signed inputs which may be added or subtracted as defined by the arithmetic operation. In some configurations the extremum value is a maximum value or a minimum value. The choice of the extremum value may be specified in the instruction encoding, e.g., in the instructions opcode. In some configurations multiple fused extremum instructions may be provided, e.g., one in which the extremum is a maximum and one in which the extremum is a minimum. Alternatively, the choice of the maximum or minimum may be provided as a parameter in the fused extremum instruction which can be set by e.g., a programmer or a compiler. In some configurations the extremum value may be the value of maximum magnitude. In some configurations the extremum value is rectified extremum value. A rectified extremum value is, where the extremum is the maximum value, the maximum of the set where that maximum is positive and zero otherwise; and where the extremum is a minimum value, the minimum of the set where the minimum is negative and zero otherwise. The type of elements accessed by the fused extremum instruction may be of any type and, in some configurations, the plurality of elements comprises: 8-bit elements; 16-bit elements; 32- bit elements, or 64-bit elements. In some configurations the plurality of elements comprises: a plurality of integer elements; a plurality of floating point elements; a plurality of single precision elements; or a plurality of double precision elements. In some configurations the plurality of elements comprises: signed elements; or unsigned elements. Particular configurations of the invention will now be described with reference to the accompanying figures. Figure 1 schematically illustrates an example of a data processing apparatus 2 according to some configurations of the present techniques. The data processing apparatus 2 has a processing pipeline 4 which includes a number of pipeline stages. In this example, the pipeline stages include a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by remaining stages of the pipeline; an issue stage 12 for checking whether operands required for the micro-operations are available in a register file 14 and issuing micro-operations for execution once the required operands for a given micro-operation are available; an execute stage 16 for executing data processing operations corresponding to the micro-operations, by processing operands read from the register file 14 to generate result values; and a writeback stage 18 for writing the results of the processing back to the register file 14. It will be appreciated that this is merely one example of possible pipeline architecture, and other systems may have additional stages or a different configuration of stages. For example, in an out-of-order processor an additional register renaming stage could be included for mapping architectural registers specified by program instructions or micro-operations to physical register specifiers identifying physical registers in the register file 14. In some examples, there may be a one-to-one relationship between program instructions decoded by the decode stage 10 and the corresponding micro-operations processed by the execute stage. It is also possible for there to be a one-to-many or many-to-one relationship between program instructions and micro-operations, so that, for example, a single program instruction may be split into two or more micro-operations, or two or more program instructions may be fused to be processed as a single micro-operation. The execute stage 16 includes a number of processing units, for executing different classes of processing operation. For example the execution units may include an arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations; a floating-point unit 22 for performing operations on floating-point values, a branch unit 24 for evaluating the outcome of branch operations and adjusting the program counter which represents the current point of execution accordingly; and a load / store unit 28 for performing load / store operations to access data in a memory system 8, 30, 32, 34. In this example the memory system include a level one data cache 30, the level one instruction cache 8, a shared level two cache 32 and main system memory 34. It will be appreciated that this is just one example of a possible memory hierarchy and other arrangements of caches can be provided. The specific types of processing unit 20 to 28 shown in the execute stage 16 are just one example, and other implementations may have a different set of processing units or could include multiple instances of the same type of processing unit so that multiple micro-operations of the same type can be handled in parallel. It will be appreciated that Figure 1 is merely a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements not illustrated for conciseness, such as branch prediction mechanisms or address translation or memory management mechanisms. Figure 2 schematically illustrates an apparatus 40 according to some configurations of the present techniques. The apparatus 40 is provided with decoder circuitry 44, processing circuitry 46 and registers 42. The registers 42 comprise a plurality of vector registers configured to store vector operands to be used by the processing circuitry 46 during processing operations. The registers 42 may also comprise a plurality of scalar registers configured to store scalar operands to be used by the processing circuitry 46 during processing operations. The decoder circuitry 44 is responsive to receipt of instructions that form part of an instruction set architecture to generate control signals to control the processing circuitry 46. In particular, the decoder circuitry 44 is responsive to a fused extremum instruction specifying a first input vector register, storing a first input vector, and a second input vector register, storing a second input vector, to generate control signals to cause the processing circuitry 46 to perform an extremum calculation procedure. The processing circuitry 46 is responsive to the control signals to perform the extremum calculation procedure. The extremum calculation procedure includes extracting a plurality of groups of elements from the first and second source vector registers. In particular, the processing circuitry 46 extracts, for each of the plurality of groups of elements, at least a first element from the first input vector and a second element from the second input vector. The processing circuitry 46 proceeds, for each of the plurality of groups of elements to the elements within that group using an arithmetic operation to generate an arithmetic result. The extremum calculation procedure also includes calculating an extremum from the set comprising the arithmetic results. In one example use case, the fused extremum instruction can be used in a matrix population stage, e.g., for the Smith-Waterman algorithm. The matrix population stage of the Smith- Waterman algorithm comprises, subsequent to an initiation stage, iteratively generating elements of a matrix using the following formulae: Here the notation indicates the element located in the i-th row and the j-th column of H, theparameters ^^(^^(^^), ^^(^^)), ^^^^^^^^, and ^^^^^^^^ are specific parameters for the matrix population in theSmith-Waterman algorithm and their precise definition is not necessary in order to understand the invention. From a computational point of view, the calculation can be rewritten as where ^^^^ is an output register to store ^^1(0) is the zeroth element of the first input vectorregister storing ^^(^^ − 1, ^^ − 1), ^^1(1) is the first element of the first input vector register storing^^(^^ − 1, ^^), ^^1(2) is the second element of the first input vector register storing ^^(^^, ^^ − 1), ^^2(0)is the zeroth element of the second input vector register storing ^^(^^(^^), ^^(^^)), ^^2(0) is the firstelement of the second input vector register storing ^^^^^^^^, and ^^2(0) is the second element of the second input vector register storing ^^^^^^^^. The matrix population stage can therefore be performed by initialising a first row and afirst column of the matrix ^^ (such that ^^(^^, 0) and ^^(0, ^^) are known) and repeatedly applying thefollowing steps: 1. Load the appropriate data into the first input vector register and the second input vector register; and 2. Use the fused extremum calculation instruction to calculate ^^^^. Figure 3 schematically illustrates the application the population (generation) of elements in the matrix ^^ on a per row basis. In the illustrated configuration, three snapshots of the matrix during population are provided for an 8 by 8 matrix with rows indexed with the index ^^ andcolumns indexed with the index ^^. The first row ^^ = 0 and the first column ^^ = 0 have beeninitialised, based on an initialisation criteria, to an element “O”, where the symbol “O” is used to represent that the element of the matrix is populated. The symbol “O” should not be construed as identifying the value of that element and two elements denoted by the symbol “O” should not be construed as having elements of the same value. The symbol “X” in figure 3 is used to denote an element that is to be calculated. The matrix is populated on a per-row basis with each row being populated in turn. The row population is performed using the fused extremum instruction. Figure 3(a) illustrates thepopulation of element ^^ = 1, ^^ = 1 using elements in three adjacent positions of the matrix. In theillustrated example, elements in the positions (^^ − 1, ^^), (^^, ^^ − 1), and (^^ − 1, ^^ − 1) are stored inthe first input vector register as indicated above. The parameters ^^(^^(^^), ^^(^^)), ^^^^^^^^, and ^^^^^^^^are calculated and stored in the second input vector register ^^2and the element of ^^ stored inposition is calculated. This process is repeated, first incrementing ^^, as illustrated in figure3(b), and when the entire row ^^ = 1 has been calculated, ^^ is incremented and ^^ is reset to 1 so thatthe next row can be calculated as illustrated in figure 3(c). Figure 4 schematically illustrates an alternative use case example of the fused extremum instruction to populate the matrix ^^. In figure 4 the matrix is populated on a per column basis with the matrix being populated one column at a time. The initialisation and population of element(^^ = 1, ^^ = 1), as illustrated in figure 4(a) is performed in the same manner as described in relationto figure 3. This process is repeated, first incrementing ^^, as illustrated in figure 4(b), and whenthe entire column ^^ = 1 has been calculated, ^^ is incremented and ^^ is reset to 1 so that the nextcolumn can be calculated as illustrated in figure 4(c). Figure 5 schematically illustrates an example of circuitry used to implement the extremum calculation procedure according to some configurations of the present techniques. The extremum procedure comprises extracting elements from a first input vector register 50 and from a second input vector register 52. In the illustrated configurations four elements are extracted from each of the first input vector register 50 and the second input vector register 52. These elements are combined using arithmetic combination circuits 54. The arithmetic combination circuits 54 are configured to perform addition of the extracted elements. The circuitry is arranged to perform the calculation in plural processing lanes. Four processing lanes are illustrated and the arithmetic combination circuits 54 are configured to take values from within a specific processing lane. The zeroth arithmetic combination unit 54(0) receives a first input element from lane 0 of the first input vector register 50 and a second input element from lane 0 of the second input vector register 52, and outputs the sum of the first input element and the second input element as a zeroth arithmetic result; the first arithmetic combination unit 54(1) receives a first input element from lane 1 of the first input vector register 50 and a second input element from lane 1 of the second input vector register 52, and outputs the sum of the first input element and the second input element as a first arithmetic result; the second arithmetic combination unit 54(2) receives a first input element from lane 2 of the first input vector register 50 and a second input element from lane 2 of the second input vector register 52, and outputs the sum of the first input element and the second input element as a second arithmetic result; and the third arithmetic combination unit 54(3) receives a first input element from lane 3 of the first input vector register 50 and a second input element from lane 3 of the second input vector register 52, and outputs the sum of the first input element and the second input element as a third arithmetic result. The zeroth, first, second, and third arithmetic results are passed to the extremum calculation unit 56 which calculates the extremum value (e.g., the maximum or the minimum of the input values) and outputs the extremum. Figure 6 schematically illustrates a further example of circuitry used to implement the extremum calculation procedure according to some configurations of the present techniques. The extremum procedure comprises extracting elements from a first input vector register 60 and from a second input vector register 62 and performing a predicated extremum calculation procedure based on a predicate contained in a third input vector register 66. In the illustrated configurations four elements are extracted from each of the first input vector register 60 and the second input vector register 62. These elements are combined using arithmetic combination circuits 64. The arithmetic combination circuits 64 are configured to perform addition of the extracted elements. The circuitry is arranged to perform the calculation in plural processing lanes. Four processing lanes are illustrated and the arithmetic combination circuits 64 are configured to take values from within a specific processing lane. The zeroth arithmetic combination unit 64(0) receives a first input element from lane 0 of the first input vector register 60 and a second input element from lane 0 of the second input vector register 62, and outputs the sum of the first input element and the second input element as a zeroth arithmetic result; the first arithmetic combination unit 64(1) receives a first input element from lane 1 of the first input vector register 60 and a second input element from lane 1 of the second input vector register 62, and outputs the sum of the first input element and the second input element as a first arithmetic result; the second arithmetic combination unit 64(2) receives a first input element from lane 2 of the first input vector register 60 and a second input element from lane 2 of the second input vector register 62, and outputs the sum of the first input element and the second input element as a second arithmetic result; and the third arithmetic combination unit 64(3) receives a first input element from lane 3 of the first input vector register 60 and a second input element from lane 3 of the second input vector register 62, and outputs the sum of the first input element and the second input element as a third arithmetic result. The zeroth, first, second, and third arithmetic results are passed to the extremum calculation unit 68 in dependence on the value of a corresponding predicate element in the third input vector register 66. Each arithmetic result is passed to the extremum calculation circuitry if the predicate bit of the third input vector register 66 in the corresponding lane is a one and is not passed to the extremum calculation circuitry if the predicate bit of the third input vector register 66 in the corresponding lane is a zero. In the illustrated example, the predicate bit in lane 0 of the third input vector register 66 is a one so the zeroth arithmetic result is passed to the extremum calculation circuitry 68, the predicate bit in lane 1 of the third input vector register 66 is a zero so the first arithmetic result is not passed to the extremum calculation circuitry 68, the predicate bit in lane 2 of the third input vector register 66 is a one so the second arithmetic result is passed to the extremum calculation circuitry 68, and the predicate bit in lane 3 of the third input vector register 66 is a one so the third arithmetic result is passed to the extremum calculation circuitry 68. The extremum calculation circuity therefore receives the arithmetic results for which the corresponding predicate bit is a one (the zeroth, second and third arithmetic results in the illustrated configuration) and calculates the extremum of those values. Whilst the extremum calculation procedure of figures 5 and 6 schematically illustrates the use of addition circuitry to perform the arithmetic combination operation, it will be readily apparent to the skilled person that, in alternative configurations, the addition circuitry could be replaced with alternative arithmetic combination circuitry, e.g., subtraction circuitry, or multiplication circuitry. Furthermore, in some alternative configurations the predicate values in the third input vector register 66 may be applied prior to the calculation of the arithmetic results rather than subsequent to the calculation of those results. Figure 7 schematically illustrates an example of extremum calculation circuitry 78 according to some configurations of the present techniques. The extremum calculation circuitry 78 receives three input values denoted A, B, and C. Values A and B are passed to first comparison circuitry 70 which determines whether the value of A is greater than the value of B. If A is greater than B, then the first comparison circuitry 70 outputs a logical one. Alternatively, if A is not greater than B (A is less than or equal to B), then the first comparison circuitry 70 outputs a logical zero. The output from the first comparison circuitry 70 is coupled to the input of de-multiplexing circuitry 72 which also receives inputs A and B. If the de-multiplexing circuitry 72 receives a logical zero from the first comparison circuitry 70, then it selects input B to be output (denoted as X). If the de-multiplexing circuitry 72 receives a logical one from the first comparison circuitry 70, then it selects input A to be output (denoted as X). The output X of the de-multiplexing circuitry 72 (e.g., the greater of A and B) is passed to the second comparison circuitry 74 along with the input C. The second comparison circuitry 74 compares the values of C and X and outputs a logical one if C is greater than X and outputs a logical zero if C is not greater than X. The output of the second comparison circuitry 74 is passed to the de-multiplexing circuitry 76. The de- multiplexing circuitry 76 also receives inputs C and X. If the de-multiplexing circuitry 76 receives a logical zero from the second comparison circuitry 74, then it selects input X to be output as the extremum value, e.g., the extremum value that is output is the greater of inputs A and B. If the de-multiplexing circuitry 76 receives a logical one from the second comparison circuitry 74, then it selects input C to be output as the extremum value. Figure 8 schematically illustrates alternative extremum calculation circuitry 90 which calculates the rectified maximum value as the extremum. In particular, extremum calculation circuitry 90 receives three input values denoted A, B, and C. Values A and B are passed to first comparison circuitry 92 which determines whether the value of A is greater than the value of B. If A is greater than B, then the first comparison circuitry 92 outputs a logical one. Alternatively, if A is not greater than B, then the first comparison circuitry 92 outputs a logical zero. The output from the first comparison circuitry 92 is coupled to the input of de-multiplexing circuitry 94 which also receives inputs A and B. If the de-multiplexing circuitry 94 receives a logical zero from the first comparison circuitry 92, then it selects input B to be output (denoted as X). If the de- multiplexing circuitry 94 receives a logical one from the first comparison circuitry 92, then it selects input A to be output (denoted as X). The output X of the de-multiplexing circuitry 94 is passed to the second comparison circuitry 96 along with the input C. The second comparison circuitry 96 compares the values of C and X and outputs a logical one if C is greater than X and outputs a logical zero if C is not greater than X. The output of the second comparison circuitry 96 is passed to the de-multiplexing circuitry 98. The de-multiplexing circuitry 98 also receives inputs C and X. If the de-multiplexing circuitry 98 receives a logical zero from the second comparison circuitry 96, then it selects input X to be output (denoted as Y). If the de-multiplexing circuitry 98 receives a logical one from the second comparison circuitry 96, then it selects input C to be output (denoted as Y). At this stage, the output Y is the greater of A, B, and C. The output Y of the de-multiplexing circuitry 98 is passed to the third comparison circuitry 102. The third comparison circuitry 102 compares the values of Y and zero and outputs a logical one if Y is greater than zero and outputs a logical zero if Y is not greater than zero. The output of the third comparison circuitry 102 is passed to the de-multiplexing circuitry 100. The de-multiplexing circuitry 100 also receives inputs Y and zero. If the de-multiplexing circuitry 100 receives a logical zero from the third comparison circuitry 102, then it selects zero to be output as the extremum value. If the de-multiplexing circuitry 100 receives a logical one from the third comparison circuitry 102, then it selects input Y (the greater of A, B, and C) to be output as the extremum value. In alternative configurations, the circuits schematically illustrated in figures 7 and 8 could each be modified to receive a greater or smaller number of inputs by coupling a larger or smaller number of comparison circuits and de-multiplexing circuits together. The comparison circuits of figures 7 and 8 may, in some configurations be configured to calculate a minimum value, e.g., by outputting the logical inverse of the outputs identified in relation to figures 7 and 8. Figure 9 schematically illustrates an alternative use case example of the fused extremum instruction being used to populate the matrix ^^. In figure 9 the matrix is populated on a diagonal basis with the matrix being populated one diagonal at a time. The initialisation and population ofelement (^^ = 1, ^^ = 1), as illustrated in figure 9(a) is performed in the same manner as describedin relation to figure 3. Once element (^^ = 1, ^^ = 1) has been populated, the next diagonal can bepopulated based on the already populated elements of the matrix ^^. As illustrated in figure 9(b),elements (^^ = 1, ^^ = 2) and (^^ = 2, ^^ = 1) can both be populated as the input elements requiredfor the scheme described above are already present in the matrix ^^. Subsequently, and asillustrated in figure 9(c), elements (^^ = 1, ^^ = 3), (^^ = 2, ^^ = 2) and (^^ = 3, ^^ = 1) can each bepopulated as the input elements required for the scheme described above are already present in the matrix ^^. Using the scheme illustrated in figure 9, it is possible to calculate multiple elements inparallel because, taking figure 9(b) as an example, the elements on the diagonal (^^ = 1, ^^ = 2) and(^^ = 2, ^^ = 1), are not dependent on one another. Figure 10 schematically illustrates an examplecircuitry arrangement for performing multiple extremum calculation procedures in parallel according to some configurations of the present techniques. The circuitry receives a first input vector register 110 and a second input vector register 112. The circuitry is arranged to perform processing in a plurality of lanes, in this case, the processing is divided into eight lanes. The extremum calculation procedure is performed on plural subsets of the first and second input vector registers in parallel. For the first subset, the extremum procedure comprises extracting elements from the first subset of the first input vector register 110 and from the first subset of the second input vector register 112. In the illustrated configurations three elements are extracted for the first subset from each of the first input vector register 110 and the second input vector register 112. These elements are combined using arithmetic combination circuits 114. The arithmetic combination circuits 114 are configured to perform addition of the extracted elements. The circuitry is arranged to perform the calculation in plural processing lanes. Three processing lanes are illustrated for the first subset and the arithmetic combination circuits 114 (the zeroth, first, and second arithmetic combination circuits 114) are each configured to take values from within a different specific one of the processing lanes. The zeroth arithmetic combination unit 114(0) receives a first input element from lane 0 of the first input vector register 110 and a second input element from lane 0 of the second input vector register 112, and outputs the sum of the first input element and the second input element as a zeroth arithmetic result; the first arithmetic combination unit 114(1) receives a first input element from lane 1 of the first input vector register 110 and a second input element from lane 1 of the second input vector register 112, and outputs the sum of the first input element and the second input element as a first arithmetic result; and the second arithmetic combination unit 114(2) receives a first input element from lane 2 of the first input vector register 110 and a second input element from lane 2 of the second input vector register 112, and outputs the sum of the first input element and the second input element as a second arithmetic result. The zeroth, first, and second arithmetic results are passed to the extremum calculation unit 116(0) for the first subset which calculates the extremum value (e.g., the maximum or the minimum of the input values) and outputs the extremum for the first subset. For the second subset, the extremum procedure comprises extracting elements from the second subset of the first input vector register 110 and from the second subset of the second input vector register 112. In the illustrated configurations three elements are extracted for the second subset from each of the first input vector register 110 and the second input vector register 112. These elements are combined using arithmetic combination circuits 114. The arithmetic combination circuits 114 are configured to perform addition of the extracted elements. The circuitry is arranged to perform the calculation in plural processing lanes. Three processing lanes are illustrated for the second subset and the arithmetic combination circuits 114 (the third, fourth, and fifth arithmetic combination circuits 114) are each configured to take values from within a different specific one of the processing lanes. The third arithmetic combination unit 114(3) receives a first input element from lane 3 of the first input vector register 110 and a second input element from lane 3 of the second input vector register 112, and outputs the sum of the first input element and the second input element as a third arithmetic result; the fourth arithmetic combination unit 114(4) receives a first input element from lane 4 of the first input vector register 110 and a second input element from lane 4 of the second input vector register 112, and outputs the sum of the first input element and the second input element as a fourth arithmetic result; and the fifth arithmetic combination unit 114(5) receives a first input element from lane 5 of the first input vector register 110 and a second input element from lane 5 of the second input vector register 112, and outputs the sum of the first input element and the second input element as a fifth arithmetic result. The third, fourth, and fifth arithmetic results are passed to the extremum calculation unit 116(1) for the second subset which calculates the extremum value (e.g., the maximum or the minimum of the input values) and outputs the extremum for the second subset. Whilst the circuitry of figure 9 illustrates the calculation of both subsets in parallel, it will be readily apparent to the skilled person that, in alternative configurations, the processing circuitry may be arranged to perform the processing in response to a single processing instruction sequentially. For example, processing circuitry may be provided that is configured to perform 8 lanes of vector processing as two sequential sets of four lanes (e.g., as multiple “beats” of processing). From the point of view of the programmer or compiler, the processing circuitry is operating on 8 lanes of processing in response to a single vector instruction, however, rather than performing the processing on all 8 lanes in parallel, a first beat of processing performs the processing operation (the extremum calculation) on 4 of the lanes and a second beat of processing carried out subsequent (or at least partially subsequent) to the first beat of processing performs the processing operation (the extremum calculation) on the remaining 4 lanes. In such a configuration, the first and second subsets may be chosen so that all elements corresponding to each extremum calculation are combined in the same beat of processing. Furthermore, in alternative configurations, the number of lanes and subsets may vary dependent on the particular implementation. Figure 11 schematically illustrates a sequence of steps carried out according to some configurations of the present techniques. Flow begins at step S110 where it is determined if a fused extremum instruction specifying a first input vector register and a second input vector register has been received by decoding circuitry. If, at step S110, it is determined that a fused extremum instruction has not been received, then flow remains at step S110. If, at step S110, it is determined that a fused extremum instruction has been received, then flow proceeds to step S112. At step S112, the decode circuitry generates control signals to control the processing circuitry to perform the fused extremum calculation procedure before flow proceeds to step S114. In response to the control signals, at step S114, variable i is set equal to 0. Flow then proceeds to step S116 where the i-th element is extracted from the first input vector register V0(i). Flow then proceeds to step S118 where the i-th element is extracted from the second input vector register V1(i). Flow then proceeds to step S120, where it is determined whether there are any more elements to extract. For an extremum calculation procedure working on N groups, this corresponds to determining if i is not equal to N-1. If, at step S120, it is determined that there are more elements to extract (e.g., i≠N-1), then flow proceeds to step S124 where i is incremented before flow returns to step S116. If, at step S120, it is determined that there are no more elements to extract (e.g,. i=N-1), then flowproceeds to step S122. At step S122 the maximum of the elements in the set X(i) = ^^0(^^) + ^^1(^^)is calculated and output as the extremum before flow is returned to step S110. The illustration of steps S114 to S120 as being performed sequentially has been provided to illustrate the functions carried out by the apparatus in response to the fused extremum instruction. It will be readily apparent to the skilled person that the extraction of elements from the vector registers may be performed in parallel. Figure 12 illustrates a simulator implementation that may be used. Whilst the earlier described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the techniques concerned, it is also possible to provide an instruction execution environment in accordance with the embodiments described herein which is implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software based implementation of a hardware architecture. Varieties of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 730, optionally running a host operating system 720, supporting the simulator program 710. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple distinct instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations which execute at a reasonable speed, but such an approach may be justified in certain circumstances, such as when there is a desire to run code native to another processor for compatibility or re-use reasons. For example, the simulator implementation may provide an instruction execution environment with additional functionality which is not supported by the host processor hardware, or provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, Pages 53 - 63. To the extent that embodiments have previously been described with reference to particular hardware constructs or features, in a simulated embodiment, equivalent functionality may be provided by suitable software constructs or features. For example, particular circuitry may be implemented in a simulated embodiment as computer program logic. Similarly, memory hardware, such as a register or cache, may be implemented in a simulated embodiment as a software data structure. In arrangements where one or more of the hardware elements referenced in the previously described embodiments are present on the host hardware (for example, host processor 730), some simulated embodiments may make use of the host hardware, where suitable. The simulator program 710 may be stored on a computer-readable storage medium (which may be a non-transitory medium), and provides a program interface (instruction execution environment) to the target code 700 (which may include applications, operating systems and a hypervisor) which is the same as the interface of the hardware architecture being modelled by the simulator program 710. Thus, the program instructions of the target code 700 may be executed from within the instruction execution environment using the simulator program 710, so that a host computer 730 which does not actually have the hardware features of the apparatus XXX discussed above can emulate these features. In particular, the simulator program 710 comprises decoder program logic 740 and processing program logic 750. The decoder program logic 740 is responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying a first input vector register and a second input vector register. The processing program logic 750 is responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of pairs of elements, each of the plurality of pairs of elements comprising a first element extracted from the first input vector data structure and a second element extracted from the second vector data structure, and outputting an extremum value selected from amongst a group comprising values generated by combining each of the plurality of pairs of elements using an arithmetic operation In brief overall summary there is provided an apparatus, a method, and a computer program. The apparatus is provided with a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements. The apparatus is also provided with decoder circuitry responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying first and second input vector registers. The apparatus is also provided with processing circuitry responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements comprising at least a first element extracted from the first input vector register and a second element extracted from the second input vector register. The extremum calculating procedure comprises outputting an extremum value from a plurality of arithmetic results, each generated from a respective group of elements by combining, using an arithmetic operation, the first and second elements. In the present application, the words “configured to…” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a “configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation. In the present application, lists of features preceded with the phrase “at least one of” mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of: [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in combination (without C), A and C in combination (without B), B and C in combination (without A), or A, B and C in combination. Although illustrative configurations of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise configurations, and that various changes, additions and modifications can be effected therein by one skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, various combinations of the features of the dependent claims could be made with the features of the independent claims without departing from the scope of the present invention.

Claims

WE CLAIM:

1. An apparatus comprising: a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements; decoder circuitry responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying a first input vector register and a second input vector register; and processing circuitry responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements, each of the plurality of groups of elements comprising at least a first element extracted from the first input vector register and a second element extracted from the second input vector register, and outputting an extremum value selected from a set comprising a plurality of arithmetic results, each of the arithmetic results generated from a respective group of elements of the plurality of groups of elements by combining, using an arithmetic operation, the first element and the second element of the respective group of elements.

2. The apparatus of claim 1, wherein for each of the plurality of groups of elements the first element is extracted from an element position in the first input vector register and the second element is extracted from the element position in the second input vector register.

3. The apparatus of claim 1 or claim 2, wherein each of the plurality of groups of elements are extracted from consecutive positions in the first input vector register and the second input vector register.

4. The apparatus of any preceding claim, wherein the processing circuitry is configured to perform processing in a plurality of vector processing lanes and the plurality of groups of elements comprises groups of elements from two or more of the plurality of vector processing lanes.

5. The apparatus of any preceding claim, wherein the fused extremum instruction specifies an output register and the processing circuitry is configured to store the extremum value to the output register.

6. The apparatus of any preceding claim, wherein: the plurality of groups of elements comprises a subset of elements extracted from the first input vector register grouped with a corresponding subset of elements extracted from the second input vector register; and the subset of elements excludes at least one element of the first input vector register and the corresponding subset of elements excludes at least one element of the second input vector register.

7. The apparatus of claim 6, wherein the processing circuitry is configured to perform the extremum calculation procedure for a plurality of subsets of elements of the first input vector register and the second input vector register.

8. The apparatus of claim 7, wherein the plurality of subsets of elements are non-overlapping subsets.

9. The apparatus of claim 7 or claim 8, when dependent on claim 5, wherein the processing circuitry is configured to output the extremum value for each of the plurality of subsets of elements in consecutive positions of an output vector register.

10. The apparatus of any preceding claim, wherein the fused extremum instruction is a matrix population instruction for iterative population of elements of a matrix.

11. The apparatus of any preceding claim, wherein the set comprises a zero value.

12. The apparatus of any preceding claim, wherein: the fused extremum instruction specifies a third input register; and the processing circuitry is configured to predicate the set of elements from which the extremum value is selected based on values of respective third elements extracted from the third input register.

13. The apparatus of any preceding claim, wherein the arithmetic operation is an addition operation or a subtraction operation.

14. The apparatus of any preceding claim, wherein the extremum value is a maximum value or a minimum value.

15. The apparatus of any preceding claim, wherein the extremum value is rectified extremum value.

16. The apparatus of any preceding claim, wherein the plurality of elements comprises: 8-bit elements; 16-bit elements; 32-bit elements, or 64-bit elements.

17. The apparatus of any preceding claim, wherein the plurality of elements comprises: a plurality of integer elements; a plurality of floating point elements; a plurality of single precision elements; or a plurality of double precision elements.

18. The apparatus of any preceding claim, wherein the plurality of elements comprises: signed elements; or unsigned elements.

19. A method of operating an apparatus comprising a plurality of vector registers, each of the plurality of vector registers configured to store a plurality of elements, the method comprising: in response to a fused extremum instruction, generating control signals, the fused extremum instruction specifying a first input vector register and a second input vector register; and in response to the control signals, performing an extremum calculation procedure comprising extracting a plurality of groups of elements, each of the plurality of groups of elements comprising at least a first element extracted from the first input vector register and a second element extracted from the second input vector register, and outputting an extremum value selectedfrom a set comprising a plurality of arithmetic results, each of the arithmetic results generated from a respective group of elements of the plurality of groups of elements by combining, using an arithmetic operation, the first element and the second element of the respective group of elements.

20. A computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: a plurality of vector data structures, each of the plurality of vector data structures configured to store a plurality of elements; decoder program logic responsive to a fused extremum instruction to generate control signals, the fused extremum instruction specifying a first input vector register and a second input vector register; and processing program logic responsive to the control signals to perform an extremum calculation procedure comprising extracting a plurality of groups of elements, each of the plurality of groups of elements comprising at least a first element extracted from the first input vector data structure and a second element extracted from the second input vector data structure, and outputting an extremum value selected from a set comprising a plurality of arithmetic results, each of the arithmetic results generated from a respective group of elements of the plurality of groups of elements by combining, using an arithmetic operation, the first element and the second element of the respective group of elements.

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