Silicon-based field-effect transistors and method of fabrication thereof

Abstract

The present invention relates to nanostructured materials, in particular to the preparation method of silicon-based field-effect transistors. The object of this invention consists of a method for manufacturing a field-effect transistor comprising the following steps: depositing a gate electrode layer onto a dielectric layer; depositing a priming layer said dielectric layer; forming a source electrode and a drain electrode by depositing conductive material on said priming layer and forming a semiconductor layer on top of the source and drain electrodes wherein the priming layer comprises a conductive material and the semiconductor layer comprises a porous polycrystalline silicon-based material, being said porous polycrystalline silicon-based material. The proposed invention aims to combine the potential of polymer-based dielectric materials and Si-based semiconductor to fabricate a FET device that can be more sustainable, readily available and low cost.

Description

[0001] DESCRIPTION

[0002] SILICON-BASED FIELD-EFFECT TRANSISTORS AND METHOD OF FABRICATION THEREOF

[0003] FIELD OF THE INVENTION

[0004] The present invention relates to nanostructured materials, in particular to the preparation method of silicon-based field-effect transistors.

[0005] PRIOR ART

[0006] The growing interest in flexible electronics has prompted a large development in fieldeffect transistor (FET) technology and the materials used in it. Applications are immense, ranging from fully transparent displays to biochemical sensing devices [1], [2], [3], FETs, in their simplest configuration, rely on the field effect to modulate current across a semiconductor, placed between two electrodes (source and drain). A dielectric layer separates the semiconductor from the third (gate) electrode, which works as a switch to allow the passing or to block this current.

[0007] Current modulation is a result of the capacitive injection of charge carriers close to the dielectric / semiconductor interface [1], [2], [3], Research into the semiconductor materials used, such as hydrogenated amorphous silicon (a-Si:H), low-temperature polycrystalline silicon (low-T poly-Si), organic semiconductors, and oxide semiconductor materials, has yielded impressive enhancements in FETs' carrier mobility, switching speed, cost, reliability, and processing complexity [1], [2], [3], [4], FETs are also attractive devices to evaluate the quality of semiconductors such as silicon-based materials, given both the mobility and nature of the charge carriers can be extracted from the currentvoltage characteristics of the devices [5], [1], [6], Paper and other cellulose-based dielectric materials have behaviors analogous to those of a solid electrolyte in that they are ionically conducting though electronically insulating

[0008] [7], [8], Furthermore, paper is compatible with vacuum-based techniques to fabricate Si-based devices, such as n-i-p Si solar cells on paper substrates and Li-ion batteries [9],

[0010] , Paper is also hydrophilic in nature, which is important for biosensing applications

[0009] [8].

[0010] The proposed invention consists in combining the potential of paper-based dielectric materials and Si-based semiconductors to fabricate ambipolar FET devices that can surpass the electrical performance of those using oxide-based semiconductors and organic semiconductors, overcoming the issues associated with different performances obtained in n- and p-type devices. FET on paper and other biopolymer substrates are of great relevance in contributing to sustainability and circularity in the electronics industry.

[0011] SUMMARY OF THE INVENTION

[0012] The object of this invention consists of a method for manufacturing a field-effect transistor (100) comprising the following steps: depositing a conductive layer that forms a single or multiple gate electrodes

[0013] (1) on a first surface of a substrate that can also function as a dielectric layer

[0014] (2); forming a patterned conductive layer that will result in two coated regions forming the source and drain contacts (3) separated by a gap on a second surface of said dielectric layer (2): depositing a semiconductor layer (4) on top the dielectric layer (2) so that said semiconductor layer is in contact with the source electrode and the drain electrode (3) and covers the gap between said source electrode and drain electrode; wherein the source and drain contacts comprise a conductive material and, when needed, a priming layer to improve adhesion and the semiconductor layer (4) comprises a porous polycrystalline silicon-based material, being said porous polycrystalline silicon- based material obtained by the following steps: flowing a precursor gas mixture into a reaction chamber, said precursor gas mixture comprising at least one silicon-based gas; applying an electromagnetic field to said precursor gas mixture, thereby forming a non-thermal plasma; forming a solid product in the plasma, wherein said solid product comprises a plurality of hydrogen-terminated silicon-based nanoparticles; depositing a plurality of hydrogen-terminated silicon-based nanoparticles on top of said source electrode, said drain electrode and said channel formed between said source electrode and drain electrode; exposing said plurality of hydrogen-terminated silicon-based nanoparticles to an oxidizing medium; and subjecting said plurality of hydrogen-terminated silicon-based nanoparticles to a trigger mechanism, thereby inducing the sintering of the plurality of hydrogen-terminated silicon-based nanoparticles through a chain reaction to form said porous polycrystalline silicon-based material.

[0015] In an advantageous aspect of the present invention, the free electrons present in the non-thermal plasma collide with the molecules of the silicon-based gas, causing dissociation and ionizing said molecules into reactive ions and radicals, ultimately forming nucleation ionic clusters that grow into hydrogen-terminated silicon-based nanoparticles (Si-NPs) which are then deposited on top of the source and drain electrodes (3) and the channel formed between the source and drain electrodes (3).

[0016] Preferably, at least one silicon-based gas is selected from the group consisting of silane, tetrachlorosilane and mixtures thereof. In addition to silicon-based gas, the precursor gas mixture comprises hydrogen and / or at least one noble gas selected from the group consisting of helium, argon and mixtures thereof. Moreover, by adding other precursor gases to the mixture such as methane or ethylene, phosphine, trimethylborane, or other hydride gases, it's possible to synthetize silicon-based composite materials with carbon, phosphorus, boron, among other elements, following the same reaction mechanism. In an advantageous aspect of the present invention, the non-thermal plasma electrons negatively charge the formed Si-NPs, thus limiting agglomeration and the size of each nanoparticle, which in turn increases the overall compactness of the granular structure formed from the depositing Si-NPs. The granular structure is, thereby, determined by the depositing step, inside a reaction chamber, of free-standing Si-NPs on top of the source and drain electrodes (3) and channel of the field-effect transistor (100), while controlling deposition rate and pressure to achieve a certain range of compactness of said granular structure.

[0017] The light emitted by a light source induces the sintering of Si-NPs irradiated at the surface of the granular structure, in the presence or after exposure to an oxidizing medium, wherein said oxidizing medium is selected from ambient air, liquid oxygen, perchlorates, nitrates, and mixtures thereof.

[0018] In an advantageous aspect of the present invention, the explosive reaction is triggered immediately (millisecond range) upon irradiation of the Si-NPs with the light source.

[0019] The sintering reaction is characterized by the chain exothermal oxidation reaction in which several Si-H bonds are ruptured due to the energy transfer from the emitted light, resulting in several Si dangling bonds that ignite an explosive exothermal reaction with the oxidating gas, such as oxygen, that propagates self-sustained throughout the whole sample as the energy release from the explosive reaction breaks more Si-H surface bonds in its vicinity which result in new Si dangling bonds, that in turn react with more oxygen. The high number of Si dangling bonds favor the formation of Si-0 bonds, releasing energy. This chain reaction will continue to propagate until there are no more Si-H surface bonds in the reaction's vicinity.

[0020] In a preferred embodiment of the present invention, the irradiation of the granular structure, on top of the source and drain electrodes (3) and channel of the field-effect transistor (100), is performed immediately after the exposure of said granular structure to ambient air or a controlled oxidizing medium, to reduce loss of Si-H bonds due to natural oxidation and to maximize the amount of initial surface Si-H bonds to be ruptured upon irradiation, thereby initiating the sintering chain reaction.

[0021] In an advantageous aspect of the present invention, the porous polycrystalline silicon- based material is obtained from the explosive sintering of the plurality of Si-NPs, which is caused by the strong exothermic nature of the oxidation reaction that leads to a large and localized increase in temperature of the Si nanocrystals of the granular structure, since their thermal conductivity is very low, and the temperature increase is sufficient to melt the silicon-based nanoparticles and fuse them together into a polycrystalline material.

[0022] Moreover, the explosive sintering of Si-NPs can be performed without the addition of oxygen or other oxidant substances, wherein oxygen present in air or in the controlled medium where the material is at standard atmospheric pressure is enough to trigger and sustain the sintering chain reaction. In addition, the method of the present invention does not require high temperatures or pressures, wherein the sintering of Si- NPs can be performed without external intentional heating, and in fact at any temperature, as the energy necessary to initiate the reaction is provided by the emitted light.

[0023] DESCRIPTION OF THE FIGURES

[0024] Figure 1 - Granular structures resulting from the deposition of Si-NPs inside the reactor: a) Structure-A; b) Structure-B; c) Structure-C

[0025] Figure 2 - Deposited Si-NPs on top of patterned gold electrodes on a glass substrate: a) before sintering; b) after sintering.

[0026] Figure 3 - Field-effect transistor (100) having a coplanar bottom-gate structure: a) representation of the FET device (100), comprising a gate electrode layer (1), a dielectric layer (2), a priming layer (not represented), a source and drain electrodes (3), a channel and a semiconductor layer (4) comprising a porous polycrystalline silicon-based material; b) constructed FET device comprising a granular structure of Si-NPs deposited on top of the source and drain electrodes (3), prior to the sintering reaction.

[0027] Figure 4 - Sintered Si-NPs on top of the source and drain electrodes (3) and respective channel of FET devices: a) FET-1, b) FET-2; c) FET-3; d) FET-4. Channel width (W) and length (L) are represented by scale bars.

[0028] Figure 5 - l-V characteristics of FET-1 at different aging periods: Day 0 aging - a) transfer curve, b) output curve; Day 44 aging - c) transfer curves; Day 84 aging - d) transfer curves.

[0029] Figure 6 - Transfer curves of the FET-2 device after a 27-day aging period.

[0030] Figure 7 - l-V characteristics of FET-3 at different aging periods: Day 0 aging - a) transfer curve, b) output curve; Day 36 aging - c) transfer curves.

[0031] Figure 8 - Transfer curves of the FET-4 device after a 33-day aging period.

[0032] Figure 9 - Key parameters extracted as a function of aging for devices FET-1 and FET-3: a) ION and IOFF currents; b) On / Off ratio; c) PFE; d) 5; e) AVhysteresis.

[0033] DETAILED DESCRIPTION

[0034] The more general and advantageous configurations of the present invention are described in the Summary of the Invention. Such configurations are detailed below in accordance with other advantageous and / or preferred embodiments of implementation of the present invention.

[0035] In a preferred embodiment of the present invention, the hydrogen-terminated silicon- based nanoparticles have a grain size of 1 - 50 nm. The small size of the Si-NPs and the space between each other in the bulk of the granular structure allows the Si-NPs (hydrogen surface concentration of 1014-1015atoms cm'2, hydrogen volumetric concentration of packed nanoparticles 1015-1022atoms cm'3) to be close enough to experience the energy transfer from the exothermic reaction, but far enough so that oxygen and hydrogen species can be present between them to sustain the propagation of the reaction in all directions through the silicon-based nanoparticle layers to form the porous polycrystalline silicon material.

[0036] In a preferred embodiment of the present invention, the sintering of the plurality of hydrogen-terminated silicon-based nanoparticles is performed without intentional external heating and at standard atmospheric pressure, 760 Torr.

[0037] The trigger mechanism for the sintering reaction can be thermal, electrical, optical, chemical, or mechanical, so long as this trigger mechanism is energetic enough to break the surface Si-H bonds in the silicon-based nanoparticles, thus initiating the chain reaction.

[0038] In an embodiment of the present invention, the conductive channel between the source electrode and the drain electrode comprises a width of 480 - 950 pm and a length of 90 - 190 pm. The conductive channel is formed when a positive voltage is applied to the drain electrode with respect to the source electrode, so that electrons flow from the source to the drain electrode.

[0039] In a preferred embodiment of the present invention, the trigger mechanism to which the reaction is subjected to comprises an optical trigger consisting of light emitted from a light source, being said light irradiated onto the hydrogen-terminated silicon-based nanoparticles deposited on top of the source and drain electrodes (3) and channel of the field-effect transistor (100).

[0040] In a preferred embodiment of the present invention, the optical trigger required to initiate the explosive sintering of hydrogen-terminated silicon-based nanoparticles consists of light emitted by a light source comprising a laser or a focused light from any other source. Preferably, the light emitted by the light source has a wavelength in the N I R-Vis-UV range, from 250 nm to 2100 nm. More preferably, the light source comprises a laser wherein the light emitted by the laser has a wavelength equal to or below 633 nm. In an advantageous aspect of the present invention, the light emitted by the laser with a wavelength equal to or below 633 nm leads to the rupture of the surface Si-H bonds, creating Si dangling bonds which ignite the explosive oxidation reaction, resulting in the sintered silicon-based material and the removal of hydrogen terminations from the Si-NPs.

[0041] It is also an object of the present invention a field-effect transistor (100) comprising a gate electrode layer (1), a dielectric layer (2), a priming layer, a source and drain electrodes (3), a channel and a semiconductor layer (4), wherein the semiconductor layer (4) comprises a porous polycrystalline silicon-based material having a crystalline fraction above 75 %.

[0042] In a preferred embodiment of the field-effect transistor (100), the porous polycrystalline silicon-based material comprises a grain size of 10 - 500 nm.

[0043] In an advantageous aspect of the present invention, the decrease in channel thickness improves the On / Off ratio and the field-effect mobility of the FET device.

[0044] In an advantageous aspect of the present invention, the good performance of the porous polycrystalline silicon-based material as the channel layer of FETs and its verified porosity demonstrate that the porous polycrystalline silicon-based material could be employed as a sensing layer for ion-sensitive field-effect transistors (ISFETs) due to its high surface-to-volume ratio, being also employed in other electronic devices. Coupling the explosive sintering procedure with solution processing may also be explored for printing applications in cellulose or oxide substrates.

[0045] In an embodiment of the field-effect transistor (100), the gate electrode layer (1) comprises a metal, preferably silver. Preferably, the gate electrode layer (1) has a thickness of at least 200 nm. In an embodiment of the field-effect transistor (100), the dielectric layer (2) comprises a paper-based material. Preferably, the dielectric layer (2) has a thickness of at least 75 pm.

[0046] In an embodiment of the field-effect transistor (100), the priming layer comprises a metal selected from titanium, chromium, tantalum, and mixtures thereof. Preferably, the priming layer has a thickness of at least 6 nm.

[0047] In an embodiment of the field-effect transistor (100), the source electrode and the drain electrode (3) comprise a metal, preferably gold. Preferably, the source and drain electrodes (3) have a thickness of at least 60 nm.

[0048] The preferred embodiments described above can, of course, be combined in various configurations, the present invention being not limited to the embodiments previously described.

[0049] EXAMPLES

[0050] Formation of hydrogen-terminated silicon nanoparticles

[0051] An Ar / SiH4 gas mixture is flown down the top through a tube connecting to a quartz tube, comprising a reaction chamber, where the plasma is formed at low pressures (1 Torr - 10 Torr). The quartz tube has two different diameters across its 30 cm length: a narrow diameter zone, with 9 mm outer diameter and stretching for 15 cm; and a wider diameter zone with 26 mm outer diameter and stretching for 14 cm. Between these two zones there is a 1 cm-long connection zone. The tube walls are 2 mm thick. The quartz tube was set up so that the hydrogen-terminated silicon nanoparticles synthesis occurred in the narrower zone. Two copper ring electrodes spaced 16 mm apart from each other are fitted to the quartz tube and connected to a radiofrequency source at 13.57 MHz to allow for the application of radiofrequency power at 80 W to the gases flowing inside the tube and generate the non-thermal plasma. From this, the volume inside the tube is calculated at 0.314 cm3between the two copper electrodes. The applied radiofrequency power was set at 80 W for all hydrogen-terminated silicon nanoparticles synthesis. Therefore, the power density applied to the gas mixture between the electrodes to form the plasma was 255 W cm'3. Hydrogen-terminated silicon nanoparticles form in the plasma through the electron impact dissociation of SiH4 and subsequent nucleation and clustering of the resulting species.

[0052] Formation of semiconductor layer for FET devices - Deposition conditions of hydrogen- terminated silicon nanoparticles

[0053] The in-situ growth of compact structures of semiconductor material made with Si-NPs was explored inside the PECVD reactor. A funnel was fixed inside the reactor between the quartz tube and the stainless-steel mesh to direct the synthetized Si-NPs onto a glass substrate which was placed on top of the mesh. The conditions for the deposition of three different granular structures of Si-NPs are presented on Table 1, with the respective granular structures being depicted in Figure 1. Each granular structure presents a different deposition time. For Structure-A and Structure-B, the deposition was only stopped once the throttle valve fully opened, meaning it could no longer function to decrease the deposition pressure. The growth of the granular structures inside the reactor was shown to be modifiable by changing the pressure, gas flow rates and funnel-to-substrate height during deposition. Slight changes to the parameters result in different structures both in shape, size, as well as in density.

[0054] Table 1 - Deposition conditions of each of the granular structures comprising hydrogen- terminated silicon-based nanoparticles, presented in Figure 1. Structure-A in Figure 1 (a) shows an early iteration of these depositions, where there would be some material accumulated on the glass substrate but most of it would flow around it and accumulate on the mesh. Structure-B in Figure 1 (b) shows the growth of a tall, conic dome-like shape after decreasing the pressure from 3 Torr to 2.5 Torr and increasing the gas flow rates from 0.279 seem to 0.650 seem of SiF and from 15 seem to 36 seem of Ar. By decreasing the deposition pressure, the gases flowing through the quartz tube will have a shorter residence time in the plasma due to increased speed, so they will be more likely to impact the substrate and lodge themselves there after being concentrated by the funnel than to just flow over the substrate and around it

[0011] , The increase in gas flow rates also decreases the residence time, resulting in the same effect as decreasing the deposition pressure

[0011] , The third sample (Structure-C) in Figure 1 (c) was obtained by increasing the deposition pressure of the second sample from 2.5 Torr to 3 Torr, which reduces the residence time, allowing for a smaller structure to be formed.

[0055] A new sample of Si-NPs was deposited on gold electrodes separated by 200 pm to check if the deposition could be targeted onto electrodes in the substrate used. Optical images of the new deposited Si-NPs structure - Disk-E - before explosive sintering and after explosive sintering are shown in Figure 2 (a) and (b), respectively. Initially, the material shows a brownish color typical of the accumulation of Si-NPs. After explosive sintering is performed, this color shifts to a blueish tone, an indication that a more crystalline material had emerged. In terms of uniformity, the Si-NPs are accumulated in a cylindrical shape with concentric steps originated from the deposition process in Figure 2 (a). The sintered material in turn shows concentric cracks around a central, continuous, and uniform area (Figure 2 (b)). This cracking is a result of a slight contraction of the semiconductor material upon sintering of the nanoparticles due to the explosive nature of the oxidation reaction that takes place.

[0056] Construction of FET devices The FET device structure follows a coplanar bottom-gate structure, presented in Figure 3 (a) [1], The coplanar bottom-gate structure allows to assemble all components of the FET prior to the deposition of the semiconductor layer (4) and consequent explosive sintering of the deposited Si-NPs, which reduces the possibility of damaging the device by adding other elements of the device after the semiconductor layer (4) being deposited. A constructed FET having the configuration described above is shown in Figure 3 (b) in which a granular structure of Si-NPs is deposited on top of the paper dielectric while covering the source and drain electrodes (3), prior to the sintering reaction.

[0057] FETs with a coplanar bottom-gate structure were constructed integrating the porous polycrystalline silicon-based material, obtained after the sintering of the deposited Si- NPs, as the semiconductor channel layer and employing a 75 pm thick standard tracing paper (STP) as both the dielectric and the substrate layers simultaneously. Previous work showed that the STP had an entangled fiber matrix with an average width of 10 pm and a root mean square roughness of 6.4 pm determined by 3D profilometry

[0012] , Impedance spectroscopy showed the paper had a capacitance value of Cdieiectric = 0.23 pF cm'2at 10 mHz, which corresponds to the formation of an electric double layer (EDL) at low frequencies. This EDL results from the polarization of the paper at its interface with the gate and subsequent polarization at the paper-semiconductor interface induced by the mobile ionic species in the paper matrix [7],

[0012] ,

[0058] A 200 nm silver (Ag) layer was printed onto the bottom of the paper dielectric layer (2) to function as the gate electrode. In-plane gold (Au) electrodes were deposited through e-beam PVD onto the top side of the paper using a shadow mask for source and drain electrodes (3) patterning, with a priming layer comprising a 6 nm thin film of titanium (Ti), being said priming layer deposited prior to deposition the 60 nm gold layer to improve the adherence of said gold electrodes to the substrate.

[0059] The paper dielectric layer (2) was fixed inside the reactor chamber, and a funnel was used to direct the as-produced Si-NPs in the reactor to accumulate on top of the dielectric and cover the source and drain electrodes (3). The paper with Si-NPs was removed from the reactor and explosive sintering was triggered with a laser within 30 min of being exposed to ambient air.

[0060] Four FETs were constructed with the structure described above, having different deposition times for the Si-NPs on top of the source and drain electrodes (3). Deposition times of 10 s, 6 s, 3 s and 1.5 s were used, respectively, for devices FET-1, FET-2, FET-3, and FET-4. A longer deposition time results in a thicker Si-NP structure being deposited. The deposition conditions of the four FETs are shown in Table 2.

[0061] Table 2 - Deposition conditions used to produce each of the semiconductor layers in the

[0062] FETs devices

[0063] Characterization of semiconductor layer of FET devices - Raman Spectroscopy

[0064] Raman spectroscopy measurements were taken both before and after the explosive sintering of each constructed FET devices. The main parameter changes in the Raman spectra related to the explosive sintering process are listed in Table 3. These are the LTO peak wavenumber, its T, and the intensity of the peak, for both before and after sintering.

[0065] Table 3 - Raman spectroscopy parameters for the semiconductor layer in each FET device, before and after sintering. The devices FET-1, FET-2, and FET-4 present similar values before sintering for their LTO peak around 515 cm , which indicates these have a mean Si-NP diameter of d ~ 2.3 nm

[0013] ,

[0014] ,

[0015] ,

[0016] ,

[0017] ,

[0018] ,

[0019] , FET-3 however shows a deviation from those values, presenting a more red-shifted and broader LTO peak (508.9 cm4) than the other samples from having smaller nanoparticles of mean diameter d ~ 1.4 nm

[0013] ,

[0014] ,

[0015] ,

[0016] ,

[0017] ,

[0018] , All samples were sintered successfully, evident by the blue shift in the LTO peak and the increase in crystallinity (Xc). The sintered FET-1 and FET-3 samples present the smallest red-shift in the LTO peak center in relation to bulk Si's 521 cm1value, so they should exhibit a larger grain size (> 10 nm)

[0020] ,

[0014] ,

[0015] ,

[0021] , From the line broadening ( / "), sintering a thinner Si-NP structure leads to a smaller grain size, evident by the higher T values of the thinner s-Si-NP layers

[0020] ,

[0014] ,

[0015] , Xc increases with sintering, especially on device FET-1 where the crystallinity after sintering is 97.1 %, which correlates with its LTO peak being so close to that of bulk Si since higher crystallinity is an indication of larger grain size

[0020] ,

[0021] ,

[0014] ,

[0022] ,

[0015] , The rest of the s-Si-NP layers show crystallinity values above 75 %, not increasing much from their corresponding initial Xc values, which together with the lower LTO peak values, indicates the explosive sintering was not as good as in FET-1

[0020] ,

[0021] ,

[0014] ,

[0022] ,

[0015] ,

[0066] Characterization of semiconductor layer of FET devices - Optical Microscopy

[0067] The size of each deposited layer of Si-NPs is slightly different after explosive sintering is performed due to contraction of the Si material. Optical microscopy imaging was used to assess the quality of the sintered semiconductor layer (4) in each FET device and, in conjunction with the software ImageJ (version 1.53t), to measure the W and L values of each Si semiconductor layer (4) after sintering and estimate its thickness. Figure 4 shows the optical microscopy images of the sintered semiconductor layers (4) deposited with the conditions of Table 2. The optical microscopy images were used to assess the quality of the sintered semiconductor layers (4), to measure the W and Lvalues of each channel, and to approximate their thickness. FET-1 and FET-3 resulted in uniform, continuous central cylinders like the one that was observed in Figure 4, while FET-2 and FET-4 resulted in fractured centers, although they can still be distinguished from the surrounding semiconductor material. All the layers show concentric cracking around the central circle, originating from the contraction of the Si material due to explosive sintering. The thicker channels (FET-1, FET-2, and FET-3) have a blue tonality that is an indication of their crystalline structure while the channel in FET-4 has a deep brown color, arising from its smaller grain size and. This is in line with what was observed on the Raman analysis of the previous section. The W, L, and thickness values of each FET device are listed below in Table 4.

[0068] Table 4 - W and L values for each FET device, as well as their approximate thickness.

[0069] The FET-2 channel has a smaller L than the other FETs due to the shadow mask with smaller separation between the source and drain electrodes (3) used forthis device. The W values vary a little between the three thicker devices while FET-4 has a much larger W than the other FETs. The W measurements took account the discontinuities in the channels of FET-2 and FET-4 that the delimitations in Figure 4 do not show. The discontinuity in the FET-4 channel may be due to the Si-NPs spreading out more when deposited inside the reactor and so, when the sintering occurs, they are not as likely to fuse together and contract into larger grains. The origin of the large crack in the center of the FET-2 channel is unclear, possibly arising from an uneven growth of the Si-NP structure inside the reactor.

[0070] Electrical Characterization of FET - Characteristic Curves

[0071] The l-V characteristics of all FET devices were measured. The transfer and output curves for the FET-1 device are presented in Figure 5. Three different measurements were performed over several days: one at the day of sintering (day 0), one after 44 days, and a final one on day 84.

[0072] All transfer curves show current modulation occurs, with the day 0 measurement showing weaker modulation when compared to the day 44 and day 84 curves due to the slope of the IDS curves being lower in this curve upon reaching the turn-on voltage (VON). In the output characteristics of Figure 5 (b), curves show linear (ohmic) behavior at low VDS (< 5 V). The output curves do not saturate completely and all curves have reduced slopes initially. These decreased slopes are explained by poor charge carrier injection into the semiconductor's conduction channel, which is caused by poor interfaces between the semiconductor and the Au source and drain electrodes (3).

[0073] The transfer curves for the FET-2 device are presented in Figure 6. Only one measurement was done on this device, after 27 days of sintering.

[0074] On the curves of Figure 6, we can observe that the 11 GS | current has similar values to the 44-day aged FET-1 measurements. Good current modulation of I DS is observed for all VDS values.

[0075] The characteristic curves for the FET-3 device are presented in Figure 7. Two different measurements were performed: one at the day of sintering (day 0) and one after 36 days.

[0076] The 0-day transfer curves of FET-3 show better current modulation in general than the 0-day one of FET-1, having a steeper slope after reaching the VON. The | IGS | currents are also in the same range as the 0-day FET-1 measurement, increasing by a degree in magnitude for the aged curves. The transfer curves for 33-day aging on FET-3 (Figure 7 (c)) have strikingly similar behavior of I DS to that of the 44-day aged FET-1 device on Figure 5 (c), apart from the | IGS | and the maximum IDS values reached, which are a degree of magnitude higher in this FET-3 device. The output curves for the 0-day measurements (Figure 7 (b)) have linear or ohmic behavior at VDS < 10 V. The transfer curves for the FET-4 device are presented in Figure 8. Only one measurement was done on this device, after 33 days of sintering. The transfer curves of FET-4 on Figure 8 show good current modulation and a VON at around 5 V. The | IGS | currents have similar values to all aged measurements on the previous FETs.

[0077] A fifth FET was created with the same deposition conditions as FET-1, without being subjected to explosive sintering. Its characterization, however, showed no current modulation (data not shown).

[0078] Electrical Characterization of FET - Parameter Extraction

[0079] The key parameters of the four FET devices were extracted from the transistors' transfer curves for a VDS of 5 V, at which the transistor is in the linear regime. These are the turnon voltage (VON), the On / Off ratio, the mobility (p), the subthreshold swing (S), and the degree of hysteresis (AVhysteresis) [1], [7], VON is the VGS value at which IDS starts to increase as seen in a log(l DS -VGS) plot, i.e., the voltage required to turn-off the transistor [1], The On / Off ratio is given by the ratio between the I ON and IOFF values, which correspond to the I DS and | IGS | currents at the maximum VGS value, respectively [1], Since we are assessing the FETs at a low VDS, the mobility is taken as the field-effect mobility (PFE) and can be calculated from the device's transconductance (gm) [1], [7], The 5 value, which indicates the switching speed of the device, i.e., how much voltage is needed for I DS to increase one order of magnitude [1], [7], Table 5 presents all the parameters for the four FET devices in their several stages of aging. Figure 9 shows the influence of the devices' aging on some extracted parameters.

[0080] Vth decreases for thinner channels and with aging for the same devices (FET-1 and FET- 3), although it increases a little again as more time passes. VON generally also decreases with a thinner channel from ~7 V to ~5 V, but it increases with aging. All the FET devices show n-type behavior due to I DS increasing for ever-more positive VGS values (positive voltage applied to the gate increases the conductivity of the semiconductor channel) and work in enhancement mode due to having positive VON values [1],

[0023] , Regarding the non-aged values of FET-1 and FET-3 in Figure 9 (a), a thinner channel does not appear to influence IOFF but does lead to an increase of ION. Aging (~30 days) in all devices leads to an increase of IOFF by around a degree of magnitude, from IO-8A to 10-7A, which then appears to stabilize around that value for posterior aging according to the FET-1 values. ION also increases with aging, and to a greater extent than I OFF, while also stabilizing for further aging (FET-1 aging). Consequently, the On / Off ratio increases with thinner channels (apart from FET-4 which is like FET-3). The On / Off ratio also varies with aging (Figure 9(b)) on FET-3 and on FET-1, likely due to changes in humidity between different characterization moments. The PFE values increase for thinner channels up to ~10x (see all FETs at around 30 to 40 days aging and FET-1 and FET-3 at 0-day aging on Table 5) having a maximum value of 1.43 cm2V1s1for the 36-day-aged FET-3 device. It also increases with aging, as seen in Figure 9 (c).

[0081] The S value appears similar in the devices with aging of ~30 to 40 days (Table 5), with values of between 0.75 V dec1and 1 V dec-1. This value, however, decreases with aging to a certain point, after which it increases back to the initial value range for FET-1 (Figure 9 (d)). The voltage hysteresis shows a generalized decrease for the ~30-to-40-day aging (FET-1 and FET-3). Its value also decreases with aging up to a certain point, at which it increases again back to the value range without aging (Figure 9 (e)). The minimum hysteresis value was found at AVhysteresis = 0.5 V for the FET-4 device, although a 1 V value was also achieved in the FET-1 device after aging for 44 days.

[0082] The increase and subsequent decrease of the S and AVhysteresis values in FET-1 can be attributed to the measurements being performed on under different temperature and humidity conditions given these values are highly dependent on the STP dielectric's ionic conductivity [1], [7], Paper is known to be dependent on the humidity of the environment surrounding it as this humidity affects its water content, which influences the displacement of ionic species and their accumulation at the STP's interface upon applied gate bias [7], One possibility for the increase with aging of ION, IOFF and PFE arises from the use of Au electrodes with a porous polycrystalline Si semiconductor layer (4). Au can diffuse at room temperature into the sintered Si material and improve the interface with the percolated networks of poly-Si grains, thus enhancing the conduction pathways between these materials

[0024] ,

[0083] The FET-1 was the longest lasting device, working for 450 days (over 1 year and 2 months) while kept in ambient conditions. The best FET parameters were found on FET- 3 at 36-day aging. This FET has similar VON and Vth values (7 V and 8.3 V, respectively), PFE = 1.43 cm2V1s’1, On / Off ratio = 1.43xl05, S = 0.75 V dec-1, and AVhysteresis = 1 V, with a channel thickness of ~60 pm. The On / Off ratio of ~105was found to be slightly higher than in other reported paper-based devices (104in oxide-based paper FETs) [8], and higher than the state of the art in Si-NP-based FETs (~101- 104)

[0017] , [4], [6],

[0025] ,

[0023] ,

[0026] ,

[0027] ,

[0028] ,

[0029] , Table 5 - Main parameters extracted from characteristic curves of each FET devices.

[0084] This may be due to the explosive nature of the sintering, which affects the interface between semiconductor layer (4) and source and drain Au electrodes, leading to poor carrier injection. The S value of 0.75 V dec1is in line with that of organic FETs and oxide FETs using a paper dielectric [1], [8],

[0085] The mobility values of this FET device are 2 degrees of magnitude lower than those of low-T poly-Si FETs obtained from the excimer laser characterization of amorphous Si ( PFE = ~102cm2V1s1) and 10 times greater than those in a-Si:H (PFE = ~101cm2V1s1) [1], [4],

[0030] , When paper / cellulose dielectrics are used, we find our devices have comparable mobilities with inorganic FETs ( PFE = ~10° cm2V1s1) and have mobilities 10 times higher than those in Organic-based FETs (PFE = ~101cm2V1s1) [8], While these mobilities are not compatible with CMOS technology, they are sufficient for sensing applications [1], [4], Our mobility value of PFE = 1.43 cm2V1s1is also comparable with the 2 cm2V1s1of Trifunovic et al., who created n-channel poly-Si FETs fabricated directly on paper substrates, while achieving similar Vth values close to 8 V

[0031] , When compared with other FET devices constructed from nanoparticles smaller than 20 nm, the devices fabricated present a record mobility value, far surpassing the previously reported PFE values of ~10-5cm2V1s-1- IO-6cm2V1s-1for undoped Si-NC FETs

[0032] ,

[0017] ,

[0033] ,

[0025] ,

[0023] ,

[0028] , and PFE = ~10-4cm2V1s1- 10’5cm2V1s1for doped Si-NCs FETs

[0023] ,

[0026] ,

[0027] , For larger Si-NPs, it also surpasses reported FET mobility values of up to PFE = ~101cm2V1s1for Si-NPs of 70 nm in diameter

[0029] ,

[0034] ,

[0035] , The presented FET devices also show better PFE values than laser-treated films of doped Si-NCs

[0032] ,

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Claims

CLAIMS1. A method for manufacturing a field-effect transistor (100) comprising the following steps: forming a gate electrode layer (1) on a first surface of a dielectric layer (2); forming a source electrode and a drain electrode (3) on a second surface of said dielectric layer (2) by depositing a patterned conductive material that results in two coated regions on top of the dielectric layer (2), being said source electrode and said drain electrode separated by a gap, and being said source electrode and said drain electrode preceded by a priming layer when needed; and forming a semiconductor layer (4) on top of the dielectric layer (2) so that it is in contact with source electrode and the drain electrode (3) and covers the gap between said source and drain electrodes, to allow the formation of a conductive channel between the source and drain electrodes (3); wherein the source and drain contacts comprise a conductive material and, when needed, a priming layer to improve adhesion and the semiconductor layer (4) comprises a porous polycrystalline silicon-based material, being said porous polycrystalline silicon-based material obtained by the following steps: flowing a precursor gas mixture into a reaction chamber, said precursor gas mixture comprising at least one silicon-based gas; applying an electromagnetic field to said precursor gas mixture, thereby forming a non-thermal plasma; forming a solid product in the plasma, wherein said solid product comprises a plurality of hydrogen-terminated silicon-based nanoparticles; depositing a plurality of hydrogen-terminated silicon-based nanoparticles on top of said source electrode, said drain electrode and said channel formed between said source electrode and drain electrode; exposing said plurality of hydrogen-terminated silicon-based nanoparticles to an oxidizing medium; and subjecting said plurality of hydrogen-terminated silicon-based nanoparticles to a trigger mechanism, thereby inducing the sintering of the plurality ofhydrogen-terminated silicon-based nanoparticles through a chain reaction to form said porous polycrystalline silicon-based material.

2. A method according to claim 1 wherein at least one silicon-based gas is selected from the group consisting of silane, tetrachlorosilane and mixtures thereof.

3. A method according to any of the previous claims wherein the precursor gas mixture comprises hydrogen and / or at least one noble gas selected from the group consisting of helium, argon and mixtures thereof.

4. A method according to any of the previous claims wherein the oxidizing medium is selected from ambient air, liquid oxygen, perchlorates, nitrates, and mixtures thereof.

5. A method according to any of the previous claims wherein said hydrogen- terminated silicon-based nanoparticles comprise a grain size of 1 - 50 nm.

6. A method according to any of the previous claims wherein the sintering of the plurality of hydrogen-terminated silicon-based nanoparticles is performed without external heating, and at standard atmospheric pressure, 760 Torr.

7. A method according to claim 1 wherein the semiconductor layer connects the source electrode and the drain electrode, forming a conduction channel.

8. A method according to any of the previous claims wherein the trigger mechanism comprises an optical trigger consisting of light emitted from a light source, being said light irradiated onto the hydrogen-terminated silicon-based nanoparticles.

9. A method according to claim 8 wherein the light source comprises a laser or a focused light from any other source.

10. A field-effect transistor (100), obtainable by method according to any of claims 1 - 9, comprising a gate electrode layer (1), a dielectric layer (2), a priming layer, a source and drain electrodes (3) and a semiconductor layer (4), wherein thesemiconductor layer (4) comprises a porous polycrystalline silicon-based material having a crystalline fraction above 75 %.

11. A field-effect transistor (100) according to claim 10 wherein the porous polycrystalline silicon-based material comprises a grain size of 10 - 500 nm.

12. A field-effect transistor (100) according to any of claims 10-11 wherein the gate electrode layer (1) comprises an electrically conductive material, preferably silver.

13. A field-effect transistor (100) according to claim 10-12 wherein the dielectric layer (2) comprises a polymer-based material, preferably a paper-based material.

14. A field-effect transistor (100) according to claim 10-13 wherein the priming layer comprises a metal selected from titanium, chromium, tantalum, and mixtures thereof, or any other material that improves the adhesion of electrically conductive materials.

15. A field-effect transistor (100) according to claim 10-14 wherein the source electrode and the drain electrode (3) comprise an electrically conductive material, preferably gold.

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