Package and electronic device

Abstract

The present application relates to the technical field of electronic element packaging. Disclosed is a package, comprising a substrate, a first electronic element, a second electronic element, a third electronic element and a first electrical conductor. The substrate comprises a first surface and a second surface that are oppositely arranged in a first direction. The first electronic element is embedded in the substrate. The second electronic element is disposed on the first surface. The third electronic element is located on the downstream side in the first direction relative to the second electronic element. The first electrical conductor is arranged between the second electronic element and the third electronic element, and is respectively connected to the second electronic element and the third electronic element. Specifically, the first electronic element is an inductor, the second electronic element is a chip, and the third electronic element is a resistor or a capacitor. The present application can enhance the heat dissipation effect of the chip, thereby enabling the package to meet more market demands. Further disclosed in the present application is an electronic device.

Description

Packaging structure and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410446746.9, filed on April 12, 2024, and entitled "Packaging structure and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronic component packaging, in particular to a packaging structure and an electronic device. BACKGROUND

[0003] Embedded Component Package (ECP) is a form of packaging electronic components by embedding them inside a substrate, which can package and power electronic components, and has been widely used in industrial production and people's life.

[0004] Embedded Component Package generally includes a chip and an inductor. In the traditional Embedded Component Package, the chip is generally embedded in the module. However, due to the large heat generated by the chip and the large thermal resistance of the heat dissipation path in the module, the traditional Embedded Component Package cannot meet the needs in some high-power or high-heat-dissipation-use scenarios. SUMMARY

[0005] The present application provides a packaging structure and an electronic device, which can enhance the heat dissipation effect of the chip, so that the Embedded Component Package can meet more market demands.

[0006] In a first aspect, the present application provides a packaging structure, comprising a substrate, a first electronic component, a second electronic component, a third electronic component and a first conductive body. The substrate comprises a first surface and a second surface arranged oppositely along a first direction, the first direction being the thickness direction of the substrate, and the first direction being from the first surface to the second surface. The first electronic component is embedded in the substrate. The second electronic component is arranged on the first surface. The third electronic component is located on the downstream side of the first direction relative to the second electronic component. The first conductive body is arranged between the second electronic component and the third electronic component, and the first conductive body is connected to the second electronic component and the third electronic component respectively. Specifically, the first electronic component is an inductor, the second electronic component is a chip, and the third electronic component is a resistor or a capacitor.

[0007] By embedding the inductor in the substrate and arranging the chip on the first surface of the substrate, the above technical solution can reduce the obstructions around the chip, enhance the heat dissipation effect of the chip, and thus enable the packaging structure to be applied in high-power or high-heat-dissipation-use scenarios, so as to meet more market demands.

[0008] In some implementations of the present application, the substrate includes a frame and a first encapsulating member, the frame is provided with a mounting slot penetrating through the frame along a first direction. The first encapsulating member is made of a first encapsulating material, the first encapsulating material fills in the mounting slot and covers the upper surface and the lower surface of the frame. The first electronic component and the third electronic component are both embedded in the mounting slot.

[0009] In some implementations of the present application, the first electronic component is provided with a mounting surface, the mounting surface faces the second electronic component, the mounting surface is provided with a recess, and the third electronic component is arranged in the recess.

[0010] In some implementations of the present application, the recess is filled with a third encapsulating material, and the third electronic component is embedded in the third encapsulating material.

[0011] In some implementations of the present application, the third electronic component is located between the first electronic component and the second electronic component, the first encapsulating member includes a first encapsulating part and a second encapsulating part arranged in the mounting slot, the first encapsulating part is located on the side close to the second surface, the second encapsulating part is located on the side close to the first surface, the first electronic component is embedded in the first encapsulating part, and the third electronic component is embedded in the second encapsulating part.

[0012] In some implementations of the present application, the first electronic component is made of a preset material, and the third electronic component is embedded in the preset material.

[0013] In some implementations of the present application, the substrate includes a first base body and a second base body arranged in sequence along the first direction, the first base body is connected with the second base body, the first base body is arranged between the second base body and the second electronic component along the first direction, the first electronic component is embedded in the second base body, and the third electronic component is embedded in the first base body.

[0014] In some implementations of the present application, the first surface is provided with a second encapsulating member, the second encapsulating member is made of a second encapsulating material, and the second electronic component is embedded in the second encapsulating material.

[0015] In some implementations of the present application, the first surface is provided with a groove, the groove is provided with a fourth electronic component, and the fourth electronic component is embedded in the second encapsulating material.

[0016] In some implementations of the present application, the first electronic component is an inductor, the second electronic component is a chip, and the third electronic component is a resistor or a capacitor.

[0017] In some implementations of the present application, the first electronic component is provided with a winding, a second conductive body is arranged between the first electronic component and the second electronic component, and the second conductive body is connected with the winding and the second electronic component respectively.

[0018] In some implementations of the present application, the first conductive body is a plurality of metal layers stacked along a first direction.

[0019] In some implementations of the present application, the second electronic element is a power chip.

[0020] In a second aspect, the present application provides an electronic device, comprising a housing, a mainboard and a packaging structure as the first aspect, wherein the mainboard and the packaging structure are both arranged in the housing, and the packaging structure is connected with the mainboard. BRIEF DESCRIPTION OF DRAWINGS

[0021] Fig. 1 shows a schematic diagram of the appearance of the packaging structure;

[0022] Fig. 2 shows a cross-sectional view of the packaging structure in some embodiments of the present application;

[0023] Fig. 3(a) shows a state diagram of the processing procedure of the packaging structure in Embodiment One of the present application;

[0024] Fig. 3(b) shows a state diagram of the processing procedure of the packaging structure in Embodiment One of the present application;

[0025] Fig. 3(c) shows a state diagram of the processing procedure of the packaging structure in Embodiment One of the present application;

[0026] Fig. 3(d) shows a state diagram of the processing procedure of the packaging structure in Embodiment One of the present application;

[0027] Fig. 4(a) shows a state diagram of the processing procedure of the packaging structure in Embodiment Two of the present application;

[0028] Fig. 4(b) shows a state diagram of the processing procedure of the packaging structure in Embodiment Two of the present application;

[0029] Fig. 4(c) shows a state diagram of the processing procedure of the packaging structure in Embodiment Two of the present application;

[0030] Fig. 4(d) shows a state diagram of the processing procedure of the packaging structure in Embodiment Two of the present application;

[0031] Fig. 5(a) shows a state diagram of the processing procedure of the packaging structure in Embodiment Three of the present application;

[0032] Fig. 5(b) shows a state diagram of the processing procedure of the packaging structure in Embodiment Three of the present application;

[0033] Fig. 5(c) shows a state diagram of the processing procedure of the packaging structure in Embodiment Three of the present application;

[0034] Fig. 5(d) shows a state diagram of the processing procedure of the packaging structure in Embodiment Three of the present application;

[0035] Figure 6(a) shows a state diagram of the processing of the packaging structure in Embodiment Four of the present application;

[0036] Figure 6(b) shows a state diagram of the processing of the packaging structure in Embodiment Four of the present application;

[0037] Figure 6(c) shows a state diagram of the processing of the packaging structure in Embodiment Four of the present application;

[0038] Figure 6(d) shows a state diagram of the processing of the packaging structure in Embodiment Four of the present application;

[0039] Figure 7(a) shows a structural schematic diagram of a winding in some embodiments of the present application;

[0040] Figure 7(b) shows a structural schematic diagram of a winding in some embodiments of the present application;

[0041] Figure 7(c) shows a structural schematic diagram of a winding in some embodiments of the present application;

[0042] Figure 7(d) shows a structural schematic diagram of a winding in some embodiments of the present application;

[0043] Figure 7(e) shows a structural schematic diagram of a winding in some embodiments of the present application;

[0044] Figure 7(f) shows a structural schematic diagram of a winding in some embodiments of the present application;

[0045] Figure 7(g) shows a structural schematic diagram of a winding in some embodiments of the present application;

[0046] Figure 8(a) shows a structural schematic diagram of a second conductive body in some embodiments of the present application;

[0047] Figure 8(b) shows a structural schematic diagram of a second conductive body in some embodiments of the present application;

[0048] Figure 8(c) shows a structural schematic diagram of a second conductive body in some embodiments of the present application;

[0049] Figure 9(a) shows a state diagram of the processing of the packaging structure in Embodiment Five of the present application;

[0050] Figure 9(b) shows a state diagram of the processing of the packaging structure in Embodiment Five of the present application;

[0051] Figure 9(c) shows a state diagram of the processing of the packaging structure in Embodiment Five of the present application;

[0052] Figure 9(d) shows a state diagram of the processing of the packaging structure in Embodiment Five of the present application;

[0053] Fig. 10 shows a structural schematic diagram of a packaging structure in some embodiments of the present application;

[0054] Fig. 11(a) shows a processing state diagram of a packaging structure in Embodiment Six of the present application;

[0055] Fig. 11(b) shows a processing state diagram of a packaging structure in Embodiment Six of the present application;

[0056] Fig. 11(c) shows a processing state diagram of a packaging structure in Embodiment Six of the present application;

[0057] Fig. 11(d) shows a processing state diagram of a packaging structure in Embodiment Six of the present application;

[0058] Fig. 12 shows a structural schematic diagram of a packaging structure in some other embodiments of the present application;

[0059] Fig. 13 shows a structural schematic diagram of a packaging structure in some other embodiments of the present application;

[0060] Fig. 14 shows a structural schematic diagram of a packaging structure in some other embodiments of the present application. DETAILED DESCRIPTION

[0061] For the purpose of making the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0062] The present application provides a packaging structure, which can be applied in various electronic devices, such as network devices, computing devices, supercomputing servers, wireless devices, routers and the like. It should be noted that the packaging structure proposed in the embodiments of the present application includes but is not limited to being applied in these and any other suitable types of electronic devices.

[0063] As shown in Fig. 1, in some embodiments, an electronic device includes a mainboard 100 and a packaging structure 200 arranged above the mainboard 100, and the bottom of the packaging structure 200 is electrically connected with the mainboard 100.

[0064] Referring to Fig. 2, the packaging structure 200 provided by the present application includes a substrate 1, an inductor 2 (as an example of a first electronic element) and a chip 3 (as an example of a second electronic element). The substrate 1 includes an upper surface 11 (as an example of a first surface) and a lower surface 12 (as an example of a second surface) arranged oppositely along the thickness direction (denoted as X direction, as an example of a first direction) thereof. As shown in Fig. 2, the X direction is directed from the upper surface 11 to the lower surface 12. The inductor 2 is embedded in the substrate 1, and the chip 3 is arranged on the upper surface 11, and the inductor 2 is electrically connected with the chip 3.

[0065] The application can reduce the shielding around the inductor 2, enhance the heat dissipation effect of the inductor 2, and thus can be applied to high-power or high-heat-dissipation use scenarios to meet more market demands.

[0066] In some implementations of the application, referring to FIG. 2, the substrate 1 includes a frame 13 and a package 14 (as an example of a first package). The frame 13 is made of resin material. The frame 13 is provided with a mounting groove 131 penetrating the frame 13 along the X direction. The package 14 is made of ABF (as an example of a first packaging material). The ABF fills the mounting groove 131 and covers the upper surface 132 and the lower surface 133 of the frame 13. The inductor 2 is embedded in the ABF in the mounting groove 131.

[0067] In some implementations of the application, referring to FIG. 2, the upper surface 11 is also provided with a package 6 (as an example of a second package), which can also be made of ABF (as an example of a second packaging material), and the chip 3 is at least partially embedded in the package 6. By providing the package 6, the chip 3 can be protected. At the same time, since the thickness of the package 6 is significantly reduced compared to the thickness of the substrate 1, the heat dissipation effect of the chip 3 can be significantly improved compared to packaging the chip 3 in the substrate 1. The applicant has proved through experiments that, based on a 6W heat conduction pad, the chip 3 arranged on the upper surface 11 of the substrate 1 can reduce the junction temperature by 22℃ compared to embedding the chip 3 in the substrate 1.

[0068] In some use scenarios, a resistor-capacitor 4 (as an example of a third electronic element) is also provided in the packaging structure, which can be a resistor or a capacitor. In the prior art, the resistor-capacitor 4 is generally arranged on the upper surface 11 of the substrate 1 and embedded in the package 6. The resistor-capacitor 4 and the chip 3 are provided with conductive material to electrically connect the resistor-capacitor 4 and the chip 3. However, when the packaging structure of the application is provided with the resistor-capacitor 4 on the upper surface 11, the problem of high electrical stress risk may occur.

[0069] The applicant has found that the main reason for the high risk of electric stress caused by the resistor-capacitor 4 on the upper surface 11 is that the inductor 2 is embedded in the substrate 1, and the chip 3 is arranged on the upper surface 11, so the resistor-capacitor 4 and the chip 3 are arranged together on the upper surface 11, as shown in FIG. 2. In this case, in order to electrically connect the resistor-capacitor 4 and the chip 3, a conductive body extending in the horizontal direction needs to be arranged below the resistor-capacitor 4 and the chip 3 to realize the interconnection of the resistor-capacitor 4 and the chip 3. However, this arrangement will lengthen the extension path of the conductive body, resulting in a large parasitic resistance or inductance between the resistor-capacitor 4 and the chip 3, and a high risk of electric stress. In addition, arranging the resistor-capacitor 4 on the upper surface 11 will also increase the thickness of the packaging 6, so the thickness of the chip 3 also needs to be increased. For example, the thickness of the chip 3 is difficult to match the thickness of the 0402 capacitor, so the processing cost and difficulty will be increased.

[0070] To solve the above problems, in the packaging structure provided by the present application, the resistor-capacitor 4 is located on the downstream side of the chip 3 in the X direction. For example, the resistor-capacitor 4 is arranged below the chip 3. The projection area of the upper surface of the resistor-capacitor 4 and the lower surface of the chip 3 on the plane parallel to the X direction can intersect and overlap, or can have a certain spacing. Preferably, the resistor-capacitor 4 is arranged below the chip 3 as a whole, and a conductive body 5 (as an example of the first conductive body) is arranged in the spacing between the chip 3 and the resistor-capacitor 4, and the conductive body 5 is connected to the chip 3 and the resistor-capacitor 4 respectively to electrically connect the chip 3 and the resistor-capacitor 4. For example, the conductive body 5 can be a plurality of metal layers stacked in the X direction. The present application does not limit the relative position between the resistor-capacitor 4 and the inductor 2, and the resistor-capacitor 4 can be located between the inductor 2 and the chip 3, or at least partially embedded in the inductor 2.

[0071] By arranging the resistor-capacitor 4 below the chip 3 as a whole, the present application can vertically arrange the conductive path between the resistor-capacitor 4 and the chip 3 to reduce the length of the conductive path, thereby reducing parasitic and reducing the risk of electric stress. In addition, moving the resistor-capacitor 4 to the lower side of the chip 3 can also reduce the thickness of the packaging 6, thereby reducing the processing cost and difficulty. The applicant has proved through experiments that, compared with arranging the resistor-capacitor 4 on the upper surface of the substrate 1, the present application can increase the capacity of the resistor-capacitor 4 in the substrate 1 by 300%, reduce the thickness of the chip by 0.2-0.3mm, and greatly reduce the parasitic of the VIN link (DCR is reduced to 10% of the original scheme, and ACL is reduced to 25% of the original scheme), reduce the risk of stress, and improve the overall efficiency of the module.

[0072] In order for those skilled in the art to better understand, the mounting position and mounting method of the resistor-capacitor 4 are described in detail through several embodiments below.

[0073] Embodiment one

[0074] Fig. 3(a) to Fig. 3(d) show the processing state diagrams of the packaging structure provided by the embodiment one.

[0075] Firstly, referring to Fig. 3(d) as the last state, the inductor 2 is provided with a mounting surface 21, the mounting surface 21 faces the chip 3, the mounting surface 21 is provided with a recess 22, the resistor-capacitor 4 is arranged in the recess 22, the lower end of the conductive body 5 is connected with the resistor-capacitor 4, and the upper end of the conductive body 5 is connected with the chip 3. Specifically, the recess 22 is filled with a packaging material 143 (as an example of the third packaging material), and the resistor-capacitor 4 is embedded in the packaging material 143. Exemplarily, the packaging material 143 can be ABF.

[0076] According to each stage shown in Fig. 3(a) to Fig. 3(d), when the packaging structure is processed, firstly, the inductor 2 and the resistor-capacitor 4 are respectively attached to the film material 30, and the resistor-capacitor 4 is arranged in the recess 22, as shown in Fig. 3(a). Then, the packaging material 143 is filled and compressed into the recess 22 and the mounting groove 131, so that the resistor-capacitor 4 is embedded in the packaging material 143, as shown in Fig. 3(b). Then, the conductive body 5 and other circuit layers are processed in the inside of the packaging material 143, so that the conductive body 5 is connected with the chip 3 and the resistor-capacitor 4 respectively, and the embedded magnetic substrate is manufactured, as shown in Fig. 3(c). Finally, the chip 3 is attached to the upper surface of the embedded magnetic substrate, and the chip 3 is packaged by using the packaging material, as shown in Fig. 3(d).

[0077] The above technical solution can not only reduce the risk of electrical stress, but also reduce the overall thickness of the module by arranging the recess 22 on the inductor 2 and arranging the resistor-capacitor 4 in the recess 22.

[0078] Embodiment two

[0079] Fig. 4(a) to Fig. 4(d) show the processing state diagrams of the packaging structure provided by the embodiment two.

[0080] Firstly, referring to Fig. 4(d) as the last state, the inductor 2 is provided with a mounting surface 21, the mounting surface 21 faces the chip 3, the mounting surface 21 is provided with a recess 22, the resistor-capacitor 4 is arranged in the recess 22, the lower end of the conductive body 5 is connected with the resistor-capacitor 4, and the upper end of the conductive body 5 is connected with the chip 3. Specifically, the recess 22 is filled with a bottom filling glue 144 (as an example of the third packaging material), and the resistor-capacitor 4 is embedded in the bottom filling glue 144.

[0081] According to the stages shown in Figs. 4(a) to 4(d), when the packaging structure is processed, firstly, the inductor 2 and the resistor-capacitor 4 are attached to the film 30 respectively, and the resistor-capacitor 4 is located in the groove 22, as shown in Fig. 4(a). Then, the underfill adhesive 144 is filled and compressed into the groove 22, so that the resistor-capacitor 4 and part of the inductor 2 are embedded in the underfill adhesive 144. Then, the packaging material 143 (which can be ABF) is filled and compressed into the remaining space of the mounting groove 131, so that the inductor 2 is completely embedded in the packaging material 143, as shown in Fig. 4(b). Then, the conductive body 5 and other circuit layers in the interior of the substrate 1 are processed to form a buried magnetic substrate, as shown in Fig. 4(c). Finally, the chip 3 is attached to the upper surface of the buried magnetic substrate, and the chip 3 is packaged by the packaging material, as shown in Fig. 4(d).

[0082] Compared with the technical solution of the first embodiment, the second embodiment fills the groove 22 by dispensing. Since the dispensing process is simpler, the manufacturing cost can be saved.

[0083] Embodiment three

[0084] Figs. 5(a) to 5(d) show the process state diagrams of the packaging structure provided by the third embodiment.

[0085] Firstly, referring to Fig. 5(d) as the final state, the resistor-capacitor 4 is located between the inductor 2 and the chip 3, and the packaging member 14 includes a first packaging part 141 and a second packaging part 142 arranged in the mounting groove 131. The first packaging part 141 is located near the lower surface 12, and the inductor 2 is embedded in the first packaging part 141. The second packaging part 142 is located near the upper surface 11, and the resistor-capacitor 4 is embedded in the second packaging part 142. Specifically, the first packaging part 141 and the second packaging part 142 can be made of the same packaging material, or can be made of different packaging materials, which are not limited in the present application. In the following, the first packaging part 141 and the second packaging part 142 are taken as examples made of ABF to describe the processing flow of the packaging structure.

[0086] According to the stages shown in Figs. 5(a) to 5(d), when the packaging structure is processed, firstly, the resistor-capacitor 4 is attached to the film 30, and the ABF is filled and compressed into the mounting groove 131, so that the resistor-capacitor 4 is embedded in the second packaging part 142 formed by the first compression of the ABF, as shown in Fig. 5(a). Then, the inductor 2 is put into the mounting groove 131, and the ABF is filled and compressed into the mounting groove 131, so that the inductor 2 is embedded in the first packaging part 141 formed by the second compression of the ABF, as shown in Fig. 5(b). Then, the conductive body 5 and other circuit layers in the interior of the substrate 1 are processed to form a buried magnetic substrate, as shown in Fig. 5(c). Finally, the chip 3 is attached to the upper surface of the buried magnetic substrate, and the chip 3 is packaged by the packaging material, as shown in Fig. 5(d).

[0087] Compared with the technical solutions in Embodiment One and Embodiment Two, in Embodiment Three, the resistor-capacitor 4 is separated from the inductor 2, and the double-layer embedding structure is realized by twice compression, thus the groove 22 does not need to be set on the inductor 2, and the manufacturing cost of the inductor 2 is saved.

[0088] Embodiment Four

[0089] Fig. 6(a) to Fig. 6(d) show the processing process state diagrams of the packaging structure provided in Embodiment Four.

[0090] Firstly, referring to Fig. 6(d) as the last state, the inductor 2 is made of magnetic paste or magnetic plastic sealing material (as an example of preset material), and the inductor 2 is provided with a winding 23, and the resistor-capacitor 4 and the winding 23 are embedded in the magnetic paste or magnetic plastic sealing material. The electric conductor 8 (as an example of the second electric conductor) is arranged between the inductor 2 and the chip 3, and the electric conductor 8 is connected with the winding 23 and the chip 3 respectively, so as to realize the electrical connection between the inductor 2 and the chip 3.

[0091] According to each stage shown in Fig. 6(a) to Fig. 6(d), when the packaging structure is processed, firstly, the resistor-capacitor 4 and the winding 23 are respectively attached on the film material 30, as shown in Fig. 6(a). Then the magnetic paste or magnetic plastic sealing material is compressed and filled into the mounting groove 131, so that the resistor-capacitor 4 and the winding 23 are embedded in the magnetic paste or magnetic plastic sealing material, and the magnetic paste or magnetic plastic sealing material forms the inductor 2, as shown in Fig. 6(b). Then the electric conductor 5, the electric conductor 8 and other circuit layers are processed in the inside of the substrate 1, and the magnetic embedding substrate is manufactured, as shown in Fig. 6(c). Finally, the chip 3 is attached on the upper surface of the magnetic embedding substrate, and the chip 3 is packaged by using the packaging material, as shown in Fig. 6(d).

[0092] The above technical solution can simplify the process flow and further reduce the manufacturing cost by embedding the resistor-capacitor 4 and the winding 23 in the inductor 2 when the inductor 2 is manufactured.

[0093] The present application does not limit the specific structure and number of the winding 23 and the conductive body 8. The inductor 2 can have one winding 23 or multiple windings 23. Exemplarily, the winding 23 includes but is not limited to the structures shown in Figs. 7(a) to 7(g), and the conductive body 8 includes but is not limited to the structures shown in Figs. 8(a) to 8(c). In some embodiments, the conductive body 8 can be arranged in a blind hole with a certain depth on the substrate 1, and the conductive body 8 is connected to the winding 23 and the metal conductive structure on the upper end of the substrate 1, respectively. Specifically, the depth of the blind hole can be equal to the depth of the winding 23 (as shown in Fig. 8(a)), or greater than the depth of the winding 23 (as shown in Fig. 8(b)). In other embodiments, the conductive body 8 can be arranged in a through hole on the substrate 1, and the conductive body 8 is connected to the winding 23, the metal conductive structure on the upper end of the substrate 1, and the metal conductive structure on the lower end of the substrate 1, respectively (as shown in Fig. 8(c)).

[0094] Embodiment Five

[0095] Figs. 9(a) to 9(d) show the processing state diagrams of the packaging structure provided by embodiment five.

[0096] Firstly, referring to Fig. 9(d) as the final state, the substrate 1 includes the capacitor plate 10 (as an example of the first base body) and the buried magnetic substrate 20 (as an example of the second base body) arranged in sequence along the X direction, the capacitor plate 10 is connected to the buried magnetic substrate 20, the capacitor plate 10 is arranged between the buried magnetic substrate 20 and the chip 3 along the X direction, the inductor 2 is embedded in the buried magnetic substrate 20, and the resistor-capacitor 4 is embedded in the capacitor plate 10.

[0097] According to each stage shown in Figs. 9(a) to 9(d), the capacitor plate 10 and the buried magnetic substrate 20 can be processed separately when the packaging structure is processed. Exemplarily, the capacitor plate 10 is provided with a frame a 134, and the buried magnetic substrate 20 is provided with a frame b 135, and each of the frame a 134 and the frame b 135 is provided with a mounting groove.

[0098] Specifically, the capacitor plate 10 is processed in the following manner: firstly, the resistor-capacitor 4 is attached to the film material 30, and the packaging material 143 is pressed and filled into the frame a 134, so that the resistor-capacitor 4 is embedded in the packaging material 143, as shown in Fig. 9(a). Then, the conductive body 5 and other circuit layers are processed inside the packaging material 143 to form the capacitor plate 10, as shown in Fig. 9(b).

[0099] The buried magnetic substrate 20 is processed in a similar manner to the processing of the capacitor plate 10. Firstly, the inductor 2 is embedded in the packaging material 143 in the frame b 135, and then the conductive circuit layer is processed to form the buried magnetic substrate 20, as shown in Fig. 9(c).

[0100] When the embedded magnetic substrate 20 and the capacitor plate 10 are both processed, the embedded magnetic substrate 20 and the capacitor plate 10 need to be assembled, and the chip 3 is arranged on the upper surface of the capacitor plate 10, as shown in FIG. 9(d). Specifically, the chip 3 can be first arranged on the upper surface of the capacitor plate 10, the chip 3 is packaged by using a packaging material, and then the embedded magnetic substrate 20 and the capacitor plate 10 are welded together by spot welding. The embedded magnetic substrate 20 and the capacitor plate 10 can also be welded together by spot welding, and then the packaged chip 3 is arranged on the upper surface of the capacitor plate 10. Exemplarily, the connecting material between the embedded magnetic substrate 20 and the capacitor plate 10 can be copper or sintered silver. The above technical solution can divide the embedded magnetic substrate 20 and the capacitor plate 10 to different manufacturers for processing, thereby enhancing the flexibility of processing.

[0101] In some embodiments, the package 6 in which the chip 3 is embedded can also be processed as an independent individual, and then the embedded magnetic substrate 20, the capacitor plate 10 and the package 6 are sequentially welded from bottom to top (as shown in FIG. 10) to form a packaging structure.

[0102] Embodiment six

[0103] FIGS. 11(a) to 11(d) show the processing process state diagram of the packaging structure provided by embodiment six.

[0104] Firstly, referring to FIG. 11(d) as the final state, the upper surface 11 of the substrate 1 is provided with a groove 15, and the groove 15 is used to install the resistor-capacitor 4 (as an example of the fourth electronic element). In some embodiments, a plurality of resistor-capacitors 4 are arranged in the packaging structure, and the space for installing the resistor-capacitors 4 in the substrate 1 is limited. Therefore, the resistor-capacitor 4 (as shown by resistor-capacitor 4a in FIG. 11(d)) with high requirement for the length of the conductive path can be arranged below the chip 3, and the resistor-capacitor 4 (as shown by resistor-capacitor 4b in FIG. 11(d)) with low requirement for the length of the conductive path can be arranged in the groove 15 on the upper surface of the substrate 1, so as to reduce the thickness of the packaging material above the substrate 1.

[0105] According to the stages shown in FIGS. 11(a) to 11(d), when the packaging structure is processed, first, a part of the resistor-capacitor 4 is attached to the film material 30, and ABF is filled and pressed into the mounting groove 131, so that the resistor-capacitor 4 is embedded in the second packaging part 142 formed by the first pressing of ABF, as shown in FIG. 11(a). Then, the inductor 2 is placed in the mounting groove 131, and ABF is filled and pressed into the mounting groove 131, so that the inductor 2 is embedded in the first packaging part 141 formed by the second pressing of ABF, as shown in FIG. 11(b). Then, the conductive body 5 and other circuit layers are processed inside the substrate 1, and the groove 15 is processed on the upper surface of the substrate 1, to form a magnetic embedding substrate, as shown in FIG. 11(c). Finally, the remaining resistor-capacitors 4 are installed in the groove 15, and the chip 3 is surface-mounted on the upper surface of the magnetic embedding substrate, and the chip 3 and the resistor-capacitors 4 are packaged with packaging material, as shown in FIG. 11(d).

[0106] The above six embodiments respectively illustrate the installation position and installation mode of the resistor-capacitor 4 in detail, but the packaging structure provided by the present application is not limited to the above six embodiments. Any packaging structure that can satisfy the condition that the resistor-capacitor 4 is located on the downstream side of the chip 3 in the X direction as a whole, and the conductive body 5 is arranged between the resistor-capacitor 4 and the chip 3 in the X direction, belongs to the protection scope of the present application.

[0107] The present application does not limit the number of layers of the resistor-capacitor 4 embedded in the substrate 1. In some implementations of the present application, the resistor-capacitor 4 embedded in the substrate 1 can be two layers (as shown in FIG. 12), or more than or equal to three layers.

[0108] In some implementations of the present application, referring to FIG. 13, the chip 3 has a front surface 31 and a back surface 32, wherein the surface of the chip 3 on which the pins are arranged is the front surface 31, and the surface opposite to the front surface 31 is the back surface 32. The present application does not limit the orientation of the chip 3. The front surface 31 of the chip 3 can face the side where the resistor-capacitor 4 is located (as shown in chip 3a in FIG. 13), or can face away from the side where the resistor-capacitor 4 is located (as shown in chip 3b in FIG. 13).

[0109] In some implementations of the present application, referring to FIG. 14, the inductor 2, the chip 3, and the resistor-capacitor 4 can be embedded in the substrate 1 together. That is, the chip 3 can be directly embedded in the substrate 1, without the need to additionally arrange a packaging member on the upper surface of the substrate 1.

[0110] In some implementations of the present application, the packaging structure is applied to a power supply device, and the chip 3 is a power supply chip.

[0111] The application also provides an electronic device, as shown in Fig. 1, comprising a shell (not shown in the figure), a mainboard 100 and any one of the packaging structures 200 introduced in combination with Fig. 3 (a) and Fig. 14 in the foregoing embodiments, wherein the mainboard 100 and the packaging structure 200 are both arranged in the shell, and the packaging structure 200 is connected with the mainboard 100.

[0112] The above describes the embodiments of the application by specific examples, and other advantages and effects of the application can be easily understood by those skilled in the art according to the content disclosed in the specification. Although the description of the application is introduced in combination with some embodiments, this does not mean that the features of the application are limited to the embodiments. On the contrary, the purpose of introducing the application in combination with the embodiments is to cover other options or modifications that can be extended based on the claims of the application. The application can also not use these details. In addition, in order to avoid confusion or obscure the focus of the application, some specific details are omitted in the description. It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other without conflict.

[0113] In the embodiments of the application, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second", "third", "fourth" can explicitly or implicitly include one or more of the features.

[0114] In the embodiments of the application, "and / or" is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. In addition, the character " / " in this paper generally represents a "or" relationship between the front and rear associated objects.

[0115] In the description of the embodiments of the application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection" should be understood in a broad sense, for example, "connection" can be detachable connection, or can be non-detachable connection; can be direct connection, or can be indirect connection through intermediate medium.

[0116] In the description of the application, it should be noted that the terms "upper", "lower", "top", "bottom" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0117] In the description of the application, it needs to be explained that, unless otherwise explicitly specified and limited, the terms "set", "install", "connect", "attach" should be understood broadly, for example, can be fixedly connected, can also be detachably connected, or integrally connected; can be mechanically connected, can also be electrically connected; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meanings of the above terms in the application can be understood according to the specific circumstances.

[0118] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A packaging structure, characterized in that: include: A substrate comprising a first surface and a second surface arranged opposite to each other along a first direction, wherein the first direction is a thickness direction of the substrate and the first direction is from the first surface to the second surface; A first electronic component embedded in the substrate; a second electronic component disposed on the first surface; a third electronic component located on a downstream side of the first direction relative to the second electronic component; The first conductor is provided between the second electronic component and the third electronic component, and the first conductor is connected to the second electronic component and the third electronic component respectively.

2. The packaging structure according to claim 1, wherein: The substrate comprises: a frame, provided with a mounting slot extending through the frame along the first direction; a first packaging member made of a first packaging material, wherein the first packaging material fills the mounting groove and covers the upper surface and the lower surface of the frame; The first electronic component and the third electronic component are both embedded in the installation groove.

3. The packaging structure according to claim 2, wherein: The first electronic component is provided with a mounting surface, the mounting surface faces the second electronic component, the mounting surface is provided with a groove, and the third electronic component is arranged in the groove.

4. The packaging structure according to claim 3, wherein: The groove is filled with a third packaging material, and the third electronic component is embedded in the third packaging material.

5. The packaging structure according to claim 2, wherein: The third electronic component is located between the first electronic component and the second electronic component. The first package includes a first packaging part and a second packaging part provided in the mounting groove. The first packaging part is located on a side close to the second surface, and the second packaging part is located on a side close to the first surface. The first electronic component is embedded in the first packaging part, and the third electronic component is embedded in the second packaging part.

6. The packaging structure according to claim 2, wherein: The first electronic component is made of a preset material, and the third electronic component is embedded in the preset material.

7. The packaging structure according to claim 1, wherein: The substrate includes a first base and a second base arranged in sequence along the first direction, the first base is connected to the second base, the first base is arranged between the second base and the second electronic component along the first direction, the first electronic component is embedded in the second base, and the third electronic component is embedded in the first base.

8. The packaging structure according to claim 1, wherein: A second packaging member is provided on the first surface. The second packaging member is made of a second packaging material. The second electronic component is embedded in the second packaging material.

9. The packaging structure according to claim 8, wherein: A slot is provided on the first surface. A fourth electronic component is provided in the slot. The fourth electronic component is embedded in the second packaging material.

10. The packaging structure according to claim 1, wherein: The first electronic component is an inductor, the second electronic component is a chip, and the third electronic component is a resistor or a capacitor.

11. The packaging structure according to claim 10, wherein: A winding is provided in the first electronic component, a second conductor is provided between the first electronic component and the second electronic component, and the second conductor is connected to the winding and the second electronic component respectively.

12. The packaging structure according to any one of claims 1 to 11, characterized in that: The first conductor is a plurality of metal layers stacked along the first direction.

13. The packaging structure according to claim 10, wherein: The second electronic component is a power chip.

14. An electronic device, characterized in that: The invention comprises a housing, a main board and the packaging structure according to any one of claims 1 to 13, wherein the packaging structure is arranged on the main board.

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