Memory, memory control method, storage system, and electronic device

Abstract

The embodiments of the present application relate to the technical field of storage, and particularly relate to a memory, a memory control method, a storage system, and an electronic device. The memory comprises a first bit line, a second bit line, a first word line select transistor, a second word line select transistor, a plurality of first capacitors, a plurality of second capacitors and a sense amplifier, wherein the first word line select transistor, which is coupled to the plurality of first capacitors, is further coupled to the first bit line; the second word line select transistor, which is coupled to the plurality of second capacitors, is further coupled to the second bit line; both the first bit line and the second bit line are coupled to the sense amplifier; a first target capacitor among the plurality of first capacitors and a second target capacitor among the plurality of second capacitors are used for storing opposite data; and the data stored in the second target capacitor is not used as output data of the memory. The memory is used for: inputting a read instruction, which is used for instructing to read the data of the first target capacitor; and outputting the data of the first target capacitor in response to the read instruction. In this way, the data read error rate can be reduced.

Description

Memory, memory control method, storage system and electronic device

[0001] The present application claims priority from the Chinese patent application No. 202410411749.9 filed with the State Intellectual Property Office on April 7, 2024 and entitled "Memory, Memory Control Method, Storage System and Electronic Device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of storage, in particular to a memory, a memory control method, a storage system and an electronic device. BACKGROUND

[0003] The development of artificial intelligence (AI) and large language models has led to massive data processing and storage requirements. How to efficiently store the growing data has become a technical challenge. Ferroelectric random access memory (FeRAM) (also known as ferroelectric memory) uses a capacitor of ferroelectric material. The ferroelectric capacitor can undergo spontaneous polarization, and the polarization strength of the ferroelectric capacitor can be reoriented with the action of an external electric field. Applying an electric field of the same direction to ferroelectric capacitors with different direction of residual polarization strength, the flipping charge of the ferroelectric capacitor is different. According to the different flipping charge, data 0 and 1 can be stored. Therefore, the ferroelectric memory can use the polarization characteristics of the ferroelectric capacitor for data storage.

[0004] The ferroelectric memory can adopt a three-dimensional stacked structure, but the three-dimensional stacked structure will affect the polarization state of the ferroelectric capacitor, resulting in the problem of a large data read error rate. SUMMARY

[0005] Embodiments of the present application provide a memory, a memory control method, a storage system and an electronic device, which solve the problem of a large data read error rate in the prior art.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, a memory is provided. The memory includes a first bit line, a second bit line, a first word line selection transistor, a second word line selection transistor, a plurality of first capacitors, a plurality of second capacitors, and a sense amplifier. First plates of the plurality of first capacitors are coupled to first ends of the first word line selection transistor respectively, and second ends of the first word line selection transistor are coupled to the first bit line. First plates of the plurality of second capacitors are coupled to first ends of the second word line selection transistor respectively, and second ends of the second word line selection transistor are coupled to the second bit line. An input of the sense amplifier is coupled to the first bit line, and a reference input of the sense amplifier is coupled to the second bit line. The plurality of first capacitors include a first target capacitor, and the plurality of second capacitors include a second target capacitor. The first target capacitor and the second target capacitor are configured to store opposite data. Data stored in the second target capacitor is not output as output data of the memory. The memory is configured to: input a read instruction, the read instruction being configured to indicate reading data of the first target capacitor; and output the data of the first target capacitor in response to the read instruction.

[0008] In the above technical solution, the memory in which the plurality of first capacitors are coupled to the first word line selection transistor is a three-dimensional stacked structure. The three-dimensional stacked structure is relatively complex, and polarization states of capacitors in different layers are different, which results in that a read margin of the three-dimensional stacked memory is smaller than a read margin of a planar structure memory. The first target capacitor and the second target capacitor in the technical solution are configured to store opposite data. Data stored in the first target capacitor is output as output data, and data stored in the second target capacitor is not output as output data. When reading data of the first target capacitor, a voltage on the bit line does not need to be identified by comparison with a reference voltage, but a voltage on the first bit line and a voltage on the second bit line are compared. In this way, the read margin of the three-dimensional stacked memory can be expanded, and a data read error rate can be reduced. Moreover, a hardware structure of a memory cell is not changed, and only a method is changed, so that a hardware cost is relatively low. On the other hand, although the three-dimensional stacked memory does not output data stored in the second target capacitor, a storage density of the three-dimensional stacked memory is still relatively large compared with a planar structure memory. The three-dimensional stacked memory can further improve the read margin and reduce the data read error rate on the basis of maintaining a relatively large storage density by using the technical solution.

[0009] In a possible implementation manner of the first aspect, the sense amplifier is configured to: in the reading phase of the memory, input a voltage of the first bit line through the input terminal, and input a voltage of the second bit line through the reference input terminal; and output data stored in the first target capacitor according to the voltage of the first bit line and the voltage of the second bit line. In the possible manner, the sense amplifier only needs to be coupled with the first bit line and the second bit line, and does not need to be coupled with a voltage source for providing a reference voltage. Therefore, the hardware coupling structure of the sense amplifier is simpler. Moreover, the sense amplifier compares the voltage of the first bit line with the voltage of the second bit line, and does not need to rely on the reference voltage for comparison, so that the reading margin is larger. Because the reading margin is larger, even if the sense amplifier is affected by transistor mismatch and process fluctuation, the data can still be correctly read out. Therefore, the requirements on the performance parameters of the transistors of the sense amplifier and the process fluctuation can be reduced.

[0010] In a possible implementation manner of the first aspect, the memory further includes a first word line, a second word line, a first plate line and a second plate line. A second plate of the first target capacitor is coupled with the first plate line, and a control terminal of the first word line selection transistor is coupled with the first word line. A second plate of the second target capacitor is coupled with the second plate line, and a control terminal of the second word line selection transistor is coupled with the second word line. The memory is configured to: in the reading phase, apply a turn-on voltage to the first word line, apply a first voltage to the first bit line, and apply a second voltage to the first plate line. In the reading phase, apply a turn-on voltage to the second word line, apply a first voltage to the second bit line, and apply a second voltage to the second plate line. The turn-on voltage is used to turn on the word line selection transistor coupled with the corresponding word line. The absolute value of the difference between the first voltage and the second voltage is greater than the coercive voltage. In the possible manner, the same voltage is applied to both sides of the plate of the first target capacitor and both sides of the plate of the second target capacitor. Therefore, the data stored in the first target capacitor and the data stored in the second target capacitor can be determined by the voltage on the first bit line and the voltage on the second bit line. In this way, the manner of applying the voltage is simpler, and the corresponding software setting is also simpler.

[0011] In a possible implementation manner of the first aspect, the memory further includes a first word line, a second word line, a first plate line and a second plate line. The second plate of the first target capacitor is coupled with the first plate line, and the control end of the first word line selection transistor is coupled with the first word line. The second plate of the second target capacitor is coupled with the second plate line, and the control end of the second word line selection transistor is coupled with the second word line. The memory is configured to: in a write phase of the memory, apply a turn-on voltage to the first word line, apply a first voltage to the first bit line, and apply a second voltage to the first plate line. In the write phase, the turn-on voltage is applied to the second word line, the second voltage is applied to the second bit line, and the first voltage is applied to the second plate line. The turn-on voltage is used to turn on the word line selection transistor coupled with the corresponding word line. The absolute value of the difference between the first voltage and the second voltage is greater than the coercive voltage. In the above possible manner, opposite voltages are applied to the two sides of the plates of the first target capacitor and the second target capacitor respectively, and opposite data can be stored in the first target capacitor and the second target capacitor in the same time period. In this way, the time for writing data is short, and the writing speed is fast.

[0012] In a possible implementation manner of the first aspect, the memory is specifically configured to: in a first time period of the write phase, apply a turn-on voltage to the first word line and the second word line, apply a first voltage to the first bit line and the second bit line, and apply a second voltage to the first plate line and the second plate line. In a second time period after the first time period of the write phase, the turn-on voltage is applied to the first word line and the second word line, a third voltage is applied to the first bit line, the second voltage is applied to the second bit line, and the first voltage is applied to the first plate line and the second plate line. The absolute value of the difference between the third voltage and the first voltage is less than or equal to the coercive voltage. The absolute value of the difference between the third voltage and the second voltage is less than or equal to the coercive voltage. In the above possible manner, the first bit line and the second bit line can be controlled together (or be the same bit line). The first plate line and the second plate line can be controlled together (or be the same plate line). In the first time period, one data (such as data 1) is written to the first target capacitor and the second target capacitor, and in the second time period, data opposite to the foregoing data (such as data 0) is written to the second target capacitor. Thus, opposite data is stored in the first target capacitor and the second target capacitor. In this way, the operations on the first bit line and the second bit line, and the operations on the first plate line and the second plate line are simple.

[0013] In a possible implementation manner of the first aspect, the first word line and the second word line are the same word line, or the first word line and the second word line are different word lines. In the above possible manner, the first word line and the second word line can be the same physical structure or different physical structures. In this way, the positions of the first target capacitor and the second target capacitor are not limited by the positions of the corresponding word lines. This embodiment does not need to change the hardware structure of the memory cell array, but only needs to change the way of storing and reading data, and the hardware cost is small.

[0014] In a possible implementation of the first aspect, the first plate line and the second plate line are the same plate line, or the first plate line and the second plate line are different plate lines. In the above possible manners, the first word line and the second word line can be the same physical structure or different physical structures. In this way, the positions of the first target capacitor and the second target capacitor are not limited by the positions of the corresponding plate lines. This implementation does not need to change the hardware structure of the memory cell array, but only needs to change the way of storing and reading data, and the hardware cost is small.

[0015] In a second aspect, a control method of a memory is provided. The memory includes a first bit line, a second bit line, a first word line selection transistor, a second word line selection transistor, a plurality of first capacitors, a plurality of second capacitors, and a sense amplifier. First plates of the plurality of first capacitors are coupled to first ends of the first word line selection transistor respectively, and a second end of the first word line selection transistor is coupled to the first bit line. First plates of the plurality of second capacitors are coupled to first ends of the second word line selection transistor respectively, and a second end of the second word line selection transistor is coupled to the second bit line. An input end of the sense amplifier is coupled to the first bit line, and a reference input end of the sense amplifier is coupled to the second bit line. The plurality of first capacitors include a first target capacitor, and the plurality of second capacitors include a second target capacitor. The first target capacitor and the second target capacitor are used to store opposite data. The data stored by the second target capacitor is not used as output data of the memory. The method includes: the memory inputs a read instruction, the read instruction being used to indicate reading data of the first target capacitor. The memory outputs the data of the first target capacitor in response to the read instruction.

[0016] In a possible implementation of the second aspect, the method further includes: in a read phase of the memory, the sense amplifier inputs a voltage of the first bit line through the input end and inputs a voltage of the second bit line through the reference input end. The sense amplifier outputs the data stored by the first target capacitor according to the voltage of the first bit line and the voltage of the second bit line.

[0017] In a possible implementation of the second aspect, the memory further includes a first word line, a second word line, a first plate line, and a second plate line. A second plate of the first target capacitor is coupled to the first plate line, and a control end of the first word line selection transistor is coupled to the first word line. A second plate of the second target capacitor is coupled to the second plate line, and a control end of the second word line selection transistor is coupled to the second word line. The method further includes: in the read phase, the memory applies a turn-on voltage to the first word line, applies a first voltage to the first bit line, and applies a second voltage to the first plate line. In the read phase, the memory applies the turn-on voltage to the second word line, applies the first voltage to the second bit line, and applies the second voltage to the second plate line. The turn-on voltage is used to turn on the word line selection transistor coupled to the corresponding word line. An absolute value of a difference between the first voltage and the second voltage is greater than a coercive voltage.

[0018] In a possible implementation manner of the second aspect, the memory further includes a first word line, a second word line, a first plate line and a second plate line. The second plate of the first target capacitor is coupled with the first plate line, and the control end of the first word line selection transistor is coupled with the first word line. The second plate of the second target capacitor is coupled with the second plate line, and the control end of the second word line selection transistor is coupled with the second word line. The method further includes: in the write stage, the memory applies a turn-on voltage to the first word line, applies a first voltage to the first bit line, and applies a second voltage to the first plate line. In the write stage, the memory applies a turn-on voltage to the second word line, applies a second voltage to the second bit line, and applies a first voltage to the second plate line. The turn-on voltage is used to turn on the word line selection transistor coupled with the corresponding word line. The absolute value of the difference between the first voltage and the second voltage is greater than the coercive voltage.

[0019] In a possible implementation manner of the second aspect, in the write stage, the memory applies a turn-on voltage to the first word line, applies a first voltage to the first bit line, and applies a second voltage to the first plate line, including: in a first time period of the write stage, the memory applies a turn-on voltage to the first word line and the second word line, applies a first voltage to the first bit line and the second bit line, and applies a second voltage to the first plate line and the second plate line. In the write stage, the memory applies a turn-on voltage to the second word line, applies a second voltage to the second bit line, and applies a first voltage to the second plate line, including: in a second time period after the first time period of the write stage, the memory applies a turn-on voltage to the first word line and the second word line, applies a third voltage to the first bit line, applies a second voltage to the second bit line, and applies a first voltage to the first plate line and the second plate line. The absolute value of the difference between the third voltage and the first voltage is less than or equal to the coercive voltage. The absolute value of the difference between the third voltage and the second voltage is less than or equal to the coercive voltage.

[0020] In a possible implementation manner of the second aspect, the first word line and the second word line are the same word line, or the first word line and the second word line are different word lines.

[0021] In a possible implementation manner of the second aspect, the first plate line and the second plate line are the same plate line, or the first plate line and the second plate line are different plate lines.

[0022] In a third aspect, a storage system is provided. The storage system includes the memory provided in the first aspect or any possible implementation manner of the first aspect, and a controller coupled with the memory.

[0023] In a fourth aspect, an electronic device is provided. The electronic device includes the storage system provided in the third aspect and a processor coupled with the storage system.

[0024] In a fifth aspect, a computer readable storage medium is provided. The computer readable storage medium includes computer instructions, which when executed on an electronic device, cause the electronic device to perform the method provided in the second aspect or any possible implementation of the second aspect.

[0025] In a sixth aspect, a computer program product is provided. The computer program product, when executed on a computer, causes the computer to perform the method provided in the second aspect or any possible implementation of the second aspect.

[0026] It can be understood that any memory control method, memory system, electronic device, computer storage medium or computer program product provided by the above can apply to the above memory. Therefore, the beneficial effects achieved thereby can refer to the beneficial effects of the corresponding memory provided above, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0027] FIG. 1 is a structural schematic diagram of a storage unit provided by an embodiment of the present application;

[0028] FIG. 2 is a schematic diagram of a storage principle of a ferroelectric capacitor provided by an embodiment of the present application;

[0029] FIG. 3 is a schematic diagram of a three-dimensional storage unit array provided by an embodiment of the present application;

[0030] FIG. 4 is a side view of a three-dimensional storage unit array provided by an embodiment of the present application;

[0031] FIG. 5 is a top view of a three-dimensional storage unit array provided by an embodiment of the present application;

[0032] FIG. 6 is a normal distribution diagram of a voltage generated by a capacitor on a corresponding bit line in a read operation provided by an embodiment of the present application;

[0033] FIG. 7 is a schematic diagram of a voltage distribution provided by an embodiment of the present application;

[0034] FIG. 8 is a structural schematic diagram of a memory provided by an embodiment of the present application;

[0035] FIG. 9 is a schematic diagram of output data provided by an embodiment of the present application;

[0036] FIG. 10 is a normal distribution diagram of a voltage generated by a capacitor on a corresponding bit line in another read operation provided by an embodiment of the present application;

[0037] FIG. 11 is a schematic diagram of a read result provided by an embodiment of the present application;

[0038] FIG. 12 is a structural schematic diagram of a memory provided by an embodiment of the present application;

[0039] FIG. 13 is a schematic diagram of a write voltage according to an embodiment of the present application;

[0040] FIG. 14 is a schematic diagram of a write voltage according to an embodiment of the present application;

[0041] FIG. 15 is a schematic diagram of a read voltage according to an embodiment of the present application;

[0042] FIG. 16 is a schematic diagram of a memory structure according to an embodiment of the present application;

[0043] FIG. 17 is a schematic diagram of a write voltage according to an embodiment of the present application;

[0044] FIG. 18 is a schematic diagram of a write voltage according to an embodiment of the present application;

[0045] FIG. 19 is a schematic diagram of a control method of a memory according to an embodiment of the present application;

[0046] FIG. 20 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] It should be noted that the terms "first" and "second" and the like in the embodiments of the present application are only used for the purpose of distinguishing the same type of features, and should not be understood as indicating relative importance, quantity or sequence.

[0048] The terms "exemplary" or "for example" and the like in the embodiments of the present application are used to indicate that the embodiments or designs so described are merely exemplary or illustrative, and should not be interpreted as meaning that the embodiments or designs so described are preferred or superior to other embodiments or designs. In fact, the use of the terms "exemplary" or "for example" and the like is intended to present the relevant concept in a specific manner.

[0049] The terms "coupled" or "connected" in the embodiments of the present application should be interpreted in a broad sense, for example, can refer to a direct physical connection, or can refer to an indirect connection through electronic devices, such as a connection through resistors, inductors, capacitors or other electronic devices.

[0050] First, some basic concepts related to the present application are explained:

[0051] A transistor is an electronic device for controlling current flow. Take a metal-oxide-semiconductor field effect transistor (MOSFET) as an example. The transistor includes a source, a drain, and a gate. In embodiments of the present application, the control terminal of the transistor can refer to the gate, the first terminal of the transistor can refer to the source (or the drain), and the second terminal of the transistor can refer to the drain (or the source).

[0052] The memory is used to store software programs and modules. The memory mainly includes a program storage area and a data storage area. The program storage area can store operating systems and at least one application required by a function, etc. The data storage area can store data created according to use, etc. The memory includes external memory and internal memory. The data stored in the external memory and the internal memory can be transmitted to each other. The external memory can include hardware, a U disk, a floppy disk, etc. The internal memory can include a random access memory and a read-only memory, etc.

[0053] Dynamic random access memory (DRAM) is a kind of internal memory. The storage unit of the DRAM can be a single-tube single-capacitor (1 transistor 1 capacitor, 1T1C) type. The 1T1C storage unit refers to: a storage unit is composed of a transistor and a capacitor. The DRAM stores different data through different voltage values stored on the capacitor. For example, when a high voltage is stored on the capacitor, the storage unit corresponds to store data 1; when a low voltage is stored on the capacitor, the storage unit corresponds to store data 0. The DRAM has the following problems: first, when the DRAM is powered off, the transistor is in an off state, but there is a leakage current between the transistor and the capacitor. The voltage signal stored in the capacitor may gradually decrease under the influence of the leakage current, thereby causing data loss. Therefore, the data of the DRAM will be lost after power off, and the DRAM belongs to a volatile memory. Second, since the DRAM is a volatile memory, in order to save the data in the DRAM, the data in the DRAM needs to be refreshed regularly. The refresh operation will generate a large amount of power consumption. Third, as the process gradually approaches the physical limit, the planar micro-shrinking speed of the DRAM has gradually slowed down, and it is difficult to meet the growing data storage demand.

[0054] Ferroelectric Random Access Memory (FeRAM), also known as ferroelectric memory, is a type of memory. The storage unit of a ferroelectric memory can be a single transistor single capacitor (1T1C) structure, a double transistor double capacitor (2T2C) structure, and a single transistor multiple capacitor (1TnC) structure, etc. A 1T1C storage unit refers to a storage unit composed of one transistor and one capacitor. A 1T1C memory can be a planar structure. As shown in FIG. 1, a 1T1C memory includes a plurality of rows and a plurality of columns of storage units, each of which includes one transistor and one capacitor. The first end of the transistor in the same storage unit is coupled to a storage node (SN) with the first plate of the capacitor. The second end of the transistor in the same row is coupled to a bit line (BL). The control end of the transistor in the same column is coupled to a word line (WL). The second plate of the capacitor in the same column is coupled to a plate line (PL). A 2T2C storage unit refers to a storage unit composed of two transistors and two capacitors. A 2T2C memory can be a planar structure. In the same storage unit, the first end of one transistor is coupled to a storage node with the first plate of one capacitor, and the first end of the other transistor is coupled to another storage node with the first plate of another capacitor. Other coupling structures of a 2T2C memory can refer to a 1T1C memory. A 1TnC storage unit refers to a storage unit composed of one transistor and n capacitors, n≥2.

[0055] A ferroelectric memory stores different data through the polarization characteristics of a ferroelectric capacitor (FeCAP). The remained polarization strength (Pr) refers to the polarization strength retained in the ferroelectric capacitor without an external electric field. The saturated polarization strength (Ps) refers to the maximum polarization strength reached by the ferroelectric capacitor under a given electric field strength. For example, if the ferroelectric capacitor stores data 1, its remained polarization strength is -Pr. If the ferroelectric capacitor stores data 0, its remained polarization strength is Pr. The following examples are based on the operations of reading and writing data by a ferroelectric memory, respectively:

[0056] For example, reading data from the ferroelectric memory: as shown in FIG. 2. When the data stored in the ferroelectric memory is 1, a voltage Vr is applied to the ferroelectric capacitor, and the polarization intensity of the ferroelectric capacitor reaches the saturation polarization intensity Ps in the direction of ①. In this process, the charge released by the ferroelectric capacitor is Ps+Pr, and the voltage change is Vr. It can be concluded that the equivalent capacitance of the ferroelectric capacitor when storing data 1 is CA1=A*(Ps+Pr) / Vr, and A is the area of the ferroelectric capacitor. When the data stored in the ferroelectric memory is 0, a voltage Vr is applied to the ferroelectric capacitor, and the ferroelectric capacitor reaches the saturation polarization intensity Ps. In this process, the charge released by the ferroelectric capacitor is Ps-Pr, and the voltage change is Vr. It can be concluded that the equivalent capacitance of the ferroelectric capacitor when storing data 0 is CA0=A*(Ps-Pr) / Vr. Wherein, Vr is greater than the coercive voltage, which is the critical value of the voltage that causes the polarization direction of the ferroelectric capacitor to reverse. The charge released by the ferroelectric capacitor will be reflected as the voltage on the corresponding bit line. The charge released by the ferroelectric capacitor storing data 1 is more than the charge released by the ferroelectric capacitor storing data 0, so the bit line voltage corresponding to the ferroelectric capacitor storing data 1 is higher than the bit line voltage corresponding to the ferroelectric capacitor storing data 0. By detecting the high and low of the bit line voltage, the data stored in the ferroelectric capacitor is read.

[0057] For example, writing data in the ferroelectric memory: when the data stored in the ferroelectric memory is 1, a voltage Vr is applied to the ferroelectric capacitor, and the polarization intensity of the ferroelectric capacitor reaches the saturation polarization intensity Ps in the direction of ①. After stopping applying the voltage Vr, the polarization intensity of the ferroelectric capacitor reaches the residual polarization intensity Pr in the direction of ②. In this way, data 1 is rewritten as data 0.

[0058] As can be seen from the above, reading data is also the process of writing data 1 or 0. If the data stored in the ferroelectric capacitor is rewritten after reading, a write-back operation is needed to write the original data back to the ferroelectric capacitor. Alternatively, the residual polarization intensity of the ferroelectric capacitor being -Pr can also indicate that data 0 is stored, and the residual polarization intensity of the ferroelectric capacitor being Pr can also indicate that data 1 is stored. In order to introduce the embodiments of the present application in detail, the embodiments of the present application will be illustrated by the case shown in FIG. 2 in the following, but not limited to the scheme of the present application.

[0059] The ferroelectric memory has the following advantages: first, the polarization strength of the ferroelectric capacitor can be reoriented with the action of the external electric field, so as to store different amounts of electric charges to represent different data. Since the polarization direction of the ferroelectric capacitor can also be maintained after the electric field is removed, the ferroelectric memory is a non-volatile memory. Second, the ferroelectric memory can save data for a long time without frequent refreshing, so the power consumption is low. Third, the ferroelectric memory stores data through the polarization direction of the ferroelectric capacitor, instead of storing data through the voltage on the capacitor like DRAM. Therefore, the requirement for reducing the transistor leakage of the ferroelectric memory is lower, and the process of the ferroelectric memory is simpler. Fourth, the ferroelectric memory has the advantage of back end of line (BEOL) compatibility, and can be used to build high-density embedded memory to replace the traditional embedded DRAM. Fifth, since the electric charge stored in the ferroelectric capacitor will only be discharged when a voltage exceeding the coercive voltage is applied, the ferroelectric memory can adopt a three-dimensional stacked structure (such as 1TnC memory). Compared with the ferroelectric memory of the planar structure (such as 1T1C and 2T2C ferroelectric memory), the ferroelectric memory of the three-dimensional stacked structure can adopt a vertical field effect transistor (VFET), and multiple ferroelectric capacitors share one transistor. The ferroelectric memory of the three-dimensional stacked structure can prepare multiple storage units under the same area overhead. In this way, the number of transistors can be saved, the area of the ferroelectric capacitor can be made larger, the requirement for the trench depth can be reduced, and the storage density can be improved.

[0060] Next, a 1TnC ferroelectric memory with a three-dimensional stack structure is introduced. Hereinafter, the ferroelectric memory is referred to as memory, and the ferroelectric capacitor is referred to as capacitor. As shown in FIG. 3, the 1TnC memory includes a plurality of bit lines (e.g., BL1-BL5) extending along a first direction, a plurality of word lines (e.g., WL1-WL5) extending along a second direction, and a plurality of plate lines (e.g., PL1-PL5) stacked along a third direction. A plurality of capacitors (e.g., C1-C5) can be stacked in the third direction of the transistor (e.g., T1) to which the capacitors are connected. For example, capacitor C1 and plate line PL1 are located at the same layer, capacitor C2 and plate line PL2 are located at the same layer, and so on, capacitor C5 and plate line PL5 are located at the same layer, thereby forming a three-dimensional memory cell array. The first direction intersects the second direction (e.g., the first direction is orthogonal to the second direction), and the third direction is perpendicular to the first direction and the second direction. For example, the first direction can be the X direction of the XYZ coordinate system shown in FIG. 3, the second direction can be the Y direction shown in FIG. 3, and the third direction can be the Z direction shown in FIG. 3. FIG. 4 is a side view of the three-dimensional memory cell array shown in FIG. 3. FIG. 5 is a top view of the three-dimensional memory cell array shown in FIG. 3. As shown in FIGS. 4 and 5, a plurality of capacitors located in the same column share a first plate, and the first plate of the plurality of capacitors in the same column is coupled to a storage node at the first end of the transistor in the same column. The plate lines corresponding to the plurality of capacitors located at the same layer serve as the second plates of the plurality of capacitors. The second end of each transistor is coupled to a bit line, and the control end of each transistor is coupled to a word line. The plurality of bit lines (e.g., BL1-BL3) are disposed on a substrate, and the plate lines are separated by a dielectric layer (not shown in FIG. 3).

[0061] In a read operation, the voltage generated on the bit line is compared to a reference voltage to distinguish between data 0 and data 1. As shown in FIG. 6, which is a graph of the normal distribution of the voltage generated on the corresponding bit line by the capacitors in a read operation. The horizontal axis is voltage and the vertical axis is the number of capacitors. The dashed line in the middle indicates the reference voltage (Vref). In a read operation in which a low voltage is applied to the bit line and a high voltage is applied to the plate line, the amount of charge released by the capacitors storing data 0 is less than the amount of charge released by the capacitors storing data 1. In this case, the curve to the left of the reference voltage represents the capacitors storing data 0 and the curve to the right of the reference voltage represents the capacitors storing data 1. In a read operation, the maximum voltage generated on the corresponding bit line by all the capacitors storing data 0 is VI. In a read operation, the minimum voltage generated on the corresponding bit line by all the capacitors storing data 1 is V2. The storage window is the distance between the voltage distributions corresponding to data 0 and data 1, i.e., the difference between V2 and VI. The read margin is the voltage difference between VI and the reference voltage, and the voltage difference between V2 and the reference voltage. Typically, the reference voltage is the middle value between VI and V2, and the read margin for data 0 and data 1 is half of the storage window. The memory can perform the operation of comparing the voltage generated on the bit line to the reference voltage through a sense amplifier coupled to the bit line. Due to the effects of transistor mismatch and process fluctuations in the sense amplifier, there needs to be a certain voltage difference (i.e., a large read margin) between the voltages compared by the sense amplifier in order to correctly identify and convert the input voltage.

[0062] The difference between the planar structure memory and the three-dimensional stacked memory is that the process of the 1T1C memory of the planar structure is simpler, and the control of the polarization state of the capacitor is easier. Therefore, the voltage distribution spread (for example, the width of the two solid curves in FIG. 6) of the 1T1C memory is narrower, the value of V1 is smaller and the value of V2 is larger. Thus, the storage window and the read margin of the 1T1C memory are larger, and the data read error rate is lower. In the three-dimensional stacked 1TnC memory, the three-dimensional stacked structure and the process are complex, and the polarization state difference of the capacitors between different layers of the stack is large. This leads to a wider voltage distribution spread (for example, the width of the two dashed curves in FIG. 6), a larger value of V1 and a smaller value of V2. Thus, the storage window and the read margin of the memory of the three-dimensional stacked structure are smaller. In addition, the multiple capacitors of the three-dimensional stacked 1TnC ferroelectric memory share one transistor, and when one of the capacitors is read or written, it will also interfere with the adjacent capacitors. This will affect the polarization state of the adjacent capacitors, further causing the storage window and the read margin to become smaller. As shown in FIG. 7, FIG. 7 shows the possible voltage distribution of the three-dimensional stacked 1TnC memory. The horizontal coordinate is the capacitor, and the vertical coordinate is the voltage. The two voltages corresponding to one point on the horizontal coordinate are: the voltage generated on the bit line when reading a capacitor storing data 1, and the voltage generated on the bit line when reading a capacitor storing data 0. The three-dimensional stacked 1TnC memory has the following problems:

[0063] First, in case 1, the voltage distributions corresponding to data 1 and data 0 are both far from the reference voltage, and the read margin is large. However, in case 2, the distance between some of the voltages and the reference voltage is small, and the read margin is small, and these voltages may not be correctly read by the sense amplifier.

[0064] Second, in case 3, the voltages corresponding to data 1 and data 0 are both distributed on the same side of the reference voltage, i.e., both greater than the reference voltage or both less than the reference voltage. In case 3, the sense amplifier cannot distinguish between these data 1 and data 0.

[0065] Third, during the use of the memory, the capacitors are directly or indirectly accessed, and the polarization direction of the capacitors repeatedly flips and the residual polarization strength gradually decreases. This will cause the read margin to become smaller, and the sense amplifier may not be able to correctly read the data.

[0066] Fourth, due to device mismatch, process fluctuations, power fluctuations, noise, and environmental temperature, the value of the reference voltage may fluctuate. This will cause the read margin to become smaller, and the sense amplifier may not be able to correctly read the data.

[0067] For the above reasons, the three-dimensional stacked 1TnC memory has advantages of saving the number of transistors, being able to make the area of the ferroelectric capacitor larger, reducing the requirement for the depth of the trench, and improving the storage density, compared with the planar structure 1T1C memory. However, the three-dimensional stacked 1TnC memory also has a problem of a larger data read error rate, compared with the planar structure 1T1C memory. How to balance the advantages and disadvantages of the three-dimensional stacked structure memory is a problem to be solved urgently.

[0068] Based on this, an embodiment of the present application provides a memory, which can be a three-dimensional stacked 2T2nC structure. The three-dimensional stacked 2T2nC memory can read data without relying on a reference voltage, but adopts a differential pair storage unit including two capacitors to read data.

[0069] In some examples, the three-dimensional stacked structure of the 2T2nC memory can refer to the three-dimensional stacked structure of the 1TnC memory, and the embodiments of the present application will not be repeated here. The difference between the two is that the division method of the storage unit is different. One storage unit of the 1TnC memory includes one capacitor, and one differential pair storage unit of the 2T2nC memory includes two capacitors. The simplified structure of the 2T2nC memory is shown in FIG. 8. The memory includes a first word line selection transistor T11, a second word line selection transistor T21, a plurality of first capacitors (such as C11, C12, C13, …, and C1n), a plurality of second capacitors (such as C21, C22, C23, …, and C2n), a first word line WL11, a second word line WL21, a first bit line BL11, a second bit line BL21, a plurality of first plate lines (such as PL11, PL12, PL13, …, and PL1n), a plurality of second plate lines (such as PL21, PL22, PL23, …, and PL2n), and a sense amplifier (SA). The first plates of the plurality of first capacitors are respectively coupled to the first ends of the first word line selection transistor T11, for example, coupled to the floating gate (FG) node. The second plates of the plurality of first capacitors are respectively coupled to the plurality of first plate lines. The second end of the first word line selection transistor T11 is coupled to the first bit line BL11. The control end of the first word line selection transistor T11 is coupled to the first word line WL11. The first plates of the plurality of second capacitors are respectively coupled to the first ends of the second word line selection transistor T21, for example, coupled to the floating gate (FG) node. The second plates of the plurality of second capacitors are respectively coupled to the plurality of second plate lines. The second end of the second word line selection transistor T21 is coupled to the second bit line BL21. The control end of the second word line selection transistor T21 is coupled to the second word line WL21. The input end of the sense amplifier is coupled to the first bit line BL11, and the reference input end of the sense amplifier is coupled to the second bit line BL21. One differential pair storage unit includes a first target capacitor C11 and a second target capacitor C21. The first target capacitor C11 and the second target capacitor C21 are used to store opposite data, and the data stored by the second target capacitor is not used as the output data of the memory. The memory is configured to: input a read instruction, the read instruction being used to indicate reading the data of the first target capacitor C11. In response to the read instruction, the data of the first target capacitor C11 is output.

[0070] Exemplarily, the first target capacitor C11 and the second target capacitor C21 storing opposite data includes two cases: the first target capacitor C11 stores data 1 and the second target capacitor C21 stores data 0; or, the first target capacitor C11 stores data 0 and the second target capacitor C21 stores data 1. As shown in FIG. 9, in the first case, the equivalent capacitance of the first target capacitor C11 is CA1 (corresponding to data 1), and the equivalent capacitance of the second target capacitor C21 is CA0 (corresponding to data 0). When performing a read operation, the voltage on the first bit line BL11 and the voltage on the second bit line BL21 are compared. According to the comparison result, it is determined that the first target capacitor C11 stores data 1 and the second target capacitor C21 stores data 0. The memory outputs the data 1 stored by the first target capacitor C11 as output data. In the second case, the equivalent capacitance of the first target capacitor C11 is CA0, and the equivalent capacitance of the second target capacitor C21 is CA1. After a similar read operation, the memory outputs the data 0 stored by the first target capacitor C11 as output data. In the read operation, the voltages on the first bit line BL11 and the second bit line BL21 can be referenced to each other, without the need to be compared with a reference voltage. As shown in FIG. 10, the read margin of the 2T2nC memory is twice that of the 1T1nC memory shown in FIG. 6.

[0071] Compared with the 1T1nC memory, in which each capacitor stores data used to represent one bit of information, in the 2T2nC memory, the first target capacitor C11 and the second target capacitor C21 store data used to represent one bit of information. The 1T1nC memory does not limit which two capacitors are used to store opposite data, while the first target capacitor C11 and the second target capacitor C21 of the 2T2nC memory are used to store opposite data. The embodiment has the following advantages:

[0072] First, as shown in FIG. 11, for the case 2 and the case 3 in FIG. 7, the two voltages on the first bit line BL11 and the second bit line BL21 have a certain voltage difference and can be correctly identified. The two voltages do not need to have a certain relative size with respect to a reference voltage. Therefore, the 2T2nC memory can expand the read margin and reduce the data read error rate.

[0073] Second, when the capacitors are directly accessed or indirectly accessed during use, the polarization direction of the capacitors repeatedly reverses, and the residual polarization strength gradually decreases. However, the polarization states of the first target capacitor C11 and the second target capacitor C21 always reverse at the same time, and the two have similar fatigue characteristics. As long as the voltage on the first bit line BL11 and the voltage on the second bit line BL21 have a certain difference, the difference can correctly read out the data stored by the memory cell. Therefore, the 2T2nC memory can reduce the data read error rate.

[0074] Third, due to the influence of device mismatch, process fluctuation, power supply fluctuation, noise and environmental temperature, the value of the reference voltage can fluctuate. But the 2T2nC memory does not need to rely on the reference voltage, and the read margin will not decrease due to the change of the reference voltage. Therefore, the 2T2nC memory can reduce the data read error rate.

[0075] Fourth, the 2T2nC memory stores the data stored in the first target capacitor C11 in the differential pair storage unit as output data, and the data stored in the second target capacitor C21 is not output data. While the 1T1C memory and the 2T2C memory of the planar structure, and all the capacitors of the 1TnC memory of the three-dimensional stacked structure store the data as output data. The hardware structure of the storage unit of the 2T2nC memory relative to the 1T1nC memory does not change, only the method changes, and the hardware cost is low.

[0076] Fifth, although the 2T2nC memory does not output the data stored in the second target capacitor C21, the storage density is smaller than that of the 1TnC memory, but the storage density is still very large relative to the 1T1C memory and the 2T2C memory of the planar structure. The 2T2nC memory can obtain larger storage density and smaller data read error rate.

[0077] In some possible embodiments, the memory further comprises a sense amplifier. The sense amplifier does not need to be coupled to a voltage source for providing a reference voltage.

[0078] In some examples, the sense amplifier is configured to: in a read phase of the memory, input a voltage of the first bit line BL11 through an input terminal, and input a voltage of the second bit line BL21 through a reference input terminal. According to the voltage of the first bit line BL11 and the voltage of the second bit line BL21, output the data stored in the first target capacitor C11. The sense amplifier can output the data stored in the second target capacitor C21. The memory receives the data stored in the first target capacitor C11 and the data stored in the second target capacitor C21 from the sense amplifier, and the memory only outputs the data stored in the first target capacitor C11.

[0079] In this embodiment, the sense amplifier only needs to be coupled to the first bit line BL11 and the second bit line BL21, and does not need to be coupled to a voltage source for providing a reference voltage. Therefore, the hardware coupling structure of the sense amplifier is simpler. And the sense amplifier compares the voltage of the first bit line BL11 with the voltage of the second bit line BL21, and does not need to rely on the reference voltage for comparison, and the read margin is larger. Because the read margin is larger, even if the sense amplifier is affected by transistor mismatch and process fluctuation, the data can still be correctly read out. Therefore, the requirements for the performance parameters of the transistors of the sense amplifier and the process fluctuation can be reduced.

[0080] In some possible embodiments, the memory comprises a plurality of memory cell arrays. The first word line selection transistor T11, the first target capacitor C11, the second word line selection transistor T21 and the second target capacitor C21 are located in the same memory cell array. The first word line WL11 and the second word line WL21 are the same word line, or the first word line WL11 and the second word line WL21 are different word lines. The first target plate line PL11 and the second target plate line PL21 are the same plate line, or the first target plate line PL11 and the second target plate line PL21 are different plate lines.

[0081] In some possible embodiments, the memory comprises a plurality of memory cell arrays. The first word line selection transistor T11, the first target capacitor C11, the second word line selection transistor T21 and the second target capacitor C21 are located in the same memory cell array. The first word line WL11 and the second word line WL21 are the same word line, or the first word line WL11 and the second word line WL21 are different word lines. The first target plate line PL11 and the second target plate line PL21 are the same plate line, or the first target plate line PL11 and the second target plate line PL21 are different plate lines.

[0082] In these embodiments, the first word line WL11 and the second word line WL21 can be the same physical structure or different physical structures. In the case that the first word line WL11 and the second word line WL21 are different physical structures, the first word line WL11 and the second word line WL21 can be coupled. The first target plate line PL11 and the second target plate line PL21 can be the same physical structure or different physical structures. In the case that the first target plate line PL11 and the second target plate line PL21 are different physical structures, the first target plate line PL11 and the second target plate line PL21 can be coupled. In this way, the positions of the two capacitors in the differential pair memory cell are not limited. This embodiment does not need to change the hardware structure of the memory cell array, only needs to change the way of storing and reading data, and the hardware cost is small.

[0083] In some possible embodiments, as shown in FIG. 12, the first word line selection transistor T11 and the first target capacitor C11 are located in the memory cell array A, and the second word line selection transistor T21 and the second target capacitor C21 are located in the memory cell array B.

[0084] In some examples, the first word line WL11 and the second word line WL21 are controlled respectively, and the first target plate line PL11 and the second target plate line PL21 are controlled respectively when performing the write operation. The memory is configured to: in a write phase of the memory, apply a turn-on voltage to the first word line WL11 and the second word line WL21, apply a first voltage to the first bit line BL11 and the second target plate line PL21, and apply a second voltage to the first target plate line PL11 and the second bit line BL21. The turn-on voltage is used to turn on a word line selection transistor coupled to the corresponding word line. The absolute value of the difference between the first voltage and the second voltage is greater than the coercive voltage. The operations of applying voltages to the first word line WL11, the first bit line BL11, the first target plate line PL11, the second word line WL21, the second bit line BL21, and the second target plate line PL21 can be performed simultaneously.

[0085] For example, the first voltage can be a low level, and the second voltage can be a high level. The turn-on voltage is applied to the first word line WL11 to couple the first bit line BL11 to the first plate of the first target capacitor C11. The first plate of the first target capacitor C11 is applied with a low level through the first bit line BL11, and the second plate of the first target capacitor C11 is applied with a high level through the first target plate line PL11, so that data 0 can be written in the first target capacitor C11. Similarly, the first plate of the second target capacitor C21 is applied with a high level through the second bit line BL21, and the second plate of the second target capacitor C21 is applied with a low level through the second target plate line PL21, so that data 1 can be written in the second target capacitor C21. For another example, the first voltage can be a high level, and the second voltage can be a low level. Similarly, data 1 can be written in the first target capacitor C11, and data 0 can be written in the second target capacitor C21.

[0086] In some other examples, the first word line WL11 and the second word line WL21 are controlled together, and the first target plate line PL11 and the second target plate line PL21 are controlled together when performing the write operation. The memory is configured to: in a first time period of the write phase, apply a turn-on voltage to the first word line WL11 and the second word line WL21, apply a first voltage to the first bit line BL11 and the second bit line BL21, and apply a second voltage to the first target plate line PL11 and the second target plate line PL21. In a second time period after the first time period of the write phase, the turn-on voltage is applied to the first word line WL11 and the second word line WL21, the second voltage is applied to the first bit line BL11 (or the second bit line BL21), the third voltage is applied to the second bit line BL21 (or the first bit line BL11), and the first voltage is applied to the first target plate line PL11 and the second target plate line PL21. The absolute value of the difference between the third voltage and the first voltage is less than or equal to the coercive voltage, and the absolute value of the difference between the third voltage and the second voltage is less than or equal to the coercive voltage.

[0087] For example, the first voltage can be a low level, the second voltage can be a high level, and the third voltage can be a middle level. As shown in FIG. 13, during a first time period (t0-t1), a turn-on voltage is applied to the first word line WL11 and the second word line WL21, so that the first bit line BL11 is coupled to the first plate of the first target capacitor C11, and the second bit line BL21 is coupled to the first plate of the second target capacitor C21. The first plate of the first target capacitor C11 is applied with a low level through the first bit line BL11, and the first plate of the second target capacitor C21 is applied with a low level through the second bit line BL21. The second plate of the first target capacitor C11 is applied with a high level through the first target plate line PL11, and the second plate of the second target capacitor C21 is applied with a high level through the second target plate line PL21. If the first target capacitor C11 previously stores data 0, the first target capacitor C11 keeps storing data 0 at this time. If the second target capacitor C21 previously stores data 1, the data stored by the first target capacitor C11 is rewritten to data 0 at this time. During a second time period (t2-t3), similarly, the first plate of the first target capacitor C11 is applied with a high level through the first bit line BL11, and the first plate of the second target capacitor C21 is applied with a middle level through the second bit line BL21. The second plate of the first target capacitor C11 is applied with a low level through the first target plate line PL11, and the second plate of the second target capacitor C21 is applied with a low level through the second target plate line PL21. At this time, only the voltage difference between the two plates of the first target capacitor C11 is greater than the coercive voltage, and only the polarity of the first target capacitor C11 is reversed. Thus, the data stored by the first target capacitor C11 is rewritten to data 1, and the data stored by the second target capacitor C21 remains data 0. For another example, as shown in FIG. 14, during a first time period (t0-t1), if the first target capacitor C11 previously stores data 1, the data stored by the first target capacitor C11 is rewritten to data 0 at this time. If the second target capacitor C21 previously stores data 0, the second target capacitor C21 keeps storing data 0 at this time. During a second time period (t2-t3), the first plate of the first target capacitor C11 is applied with a middle level through the first bit line BL11, and the first plate of the second target capacitor C21 is applied with a high level through the second bit line BL21. The second plate of the first target capacitor C11 is applied with a low level through the first target plate line PL11, and the second plate of the second target capacitor C21 is applied with a low level through the second target plate line PL21. At this time, only the voltage difference between the two plates of the second target capacitor C21 is greater than the coercive voltage, and only the polarity of the second target capacitor C21 is reversed. Thus, the data stored by the first target capacitor C11 remains data 0, and the data stored by the second target capacitor C21 is rewritten to data 1. Here, the middle level is applied to the first bit line BL11 or the second bit line BL21 instead of the same level as the corresponding plate line, so as not to affect the voltage of the adjacent bit line of the bit line.In this way, the polarization state of the adjacent capacitor is not affected.

[0088] In some examples, the voltage applied by the read operation is similar to the voltage applied by the first target capacitor C11 and the second target capacitor C21 to write data 0, or similar to the voltage applied by the first target capacitor C11 and the second target capacitor C21 to write data 1. When performing the read operation, the first word line WL11 and the second word line WL21 are controlled respectively, and the first target plate line PL11 and the second target plate line PL21 are controlled respectively. Alternatively, the first word line WL11 and the second word line WL21 are controlled together, and the first target plate line PL11 and the second target plate line PL21 are controlled together. The memory is configured to: in a read phase of the memory, apply a turn-on voltage to the first word line WL11 and the second word line WL21, apply a first voltage to the first bit line BL11 and the second bit line BL21, and apply a second voltage to the first target plate line PL11 and the second target plate line PL21. The operations of applying voltages to the first word line WL11, the first bit line BL11, the first target plate line PL11, the second word line WL21, the second bit line BL21, and the second target plate line PL21 can be performed simultaneously.

[0089] Exemplarily, as shown in FIG. 15, the first target capacitor C11 previously stores data 1, and the second target capacitor C21 previously stores data 0. The first voltage can be a low level, and the second voltage can be a high level. The read operation is similar to the operation of writing data 0 to the first target capacitor C11 and the second target capacitor C21. The polarization direction of the first target capacitor C11 is reversed, and more charges are released, so the voltage of the first bit line BL11 is higher. The polarization direction of the second target capacitor C21 is not reversed, and fewer charges are released, so the voltage of the second bit line BL21 is lower. The sense amplifier inputs the voltage of the first bit line BL11 and the voltage of the second bit line BL21, and outputs the data 1 stored by the first target capacitor C11 and the data 0 stored by the second target capacitor C21 by comparing the two voltages. Exemplarily, the first target capacitor C11 previously stores data 1, and the second target capacitor C21 previously stores data 0. The first voltage can be a high level, and the second voltage can be a low level. The read operation is similar to the operation of writing data 1 to the first target capacitor C11 and the second target capacitor C21. The polarization direction of the first target capacitor C11 is not reversed, and the polarization direction of the second target capacitor C21 is reversed. The sense amplifier outputs the data 1 stored by the first target capacitor C11 and the data 0 stored by the second target capacitor C21. The memory receives the data 1 stored by the first target capacitor C11 and the data 0 stored by the second target capacitor C21 from the sense amplifier, and the memory only outputs the data 1 stored by the first target capacitor C11.

[0090] In yet some examples, the read operation causes the first target capacitor C11 and the second target capacitor C21 to be written with data 1 or data 0. Thus, a write-back operation is needed to the capacitors of the rewritten data after the read operation.

[0091] Exemplarily, as shown in FIG. 15, the data 1 previously stored in the first target capacitor C11 is rewritten as data 0, and the data 0 stored in the second target capacitor C21 is not rewritten. The memory is configured to, in a write-back phase of the memory, apply a turn-on voltage to the first word line WL11 and the second word line WL21, apply a high level to the first bit line BL11, apply an intermediate level to the second bit line BL21, and apply a low level to the first target plate line PL11 and the second target plate line PL21. In this way, the data in the first target capacitor C11 can be written back as data 1, and the data in the second target capacitor C21 remains as data 0.

[0092] In another possible implementation, as shown in FIG. 16, the first word line selection transistor T11, the first target capacitor C11, the second word line selection transistor T21 and the second target capacitor C21 are located in the same memory cell array. The first word line WL11 and the second word line WL21 are the same word line, and the first target plate line PL11 and the second target plate line PL21 are the same plate line.

[0093] In some examples, the write operation of this implementation can refer to the write operation shown in FIG. 17 and FIG. 18 described above.

[0094] Exemplarily, as shown in FIG. 17, in a first time period (t0-t1), if the first target capacitor C11 previously stores data 0, the first target capacitor C11 keeps storing data 0 at this time. If the second target capacitor C21 previously stores data 1, the data stored in the first target capacitor C11 is rewritten as data 0 at this time. In a second time period (t2-t3), the data stored in the first target capacitor C11 is rewritten as data 1, and the data stored in the second target capacitor C21 remains as data 0. Exemplarily, as shown in FIG. 18, in a first time period (t0-t1), if the first target capacitor C11 previously stores data 1, the data stored in the first target capacitor C11 is rewritten as data 0 at this time. If the second target capacitor C21 previously stores data 0, the second target capacitor C21 keeps storing data 0 at this time. In a second time period (t2-t3), the data stored in the first target capacitor C11 remains as data 0, and the data stored in the second target capacitor C21 is rewritten as data 1.

[0095] In yet some examples, the read operation and the write-back operation of this implementation can refer to the read operation and the write-back operation shown in FIG. 15 described above, and the embodiments of the present application will not be repeated here.

[0096] Based on the memory including the structures of FIG. 8, FIG. 12 and FIG. 16, a memory control method including the following steps can be performed, as shown in FIG. 19.

[0097] S210: The memory inputs a read instruction, the read instruction being used to instruct to read data stored in the first target capacitor C11.

[0098] S220: The memory outputs the data stored in the first target capacitor C11 in response to the read instruction.

[0099] In some possible implementation manners, before S220, the memory can further include the steps of obtaining the data stored in the first target capacitor C11 and the data stored in the second target capacitor C21. For example, steps S211 to S215 are further included.

[0100] S211: The memory applies a turn-on voltage to the first word line WL11, applies a first voltage to the first bit line BL11, and applies a second voltage to the first target plate line PL11 in the read stage.

[0101] S212: The memory applies a turn-on voltage to the second word line WL21, applies a first voltage to the second bit line BL21, and applies a second voltage to the second target plate line PL21 in the read stage.

[0102] Exemplarily, S201 and S202 can be performed in the same time period or in different time periods. The turn-on voltage is used to turn on the word line selection transistor coupled to the corresponding word line. The absolute value of the difference between the first voltage and the second voltage is greater than the coercive voltage.

[0103] S213: The sense amplifier inputs the voltage of the first bit line BL11 through an input terminal and inputs the voltage of the second bit line BL21 through a reference input terminal in the read stage.

[0104] S214: The sense amplifier outputs the data stored in the first target capacitor C11 according to the voltage of the first bit line BL11 and the voltage of the second bit line BL21.

[0105] S215: The memory receives the data stored in the first target capacitor C11 and the data stored in the second target capacitor C21 from the sense amplifier in the read stage.

[0106] Exemplarily, the memory receives the data stored in the first target capacitor C11 and the data stored in the second target capacitor C21, and only the data stored in the first target capacitor C11 is output as the output data instructed by the read instruction, and the data stored in the second target capacitor C21 is not output as the output data instructed by the read instruction.

[0107] In some possible implementation manners, S210 can further include a step of writing data to the first target capacitor C11 and the second target capacitor C21. For example, S101-S102 are further included, or S103-S104 are included.

[0108] S101: In a write phase, the memory applies a turn-on voltage to the first word line WL11, applies a first voltage to the first bit line BL11, and applies a second voltage to the first target plate line PL11.

[0109] S102: In a write phase, the memory applies a turn-on voltage to the second word line WL21, applies a second voltage to the second bit line BL21, and applies a first voltage to the second target plate line PL21.

[0110] For example, S101 and S102 can be performed in the same time period or in different time periods.

[0111] S103: In a first time period of a write phase, the memory applies a turn-on voltage to the first word line WL11 and the second word line WL21, applies a first voltage to the first bit line BL11 and the second bit line BL21, and applies a second voltage to the first target plate line PL11 and the second target plate line PL21.

[0112] S104: In a second time period after the first time period of a write phase, the memory applies a turn-on voltage to the first word line WL11 and the second word line WL21, applies a third voltage to the first bit line BL11 (or the second bit line BL21), applies a second voltage to the second bit line BL21 (or the first bit line BL11), and applies a first voltage to the first target plate line PL11 and the second target plate line PL21.

[0113] For example, an absolute value of a difference between the third voltage and the first voltage is less than or equal to the coercive voltage. An absolute value of a difference between the third voltage and the second voltage is less than or equal to the coercive voltage. The first voltage represents a low level and the second voltage represents a high level, or the first voltage represents a high level and the second voltage represents a low level. The voltage value of the first voltage applied to each bit line or plate line can be different. The voltage value of the second voltage applied to each bit line or plate line can be different. As long as the absolute value of the voltage difference between the first voltage and the second voltage is greater than the coercive voltage, the scheme of the embodiments of the present application is satisfied. Similarly, the voltage value of the third voltage applied to each bit line or plate line can be different. The voltage value of the turn-on voltage applied to each word line can be different.

[0114] It can be understood that the control method of the memory described above can be applied to the aforementioned 2T2nC memory. Since the functions and effects of the 2T2nC memory have been described in detail in the embodiments of the aforementioned 2T2nC memory, they will not be described here again.

[0115] Embodiments of the present application provide an electronic device. The electronic device can include a mobile phone, a pad, a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and the like. Embodiments of the present application do not specially limit the specific form of the electronic device.

[0116] In some possible implementation manners, as shown in FIG. 20, the electronic device 1000 includes a storage system 100 and a processor 200. The storage system 100 includes a memory 110 and a controller 120. The processor 200 and the memory 110 are both coupled with the controller 120. The controller 120 can be a separate chip, or can be integrated in the processor 200 or the memory 110. In addition to the devices shown in FIG. 20, the electronic device 1000 can also include a communication interface and other devices such as a disk as a secondary storage, and embodiments of the present application do not specially limit this. The processor 200 can be used to realize access to the memory 110 through the controller 120. The controller 120 can send a command (command, CMD), an address (address, ADD) and data (data, DATA) to the memory 110 according to the indication of the processor 200. For example, the CMD can include a write instruction (write, WR), a read instruction (read, RD), and the like. The memory 110 can receive the address sent by the controller 120, and perform an operation of a corresponding instruction on data in a region selected according to the address. The controller 120 can also be used to manage a storage block in the memory 110.

[0117] The processor 200 involved in embodiments of the present application can be a chip. For example, it can be a field programmable gate array (FPGA), can be an application specific integrated circuit (ASIC), can also be a system on chip (SoC), can also be a central processor unit (CPU), can also be a network processor (NP), can also be a digital signal processor (DSP), can also be a micro controller unit (MCU), can also be a programmable logic device (PLD) or other integrated chip.

[0118] The memory 110 involved in the embodiments of the present application can be a ferroelectric memory. The memory cell of the ferroelectric memory includes a transistor and a ferroelectric capacitor. The transistor can be a word line select transistor, which is a kind of transistor used in a memory chip and can be simply referred to as a word line select transistor. It is mainly used for read or write operation under the selection of a specific word line. In the memory cell of a three-dimensional stacked structure, a vertical transistor can be used to reduce the area of the memory cell. The vertical transistor includes a multi-gate transistor, such as a gate-all-around (GAA) transistor, a triple-gate transistor, or a double-gate transistor. The multi-gate transistor can have a larger gate control area, better channel control, and lower leakage current through a smaller subthreshold swing.

[0119] It can be understood that the memory 110 in the electronic device 1000 described above can be the aforementioned 2T2nC memory. Since the functions and effects of the 2T2nC memory have been described in detail in the embodiments of the aforementioned 2T2nC memory, they will not be described here.

[0120] The embodiments of the present application also provide a computer readable storage medium, which stores program codes, and when the program codes are run on a device (for example, the device can be a device including a memory), the program codes can be called and executed by the memory to perform one or more steps in the above method embodiments.

[0121] Based on such understanding, the embodiments of the present application also provide a computer program product containing instructions. The technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) or a memory therein execute all or part of the steps of the method described in the embodiments of the present application.

[0122] It should be understood that in various embodiments of the present application, the size of the sequence number of the above processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0123] Those skilled in the art can clearly understand that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0124] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described methods, systems, devices and modules can refer to the corresponding processes in the foregoing memory embodiments, which will not be repeated here.

[0125] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely illustrative, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, for example, multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between devices or modules, which can be electrical, mechanical or other forms.

[0126] The modules described as separate components can or can not be physically separated, and the components displayed as modules can or can not be physical modules, that is, they can be located in one device, or can be distributed to multiple devices. According to actual needs, part or all of the modules can be selected to achieve the purpose of the present embodiment.

[0127] In addition, each functional module in each embodiment of the present application can be integrated in one device, or each module can exist physically alone, or two or more modules can be integrated in one device.

[0128] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by using a software program, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more servers, data centers, etc. integrated with the medium. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0129] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that: The memory includes a first bit line, a second bit line, a first word line selection tube, a second word line selection tube, a plurality of first capacitors, a plurality of second capacitors, and a sense amplifier; the first plates of the plurality of first capacitors are respectively coupled to the first end of the first word line selection tube, and the second end of the first word line selection tube is coupled to the first bit line; the first plates of the plurality of second capacitors are respectively coupled to the first end of the second word line selection tube, and the second end of the second word line selection tube is coupled to the second bit line; the input end of the sense amplifier is coupled to the first bit line, and the reference input end of the sense amplifier is coupled to the second bit line; the plurality of first capacitors include a first target capacitor, and the plurality of second capacitors include a second target capacitor, the first target capacitor and the second target capacitor are used to store opposite data; the data stored in the second target capacitor is not used as output data of the memory; the memory is used to: Inputting a read instruction, wherein the read instruction is used to instruct to read data of the first target capacitor; In response to the read instruction, data of the first target capacitance is output.

2. The memory according to claim 1, wherein The sense amplifier is used to: In a read phase of the memory, a voltage of the first bit line is inputted through the input terminal, and a voltage of the second bit line is inputted through the reference input terminal; Data stored in the first target capacitor is output according to the voltage of the first bit line and the voltage of the second bit line.

3. The memory according to claim 1 or 2, characterized in that The memory further includes a first word line, a second word line, a first plate line, and a second plate line; the second plate of the first target capacitor is coupled to the first plate line, and the control end of the first word line selection transistor is coupled to the first word line; the second plate of the second target capacitor is coupled to the second plate line, and the control end of the second word line selection transistor is coupled to the second word line; the memory is configured to: In the read phase, a turn-on voltage is applied to the first word line, a first voltage is applied to the first bit line, and a second voltage is applied to the first plate line; In the read phase, the turn-on voltage is applied to the second word line, the first voltage is applied to the second bit line, and the second voltage is applied to the second plate line; The turn-on voltage is used to turn on a word line selection transistor coupled to a corresponding word line; and the absolute value of the difference between the first voltage and the second voltage is greater than a coercive voltage.

4. The memory according to any one of claims 1 to 3, characterized in that: The memory further includes a first word line, a second word line, a first plate line, and a second plate line; the second plate of the first target capacitor is coupled to the first plate line, and the control end of the first word line selection transistor is coupled to the first word line; the second plate of the second target capacitor is coupled to the second plate line, and the control end of the second word line selection transistor is coupled to the second word line; the memory is configured to: In a write phase of the memory, a turn-on voltage is applied to the first word line, a first voltage is applied to the first bit line, and a second voltage is applied to the first plate line; In the write phase, the turn-on voltage is applied to the second word line, the second voltage is applied to the second bit line, and the first voltage is applied to the second plate line; The turn-on voltage is used to turn on a word line selection transistor coupled to a corresponding word line; and the absolute value of the difference between the first voltage and the second voltage is greater than a coercive voltage.

5. The memory according to claim 4, wherein: The memory is specifically used for: In a first time period of the write phase, applying the turn-on voltage to the first word line and the second word line, applying the first voltage to the first bit line and the second bit line, and applying the second voltage to the first plate line and the second plate line; In a second time period after the first time period of the write phase, applying the turn-on voltage to the first word line and the second word line, applying a third voltage to the first bit line, applying the second voltage to the second bit line, and applying the first voltage to the first plate line and the second plate line; The absolute value of the difference between the third voltage and the first voltage is less than or equal to the coercive voltage; and the absolute value of the difference between the third voltage and the second voltage is less than or equal to the coercive voltage.

6. The memory according to any one of claims 3 to 5, characterized in that: The first word line and the second word line are the same word line, or the first word line and the second word line are different word lines.

7. The memory according to any one of claims 3 to 6, characterized in that: The first plate line and the second plate line are the same plate line, or the first plate line and the second plate line are different plate lines.

8. A memory control method, characterized in that: The memory includes a first bit line, a second bit line, a first word line selection tube, a second word line selection tube, a plurality of first capacitors, a plurality of second capacitors, and a sense amplifier; the first plates of the plurality of first capacitors are respectively coupled to the first end of the first word line selection tube, and the second end of the first word line selection tube is coupled to the first bit line; the first plates of the plurality of second capacitors are respectively coupled to the first end of the second word line selection tube, and the second end of the second word line selection tube is coupled to the second bit line; the input end of the sense amplifier is coupled to the first bit line, and the reference input end of the sense amplifier is coupled to the second bit line; the plurality of first capacitors include a first target capacitor, and the plurality of second capacitors include a second target capacitor, and the first target capacitor and the second target capacitor are used to store opposite data; The data stored in the second target capacitor is not used as output data of the memory; the method includes: The memory inputs a read instruction, where the read instruction is used to instruct reading data of the first target capacitor; The memory outputs data of the first target capacitor in response to the read instruction.

9. The method according to claim 8, characterized in that The method further comprises: In a read phase of the memory, the sense amplifier inputs the voltage of the first bit line through the input terminal and inputs the voltage of the second bit line through the reference input terminal; The sense amplifier outputs data stored in the first target capacitor according to a voltage of the first bit line and a voltage of the second bit line.

10. The method according to claim 8 or 9, characterized in that The memory further includes a first word line, a second word line, a first plate line, and a second plate line; the second plate of the first target capacitor is coupled to the first plate line, and the control terminal of the first word line selection transistor is coupled to the first word line; The second plate of the second target capacitor is coupled to the second plate line, and the control end of the second word line selection transistor is coupled to the second word line; The method further comprises: In the read phase, the memory applies a turn-on voltage to the first word line, applies a first voltage to the first bit line, and applies a second voltage to the first plate line; In the read phase, the memory applies the turn-on voltage to the second word line, applies the first voltage to the second bit line, and applies the second voltage to the second plate line; The turn-on voltage is used to turn on a word line selection transistor coupled to a corresponding word line; and the absolute value of the difference between the first voltage and the second voltage is greater than a coercive voltage.

11. The method according to any one of claims 8 to 10, characterized in that: The memory further includes a first word line, a second word line, a first plate line, and a second plate line; the second plate of the first target capacitor is coupled to the first plate line, and the control terminal of the first word line selection transistor is coupled to the first word line; The second plate of the second target capacitor is coupled to the second plate line, and the control terminal of the second word line selection transistor is coupled to the second word line; the method further includes: In a write phase, the memory applies a turn-on voltage to the first word line, a first voltage to the first bit line, and a second voltage to the first plate line; In the write phase, the memory applies the turn-on voltage to the second word line, applies the second voltage to the second bit line, and applies the first voltage to the second plate line; The turn-on voltage is used to turn on a word line selection transistor coupled to a corresponding word line; and the absolute value of the difference between the first voltage and the second voltage is greater than a coercive voltage.

12. The method according to claim 11, characterized in that In a write phase, the memory applies a turn-on voltage to the first word line, applies a first voltage to the first bit line, and applies a second voltage to the first plate line, including: In a first time period of the write phase, the memory applies the turn-on voltage to the first word line and the second word line, applies the first voltage to the first bit line and the second bit line, and applies the second voltage to the first plate line and the second plate line; The memory applies the turn-on voltage to the second word line, applies the second voltage to the second bit line, and applies the first voltage to the second plate line during the write phase, including: In a second time period after the first time period of the write phase, the memory applies the turn-on voltage to the first word line and the second word line, applies the third voltage to the first bit line, applies the second voltage to the second bit line, and applies the first voltage to the first plate line and the second plate line; The absolute value of the difference between the third voltage and the first voltage is less than or equal to the coercive voltage; and the absolute value of the difference between the third voltage and the second voltage is less than or equal to the coercive voltage.

13. The method according to any one of claims 10 to 12, characterized in that: The first word line and the second word line are the same word line, or the first word line and the second word line are different word lines.

14. The method according to any one of claims 10 to 13, characterized in that: The first plate line and the second plate line are the same plate line, or the first plate line and the second plate line are different plate lines.

15. A storage system, characterized in that: The storage system includes a controller and the memory according to any one of claims 1 to 7; the controller is coupled to the memory.

16. An electronic device, characterized in that: The electronic device comprises a processor and the memory system according to claim 15; the processor is coupled to the memory system.

17. A computer-readable storage medium, characterized in that The method comprises computer instructions, which, when executed on an electronic device, enable the electronic device to execute the method according to any one of claims 8 to 14.

18. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to perform the method according to any one of claims 8 to 14.

Images