Self-calibration circuit, power management chip, and display apparatus

Abstract

A self-calibration circuit, a power management chip, and a display apparatus. The self-calibration circuit is configured to adjust a driving voltage generated by a voltage generation circuit in a power management chip; the self-calibration circuit comprises a sampling sub-circuit (1), a comparison sub-circuit (2), and a compensation sub-circuit (3); the sampling sub-circuit (1) is configured to collect a driving voltage and generate a sampling voltage; on the basis of a time node of a display frame in which a display panel is located, the comparison sub-circuit (2) is configured to compare the sampling voltage with a reference voltage and output a comparison voltage; the compensation sub-circuit (3) is configured to adjust the current driving voltage on the basis of the comparison voltage.

Description

Self-calibration circuit, power management chip and display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a self-calibration circuit, a power management chip and a display device. BACKGROUND

[0002] The existing TV / MNT / NB display products all have howling problems (noise). When the display panel switches between the display stage and the blanking stage, the voltage of the plate of the capacitor in the circuit will change. When affected by an alternating current signal of a certain frequency and amplitude, the dielectric material - BaTiO3 (barium titanate) with piezoelectric effect that constitutes the dielectric layer will produce elastic strain. The capacitor is welded on the PCB (printed circuit board), and the capacitor vibration drives the PCB to resonate. When the vibration frequency falls into the human ear recognition frequency band (20 Hz-20 KHz), and the sound loudness is large enough, it will be distinguished by the human ear, that is, the PCB capacitor howling or current sound problem occurs. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a self-calibration circuit, a power management chip and a display device.

[0004] The self-calibration circuit is configured to adjust a driving voltage generated by a voltage generation circuit in a power management chip; the self-calibration circuit comprises a sampling sub-circuit, a comparison sub-circuit and a compensation sub-circuit.

[0005] The sampling sub-circuit is configured to collect the driving voltage and generate a sampling voltage.

[0006] Based on a time node of a display frame in which the display panel is located, the comparison sub-circuit is configured to compare the sampling voltage and a reference voltage and output a comparison voltage; and the compensation sub-circuit is configured to adjust the current driving voltage based on the comparison voltage.

[0007] The comparison sub-circuit comprises a reference voltage generation module and a comparison module.

[0008] The reference voltage generation module is configured to output the corresponding reference voltage based on the time node of the display frame in which the display panel is located.

[0009] The comparison module is configured to output the corresponding comparison voltage according to the collection voltage and the reference voltage.

[0010] The display frame comprises a display stage and a blanking stage.

[0011] when the display panel is at a time node of the display frame being a first preset moment, the reference voltage output by the reference voltage generation module is switched from a currently output first reference voltage to a second reference voltage; a difference between the first preset moment and a start moment of the blanking stage is a preset time;

[0012] when the display panel is at a time node of the display frame being a second preset moment, the reference voltage output by the reference voltage generation module is switched from a currently output second reference voltage to a third reference voltage; a difference between the second preset moment and an end moment of the blanking stage is a preset time;

[0013] the second reference voltage is less than the first reference voltage, and the third reference voltage is greater than the first reference voltage; a difference between the first preset moment and the second preset moment is a duration of the blanking stage.

[0014] wherein the first preset moment is earlier than the start moment of the blanking stage.

[0015] wherein the preset time is 30us.

[0016] the comparison module comprises an error amplifier; a noninverting input terminal of the error amplifier is connected to the reference voltage generation module, an inverting input terminal of the error amplifier is connected to the acquisition subcircuit, and an output terminal of the error amplifier is connected to the compensation subcircuit.

[0017] wherein the compensation subcircuit comprises a logic operation module and an output module; the output module comprises an input filter capacitor, an energy storage inductor, a switch tube and a third resistor;

[0018] a signal output terminal of the comparison subcircuit is connected to a signal input terminal of the logic operation module, and a signal output terminal of the logic operation module is connected to a control electrode of the switch tube; a first electrode of the switch tube is connected to an output signal terminal of the driving voltage, a second electrode of the switch tube is connected to a first end of the third resistor, and a second end of the third resistor is connected to a reference ground; a first end of the input filter capacitor is connected to a first end of the energy storage inductor and an input voltage terminal, and a second end of the energy storage inductor is connected to the output signal terminal of the driving voltage.

[0019] wherein the compensation subcircuit comprises a first compensation module and a second compensation module;

[0020] the first compensation module is configured to perform a first adjustment on the driving voltage based on the comparison voltage;

[0021] the second compensation module is configured to perform a second adjustment on the driving voltage after the first adjustment based on a time node of the display frame in which the display panel is located.

[0022] Wherein, the display frame includes a display phase and a blanking phase;

[0023] When the time node of the display frame of the display panel is a first preset moment, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to the second driving voltage; the difference between the first preset moment and the start time of the blanking phase is a preset time;

[0024] When the time node of the display frame of the display panel is a second preset moment, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to a third driving voltage; the difference between the second preset moment and the end moment of the blanking phase is a preset time;

[0025] The difference between the first preset time and the second preset time is the duration of the blanking phase.

[0026] The first preset time is earlier than the start time of the blanking phase.

[0027] The comparison module includes an error amplifier; the non-inverting input terminal of the error amplifier is connected to the reference voltage signal terminal, the inverting input terminal is connected to the acquisition sub-circuit, and the output terminal is connected to the first compensation module.

[0028] Wherein, the first compensation module includes a logic operation module and an output module; the output module includes a switch tube and a third resistor;

[0029] The signal input end of the logic operation module is connected to the signal output end of the comparison sub-circuit, and the signal output end of the logic operation module is connected to the control electrode of the switching tube; the first electrode of the switching tube is connected to the signal end outputting the driving voltage, the second electrode is connected to the first end of the third resistor, and the second end of the third resistor is connected to the reference ground.

[0030] Wherein, the acquisition subcircuit includes a first resistor and a second resistor;

[0031] The first end of the first resistor is connected to the signal end outputting the driving voltage, the second end of the first resistor and the first end of the second resistor are both connected to the comparison sub-circuit, and the second end of the second resistor is connected to the reference ground.

[0032] The self-calibration circuit further includes: a phase identification sub-circuit configured to receive the row number of the system data decoded by the timing controller and determine the time node of the display frame of the display panel.

[0033] The self-calibration circuit further includes: a phase identification subcircuit configured to detect the current magnitude of the voltage generating circuit to determine the time node of the display frame of the display panel.

[0034] An embodiment of the present disclosure provides a power management chip, comprising any of the above-mentioned self-calibration circuits; and a voltage generation circuit;

[0035] The voltage generating circuit is configured to output a driving voltage in response to a first voltage and a modulation signal output by the timing controller; a signal output terminal of the voltage generating circuit is multiplexed as a signal input terminal of the self-calibration circuit.

[0036] An embodiment of the present disclosure provides a display device, comprising the above-mentioned power management chip and a timing controller; the timing controller is configured to generate a first voltage and a modulation signal for a voltage generating circuit to generate a driving voltage.

[0037] An embodiment of the present disclosure provides a display device, which includes a power management chip, a timing controller, and a display panel; the display panel includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines intersecting to define a plurality of pixel units, a gate drive circuit that provides gate drive signals to the gate lines, and a source drive circuit that provides data voltages to the data lines; the power management chip is configured to generate a drive voltage based on a first voltage provided by the timing controller and a modulation signal, so as to load the drive voltage to the source driver; wherein,

[0038] The gate driving circuit includes a plurality of shift registers and at least one redundant shift register; the plurality of gate lines connected to the redundant shift register are redundant gate lines, and the pixel units connected to the redundant gate lines are redundant pixel units;

[0039] The timing controller is configured to control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to work, and control the source drive circuit to provide a data voltage to the data line when the display panel is in a blanking phase.

[0040] The blanking phase is divided into a first period, a second period and a third period from its starting time to its ending time;

[0041] The timing controller is specifically configured to, when the display panel is in a blanking phase, control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to operate, and control the drive current of the operational amplifier of the source drive circuit to decrease in a step-by-step manner in the first time period, to have no current output in the second time period, and to increase in a step-by-step manner in the third time period.

[0042] The blanking phase is divided into a first period, a second period and a third period from its starting time to its ending time;

[0043] The timing controller is specifically configured to, when the display panel is in a blanking phase, control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to operate, and control the data voltage written by the source driver circuit to decrease in a step-by-step manner in the first time period, to be the first data voltage in the second time period, and to increase in a step-by-step manner in the third time period; the first data voltage is not greater than the minimum voltage written in the first and third time periods of the source driver circuit.

[0044] The blanking phase is divided into a first period, a second period and a third period from its starting time to its ending time;

[0045] The timing controller is specifically configured to, when the display panel is in a blanking phase, control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to operate, and control the number of output channels of the source drive circuit to be turned on, decreasing in a step-by-step manner in the first time period, turning off all in the second time period, and increasing in a step-by-step manner in the third time period. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a circuit structure diagram of a voltage generating circuit according to an embodiment of the present disclosure.

[0047] FIG2 is a structural block diagram of a self-calibration circuit according to an embodiment of the present disclosure.

[0048] FIG3 is a schematic structural diagram of a self-calibration circuit according to an embodiment of the present disclosure.

[0049] 4a-4b are timing diagrams of the reference voltage generation module according to an embodiment of the present disclosure generating a reference voltage.

[0050] FIG5 is a schematic structural diagram of another self-calibration circuit according to an embodiment of the present disclosure.

[0051] FIG6 is an output waveform diagram of the self-calibration circuit shown in FIG5 .

[0052] FIG7 is a schematic diagram of the structure of a power management chip according to an embodiment of the present disclosure.

[0053] FIG8 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.

[0054] FIG. 9 is a timing diagram of a display panel according to an embodiment of the present disclosure.

[0055] FIG10 is a timing diagram of gate driving signals provided by the gate driving circuit corresponding to FIG8 .

[0056] FIG. 11 is a diagram showing driving current data of an operational amplifier of a source driving circuit when the display panel is in a blanking phase according to an embodiment of the present disclosure.

[0057] FIG. 12 is a grayscale data diagram of a data signal written when the display panel is in a blanking phase according to an embodiment of the present disclosure.

[0058] FIG13 is a data diagram of the output channels of the source driving circuit when the display panel is in the blanking phase according to the embodiment of the present disclosure.

[0059] FIG14 is a waveform diagram of a data signal written in a time-sharing manner during a blanking phase of a display panel provided by the present disclosure. DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0061] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates an "or" relationship between the preceding and following objects. Terms such as "first," "second," and "third" used in this application merely distinguish similar objects and do not indicate a specific ordering of the objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative position. If the absolute position of the described objects changes, the relative position may also change accordingly.

[0062] In the related art, a power management chip (PMIC) refers to a chip that integrates multiple voltage generation circuits. When used in display products, it is mainly responsible for providing multiple driving voltages to the display panel, such as the driving voltage (AVDD) and the digital voltage (DVDD). Taking the AVDD voltage as an example, it is generated by the voltage generation circuit (specifically, the BOOST boost circuit) in the power management chip. The specific circuit structure is shown in Figure 1. It should be noted that the control logic of the present disclosure is only described below using the Boost loop architecture. Other types of loops, such as the Buck boost circuit that generates the digital signal DVDD and the charge pump circuit that generates the shutdown voltage Vgh, can also use the dynamically adjusted control logic of the present disclosure to achieve voltage control.

[0063] As shown in Figure 1, the boost circuit is a DC / DC converter (DC / DC) that converts the electrical energy of an input signal into the electrical energy of an output signal within a DC circuit. Here, the input signal Vi is the first voltage V1 provided by the timing controller, and the output signal Vo is the drive voltage AVDD. The boost circuit specifically includes a switching transistor Q, a diode D, an energy storage inductor L, an input filter capacitor C1, an output filter capacitor C2, and a load R. The first terminal of the input filter capacitor C1 is connected to the signal input terminal, and the second terminal is connected to the reference ground. The first terminal of the energy storage inductor L is connected to the signal input terminal, and the second terminal is connected to the first terminal of the switching transistor Q. The switching transistor Q is an N-type transistor. The control terminal of the switching transistor Q is connected to the PWM pulse signal provided by the timing controller. The PWM pulse signal is a square wave with alternating high and low levels. The second terminal of the switching transistor Q is connected to the reference ground. The positive terminal of the diode D is connected to the first terminal of the switching transistor Q, and the negative terminal is connected to the first terminal of the output filter capacitor C2. The second terminal of the output filter capacitor C2 is connected to the reference ground. The first terminal of the load R is connected to the signal output terminal, and the second terminal is connected to the reference ground. It can be understood that the output filter capacitor C2 and the load R are in a parallel relationship, and the voltage difference between the two plates of the output filter capacitor C2, or the voltage across the load R, is the output voltage Vo.

[0064] The specific operating process of the boost circuit includes the following: When the PWM wave is at a high level, the switch Q is turned on, which is equivalent to a short circuit. At this time, the first voltage V1 charges the energy storage inductor L. Over time, the current in the energy storage inductor L increases. The diode D is in reverse blocking mode, which is equivalent to an open circuit. The output filter capacitor C2 discharges to the load R. Over time, the voltage across the output filter capacitor C2 (i.e., the output voltage Vo) decreases. When the PWM wave is at a low level, the switch Q is turned off, which is equivalent to an open circuit. At this time, the voltage across the energy storage inductor L is positive on the right and negative on the left. The diode D is turned on, and the energy storage inductor L begins to discharge. Over time, the current in the energy storage inductor decreases. At this time, the first voltage V1 and the voltage across the energy storage inductor L are superimposed, and together they charge the output filter capacitor C2 and supply power to the load R. Over time, the voltage across the output filter capacitor C2 (i.e., the output voltage Vo) increases. By inputting a PWM pulse signal to the switch tube Q, the switching state of the switch tube changes continuously, repeating the above process, and eventually making the output voltage of the circuit greater than the input voltage.

[0065] It can be understood that during the operation of the above-mentioned boost circuit, the output filter capacitor and the load are in parallel. The load R can be equivalent to a resistor, which has the function of blocking the passage of current. That is to say, the presence of the load can slow down the increase rate of the voltage difference between the two plates of the output filter capacitor, and prevent the capacitor from howling due to the drastic change in the voltage difference between the two plates of the capacitor, thereby extending the service life of the capacitor and improving the user experience.

[0066] In actual use, the display panel is divided into two stages during the display process, specifically the display stage and the blanking stage. The display stage refers to the scanning stage of the frame image, and the blanking stage is the time interval between scanning two frame images. In other words, the display process of the display panel is an alternation of the display stage and the blanking stage. When the display panel is in different stages, the load driven in the display panel is different. The load here can specifically include the gate drive circuit and the pixel unit in the display panel. When switching between the display stage and the blanking stage, the drastic change in the load causes the driving voltage to generate ripples, which in turn causes the filter capacitor to generate howling.

[0067] In order to solve the above problems, the present disclosure provides a self-calibration circuit for adjusting the driving voltage AVDD generated by the above voltage generating circuit. The signal output end of the above voltage generating circuit is multiplexed as the signal input end of the self-calibration circuit. Wherein, referring to Figure 2, the self-calibration circuit includes a sampling sub-circuit 1, a comparison sub-circuit 2 and a compensation sub-circuit 3. The sampling sub-circuit 1 is configured to collect the driving voltage AVDD and generate a sampling voltage Vs; the comparison sub-circuit 2 is configured to compare the sampling voltage Vs with the reference voltage Vref and output a comparison voltage △V; the compensation sub-circuit 3 is configured to adjust the current driving voltage AVDD based on the comparison voltage △V. Through the above sampling, comparison and compensation processes, it can be ensured that the driving voltage is within a relatively stable range, thereby ensuring that the driving voltage has sufficient driving force and improving the service life of the display panel.

[0068] In some examples, the display frame of the display panel includes a display phase AA and a blanking phase Blanking. The display phase AA and the blanking phase Blanking are determined by the valid data selection signal DE provided by the timing controller Tcon, as shown in FIG4 . The valid data selection signal DE is a high-level valid signal. When the valid data selection signal is high, the display panel is in the display phase AA. When the valid data selection signal is low, the display panel is in the blanking phase Blanking. In other words, the self-calibration circuit may include a phase identification subcircuit. The phase identification subcircuit may specifically determine whether the display panel is in the display phase AA or the blanking phase Blanking based on the valid data selection signal DE provided by the timing controller Tcon. At the same time, the time node of the display frame in which the display panel is located may also be determined based on the number of rows of display data obtained by decoding the display frame data by the timing controller Tcon (that is, the number of rows of pixel units currently written with display data).

[0069] In some examples, the phase identification subcircuit can also determine the time node of the display frame of the display panel by detecting the current level of the voltage generation circuit. Specifically, due to the small load in the blanking phase, the current level of the corresponding voltage generation circuit is small. In the display phase, due to the large load, the current level of the corresponding voltage generation circuit is small.

[0070] In some examples, the time node of the display frame in which the display panel is located may be related to the starting moment T3 or the ending moment T4 of the blanking stage. Specifically, the moment that is different from the starting moment T3 of the blanking stage by a preset time t is the first preset moment T1, and the moment that is different from the ending moment T4 of the blanking stage by a preset time t is the second preset moment T2. Preferably, the preset time t may be 5us or 10us (determined according to the ripple amplitude generated by the driving voltage during the stage switching). The first preset moment T1 may be earlier than the starting moment T3 of the blanking stage (at this time, the first preset moment T1 is in the display stage AA), and the first preset moment T1 may also be later than the starting moment T3 of the blanking stage (at this time, the first preset moment T1 is in the blanking stage), but it is necessary to ensure that the difference between the first preset moment T1 and the second preset moment T2 is equal to the duration of the blanking stage. That is to say, if the first preset time T1 is earlier than the start time T3 of the blanking phase, the second preset time T2 is also earlier than the end time T4 of the blanking phase; if the first preset time T1 is later than the end time T4 of the blanking phase, the second preset time T2 is also later than the end time T4 of the blanking phase.

[0071] The self-calibration circuit according to the embodiment of the present disclosure is described in detail below with reference to specific examples.

[0072] Example 1: The self-calibration circuit includes a sampling subcircuit, a comparison subcircuit, and a compensation subcircuit. Comparison subcircuit 2 includes a reference voltage generation module 201 and a comparison module 202 (see Figure 3). Reference voltage generation module 201 is configured to output a corresponding reference voltage based on the time node of the display frame in which the display panel is located. Comparison module 202 is configured to output a corresponding comparison voltage ΔV based on the sampled voltage Vs collected by sampling subcircuit 1 and the reference voltage Vref generated by reference voltage generation module 201.

[0073] Specifically, when the time node of the display frame of the display panel is the first preset time T1, the reference voltage Vref output by the reference voltage generation module 201 switches from the first reference voltage Vref1 output when in the display stage AA to the second reference voltage Vref2, and the corresponding comparison voltage ΔV output by the comparison module 202 switches from the first comparison voltage ΔV1 output when in the display stage AA to the second comparison voltage ΔV2. When the time node of the display frame of the display panel is the second preset time T2, the reference voltage Vref output by the reference voltage generation module 201 switches from the second reference voltage Vref2 output when in the blanking stage to the third reference voltage Vref3, and the corresponding comparison voltage ΔV output by the comparison module 202 switches from the second comparison voltage ΔV2 output when in the blanking stage to the third comparison voltage ΔV3. The second reference voltage Vref2 is less than the first reference voltage Vref1, and the third reference voltage Vref3 is greater than the first reference voltage Vref1; the second comparison voltage ΔV2 is less than the first comparison voltage ΔV1, and the third comparison voltage ΔV3 is greater than the first comparison voltage ΔV1. In this example, the first preset time T1 is set earlier than the start time T3 of the blanking phase. That is, the change time of the valid data strobe signal DE is detected in advance, and the reference voltage value is adjusted in advance. Further, the comparison voltage value is adjusted in advance. This can prevent the driving voltage AVDD from changing drastically during phase switching, thereby preventing the occurrence of howling problems.

[0074] As shown in FIG4a, the voltage of Vo' is the driving voltage output by the voltage generating circuit without adding the self-calibration circuit of the present invention. It will experience drastic changes when switching between the display stage and the blanking stage. After adding the self-calibration circuit of the present invention, the voltage of the output signal terminal Vo, that is, the driving voltage AVDD, will only experience small changes when switching between stages, which has higher reliability. Of course, the first preset time T1 can also be set later than the starting time T3 of the blanking stage. At this time, the change of the reference voltage and the comparison voltage can compensate for the driving voltage AVDD that has ripples, thereby reducing the impact of the ripples. It should be noted that the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2, as well as the voltage difference between the first reference voltage Vref1 and the third reference voltage Vref3, can be set according to the amplitude of the ripples generated when Vo' switches between the display stage AA and the blanking stage Blanking. For example, when the amplitude of the ripple is 1000mV, the voltage difference between the first reference voltage Vref1 and the third reference voltage Vref3 can be set to 500mV; for another example, when the amplitude of the ripple is 500mV, the voltage difference between the first reference voltage Vref1 and the third reference voltage Vref3 can be set to 300mV.

[0075] It should be further noted that in the above embodiments, the reference voltage generation module 201 is switched from the first reference voltage Vref1 to the second reference voltage Vref2 at the first preset time T1 and remains until the second preset time T2, and is switched from the second reference voltage Vref2 to the third reference voltage Vref3 at the second preset time T2. Alternatively, in other examples, as shown in FIG. 4b, after the reference voltage is switched from the first reference voltage Vref1 to the second reference voltage Vref2, the second reference voltage Vref2 will only be maintained for a period of time t1, and then the power management chip PMIC will automatically switch it back to the first reference voltage Vref1. At this time, the first reference voltage Vref1 will be maintained for a period of time t2 until the second preset time T2 is switched to the third reference voltage Vref3. Here, t1 and t2 can be adjusted in the power management chip PMIC to improve the flexibility of the circuit.

[0076] With reference back to FIG. 3, in some examples, the sampling sub-circuit 1 includes a first resistor R1 and a second resistor R2, a first end of the first resistor R1 is connected to a signal end of the output driving voltage AVDD, a first end of the second resistor R2 is connected to a second end of the first resistor R1, and a connection node of the two is connected to the comparison sub-circuit 2 as a signal output end of the sampling sub-circuit 1, and a second end of the second resistor R2 is connected to a reference ground. According to a voltage division formula, a sampling voltage Vs collected by the sampling sub-circuit 1 is Vs = R2 / (R1+R2)*Vo.

[0077] In some examples, the comparison sub-circuit 2 includes a reference voltage generation module 201 and a comparison module 202. The comparison module 202 includes an error amplifier OP, wherein a non-inverting input end of the error amplifier OP is connected to a signal output end of the reference voltage generation module 201, an inverting input end of the error amplifier OP is connected to a signal output end of the sampling sub-circuit 1, and an output end of the error amplifier OP is connected to the compensation sub-circuit 3. The error amplifier OP compares the reference voltage Vref and the sampling voltage Vs and outputs a corresponding comparison voltage to the compensation sub-circuit 3.

[0078] In some examples, the compensation sub-circuit 3 includes a logic operation module 301 and an output module 302, and the output module 302 specifically includes an input filter capacitor C1, an energy storage inductor L, a switch tube Q and a third resistor R3. Wherein a signal input end of the logic operation module 301 is connected to a signal output end of the comparison sub-circuit 2, a signal output end of the logic operation module 301 is connected to a control electrode of the switch tube Q, a first electrode of the switch tube Q is connected to a signal end of the output driving voltage AVDD, a second electrode of the switch tube Q is connected to a first end of the third resistor R3, and a second end of the third resistor R3 is connected to a reference ground; a first end of the input filter capacitor C1 is connected to a first end of the energy storage inductor L and an input voltage end Vi, and a second end of the energy storage inductor L is connected to an output signal end V0 of the driving voltage AVDD.

[0079] Specifically, the logic operation module 301 receives the comparison voltage, and generates a switching control signal through a series of logic operations to adjust the duty cycle of the effective level and the ineffective level of the switch tube Q. When the switch tube Q is turned on, the voltage written by the input voltage terminal Vi charges the energy storage inductor L; when the switch tube Q is turned off, the energy storage inductor L charges the input filter capacitor C1, thereby adjusting the size of the driving voltage AVDD output by the output signal terminal V0. That is, by detecting the size of the driving voltage AVDD output by the output signal terminal V0, comparing it with the reference voltage Vref, controlling the size of the comparison voltage AV, and further controlling the duty cycle of the effective level and the ineffective level of the switch tube Q for adjustment, the amount of energy of the energy storage inductor in a period can be controlled to adjust the driving voltage AVDD.

[0080] Specifically, taking the self-calibration circuit shown in FIG. 3 as an example, when the display panel is at the first preset time T1 of the display frame, the acquisition voltage Vs collected by the acquisition sub-circuit 1 is Vs = R2 / (R1+R2)*Vo. The acquisition voltage Vs is transmitted to the inverting input terminal of the error amplifier OP, the reference voltage generation module 201 is switched from the first reference voltage Vref1 to the second reference voltage Vref2, the comparison module 202 compares the sampling voltage Vs with the second reference voltage Vref2, and switches from the first comparison voltage AV1 to the second comparison voltage AV2, and the compensation sub-circuit 3 generates a compensation signal that can lower the driving voltage AVDD according to the second comparison voltage AV2.

[0081] When the display panel is at the second preset time T2 of the display frame, the acquisition voltage Vs collected by the acquisition sub-circuit 1 is Vs = R2 / (R1+R2)*Vo. The sampling voltage Vs is transmitted to the inverting input terminal of the error amplifier OP, the reference voltage generation module 201 is switched from the second reference voltage Vref2 to the third reference voltage Vref3, the comparison module 202 compares the sampling voltage Vs with the third reference voltage Vref3, and switches from the second comparison voltage AV2 to the third comparison voltage AV3, and the compensation sub-circuit 3 generates a compensation signal that can raise the driving voltage AVDD according to the third comparison voltage AV3.

[0082] It should be noted that the second reference voltage Vref2 is less than the first reference voltage Vref1, and the third reference voltage Vref3 is greater than the first reference voltage Vref1. Here, the size relationship of the first reference voltage Vref1, the second reference voltage Vref2 and the third reference voltage Vref3 is only for the self-calibration circuit shown in FIG. 3, and it should be understood that when the circuit structure changes, the size relationship of the three reference voltages also changes. For example, when the inverting input terminal of the error amplifier OP is connected to the signal output terminal of the reference voltage generation module 201, and the non-inverting input terminal is connected to the signal output terminal of the acquisition sub-circuit 1, the second reference voltage Vref2 is greater than the first reference voltage Vref1, and the third reference voltage Vref3 is less than the first reference voltage Vref1.

[0083] When the display panel is switched from the display stage AA to the blanking stage Blanking, the driving voltage AVDD will increase rapidly due to the decrease in load. The compensation signal generated by the self-calibration circuit of the present disclosure at the first preset time T1 can pre-pull down the driving voltage AVDD, thereby reducing the increase amplitude of the driving voltage AVDD, controlling the voltage value of the driving voltage AVDD within a relatively small range, and avoiding the problem of capacitor howling. Similarly, when the display panel is switched from the blanking stage Blanking to the display stage AA, the compensation signal can pre-pull up the driving voltage AVDD, and control the voltage value of the driving voltage AVDD within a relatively small range.

[0084] The second example is substantially the same as the first example, and the only difference is that in this example, the reference voltage Vref connected to the comparison sub-circuit is a fixed voltage. The compensation sub-circuit in this example specifically includes a first sub-compensation module and a second sub-compensation module. The first compensation module is configured to adjust the current driving voltage AVDD based on the comparison voltage AV. The second compensation module is configured to adjust the driving voltage AVDD based on the time node of the display frame in which the display panel is located. That is, not only after the initial adjustment of the driving voltage AVDD based on the comparison voltage AV, but also according to the time node of the display frame in which the display panel is located, the driving voltage AVDD is adjusted again to reduce the influence of the moire.

[0085] Specifically, when the time node of the display frame in which the display panel is located is the first preset time T1, the second compensation module adjusts the driving voltage AVDD adjusted by the first compensation module for the first time, and the first driving voltage AVDD1 output when the display panel is in the display stage AA is switched to the second driving voltage AVDD2; when the time node of the display frame in which the display panel is located is the second preset time T2, the second compensation module adjusts the driving voltage AVDD adjusted by the first compensation module for the first time, and the second driving voltage AVDD2 output when the display panel is in the blanking stage Blanking is switched to the third driving voltage AVDD3. Wherein, the second driving voltage AVDD2 is less than the first driving voltage AVDD1, and the third driving voltage AVDD3 is greater than the first driving voltage AVDD1.

[0086] In this example, the first preset time T1 is set to be earlier than the starting time T3 of the blanking stage Blanking, that is, the change time of the valid data selection signal is detected in advance, and the driving voltage AVDD is adjusted in advance, so that the driving voltage AVDD can be prevented from changing sharply during stage switching, thereby preventing the occurrence of the howling problem. Of course, the first preset time T1 can also be set to be earlier than or later than the starting time T3 of the blanking stage Blanking. At this time, the change of the comparison voltage can compensate for the driving voltage AVDD with ripples and reduce the influence of the ripples.

[0087] In this example, the first compensation sub-circuit has the same architecture as the compensation circuit in the first example, that is, the first compensation sub-circuit includes a logic operation module 301 and an output module 302.

[0088] The output module 302 specifically includes an input filter capacitor C1, an energy storage inductor L, a switch tube Q and a third resistor R3. Wherein, the signal input end of the logic operation module 301 is connected to the signal output end of the comparison sub-circuit 2, the signal output end of the logic operation module 301 is connected to the control electrode of the switch tube Q, the first electrode of the switch tube Q is connected to the signal end of the output driving voltage AVDD, the second electrode is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the reference ground; the first end of the input filter capacitor C1 is connected to the first end of the energy storage inductor L and the input voltage end Vi, and the second end of the energy storage inductor L is connected to the output signal end V0 of the driving voltage AVDD.

[0089] Specifically, the logic operation module 301 receives the comparison voltage, and obtains the switch control signal through a series of logic operations, so as to adjust the duty cycle of the effective level and the invalid level of the switch tube Q. When the switch tube Q is turned on, the voltage written by the input voltage end Vi charges the energy storage inductor L; when the switch tube Q is turned off, the energy storage inductor L charges the input filter capacitor C1, so as to adjust the size of the driving voltage AVDD output by the output signal end V0. That is, by detecting the size of the driving voltage AVDD output by the output signal end V0, comparing with the reference voltage Vref, controlling the size of the comparison voltage AV, and then controlling the on-off duty cycle of the switch tube Q, and then controlling the energy of the energy storage inductor in a period, the adjustment of the driving voltage AVDD can be realized. The comparison sub-circuit in the embodiment of the present disclosure is the same as the comparison module in the first example, and the sampling sub-circuit 1 is the same as the sampling sub-circuit 1 in the first example, so it will not be repeated here.

[0090] Specifically, taking the self-calibration circuit shown in FIG. 5 as an example, when the display panel is at the first preset time T1 of the display frame, the sampling voltage Vs collected by the sampling sub-circuit 1 is Vs=R2 / (R1+R2)*Vo. The sampling voltage Vs is transmitted to the inverting input end of the error amplifier OP, the comparison module 202 compares the sampling voltage and the reference voltage, outputs the comparison voltage, and the first compensation module 303 is configured to adjust the current driving voltage AVDD based on the comparison voltage AV; the second compensation module 304 is configured to adjust the driving voltage AVDD adjusted for the first time based on the time node of the display frame of the display panel.

[0091] When the display panel is at the second preset time T2 of the display frame, the sampling voltage Vs collected by the sampling sub-circuit 1 is Vs=R2 / (R1+R2)*Vo. The sampling voltage Vs is transmitted to the inverting input end of the error amplifier OP, the comparison module 202 compares the sampling voltage and the reference voltage, outputs the comparison voltage. The first compensation module 303 adjusts the driving voltage AVDD for the first time according to the comparison voltage, and the second compensation module 304 switches the second driving voltage AVDD2 output when the display stage AA to the third driving voltage AVDD3 after the first compensation module 303 adjusts the driving voltage AVDD for the first time, and the second compensation module 304 generates a compensation signal that can lower the driving voltage AVDD according to the third driving voltage AVDD3.

[0092] As shown in FIG. 6, the second driving voltage AVDD2 is less than the first driving voltage AVDD1, and the third driving voltage AVDD3 is greater than the first driving voltage AVDD1. When the display panel is switched from the display stage AA to the blanking stage, the load decreases rapidly, and the voltage value of the driving voltage AVDD increases rapidly. The compensation signal generated by the self-calibration circuit at the first preset time T1 can pre-pull down the driving voltage AVDD, thereby reducing the increase amplitude of the driving voltage AVDD, controlling the voltage value of the driving voltage AVDD within a relatively small range, and avoiding the problem of capacitor howling. Similarly, when the display panel is switched from the blanking stage to the display stage, the compensation signal can pre-pull up the driving voltage AVDD, thereby controlling the voltage value of the driving voltage AVDD within a relatively small range.

[0093] It should be noted that in the first example, the reference voltage Vref is pre-adjusted by the power management chip PMIC, and then the comparison voltage is pre-adjusted. In the second example, the driving voltage AVDD is directly pre-adjusted. By pre-adjusting the driving voltage AVDD and then pre-adjusting the logic control signal output by the logic operation module, the response speed of the self-calibration circuit can be accelerated, thereby reducing the ripple amplitude generated when the driving voltage AVDD is switched between different stages, controlling the driving voltage AVDD to fluctuate within a relatively small range, avoiding the howling of the filter capacitor, and affecting the service life. It should be understood that adjusting other parameters in the self-calibration circuit can also achieve the same effect and also belongs to the protection scope of the present disclosure. For example, the collected voltage collected by the collection sub-circuit can be pre-adjusted, the split tail current (gm) of the error amplifier can be pre-adjusted, or the logic control signal output by the logic operation module can be directly pre-adjusted.

[0094] As shown in FIG. 7, the present disclosure also provides a power management chip PMIC including the self-calibration circuit of any of the above embodiments. The power management chip PMIC also includes the voltage generation circuit (taking the above boost circuit as an example) described above. The signal output end of the boost circuit is multiplexed as the signal input end of the self-calibration circuit.

[0095] The present disclosure also provides a display device including the power management chip PMIC, the timing controller Tcon, and the display panel described above. The timing controller Tcon is configured to generate a first voltage and a modulation signal for the voltage generation circuit to generate a driving voltage, and the power management chip PMIC provides a working voltage for the source driving circuit of the display panel based on the driving voltage generated by the timing controller Tcon.

[0096] As shown in FIG. 8, the display device according to the embodiments of the present disclosure also provides a display device including a power management chip PMIC, a timing controller Tcon and a display panel. The display panel includes a plurality of gate lines Gate and a plurality of data lines Data, the gate lines Gate and the data lines Data are arranged to cross to define a plurality of pixel units, a gate driving circuit Gate Driver configured to provide a gate driving signal for the gate lines Gate, and a source driving circuit Source Driver IC configured to provide a data voltage DATA for the data lines Data. The power management chip PMIC is configured to generate a driving voltage AVDD according to a first voltage provided by the timing controller Tcon and a modulation signal, and load the driving voltage AVDD to the source driver Source Driver IC. The gate driving circuit includes a plurality of shift registers GOA and at least one redundant shift register Dummy GOA. The gate lines Gate connected to the redundant shift register Dummy GOA are redundant gate lines, and the pixel units connected to the redundant gate lines are redundant pixel units. The timing controller Tcon is configured to control the redundant shift register Dummy GOA to provide a gate driving signal for the redundant gate lines to drive the redundant pixel units to work when the display panel is in a blanking stage, and control the source driving circuit Source Driver IC to provide the data voltage DATA for the data lines Data.

[0097] The display panel can be divided into a display area and a peripheral area surrounding the display area. Referring to FIG. 8, the timing controller Tcon, the power management chip PMIC, the source driving circuit Source Driver, the gate driving circuit, the redundant pixel units and the redundant gate lines are arranged in the peripheral area.

[0098] Specifically, the shift registers are sequentially cascaded, and the rising edges of the clock signals transmitted by the clock signal lines connected to the shift registers GOA are sequentially different by 1H, where H is a unit scanning time. The redundant shift registers Dummy GOA are sequentially cascaded, and the rising edges of the clock signals transmitted by the clock signal lines connected to the redundant shift registers Dummy GOA are sequentially different by 1H. In addition, the first redundant shift register Dummy GOA is cascaded with the last shift register GOA, that is, the signal output end of the last shift register GOA is connected to the signal input end of the first redundant shift register Dummy GOA, and the signal output end of the first redundant shift register Dummy GOA is connected to the reset signal end of the last shift register GOA. The rising edge of the clock signal transmitted by the clock signal line connected to the first redundant shift register Dummy GOA is also different by 1H from the rising edge of the clock signal transmitted by the clock signal line connected to the last shift register GOA.

[0099] Continuing to refer to FIG. 9, the display panel includes 1200 rows of pixel units connected one-to-one with 1200 shift registers GOA, and further includes 6 rows of redundant pixel units connected one-to-one with 6 redundant shift registers Dummy GOA. The clock signals corresponding to the 1200 shift registers GOA are all in the display stage, so as to drive the shift registers GOA to output gate drive signals in the display stage AA to make the pixel units display. The clock signals corresponding to the 6 redundant shift registers Dummy GOA are all in the blanking stage Blanking, so as to drive the redundant shift registers Dummy GOA to make the load of the driving voltage not be zero in the blanking stage Blanking. FIG. 10 is the gate drive signals output by the 1206 shift registers GOA corresponding to FIG. 9, and the rising edges of the 1206 gate drive signals are sequentially different by 1H, and H is a unit scanning time.

[0100] In the embodiments of the present disclosure, the timing controller Tcon is configured to control the redundant shift registers Dummy GOA to provide the gate drive signals for the redundant gate lines in the blanking stage Blanking, so as to drive the redundant pixel units to work, and control the source drive circuit Source Driver IC to provide the data voltage for the data lines, so as to adjust the load of the output signal end Vo of the power management chip PMIC in the blanking stage Blanking, thereby reducing the jitter of the driving voltage AVDD output by the output signal end Vo.

[0101] The following is described in conjunction with specific examples.

[0102] The first example is shown in FIG. 11. The timing controller controls the power management chip PMIC to generate the driving voltage AVDD, and controls the gate driving circuit to scan the gate line Gate row by row in the display stage AA, and controls the operational amplifier AMPB in the source driving circuit Source Driver IC to output corresponding data voltage to the data line through the driving voltage AVDD with the first preset driving current, so as to charge the corresponding pixel unit. In particular, the blanking stage Blanking is divided into the first period T1, the second period T2 and the third period T3 from the start time to the end time. In the blanking stage Blanking, the timing controller controls the redundant shift register Dummy GOA in the gate driving circuit to work, that is, increases the timing control signal CLK to scan the redundant gate line, so as to make the redundant pixel unit work. At the same time, the timing controller Tcon controls the driving current of the operational amplifier AMPB in the source driving circuit Source Driver IC to decrease in the first period T1, to be zero in the second period T2, and to increase in the third period T3. It should be noted that the maximum driving current of the operational amplifier AMPB in the first period T1 and the third period T3 is not greater than the first preset driving current in the display stage AA. For example, as shown in FIG. 11, the first preset driving current in the display stage AA is 100% driving current, the driving current in the first period T1 is changed to 75%→50%→25% driving current ratio, and the driving current in the third period T3 is changed to 25%→50%→75% driving current ratio. In this way, the display panel can effectively alleviate the problem that the display stage AA is switched to the blanking stage Blanking, the load changes greatly, and the driving voltage AVDD is dithered.

[0103] It should be noted that the driving current of the operational amplifier AMPB in the source driving circuit Source Driver IC is adjusted to alleviate the problem of dithering of the driving voltage AVDD because the operational amplifier AMPB in the source driving circuit Source Driver IC is connected to the output signal end Vo of the power management chip PMIC, that is, is affected by the driving voltage AVDD. Therefore, when the driving current of the operational amplifier AMPB in the source driving circuit Source Driver IC changes, the size of the load connected to the output signal end Vo of the power management chip PMIC can be adjusted, so that the fluctuation of the driving voltage AVDD can be adjusted.

[0104] The second example is shown in FIG. 12. The timing controller Tcon controls the power management chip PMIC to generate the driving voltage AVDD, and controls the gate driving circuit to scan the gate lines Gate row by row in the display phase AA, and controls the source driving circuit Source Driver IC to write the corresponding data voltage into the data lines according to the driving voltage AVDD to charge the corresponding pixel units. In particular, the blanking phase Blanking is divided into a first period T1, a second period T2 and a third period T3 from the start time to the end time. In the blanking phase Blanking, the timing controller Tcon controls the redundant shift register Dummy GOA in the gate driving circuit to work, that is, increases the timing control signal CLK to scan the redundant gate lines to make the redundant pixel units work, and at the same time, the timing controller Tcon controls the data voltage written by the source driving circuit Blanking to decrease step by step in the first period T1, to be the first data voltage in the second period T2, and to increase step by step in the third period T3; the first data voltage is not greater than the minimum voltage written by the source driving circuit Source Driver IC in the first period T1 and the third period T3. In this way, the problem of the display panel display from the display phase AA to the blanking phase Blanking, the minimum load of the output of the data voltage signal in the blanking phase Blanking, and the resulting driving voltage AVDD jitter can be effectively alleviated.

[0105] In some examples, in the display phase AA, the data signal written into the pixel units connected with the shift register is the valid data signal needed to be displayed, and in the blanking phase Blanking, the data signal written into the pixel units connected with the redundant shift register Dummy GOA is the invalid data signal. For example, the invalid data signal can include the full black display with the gray scale value of 0.

[0106] In other examples, the invalid data signal can be determined according to the gray scale voltage corresponding to the data signal written into the last row of pixel units at the end of the display phase. For details, refer to Table 1. As shown in Table 1, when the gray scale value corresponding to the data signal written into the last row of pixel units is 192-255, the gray scale value 192 can be selected as the gray scale in invalid display; when the gray scale value corresponding to the data signal written into the last row of pixel units is 128-192, the gray scale value 128 can be selected as the gray scale in invalid display; and so on.

[0107] Table 1

[0108] Optionally, in the invalid display process, the gray scale value corresponding to the written data signal can change in steps, referring to FIG. 10, when the gray scale value 192 is selected as the gray scale value in the invalid display, it can first decrease to 0 in steps and then increase to 255 in steps, facilitating the data signal writing in the next display stage AA. Specifically, the blanking stage Blanking is divided into three time periods, namely, a first time period T1, a second time period T2 and a third time period T3, the gray scale value in the first time period T1 can change as follows: 192→128→64, the gray scale value in the second time period T2 can be 0, and the gray scale value in the third time period T3 can change as follows: 64→128→192→255.

[0109] In some examples, when the display panel is in the blanking stage Blanking, the data signals provided by at least part of the data lines are the same. It should be noted that the data voltage provided in the blanking stage Blanking is an invalid display signal. Grouping and writing multiple data signals provided by the source driving circuit Source Driver IC into the data lines can make the number of loads driven by the driving voltage AVDD decrease in steps, for example, for a display panel including 960 column pixel units, the 960 column pixel units can be divided into three groups, and the data signals are written in sequence, at a first time, the first group of pixel units is written with a first data signal DATA1, at a second time, the second group of pixel units is written with a second data signal DATA2, and at a third time, the third group of pixel units is written with a third data signal DATA3, at this time, referring to FIG. 11, the driving voltage AVDD will increase three times with a small amplitude, and will not change dramatically to cause the filter capacitor to howl.

[0110] A third example is shown in FIG. 13. The timing controller controls the power management chip to generate the driving voltage AVDD, and controls the gate driving circuit to scan the gate lines Gate row by row in the display stage AA, and controls the source driving circuit Source Driver IC to write the corresponding data voltage into the data lines according to the driving voltage AVDD to charge the corresponding pixel units. In particular, the blanking stage Blanking is divided into a first period T1, a second period T2 and a third period T3 from the start time to the end time. In the blanking stage Blanking, the timing controller Tcon controls the redundant shift register Dummy GOA in the gate driving circuit to work, that is, increases the timing control signal CLK to scan the redundant gate lines to make the redundant pixel units work, and at the same time, the timing controller Tcon controls the number of output channels of the source driving circuit to be opened to decrease step by step in the first period T1, to be all turned off in the second period T2, and to increase step by step in the third period T3. In this way, the problem of the display panel display from the display stage AA to the blanking stage Blanking can be effectively alleviated, the output load of the data voltage signal in the blanking stage Blanking is minimized, and the driving voltage AVDD is dithered, as shown in FIG. 14.

[0111] In some examples, the blanking stage Blanking is divided into 5 equal parts, each being t / 5, and the first period T1 of the blanking stage is the first and second t / 5, the second period T2 is the third t / 5, and the third period T3 is the fourth and fifth t / 5. At this time, in the first t / 5, 2 / 3 of the output channels of the source driving circuit Source Driver IC are opened, in the second t / 5, 1 / 3 of the output channels of the source driving circuit Source Driver IC are opened, in the second t / 5, the output channels of the source driving circuit Source Driver IC are turned off, in the fourth t / 5, 1 / 3 of the output channels of the source driving circuit Source Driver IC are opened, and in the fifth t / 5, 2 / 3 of the output channels of the source driving circuit Source Driver IC are opened.

[0112] In some examples, the power management chip PMIC includes a voltage generating circuit and a self-calibration circuit. The self-calibration circuit can include a sampling sub-circuit, a comparison sub-circuit and a compensation sub-circuit. The sampling sub-circuit and the compensation sub-circuit can adopt the structure in FIG. 3, and the comparison sub-circuit can adopt the comparison sub-circuit in FIG. 5, which will not be repeated here.

[0113] It is understood that the above embodiments are only exemplary for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. A self-calibration circuit configured to adjust a driving voltage generated by a voltage generation circuit in a power management chip; The self-calibration circuit includes a sampling subcircuit, a comparison subcircuit and a compensation subcircuit; The sampling sub-circuit is configured to collect the driving voltage and generate a sampling voltage; Based on the time node of the display frame of the display panel, the comparison subcircuit is configured to compare the sampling voltage with the reference voltage and output a comparison voltage; the compensation subcircuit is configured to adjust the current driving voltage based on the comparison voltage.

2. The self-calibration circuit according to claim 1, wherein: The comparison subcircuit includes a reference voltage generation module and a comparison module; The reference voltage generating module is configured to output the corresponding reference voltage based on a time node of a display frame in which the display panel is located; The comparison module is configured to output the corresponding comparison voltage according to the collected voltage and the reference voltage.

3. The self-calibration circuit according to claim 2, wherein: The display frame includes a display phase and a blanking phase; When the time node of the display frame of the display panel is a first preset moment, the reference voltage output by the reference voltage generating module is switched from the currently output first reference voltage to a second reference voltage; the difference between the first preset moment and the start moment of the blanking phase is a preset time; When the time node of the display frame of the display panel is a second preset moment, the reference voltage output by the reference voltage generating module is switched from the currently output second reference voltage to a third reference voltage; the difference between the second preset moment and the end moment of the blanking phase is a preset time; The second reference voltage is less than the first reference voltage, and the third reference voltage is greater than the first reference voltage; the difference between the first preset time and the second preset time is the duration of the blanking phase.

4. The self-calibration circuit according to claim 3, wherein: The first preset time is earlier than the start time of the blanking phase.

5. The self-calibration circuit according to claim 3, wherein: The preset time is 30us.

6. The self-calibration circuit according to claim 2, wherein the comparison module comprises an error amplifier; a non-inverting input terminal of the error amplifier is connected to the reference voltage generation module, an inverting input terminal is connected to the acquisition sub-circuit, and an output terminal is connected to the compensation sub-circuit.

7. The self-calibration circuit according to claim 2, wherein: The compensation subcircuit includes a logic operation module and an output module; the output module includes an input filter capacitor, an energy storage inductor, a switch tube and a third resistor; The signal input end of the logic operation module is connected to the signal output end of the comparison sub-circuit, and the signal output end of the logic operation module is connected to the control electrode of the switching tube; the first electrode of the switching tube is connected to the output signal end of the driving voltage, the second electrode is connected to the first end of the third resistor, and the second end of the third resistor is connected to the reference ground; the first end of the input filter capacitor is connected to the first end of the energy storage inductor and the input voltage end, and the second end of the energy storage inductor is connected to the output signal end of the driving voltage.

8. The self-calibration circuit according to claim 1, wherein: The compensation subcircuit includes a first compensation module and a second compensation module; The first compensation module is configured to perform an initial adjustment on the current driving voltage based on the comparison voltage; The second compensation module is configured to adjust the driving voltage after the initial adjustment again based on a time node of a display frame in which the display panel is located.

9. The self-calibration circuit according to claim 8, wherein: The display frame includes a display phase and a blanking phase; When the time node of the display frame of the display panel is a first preset moment, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to the second driving voltage; the difference between the first preset moment and the start time of the blanking phase is a preset time; When the time node of the display frame of the display panel is a second preset moment, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to a third driving voltage; the difference between the second preset moment and the end moment of the blanking phase is a preset time; The difference between the first preset time and the second preset time is the duration of the blanking phase.

10. The self-calibration circuit according to claim 9, wherein: The first preset time is earlier than the start time of the blanking phase.

11. The self-calibration circuit according to claim 8, wherein: The comparison module includes an error amplifier; the error amplifier has a non-inverting input terminal connected to the reference voltage signal terminal, an inverting input terminal connected to the acquisition sub-circuit, and an output terminal connected to the first compensation module.

12. The self-calibration circuit according to claim 8, wherein: The first compensation module includes a logic operation module and an output module; the output module includes a switch tube and a third resistor; The signal input end of the logic operation module is connected to the signal output end of the comparison sub-circuit, and the signal output end of the logic operation module is connected to the control electrode of the switching tube; the first electrode of the switching tube is connected to the signal end outputting the driving voltage, the second electrode is connected to the first end of the third resistor, and the second end of the third resistor is connected to the reference ground.

13. The self-calibration circuit according to claim 1, wherein: The acquisition subcircuit includes a first resistor and a second resistor; The first end of the first resistor is connected to the signal end outputting the driving voltage, the second end of the first resistor and the first end of the second resistor are both connected to the comparison sub-circuit, and the second end of the second resistor is connected to the reference ground.

14. The self-calibration circuit according to claim 1, wherein: Also includes: The phase identification sub-circuit is configured to receive the row number of the system data decoded by the timing controller and determine the time node of the display frame of the display panel.

15. The self-calibration circuit according to claim 1, wherein: Also includes: The phase identification subcircuit is configured to detect the current magnitude of the voltage generating circuit and determine the time node of the display frame of the display panel.

16. A power management chip, comprising the self-calibration circuit according to any one of claims 1 to 15, and a voltage generation circuit; The voltage generating circuit is configured to output a driving voltage in response to a first voltage and a modulation signal output by a timing controller; a signal output terminal of the voltage generating circuit is multiplexed as a signal input terminal of the self-calibration circuit. 17 . A display device comprising the power management chip and a timing controller according to claim 16 ; the timing controller is configured to generate a first voltage and a modulation signal for a voltage generating circuit to generate a driving voltage.

18. A display device comprising a power management chip, a timing controller, and a display panel; the display panel comprising a plurality of gate lines and a plurality of data lines, the gate lines and the data lines intersecting to define a plurality of pixel units, a gate drive circuit providing a gate drive signal to the gate lines, and a source drive circuit providing a data voltage to the data lines; the power management chip is configured to generate a drive voltage based on a first voltage provided by the timing controller and a modulation signal, to be applied to the source driver; wherein, The gate driving circuit includes a plurality of shift registers and at least one redundant shift register; the plurality of gate lines connected to the redundant shift register are redundant gate lines, and the pixel units connected to the redundant gate lines are redundant pixel units; The timing controller is configured to control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to work, and control the source drive circuit to provide a data voltage to the data line when the display panel is in a blanking phase.

19. The display device according to claim 18, wherein The blanking phase is divided into a first period, a second period and a third period from its starting time to its ending time; The timing controller is specifically configured to, when the display panel is in a blanking phase, control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to operate, and control the drive current of the operational amplifier of the source drive circuit to decrease in a step-by-step manner in the first time period, to have no current output in the second time period, and to increase in a step-by-step manner in the third time period.

20. The display device according to claim 18, wherein The blanking phase is divided into a first period, a second period and a third period from its starting time to its ending time; The timing controller is specifically configured to, when the display panel is in a blanking phase, control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to operate, and control the data voltage written by the source driver circuit to decrease in a step-by-step manner in the first time period, to be the first data voltage in the second time period, and to increase in a step-by-step manner in the third time period; the first data voltage is not greater than the minimum voltage written in the first and third time periods of the source driver circuit.

21. The display device according to claim 18, wherein The blanking phase is divided into a first period, a second period and a third period from its starting time to its ending time; The timing controller is specifically configured to, when the display panel is in a blanking phase, control the redundant shift register to provide a gate drive signal to the redundant gate line to drive the redundant pixel unit to operate, and control the number of output channels of the source drive circuit to be turned on, decreasing in a step-by-step manner in the first time period, turning off all in the second time period, and increasing in a step-by-step manner in the third time period.

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