Switched-capacitor converter circuit and power supply device

Abstract

Provided in the present application are a switched-capacitor converter circuit and a power supply device. The circuit may comprise: a switched-capacitor converter, one or more sampling circuits, and a loop compensation circuit, wherein the switched-capacitor converter converts an input voltage into an output voltage; each of the one or more sampling circuits is used for collecting a circuit parameter, so as to obtain a first value corresponding to the circuit parameter; when the first value is greater than a corresponding first limit value, the loop compensation circuit adjusts a voltage at a control end of a first switch to make the first switch operate in a variable resistance region, and increases the on-resistance of the first switch to partially accommodate, by means of an increase in the on-resistance, a sudden change in the first value with respect to the corresponding first limit value, so as to stabilize each first value to the corresponding first limit value, thereby preventing the fluctuation of the input voltage from being transmitted to an output end, and thus ensuring the stability of an output; and the first switch is a switch among switches, which are currently in an on state and have adjustable on-resistances, in the switched-capacitor converter.

Description

Switched capacitor conversion circuit and power supply device

[0001] Cross Reference to Related Applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202410408159.0, filed on April 7, 2024, entitled “Switched capacitor conversion circuit and power supply device”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the field of electronic technology, and in particular, to a switched capacitor conversion circuit and a power supply device. BACKGROUND

[0004] Switched capacitor converters are used to convert input voltages into output voltages to power loads. Switched capacitor converters are widely used in various power supply scenarios due to their high efficiency. However, since the switched capacitor converter is an open-loop topology, fluctuations in the input voltage are transmitted to the output, affecting the stability of the output. Therefore, there is an urgent need to design a switched capacitor conversion circuit that can solve the aforementioned problem. SUMMARY

[0005] The present application provides a switched capacitor conversion circuit and a power supply device to solve the problem that fluctuations in the input voltage are transmitted to the output, affecting the stability of the output, to achieve stable output voltage and avoid fluctuations in the input voltage being transmitted to the output.

[0006] In a first aspect, the present application provides a switched capacitor conversion circuit, comprising: a switched capacitor converter, an input end of which is connected to an input end of the switched capacitor conversion circuit, and an output end of which is connected to an output end of the switched capacitor conversion circuit, for converting an input voltage into an output voltage; one or more sampling circuits corresponding to one or more circuit parameters, wherein each sampling circuit in the one or more sampling circuits is configured to collect the circuit parameter to obtain a first value corresponding to the circuit parameter; wherein the first value corresponds to a first limit value; a loop compensation circuit configured to, when the first value is greater than the corresponding first limit value, adjust the voltage at the control end of a first switch, so that the first switch works in a variable resistance region and increases the on-resistance of the first switch; wherein the first switch is a switch in the switched capacitor converter that is currently in an on state and has an adjustable on-resistance.

[0007] The one or more sampling circuits are capable of sampling the circuit parameter to obtain a first value corresponding to the circuit parameter. Therefore, when the input voltage fluctuates during the voltage conversion of the switched-capacitor converter, the first value sampled by the one or more sampling circuits also carries the fluctuation information of the input voltage. In this way, when the fluctuation of the input voltage causes the first value to exceed the corresponding first limit value, the loop compensation circuit adjusts the voltage at the control end of the first switch (i.e., the switch in the switched-capacitor converter that is currently in the on state and has a variable on resistance) to make the first switch work in the variable resistance region and increase the on resistance of the first switch, so as to partially bear the sudden change of the first value relative to the corresponding first limit value by the increase of the on resistance, to stabilize the first value at the corresponding first limit value, and avoid the fluctuation of the input voltage being transmitted to the output end, thereby ensuring the stability of the output. In addition, since the first switch is the switch in the switched-capacitor converter that is currently in the on state and has a variable on resistance, i.e., the switch in the switched-capacitor converter is reused, the area and cost of the circuit are reduced. Furthermore, since the switched-capacitor converter is capable of converting the input voltage into the output voltage, the voltage conversion is realized.

[0008] In a possible implementation, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip.

[0009] Since the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip, compared with being distributed on different chips, the number of pins and the area of the switched-capacitor conversion circuit are reduced, the cost is low, and the packaging is easy. In addition, since when the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are distributed on different chips, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit need to be connected through metal traces on a PCB, the traces are long and have high loss, while in the application embodiment, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip, and the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are connected through internal traces in the chip, so that the traces are reduced and the loss is reduced. It should be noted that the application embodiment also has the same effect as the switched-capacitor conversion circuit in the foregoing, which will not be described here.

[0010] In a possible implementation, the switched-capacitor conversion circuit further comprises: a power switch; an input terminal of the switched-capacitor converter is connected to an input terminal of the switched-capacitor conversion circuit through the power switch; the power switch is used to be turned on when the switched-capacitor converter performs voltage conversion, so that the input voltage is transmitted to the input terminal of the switched-capacitor converter; and the first switch is specifically one or more of the power switch and a switch in the switched-capacitor converter that is currently in a conduction state and has an adjustable conduction resistance.

[0011] Since the first switch is specifically one or more of the power switch and a switch in the switched-capacitor converter that is currently in a conduction state and has an adjustable conduction resistance, more ways are provided for the selection of the first switch. In addition, when the first switch is a switch in the switched-capacitor converter that is currently in a conduction state and has an adjustable conduction resistance, since the first switch reuses the switch in the switched-capacitor converter, the area and cost of the circuit are reduced.

[0012] In a possible implementation, the power switch, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip.

[0013] Since the power switch, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip, compared with being distributed on different chips, the pins and the area of the switched-capacitor conversion circuit are reduced, the cost is low, and the packaging is easy. In addition, since when the power switch, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are distributed on different chips, the power switch, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit need to be connected through metal traces on a PCB, the traces are long and have high loss, while in the embodiment of the present application, the power switch, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip, the power switch, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are connected through internal traces in the chip, the traces are reduced, and the loss is reduced.

[0014] In a possible implementation, the loop compensation circuit is further configured to, when the first value is less than or equal to the corresponding first limit value, adjust the voltage at the control terminal of the first switch, so that the first switch works in a first working zone; when the first switch is a metal-oxide semiconductor field effect transistor, the first working zone is a saturation zone; and when the first switch is a bipolar transistor, the first working zone is an amplification zone.

[0015] Obviously, the loop compensation circuit adjusts the voltage at the control terminal of the first switch when the first value is less than or equal to the corresponding first limit value, so that the first switch works in the first working region (i.e. the amplification region or the saturation region), to reduce the on-resistance of the first switch to the lowest, reduce the power consumption, and also ensure the stability of the output.

[0016] In a possible implementation, the one or more circuit parameters include a plurality of circuit parameters, and the one or more first values include a plurality of first values; the loop compensation circuit includes a plurality of first operational amplifiers, a plurality of diodes, a second operational amplifier, and a first driving circuit, wherein: the plurality of first operational amplifiers correspond to the plurality of diodes one by one, and the plurality of first operational amplifiers correspond to the plurality of first values one by one; a forward input terminal of a first operational amplifier in the plurality of first operational amplifiers is configured to receive the first value corresponding to the first operational amplifier, a reverse input terminal of the first operational amplifier is configured to receive the first limit value corresponding to the first value corresponding to the first operational amplifier, and an output terminal of the first operational amplifier is connected to a positive electrode of the diode corresponding to the first operational amplifier; negative electrodes of the plurality of diodes are connected to a reverse input terminal of the second operational amplifier, a forward input terminal of the second operational amplifier is configured to receive a second limit value, an output terminal of the second operational amplifier is connected to an input terminal of the first driving circuit, and an output terminal of the first driving circuit is connected to the control terminal of the first switch; the plurality of first operational amplifiers, the plurality of diodes, and the second operational amplifier are configured to output a first control signal when at least one of the one or more first values is greater than the corresponding first limit value, or output a second control signal when each of the one or more first values is less than or equal to the corresponding first limit value; and the first driving circuit is configured to adjust the voltage at the control terminal of the first switch so that the first switch works in the variable resistance region and increases the on-resistance of the first switch in response to the first control signal, or adjust the voltage at the control terminal of the first switch so that the first switch works in the first working region in response to the second control signal.

[0017] In a possible implementation, the one or more circuit parameters include one circuit parameter, and the one or more first values include one first value; and the loop compensation circuit includes a third operational amplifier and a second driving circuit, wherein: a positive input terminal of the third operational amplifier is configured to receive the first value, a negative input terminal of the third operational amplifier is configured to receive the first limit value corresponding to the first value, an output terminal of the third operational amplifier is connected with an input terminal of the second driving circuit, and an output terminal of the second driving circuit is connected with a control terminal of the first switch; the third operational amplifier is configured to output a first control signal when the first value is greater than the first limit value corresponding thereto, or output a second control signal when the first value is less than or equal to the first limit value; and the second driving circuit is configured to adjust a voltage of the control terminal of the first switch to make the first switch work in a variable resistance region and increase an on-resistance of the first switch in response to the first control signal, and adjust the voltage of the control terminal of the first switch to make the first switch work in the first working region in response to the second control signal.

[0018] In a possible implementation, the one or more circuit parameters include one or more of an input current, an output current, an output voltage, an input voltage, and a difference between the input voltage and the output voltage.

[0019] In a possible implementation, the sampling circuit corresponding to the output current includes a fourth operational amplifier, wherein: a positive input terminal of the fourth operational amplifier is connected with a high-voltage terminal of a low-side sampling resistor, a negative input terminal of the fourth operational amplifier is connected with a low-voltage terminal of the low-side sampling resistor, and an output terminal of the fourth operational amplifier is configured to output the first value corresponding to the output current; and the low-side sampling resistor and a load are connected in series between an output terminal of the switched-capacitor conversion circuit and the ground.

[0020] In a possible implementation, the sampling circuit corresponding to the output voltage includes a fifth operational amplifier, wherein:

[0021] a positive input terminal of the fifth operational amplifier is connected with an output terminal of the switched-capacitor conversion circuit, a negative input terminal of the fifth operational amplifier is connected with a low-voltage terminal of a load, and an output terminal of the fifth operational amplifier is configured to output the first value corresponding to the output voltage; and the load is connected between the output terminal of the switched-capacitor conversion circuit and the ground.

[0022] In a possible implementation, the sampling circuit corresponding to the difference between the input voltage and the output voltage comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a sixth operational amplifier, wherein: the first resistor and the second resistor are connected in series and then connected between an input terminal of the switched-capacitor converter and a positive input terminal of the sixth operational amplifier, the third resistor is connected between a connection point of the first resistor and the second resistor and a ground, the fourth resistor is connected between an output terminal of the switched-capacitor conversion circuit and a negative input terminal of the sixth operational amplifier, the fifth resistor is connected between the negative input terminal of the sixth operational amplifier and the ground, and the sixth resistor is connected between the positive input terminal of the sixth operational amplifier and an output terminal of the sixth operational amplifier; and the output terminal of the sixth operational amplifier is configured to output the first value corresponding to the difference between the input voltage and the output voltage.

[0023] In a possible implementation, when the switches in the switched-capacitor converter are metal-oxide semiconductor field effect transistors, the switches are switches with body diodes in an off state; or when the switches in the switched-capacitor converter are bipolar transistors, the switches are switches in the switched-capacitor converter that are currently in an on state.

[0024] In a possible implementation, the switched-capacitor converter comprises an N:1 step-down switched-capacitor converter, where N is an integer greater than 1.

[0025] In a second aspect, the present application also provides a power supply device, comprising the switched-capacitor conversion circuit in any of the first aspects.

[0026] The power supply device provided in the second aspect and possible designs of the second aspect has the advantages of the first aspect and possible implementations of the first aspect, which will not be described here.

[0027] In a third aspect, the present application also provides a chip, comprising the switched-capacitor conversion circuit in any of the first aspects.

[0028] The chip provided in the third aspect and possible designs of the third aspect has the advantages of the first aspect and possible implementations of the first aspect, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 is a schematic diagram of a switched-capacitor converter;

[0030] FIG. 2 is a schematic diagram of the switched-capacitor converter in FIG. 1 in a first working stage;

[0031] Fig. 3 is a schematic diagram of the switched-capacitor converter in Fig. 1 in a second phase of operation;

[0032] Fig. 4 is a schematic diagram of another switched-capacitor converter;

[0033] Fig. 5 is a schematic diagram of the switched-capacitor converter in Fig. 4 in a first phase of operation;

[0034] Fig. 6 is a schematic diagram of the switched-capacitor converter in Fig. 4 in a second phase of operation;

[0035] Fig. 7 is a schematic diagram of yet another switched-capacitor converter;

[0036] Fig. 8 is a schematic diagram of the switched-capacitor converter in Fig. 7 in a first phase of operation;

[0037] Fig. 9 is a schematic diagram of the switched-capacitor converter in Fig. 7 in a second phase of operation;

[0038] Fig. 10 is a schematic diagram of still another switched-capacitor converter;

[0039] Fig. 11 is a schematic diagram of the switched-capacitor converter in Fig. 10 in a first phase of operation;

[0040] Fig. 12 is a schematic diagram of the switched-capacitor converter in Fig. 10 in a second phase of operation;

[0041] Fig. 13 is a schematic diagram of the switched-capacitor converter in Fig. 1 with an anti-creep switch added;

[0042] Fig. 14 is a schematic diagram of a wireless charging circuit provided by an embodiment of the present application;

[0043] Fig. 15 is a schematic diagram of a power supply circuit provided by an embodiment of the present application;

[0044] Fig. 16 is a schematic diagram of a structure of a switched-capacitor conversion circuit provided by an embodiment of the present application;

[0045] Fig. 17 is a circuit diagram of a loop compensation circuit provided by an embodiment of the present application;

[0046] Fig. 18 is a circuit diagram of another loop compensation circuit provided by an embodiment of the present application;

[0047] Fig. 19 is a circuit diagram of a switched-capacitor conversion circuit based on the switched-capacitor converter in Fig. 13;

[0048] Fig. 20 is a timing diagram of the switched-capacitor conversion circuit in Fig. 19;

[0049] Fig. 21 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in Fig. 13;

[0050] Figure 22 is a circuit diagram of a switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 4;

[0051] Figure 23 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 4;

[0052] Figure 24 is a circuit diagram of yet another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 4;

[0053] Figure 25 is a circuit diagram of still another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 4;

[0054] Figure 26 is a circuit diagram of a switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 7;

[0055] Figure 27 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 7;

[0056] Figure 28 is a circuit diagram of yet another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 7;

[0057] Figure 29 is a circuit diagram of still another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 7;

[0058] Figure 30 is a circuit diagram of a switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 10;

[0059] Figure 31 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 10;

[0060] Figure 32 is a circuit diagram of yet another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 10;

[0061] Figure 33 is a circuit schematic of a switched-capacitor conversion circuit including a first power switch;

[0062] Figure 34 is a timing diagram for the switched-capacitor conversion circuit in Figure 33. DETAILED DESCRIPTION

[0063] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c alone, can represent: a alone, b alone, c alone, combination of a and b, combination of a and c, combination of b and c, or combination of a, b and c, where a, b, c can be single or multiple. In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance.

[0064] The terms "center", "longitudinal", "lateral", "upper", "lower", "left", "right", "front", "back", and the like indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0065] The terms "connected" and "connected" should be broadly understood, for example, the "connected" or "connected" of the circuit structure can mean physical connection, but also means electrical connection or signal connection, for example, it can be directly connected, that is, physically connected, or indirectly connected through one or more intermediate elements, as long as the circuit is connected, it can also be the internal connection of two elements; signal connection can not only be signal connection through the circuit, but also signal connection through media medium, such as radio waves. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0066] Before the embodiments of the present application are described, the switch capacitor converter involved in the embodiments of the present application is exemplarily described.

[0067] The switch capacitor converter is a DC-DC converter that uses a "fast" or "pumping" capacitor to store energy. The switch capacitor converter can increase or decrease the input voltage, and can also be used to generate a negative voltage. The switch capacitor converter includes a capacitor network and a switch network, and by controlling the switches in the switch network to turn on and off in a certain order, the charging and discharging operations of the capacitors in the capacitor network are controlled, so that the input voltage is multiplied or divided by a certain factor (for example, 1 / 2, 2 or 3, etc.), thereby obtaining an output voltage to power the load through the output voltage.

[0068] It should be noted that the switches in the switch network can be MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or BJTs (bipolar junction transistors), and the embodiments of the present application do not make special limitations thereon. The MOSFETs can be N-type MOSFETs or P-type MOSFETs, and the embodiments of the present application do not make special limitations thereon. The BJTs can be NPN-type BJTs or PNP-type BJTs, and the embodiments of the present application do not make special limitations thereon.

[0069] The switch capacitor converter can be an N:1 switch capacitor converter, where N:1 refers to the ratio of the input voltage to the output voltage of the switch capacitor converter. For a step-down switch capacitor converter, N is an integer greater than 1. For example, N includes but is not limited to 2, 3, or 4, etc. For a step-up switch capacitor converter, N is greater than zero and N is less than 1. For a switch capacitor converter generating a negative voltage, N is a negative number.

[0070] It should be noted that the ratio of the input voltage to the output voltage N:1 can be understood as N:1 or approximately N:1.

[0071] In the following, the structure of the switch capacitor converter according to the embodiments of the present application will be described exemplarily by taking the switches in the switch capacitor converter as N-type MOSFETs as an example.

[0072] FIG. 1 is a schematic diagram of a switch capacitor converter. In FIG. 1, the switch capacitor converter is a 2:1 step-down switch capacitor converter. The switch capacitor converter includes a capacitor network and a switch network, where the capacitor network includes two capacitors (capacitor C1A and capacitor C1B). The switch network includes eight switches (switches Q1A-Q4A and switches Q1B-Q4B).

[0073] As shown in FIG. 1, the connection relationship between each element in the switch capacitor converter is as follows:

[0074] The drain of the switch Q1A is connected with the input terminal Vin1 of the switched capacitor converter, the source of the switch Q1A is connected with the drain of the switch Q2A, the source of the switch Q2A, the drain of the switch Q3A and the output terminal Vout1 of the switched capacitor converter are connected, the source of the switch Q3A is connected with the drain of the switch Q4A, and the source of the switch Q4A is grounded. The drain of the switch Q1B is connected with the input terminal Vin1 of the switched capacitor converter, the source of the switch Q1B is connected with the drain of the switch Q2B, the source of the switch Q2B, the drain of the switch Q3B and the output terminal Vout1 of the switched capacitor converter are connected, the source of the switch Q3B is connected with the drain of the switch Q4B, and the source of the switch Q4B is grounded. One end of the capacitor C1A is connected with the connection point of the switch Q1A and the switch Q2A, and the other end of the capacitor C1A is connected with the connection point of the switch Q3A and the switch Q4A. One end of the capacitor C1B is connected with the connection point of the switch Q1B and the switch Q2B, and the other end of the capacitor C1B is connected with the connection point of the switch Q3B and the switch Q4B. The gates of the switches Q1A-Q4A and the switches Q1B-Q4B are used to receive corresponding driving signals (G1A-G4A and G1B-G4B). The correspondence between the driving signals and the gates of the switches is shown in FIG. 1, and each driving signal is used to control the on-off of the corresponding switch. The output terminal Vout1 of the switched capacitor converter is also connected with the ground GND through the load R.

[0075] The operation process of the switched capacitor converter includes a plurality of working periods, and each working period includes a first working stage and a second working stage. As shown in FIG. 2, in the first working stage, the switches Q1A, Q3A, Q2B and Q4B are turned on, the switches Q2A, Q4A, Q1B and Q3B are turned off, the input voltage charges the capacitor C1A along the power supply loop 201 and supplies power to the load R, at the same time, the capacitor C1B discharges and supplies power to the load R along the discharge loop 202. As shown in FIG. 3, in the second working stage, the switches Q2A, Q4A, Q1B and Q3B are turned on, the switches Q1A, Q3A, Q2B and Q4B are turned off, the capacitor C1A discharges and supplies power to the load R along the discharge loop 301, at the same time, the input voltage charges the capacitor C1B along the power supply loop 302 and supplies power to the load R.

[0076] FIG. 4 is a schematic diagram of another switched capacitor converter. In FIG. 4, the switched capacitor converter is a 4:1 switched capacitor converter in series-parallel connection. The switched capacitor converter includes a capacitor network and a switch network, wherein the capacitor network includes six capacitors (capacitors C1A-C3A and capacitors C1B-C3B). The switch network includes twenty switches (switches Q1A-Q10A and switches Q1B-Q10B).

[0077] As shown in FIG. 4, the connection relationship between each element in the switched capacitor converter is as follows:

[0078] The drain of the switch Q1A is connected with the input terminal Vin1 of the switched-capacitor converter, the source of the switch Q1A, the drain of the switch Q2A and one end of the capacitor C1A are connected, the other end of the capacitor C1A, the drain of the switch Q3A and the source of the switch Q4A are connected, the drain of the switch Q4A, the drain of the switch Q5A and one end of the capacitor C2A are connected, the other end of the capacitor C2A, the drain of the switch Q6A and the source of the switch Q7A are connected, the drain of the switch Q7A, the drain of the switch Q8A and one end of the capacitor C3A are connected, the other end of the capacitor C3A, the drain of the switch Q9A and the source of the switch Q10A are connected, the source of the switch Q2A, the source of the switch Q5A, the source of the switch Q8A and the drain of the switch Q10A are all connected with the output terminal Vout1 of the switched-capacitor converter. The source of the switch Q3A, the source of the switch Q6A and the source of the switch Q9A are all grounded.

[0079] The drain of the switch Q1B is connected with the input terminal Vin1 of the switched-capacitor converter, the source of the switch Q1B, the drain of the switch Q2B and one end of the capacitor C1B are connected, the other end of the capacitor C1B, the drain of the switch Q3B and the source of the switch Q4B are connected, the drain of the switch Q4B, the drain of the switch Q5B and one end of the capacitor C2B are connected, the other end of the capacitor C2B, the drain of the switch Q6B and the source of the switch Q7B are connected, the drain of the switch Q7B, the drain of the switch Q8B and one end of the capacitor C3B are connected, the other end of the capacitor C3B, the drain of the switch Q9B and the source of the switch Q10B are connected, the source of the switch Q2B, the source of the switch Q5B, the source of the switch Q8B and the drain of the switch Q10B are all connected with the output terminal Vout1 of the switched-capacitor converter. The source of the switch Q3B, the source of the switch Q6B and the source of the switch Q9B are all grounded.

[0080] The gate of each of the switches Q1A-Q10A and the switches Q1B-Q10B is used for receiving a corresponding driving signal (G1A-G10A and G1B-G10B). The corresponding relationship between the driving signal and the gate of the switch is shown in FIG. 4, and the driving signal is used for controlling the on-off of the corresponding switch. The output terminal Vout1 of the switched-capacitor converter and the ground GND are further connected with a load R.

[0081] The operation of the switched-capacitor converter includes a plurality of operation cycles, each of which includes a first operation phase and a second operation phase. In the first operation phase, as shown in FIG. 5, switches Q1A, Q4A, Q7A, Q10A, Q2B, Q3B, Q5B, Q6B, Q8B and Q9B are turned on, switches Q2A, Q3A, Q5A, Q6A, Q8A, Q9A, Q1B, Q4B, Q7B and Q10B are turned off, the input voltage charges capacitors C1A, C2A and C3A along a power supply loop 501 and supplies power to the load R, at the same time, capacitor C1B discharges and supplies power to the load R along a discharge loop 502, 505, capacitor C2B discharges and supplies power to the load R along a discharge loop 503, 506, and capacitor C3B discharges and supplies power to the load R along a discharge loop 504, 507.

[0082] In the second operation phase, as shown in FIG. 6, switches Q2A, Q3A, Q5A, Q6A, Q8A, Q9A, Q1B, Q4B, Q7B and Q10B are turned on, switches Q1A, Q4A, Q7A, Q10A, Q2B, Q3B, Q5B, Q6B, Q8B and Q9B are turned off, capacitor C1A discharges and supplies power to the load R along a discharge loop 601, 604, capacitor C2A discharges and supplies power to the load R along a discharge loop 602, 605, and capacitor C3A discharges and supplies power to the load R along a discharge loop 603, 606. At the same time, the input voltage charges capacitors C1B, C2B and C3B along a power supply loop 607 and supplies power to the load R.

[0083] FIG. 7 is a schematic diagram of another switched-capacitor converter. In FIG. 7, the switched-capacitor converter is a Dickson 4:1 switched-capacitor converter. The switched-capacitor converter includes a capacitor network and a switch network, wherein the capacitor network includes 6 capacitors (capacitors C1A-C3A and capacitors C1B-C3B). The switch network includes 16 switches (switches Q1A-Q8A and switches Q1B-Q8B).

[0084] As shown in FIG. 7, the connection relationship between each element in the switched-capacitor converter is as follows:

[0085] The drain of the switch Q1A is connected with the input terminal Vin1 of the switched-capacitor converter, the source of the switch Q1A is connected with the drain of the switch Q2A, the source of the switch Q2A is connected with the drain of the switch Q3A, the source of the switch Q3A is connected with the drain of the switch Q4A, the source of the switch Q4A, the drain of the switch Q5A and the drain of the switch Q7A are connected with the output terminal Vout1 of the switched-capacitor converter, the source of the switch Q5A is connected with the drain of the switch Q6A, the source of the switch Q7A is connected with the drain of the switch Q8A, and the source of the switch Q8A and the source of the switch Q6A are both connected with the ground GND. One end of the capacitor C1A is connected with the connection point of the switch Q1A and the switch Q2A, and the other end of the capacitor C1A is connected with the connection point of the switch Q5A and the switch Q6A. One end of the capacitor C2A is connected with the connection point of the switch Q2A and the switch Q3A, and the other end of the capacitor C2A is connected with the connection point of the switch Q7A and the switch Q8A. One end of the capacitor C3A is connected with the connection point of the switch Q3A and the switch Q4A, and the other end of the capacitor C3A is connected with the connection point of the switch Q5A and the switch Q6A.

[0086] The drain of the switch Q1B is connected with the input terminal Vin1 of the switched-capacitor converter, the source of the switch Q1B is connected with the drain of the switch Q2B, the source of the switch Q2B is connected with the drain of the switch Q3B, the source of the switch Q3B is connected with the drain of the switch Q4B, the source of the switch Q4B, the drain of the switch Q5B and the drain of the switch Q7B are connected with the output terminal Vout1 of the switched-capacitor converter, the source of the switch Q5B is connected with the drain of the switch Q6B, the source of the switch Q7B is connected with the drain of the switch Q8B, and the source of the switch Q8B and the source of the switch Q6B are both connected with the ground GND. One end of the capacitor C1B is connected with the connection point of the switch Q1B and the switch Q2B, and the other end of the capacitor C1B is connected with the connection point of the switch Q5B and the switch Q6B. One end of the capacitor C2B is connected with the connection point of the switch Q2B and the switch Q3B, and the other end of the capacitor C2B is connected with the connection point of the switch Q7B and the switch Q8B. One end of the capacitor C3B is connected with the connection point of the switch Q3B and the switch Q4B, and the other end of the capacitor C3B is connected with the connection point of the switch Q5B and the switch Q6B.

[0087] The gate of each of the switches Q1A-Q8A and the switches Q1B-Q8B is used for receiving a corresponding driving signal (G1A-G8A and G1B-G8B). The corresponding relationship between the driving signal and the gate of the switch is shown in FIG. 7, and the driving signal is used for controlling the on-off of the corresponding switch. The output terminal Vout1 of the switched-capacitor converter is also connected with the ground GND through a load R.

[0088] The operation of the switched-capacitor converter includes a plurality of operation cycles, each of which includes a first operation phase and a second operation phase. In the first operation phase, as shown in FIG. 8, switches Q1A, Q3A, Q5A, Q8A, Q2B, Q4B, Q6B and Q7B are turned on, switches Q2A, Q4A, Q6A, Q7A, Q1B, Q3B, Q5B and Q8B are turned off, the input voltage charges capacitor C1A along supply loop 801 and supplies power to load R, capacitor C2A discharges and charges capacitor C3A along discharge loops 802, 803 and supplies power to load R, at the same time, capacitor C1B discharges and charges capacitor C2B along discharge loops 804, 805 and supplies power to load R, and capacitor C3B discharges and supplies power to load R along discharge loops 806, 807.

[0089] In the second operation phase, as shown in FIG. 9, switches Q2A, Q4A, Q6A, Q7A, Q1B, Q3B, Q5B and Q8B are turned on, switches Q1A, Q3A, Q5A, Q8A, Q2B, Q4B, Q6B and Q7B are turned off, capacitor C1A discharges and charges capacitor C2A along discharge loops 901, 902 and supplies power to load R, capacitor C3A discharges and supplies power to load R along discharge loops 903, 904, at the same time, the input voltage charges capacitor C1B along supply loop 905 and supplies power to load R, capacitor C2B discharges and charges capacitor C3B along discharge loops 906, 907 and supplies power to load R.

[0090] FIG. 10 is a schematic diagram of another switched-capacitor converter. In FIG. 10, the switched-capacitor converter is an interleaved cascaded 4:1 switched-capacitor converter. The switched-capacitor converter includes a capacitor network and a switch network, wherein the capacitor network includes four capacitors (capacitors C1A, C2A and capacitors C1B, C2B). The switch network includes 14 switches (i.e., switches Q1A-Q7A and switches Q1B-Q7B).

[0091] As shown in FIG. 10, the connection relationship between each element in the switched-capacitor converter is as follows:

[0092] The drain of the switch Q1A is connected with the input terminal Vin1 of the switched-capacitor converter, the source of the switch Q1A is connected with the drain of the switch Q2A, the source of the switch Q2A, the drain of the switch Q5B and one end of the capacitor C2B are connected with the drain of the switch Q3B, the source of the switch Q3B is connected with the drain of the switch Q4B, the source of the switch Q5B and the drain of the switch Q6B are connected with the output terminal Vout1 of the switched-capacitor converter, the source of the switch Q6B and the other end of the capacitor C2B are connected with the drain of the switch Q7B, the source of the switch Q4B and the source of the switch Q7B are both grounded. The drain of the switch Q1B is connected with the input terminal Vin1 of the switched-capacitor converter, the source of the switch Q1B is connected with the drain of the switch Q2B, the source of the switch Q2B, the drain of the switch Q5A and one end of the capacitor C2A are connected with the drain of the switch Q3A, the source of the switch Q3A is connected with the drain of the switch Q4A, the source of the switch Q5A and the drain of the switch Q6A are connected with the output terminal Vout1 of the switched-capacitor converter, the source of the switch Q6A and the other end of the capacitor C2A are connected with the drain of the switch Q7A, the source of the switch Q4A and the source of the switch Q7A are both grounded. One end of the capacitor C1A is connected with the connection point of the switch Q1A and the switch Q2A, the other end of the capacitor C1A is connected with the connection point of the switch Q3A and the switch Q4A. One end of the capacitor C1B is connected with the connection point of the switch Q1B and the switch Q2B, the other end of the capacitor C1B is connected with the connection point of the switch Q3B and the switch Q4B.

[0093] The gate of each of the switches Q1A-Q7A and the switches Q1B-Q7B is used for receiving a corresponding driving signal (G1A-G7A and G1B-G7B). The corresponding relationship between the driving signal and the gate of the switch is shown in FIG. 10, and the driving signal is used for controlling the on-off of the corresponding switch. The output terminal Vout1 of the switched-capacitor converter is also connected with the ground GND through a load R.

[0094] The operation process of the switched-capacitor converter includes a plurality of working periods, and each working period includes a first working stage and a second working stage. As shown in FIG. 11, in the first working stage, the switches Q1A, Q3A, Q6A, Q2B, Q4B, Q5B and Q7B are turned on, the switches Q2A, Q4A, Q5A, Q7A, Q1B, Q3B and Q6B are turned off, the input voltage charges the capacitors C1A and C2A along the power supply loop 1101 and supplies power to the load R, at the same time, the capacitor C1B discharges and charges the capacitor C2A along the discharge loops 1102, 1103 and supplies power to the load R, and the capacitor C2B discharges and supplies power to the load R along the discharge loops 1104, 1105.

[0095] As shown in FIG. 12, in the second working stage, switches Q2A, Q4A, Q5A, Q7A, Q1B, Q3B and Q6B are turned on, switches Q1A, Q3A, Q6A, Q2B, Q4B, Q5B and Q7B are turned off, capacitor C1A discharges and charges capacitor C2B along discharge loops 1201, 1202 and supplies power to load R, capacitor C2A discharges and supplies power to load R along discharge loops 1203, 1204, and meanwhile, input voltage charges capacitor C1B and capacitor C2B along supply loop 1205 and supplies power to load R.

[0096] It should be noted that in the above-mentioned switch capacitor converter, a filter capacitor can be connected between the input terminal Vin1 of the switch capacitor converter and the ground GND, so as to reduce noise such as interference and ripple in the input voltage through the filter capacitor and stabilize the input voltage.

[0097] It should be noted that in the above-mentioned switch capacitor converter, the switches in the switch capacitor converter can also be P-type MOSFET, NPN-type BJT or PNP-type BJT. In the case where the switches in the switch capacitor converter are P-type MOSFET, NPN-type BJT or PNP-type BJT, the working process of the switch capacitor converter is similar to the above-mentioned working process, and the difference lies in that the connection mode of the switches needs to be adaptively adjusted according to the type of the switches.

[0098] It should be noted that the above-mentioned description of the switch capacitor converter is only exemplary and does not limit the switch capacitor converter in the present application. In addition, the load R can be a battery (i.e., it can be understood that the switch capacitor converter is used for voltage conversion to charge the battery). The load R can also be a subsequent load of the system in which the switch capacitor converter is located, which is not specially limited here.

[0099] It should be noted that in the case where the load R is a battery and the switches in the switch capacitor converter are MOSFET, in order to avoid the battery from leaking to the input terminal of the switch capacitor converter along the body diode of the switch when stopping charging the battery, an anti-leakage switch can be connected in series at the input terminal of the switch capacitor converter, so as to block the battery from leaking to the input terminal of the switch capacitor converter through the body diode of the switch by means of the anti-leakage switch. The anti-leakage switch includes but is not limited to MOSFET and BJT.

[0100] Next, based on the switched-capacitor converter in FIG. 1, the leakage-proof switch is exemplarily described by taking the N-type MOSFET as an example. FIG. 13 is a schematic diagram in which the leakage-proof switch is added based on FIG. 1. As shown in FIG. 13, the drain of the leakage-proof switch QC is connected with the input end Vin1 of the switched-capacitor converter, and the source of the leakage-proof switch QC is configured to receive the input voltage. The gate of the leakage-proof switch QC is configured to receive the driving signal GC. When charging the battery BAT (i.e., the load R), the leakage-proof switch QC is turned on under the action of the driving signal GC, the input voltage is transmitted to the input end Vin1 of the switched-capacitor converter through the leakage-proof switch QC, and the input voltage is converted into the output voltage by the switched-capacitor converter, and then the battery BAT is charged. When stopping charging the battery BAT, since the leakage-proof switch QC is turned off under the action of the driving signal GC and the body diode of the leakage-proof switch QC is reversely connected (as shown in FIG. 13), the battery BAT cannot leak to the input end Vin1 through the body diodes of the switches Q2A and Q1A, the switches Q2B and Q1B.

[0101] The switched-capacitor converter is widely used in various power supply scenarios due to its high efficiency. For example, in the wireless charging application scenario of a mobile phone, a receiver is configured to receive a power signal and transmit the power signal to a rectifier. The rectifier rectifies the power signal to obtain an input voltage and provides the input voltage to the input end of the switched-capacitor converter. The switched-capacitor converter converts the input voltage into an output voltage to charge the battery of the mobile phone.

[0102] However, since the switched-capacitor converter is an open-loop topology, fluctuations in the input voltage will be transmitted to the output end, affecting the stability of the output. For example, in the wireless charging application scenario of a mobile phone, when voltage fluctuations caused by amplitude shift, keying, and modulation occur at the input end of the receiver, the voltage fluctuations will be transmitted to the input end of the switched-capacitor converter through the receiver and the rectifier, and then transmitted to the output end of the switched-capacitor converter through the input end of the switched-capacitor converter, affecting the stability of the output.

[0103] To solve the above technical problems, the embodiment of the present application provides a switched-capacitor conversion circuit, which can include a switched-capacitor converter, one or more sampling circuits and a loop compensation circuit. The switched-capacitor converter converts an input voltage into an output voltage, each of the one or more sampling circuits collects a circuit parameter to obtain a first value corresponding to the circuit parameter, and the loop compensation circuit, when the first value is greater than a corresponding first limit value, adjusts the voltage at the control end of a first switch, so that the first switch works in a variable resistance region and increases the on-resistance of the first switch, to bear the mutation of the first value relative to the corresponding first limit value through the increased part of the on-resistance, so as to stabilize the first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output. Wherein, the first switch is a switch in the switched-capacitor converter which is currently in a conduction state and has an adjustable on-resistance.

[0104] The switched-capacitor conversion circuit provided by the embodiment of the present application can be applied to a charging circuit or a power supply circuit and other scenarios requiring voltage conversion. For example, in the application scenario of wireless charging, FIG. 14 is a schematic diagram of a wireless charging circuit provided by the embodiment of the present application. As shown in FIG. 14, the wireless charging circuit can include a wireless power supply 141, a receiver 142, a rectifier 143, a switched-capacitor conversion circuit 144, a switched-inductor converter 145 and a battery BAT. The receiver 142 is configured to receive a power supply signal provided by the wireless power supply 141 and transmit the power supply signal to the rectifier 143. The rectifier 143 rectifies the power supply signal to obtain an input voltage and transmits the input voltage to the switched-capacitor conversion circuit 144 or the switched-inductor converter 145. In the wireless charging circuit, the switched-capacitor conversion circuit 144 or the switched-inductor converter 145 can be selected to charge the battery BAT. Specifically, when the battery BAT is charged by the switched-capacitor conversion circuit 144, the switched-capacitor conversion circuit 144 converts the input voltage into an output voltage and charges the battery BAT by the output voltage. When the battery BAT is charged by the switched-inductor converter 145, the switched-inductor converter 145 converts the input voltage into an output voltage.

[0105] For example, in the application scenario of supplying power to a subsequent system, FIG. 15 is a schematic diagram of a power supply circuit provided by the embodiment of the present application. The difference between the power supply circuit and the wireless charging circuit in FIG. 14 is that the load is replaced from the battery BAT to the subsequent system 146. The working process can refer to the working process of the wireless charging circuit, which will not be described here.

[0106] FIG. 16 is a structural schematic diagram of a switched-capacitor conversion circuit provided by an embodiment of the present application. As shown in FIG. 16, the switched-capacitor conversion circuit 144 can include a switched-capacitor converter 1441, one or more sampling circuits 1442, and a loop compensation circuit 1443. Wherein:

[0107] The input end of the switched-capacitor converter 1441 is connected with the input end of the switched-capacitor conversion circuit 144, and the output end of the switched-capacitor converter 1441 is connected with the output end of the switched-capacitor conversion circuit 144, and the switched-capacitor converter 1441 is configured to convert the input voltage into the output voltage. The switched-capacitor converter 1441 includes but is not limited to an N: 1 step-down switched-capacitor converter, where N is an integer greater than 1. The switched-capacitor converter 1441 has been described above and will not be repeated here.

[0108] The one or more sampling circuits 1442 correspond to one or more circuit parameters of the switched-capacitor conversion circuit 144 one by one, and the one or more sampling circuits 1442 are configured to collect the one or more circuit parameters to obtain one or more first values. The one or more first values correspond to the one or more circuit parameters one by one. It can be understood that each sampling circuit in the one or more sampling circuits 1442 is configured to collect the corresponding circuit parameter to obtain the corresponding first value. That is, each first value in the one or more first values refers to the value obtained by collecting the corresponding circuit parameter.

[0109] The one or more first values correspond to one or more first limit values one by one. Each first limit value in the one or more first limit values refers to the upper limit value of the corresponding first value.

[0110] For example, the one or more circuit parameters include one or more of the input current, the output current, the output voltage, and the difference between the input voltage and the output voltage. The one or more first values include one or more of the collected input current, the collected output current, the collected output voltage, and the collected difference between the input voltage and the output voltage. The one or more first limit values include one or more of the upper limit value of the input current, the upper limit value of the output current, the upper limit value of the output voltage, and the upper limit value of the difference between the input voltage and the output voltage.

[0111] The loop compensation circuit 1443 is configured to, when at least one first value in the one or more first values is greater than the corresponding first limit value, adjust (i.e., reduce) the voltage at the control end of the first switch, so that the first switch works in the variable resistance region and increases the on-resistance of the first switch, so that the increase in the on-resistance bears part of the mutation of the first value relative to the corresponding first limit value, so as to stabilize the first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0112] In the case that the one or more first values comprise one first value, the one or more first values being greater than the corresponding first limit value means that the one first value is greater than the corresponding first limit value. In the case that the one or more first values comprise a plurality of first values, the one or more first values being greater than the corresponding first limit value means that one of the plurality of first values is greater than the corresponding first limit value, or each of the plurality of first values is greater than the corresponding first limit value, or some of the plurality of first values are greater than the corresponding first limit value.

[0113] The first switch is a switch in the switched-capacitor converter 1441 that is currently in an on state and has an adjustable on resistance. Specifically, in the case that the switches in the switched-capacitor converter 1441 are MOSFETs, the switch in the switched-capacitor converter 1441 that is currently in an on state and has an adjustable on resistance is a switch whose body diode is in an off state. In the case that the switches in the switched-capacitor converter 1441 are BJTs, the switch in the switched-capacitor converter 1441 that is currently in an on state and has an adjustable on resistance is a switch in the switched-capacitor converter 1441 that is currently in an on state.

[0114] In the case that the first switch is a MOSFET, the control terminal of the first switch is a gate. In the case that the first switch is a BJT, the control terminal of the first switch is a base.

[0115] In the following, the selection of the first switch is exemplarily explained based on different switched-capacitor converters 1441. For example:

[0116] In the case that the switched-capacitor converter 1441 is as shown in FIG. 1, the first switch can be switch Q1A and / or switch Q2B in the first working phase, and the first switch can be switch Q1B and / or switch Q2A in the second working phase.

[0117] In the case that the switched-capacitor converter 1441 is as shown in FIG. 4, the first switch can be one or more of switch Q1A, switch Q2B, switch Q5B and switch Q8B in the first working phase, and the first switch can be one or more of switch Q1B, switch Q2A, switch Q5A and switch Q8A in the second working phase.

[0118] In the case that the switched-capacitor converter 1441 is as shown in FIG. 7, the first switch can be one or more of switch Q1A, switch Q3A, switch Q2B and switch Q4B in the first working phase, and the first switch can be one or more of switch Q1B, switch Q3B, switch Q2A and switch Q4A in the second working phase.

[0119] If the switch capacitor converter 1441 is as shown in FIG. 10, in the first working stage, the first switch can be one or more of the switch Q1A, the switch Q2B and the switch Q5B, and in the second working stage, the first switch can be one or more of the switch Q1B, the switch Q2A and the switch Q5A.

[0120] As can be seen from the above, since each of the one or more sampling circuits 1442 is capable of collecting the circuit parameter to obtain the first value corresponding to the circuit parameter. Therefore, in the process of voltage conversion of the switch capacitor converter 1441, when there is fluctuation in the input voltage, the first value collected by the sampling circuit 1442 also carries the fluctuation information of the input voltage. In this way, when the fluctuation of the input voltage causes the first value to exceed the first limit value, the loop compensation circuit 1443 adjusts the voltage at the control end of the first switch (i.e. the switch among the switches in the switch capacitor converter 1441 which is currently in the on state and whose on resistance is adjustable) to make the first switch work in the variable resistance region and increase the on resistance of the first switch, so as to bear part of the mutation of the first value relative to the corresponding first limit value through the increase of the on resistance, so as to stabilize the first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output. In addition, since the first switch is the switch in the switch capacitor converter 1441 which is currently in the on state and whose on resistance is adjustable, i.e. the switch in the switch capacitor converter 1441 is reused, the area and cost of the circuit are reduced. Furthermore, since the switch capacitor converter 1441 is capable of converting the input voltage into the output voltage, the transformation of the voltage is realized.

[0121] In some embodiments, the loop compensation circuit 1443 is further configured to, when the first value is less than or equal to the corresponding first limit value, adjust the voltage at the control end of the first switch to make the first switch work in the first working region. Wherein, in the case that the first switch is a MOSFET, the first working region is the saturation region. In the case that the first switch is a BJT, the first working region is the amplification region.

[0122] Obviously, the loop compensation circuit 1443 adjusts the voltage at the control end of the first switch to make the first switch work in the first working region (i.e. the amplification region or the saturation region) when the first value is less than or equal to the corresponding first limit value, so as to reduce the on resistance of the first switch to the lowest, reduce the power consumption, and at the same time also ensure the stability of the output.

[0123] Next, the loop compensation circuit 1443 and the one or more sampling circuits 1442 will be exemplarily described.

[0124] In a case that the one or more circuit parameters include a plurality of circuit parameters, the one or more first values include a plurality of first values, and the one or more first limit values include a plurality of first limit values. The number of the plurality of circuit parameters, the number of the plurality of first values, and the number of the plurality of first limit values are the same.

[0125] Based on this, FIG. 17 is a circuit diagram of a loop compensation circuit provided by an embodiment of the present application. As shown in FIG. 17, the loop compensation circuit 1443 can include a plurality of first operational amplifiers (CF1-CFM), a plurality of diodes (D1-DM), a second operational amplifier 14431, and a first driving circuit 14432, where M is an integer greater than 1. The plurality of first operational amplifiers (CF1-CFM) correspond to the plurality of diodes (D1-DM) one by one, and the plurality of first operational amplifiers (CF1-CFM) correspond to the plurality of first values one by one. Wherein:

[0126] For each first operational amplifier CFm (1≤m≤M), the positive input end of the first operational amplifier CFm is used to receive the corresponding first value (i.e., the first value corresponding to the first operational amplifier CFm), the reverse input end of the first operational amplifier CFm is used to receive the corresponding first limit value (i.e., the first limit value corresponding to the first value corresponding to the first operational amplifier CFm), and the output end of the first operational amplifier CFm is connected to the positive electrode of the corresponding diode Dm (1≤m≤M).

[0127] The negative electrodes of the plurality of diodes (D1-DM) are connected to the reverse input end of the second operational amplifier 14431, the positive input end of the second operational amplifier 14431 is used to receive the second limit value, the output end of the second operational amplifier 14431 is connected to the input end of the first driving circuit 14432, and the output end of the first driving circuit 14432 is connected to the control end of the first switch.

[0128] It should be noted that in a case that the first switch is a plurality, the output end of the first driving circuit 14432 and the input end of the first driving circuit 14432 are also a plurality, and the plurality of output ends of the first driving circuit 14432 correspond to the plurality of first switches one by one, and each output end of the first driving circuit 14432 is connected to the control end of the corresponding first switch. Each input end of the first driving circuit 14432 is connected to the output end of the second operational amplifier 14431.

[0129] The plurality of first operational amplifiers (CF1-CFM), the plurality of diodes (D1-DM), and the second operational amplifier 14431 are used to output a first control signal when one or more first values are greater than the corresponding first limit value, and output a second control signal when each first value is less than or equal to the corresponding first limit value.

[0130] Specifically, as shown in FIG. 17, for each first operational amplifier CFm, the first operational amplifier CFm compares the corresponding first value with the corresponding first limit value, and when the corresponding first value is greater than the corresponding first limit value, the first operational amplifier CFm outputs a high level to the diode Dm, and the diode Dm is turned on and transmits the high level to the reverse input end of the second operational amplifier 14431. When the corresponding first value is less than or equal to the corresponding first limit value, the first operational amplifier CFm outputs a low level to the diode Dm, and since the anode of the diode Dm is at a low level at this time, the diode Dm is turned off, and no signal is transmitted to the reverse input end of the second operational amplifier 14431, and the reverse input end of the second operational amplifier 14431 becomes a low level.

[0131] In this way, when at least one of the one or more first values is greater than the corresponding first limit value, the reverse input end of the second operational amplifier 14431 becomes a high level, and the high level is greater than the second limit value, and the second operational amplifier 14431 outputs the first control signal (i.e., a low level) based on that the high level is greater than the second limit value. When each of the first values is less than or equal to the corresponding first limit value, the voltage of the reverse input end of the second operational amplifier 14431 becomes a low level, and the low level is less than the second limit value, and the second operational amplifier 14431 outputs the second control signal (i.e., a high level) based on that the low level is less than the second limit value.

[0132] It should be noted that the second limit value can be set according to the high level and the low level output by the first operational amplifier CFm, so as to ensure that the second operational amplifier 14431 can output a low level (i.e., the first control signal) when the reverse input end of the second operational amplifier 14431 is at a high level, and the second operational amplifier 14431 can output a high level (i.e., the second control signal) when the reverse input end of the second operational amplifier 14431 is at a low level.

[0133] The first drive circuit 14432 is configured to adjust the voltage provided to the control end of the first switch to make the first switch work in the variable resistance region and increase the on-resistance of the first switch in response to the first control signal (i.e., a low voltage), and adjust the voltage of the control end of the first switch to make the first switch work in the first working region in response to the second control signal (i.e., a high voltage).

[0134] In a case where the one or more circuit parameters include one circuit parameter, the one or more first values include one first value, and the one or more first limit values include one first limit value.

[0135] Based on this, FIG. 18 is a circuit diagram of another loop compensation circuit provided by the embodiment of the present application, as shown in FIG. 18, the loop compensation circuit 1443 can include: a third operational amplifier 14433 and a second driving circuit 14434, wherein:

[0136] The positive input end of the third operational amplifier 14433 is configured to receive a first value, the negative input end of the third operational amplifier 14433 is configured to receive a first limit value corresponding to the first value, the output end of the third operational amplifier 14433 is connected with the input end of the second driving circuit 14434, and the output end of the second driving circuit 14434 is connected with the control end of the first switch.

[0137] It should be noted that in the case of multiple first switches, the output end of the second driving circuit 14434 and the input end of the second driving circuit 14434 are also multiple, and the multiple output ends of the second driving circuit 14434 correspond to the multiple first switches one by one, and each output end of the second driving circuit 14434 is connected with the control end of the corresponding first switch. Each input end of the second driving circuit 14434 is connected with the output end of the third operational amplifier 14433.

[0138] The third operational amplifier 14433 is configured to output a first control signal (i.e., high level) when the first value is greater than the corresponding first limit value, or output a second control signal (i.e., low level) when the first value is less than or equal to the first limit value.

[0139] The second driving circuit 14434 is configured to adjust the voltage of the control end of the first switch to make the first switch work in the variable resistance region and increase the on-resistance of the first switch in response to the first control signal, and adjust the voltage of the control end of the first switch to make the first switch work in the first working region in response to the second control signal.

[0140] In the case of the circuit parameter being an output current, the sampling circuit corresponding to the output current can include: a fourth operational amplifier. The positive input end of the fourth operational amplifier is connected with the high voltage end of the low-side sampling resistor, the negative input end of the fourth operational amplifier is connected with the low voltage end of the low-side sampling resistor, and the output end of the fourth operational amplifier is configured to output a first value corresponding to the output current. Wherein, the low-side sampling resistor and the load are connected in series between the output end of the switched-capacitor conversion circuit and the ground. It should be noted that the low-side sampling resistor here is set to collect the current (i.e., the output current) flowing through the load from the low side. After setting the low-side sampling resistor, the output current can be collected by collecting the voltage across the low-side sampling resistor.

[0141] In the case that the circuit parameter is the output voltage, the sampling circuit corresponding to the output voltage can comprise a fifth operational amplifier. The positive input terminal of the fifth operational amplifier is connected with the output terminal of the switched-capacitor conversion circuit (i.e. the high-voltage terminal of the load), the negative input terminal of the fifth operational amplifier is connected with the low-voltage terminal of the load, and the output terminal of the fifth operational amplifier is used to output a first value corresponding to the output voltage. It can be understood that the fifth operational amplifier collects the voltage across the load to output the first value corresponding to the output voltage.

[0142] It should be noted that the load connected between the output terminal of the switched-capacitor conversion circuit and the ground can be understood as that the load is directly connected between the output terminal of the switched-capacitor conversion circuit and the ground, or the load is connected between the output terminal of the switched-capacitor conversion circuit and the ground in series with other elements (low-side sampling resistor). The present application does not make special limitations on this.

[0143] In the case that the circuit parameter is the difference between the input voltage and the output voltage, the sampling circuit corresponding to the difference between the input voltage and the output voltage can comprise a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a sixth operational amplifier, wherein: the first resistor and the second resistor are connected in series between the input terminal of the switched-capacitor converter and the positive input terminal of the sixth operational amplifier. The third resistor is connected between the connection point of the first resistor and the second resistor and the ground. The fourth resistor is connected between the output terminal of the switched-capacitor conversion circuit and the negative input terminal of the sixth operational amplifier. The fifth resistor is connected between the negative input terminal of the sixth operational amplifier and the ground. The sixth resistor is connected between the positive input terminal of the sixth operational amplifier and the output terminal of the sixth operational amplifier. The output terminal of the sixth operational amplifier is used to output a first value corresponding to the difference between the input voltage and the output voltage. It can be understood that the sampling circuit corresponding to the difference between the input voltage and the output voltage can be understood as a differential amplification circuit, which is used to amplify and output the difference between the input voltage and the output voltage.

[0144] In the case that the circuit parameter is the input current, a MOSFET or a BJT can be connected in series between the input terminal of the switched-capacitor conversion circuit and the input terminal of the switched-capacitor converter, and the input current is collected by collecting the voltage difference across the MOSFET or the BJT. It should be noted that if an anti-leakage switch is provided in the switched-capacitor converter, the anti-leakage switch can be reused, i.e. a MOSFET or a BJT is no longer connected in series between the input terminal of the switched-capacitor conversion circuit and the input terminal of the switched-capacitor converter, and the input current is collected by collecting the voltage difference across the anti-leakage switch.

[0145] Next, the switch capacitor conversion circuit is exemplarily described in combination with the switch capacitor converter, the loop compensation circuit and the sampling circuit in the foregoing.

[0146] FIG. 19 is a circuit diagram of a switch capacitor conversion circuit based on the switch capacitor converter in FIG. 13. As shown in FIG. 19, the switch capacitor conversion circuit can include the switch capacitor converter, the loop compensation circuit, four sampling circuits, a battery BAT (i.e., a load) and a low-side sampling resistor RSENSE shown in FIG. 13. The circuit parameters include an input current, an output current, an output voltage and a difference between the input voltage and the output voltage. The first switches include switches Q2A and Q2B.

[0147] The output end VOUT of the switch capacitor conversion circuit is connected to the positive pole of the battery BAT, and the low-side sampling resistor RSENSE is connected between the negative pole of the battery BAT and the ground GND. The input end of the switch capacitor converter is connected to the input end VIN of the switch capacitor conversion circuit through the leakage prevention switch QC, and the output end of the switch capacitor converter is connected to the output end VOUT of the switch capacitor conversion circuit. The specific structure of the switch capacitor converter has been described in the foregoing and will not be described herein again.

[0148] The loop compensation circuit can include four first operational amplifiers (CF1-CF4), four diodes (D1-D4), a second operational amplifier 14431 and a first driving circuit 14432. The first driving circuit 14432 includes a first gate driving circuit 144321 and a second gate driving circuit 144322.

[0149] The four first operational amplifiers (CF1-CF4) correspond to the four diodes (D1-D4) one by one. The output end of the first operational amplifier CF1 is connected to the positive pole of the diode D1, the output end of the first operational amplifier CF2 is connected to the positive pole of the diode D2, the output end of the first operational amplifier CF3 is connected to the positive pole of the diode D3, and the output end of the first operational amplifier CF4 is connected to the positive pole of the diode D4. The negative poles of the four diodes (D1-D4) are all connected to the inverting input end of the second operational amplifier 14431, and the non-inverting input end of the second operational amplifier 14431 is used to receive a second limit value. The output end of the second operational amplifier 14431 is connected to the input ends of the first gate driving circuit 144321 and the second gate driving circuit 144322, the output end of the first gate driving circuit 144321 is connected to the gate of the switch Q2A, and the output end of the second gate driving circuit 144322 is connected to the gate of the switch Q2B.

[0150] It should be noted that the output end of the first gate drive circuit 144321 and the output end of the second gate drive circuit 144322 can be understood as two output ends of the first drive circuit 14432. The input end of the first gate drive circuit 144321 and the input end of the second gate drive circuit 144322 can be understood as two input ends of the first drive circuit 14432.

[0151] The four sampling circuits are a sampling circuit 14421 corresponding to the input current, a sampling circuit 14422 corresponding to the output current, a sampling circuit 14423 corresponding to the output voltage, and a sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage.

[0152] The input end of the sampling circuit 14421 corresponding to the input current is connected with the input end VIN of the switched capacitor conversion circuit, and the output end of the sampling circuit 14421 corresponding to the input current is connected with the positive input end of the first operational amplifier CF2. The reverse input end of the first operational amplifier CF2 is used to receive the first limit value IBUS_REG_REF (i.e. the first limit value corresponding to the first value obtained after sampling the input current). The sampling circuit 14421 corresponding to the input current is used to sample the input current to obtain the first value IBUS_SNS, and transmit the first value IBUS_SNS to the positive input end of the first operational amplifier CF2.

[0153] The sampling circuit 14422 corresponding to the output current can include a fourth operational amplifier OP4, the positive input end of the fourth operational amplifier OP4 is connected with the high voltage end of the low-side sampling resistor RSENSE, the reverse input end of the fourth operational amplifier OP4 is connected with the low voltage end of the low-side sampling resistor RSENSE, the output end of the fourth operational amplifier OP4 is connected with the positive input end of the first operational amplifier CF4, and the reverse input end of the first operational amplifier CF4 is used to receive the first limit value IBAT_REG_REF (i.e. the first limit value corresponding to the first value obtained after sampling the output current). The fourth operational amplifier OP4 is used to sample the output current to obtain the first value IBAT_SNS, and transmit the first value IBAT_SNS to the positive input end of the first operational amplifier CF4.

[0154] The sampling circuit 14423 corresponding to the output voltage can include a fifth operational amplifier OP5, a positive input terminal of the fifth operational amplifier OP5 connected with an output terminal VOUT of the switched capacitor conversion circuit, a negative input terminal of the fifth operational amplifier OP5 connected with a low voltage terminal of the battery BAT, an output terminal of the fifth operational amplifier OP5 connected with a positive input terminal of the first operational amplifier CF3, and a negative input terminal of the first operational amplifier CF3 used for receiving a first limit value VBAT_REG_REF (i.e., a first limit value corresponding to a first value obtained after sampling the output voltage). The fifth operational amplifier OP5 is used for sampling the output voltage to obtain the first value VBAT_SNS, and transmitting the first value VBAT_SNS to the positive input terminal of the first operational amplifier CF3.

[0155] The sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage can include a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a sixth operational amplifier OP6, wherein:

[0156] The first resistor R1 and the second resistor R2 are connected in series between an input terminal of the switched capacitor converter and a positive input terminal of the sixth operational amplifier OP6, the third resistor R3 is connected between a connection point of the first resistor R1 and the second resistor R2 and the ground GND, the fourth resistor R4 is connected between an output terminal VOUT of the switched capacitor conversion circuit and a negative input terminal of the sixth operational amplifier OP6, the fifth resistor R5 is connected between the negative input terminal of the sixth operational amplifier OP6 and the ground GND, and the sixth resistor R6 is connected between the positive input terminal of the sixth operational amplifier OP6 and an output terminal of the sixth operational amplifier OP6. The output terminal of the sixth operational amplifier OP6 is connected with a positive input terminal of the first operational amplifier CF1, and a negative input terminal of the first operational amplifier CF1 is used for receiving a first limit value VDROP_REG_REF (i.e., a first limit value corresponding to a first value obtained after sampling the difference between the input voltage and the output voltage). The sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage is used for sampling the difference between the input voltage and the output voltage to obtain the first value VDROP_SNS, and transmitting the first value VDROP_SNS to the positive input terminal of the first operational amplifier CF1.

[0157] In combination with the above, during the voltage conversion of the switched capacitor converter, the four sampling circuits collect the corresponding circuit parameters to obtain four first values. When the second operational amplifier 14431 determines that at least one of the four first values is greater than the corresponding first limit value, the second operational amplifier 14431 outputs a low level (i.e., a first control signal) to the first gate drive circuit 144321 and the second gate drive circuit 144322.

[0158] In the first working phase, the second gate drive circuit 144322, in response to the low level, reduces the gate voltage of the switch Q2B (i.e., the voltage of the drive signal G2B), so that the switch Q2B works in the variable resistance region and the on-resistance of the switch Q2B is increased, to partially bear the mutation of the first value relative to the corresponding first limit value through the increase of the on-resistance, so as to stabilize the first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0159] In the second working phase, the first gate drive circuit 144321, in response to the low level, reduces the gate voltage of the switch Q2A, so that the switch Q2A works in the variable resistance region and the on-resistance of the switch Q2A is increased, to partially bear the mutation of the first value relative to the corresponding first limit value through the increase of the on-resistance, so as to stabilize the first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0160] In combination with the above, during the voltage conversion of the switched capacitor converter, the four sampling circuits collect the corresponding circuit parameters to obtain four first values. When the second operational amplifier 14431 determines that at least one of the four first values is greater than the corresponding first limit value, the second operational amplifier 14431 outputs a low level (i.e., a first control signal) to the first gate drive circuit 144321 and the second gate drive circuit 144322.

[0161] In the first working phase, the second gate drive circuit 144322, in response to the low level, reduces the gate voltage of the switch Q2B (i.e., the voltage of the drive signal G2B), so that the switch Q2B works in the variable resistance region and the on-resistance of the switch Q2B is increased, to partially bear the mutation of the first value relative to the corresponding first limit value through the increase of the on-resistance, so as to stabilize the first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0162] In the second working phase, the first gate drive circuit 144321, in response to the low level, reduces the gate voltage of the switch Q2A, so that the switch Q2A works in the variable resistance region and the on-resistance of the switch Q2A is increased, to partially bear the mutation of the first value relative to the corresponding first limit value through the increase of the on-resistance, so as to stabilize the first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0163] Based on this, as shown in FIG. 20, before the time t1, there is fluctuation on the input voltage and the fluctuation continues to increase over time, the first value IBUS SNS (i.e. the input current collected) also continues to increase, and before the time t1, the first value IBUS SNS is less than or equal to the first limit value IBUS REG REF, therefore, before the time t1, in combination with the driving signals (G1A~G4A, G1B~G4B), it can be seen that the switches Q1A~Q4A and Q1B~Q4B are working in the saturation region when turned on, the output voltage is approximately half of the input voltage, and the output voltage is stable.

[0164] At the time t1, the fluctuation on the input voltage continues to increase, so that the first value IBUS SNS also continues to increase, and the first value IBUS SNS is greater than the first limit value IBUS REG REF. At this time, in combination with the timing diagram of each switch, it can be seen that the switch capacitor converter is working in the second working stage at the time t1, therefore, the voltage at the control end of the switch Q2A (i.e. the voltage of the driving signal G2A) is reduced, so that the switch Q2A works in the variable resistance region and increases the on-resistance of the switch Q2A, to partially bear the mutation of the first value IBUS SNS relative to the first limit value IBUS REG REF through the increase of the on-resistance, so as to stabilize the first value IBUS SNS at the first limit value IBUS REG REF, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0165] From the time t1 to the time t2, the fluctuation on the input voltage first continues to increase and then decreases, and the first value IBUS SNS is greater than the first limit value IBUS REG REF. Therefore, by reducing the voltage at the control end of the switch Q2B in the first working stage and reducing the voltage at the control end of the switch Q2A in the second working stage, the switches Q2B and Q2A work in the variable resistance region when turned on and increase the on-resistance of the switches Q2B and Q2A, to partially bear the mutation of the first value IBUS SNS relative to the first limit value IBUS REG REF through the increase of the on-resistance, so as to stabilize the first value IBUS SNS at the first limit value IBUS REG REF, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0166] At the moment t2 and after the moment t2, the input voltage continues to decrease and then tends to be stable, so the first value IBUS_SNS continues to decrease and then tends to be stable, and the first value IBUS_SNS is less than or equal to the first limit value IBUS_REG_REF. At this time, by increasing the control voltage of the switch Q2B and the switch Q2A when they are turned on, the switch Q2B and the switch Q2A are operated in the saturation region, the on-resistance of the switch Q2B and the switch Q2A is reduced, and thus the power consumption of the circuit is reduced and the output is stabilized.

[0167] Fig. 21 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in Fig. 13. As shown in Fig. 21, the switched-capacitor conversion circuit can include the switched-capacitor converter shown in Fig. 13, a loop compensation circuit, a sampling circuit 14423 corresponding to the output voltage, and a battery BAT (i.e., a load). The first switches include switches Q1A and Q1B. The battery BAT is connected between the output VOUT of the switched-capacitor conversion circuit and the ground GND.

[0168] The input of the switched-capacitor converter is connected to the input VIN of the switched-capacitor conversion circuit through an anti-leakage switch QC, and the output of the switched-capacitor converter is connected to the output VOUT of the switched-capacitor conversion circuit. The specific structure of the switched-capacitor converter has been described above and will not be repeated here.

[0169] The loop compensation circuit can include a third operational amplifier 14433 and a second driving circuit 14434, wherein the second driving circuit 14434 includes a third gate driving circuit 144341 and a fourth gate driving circuit 144342.

[0170] The output of the third operational amplifier 14433 is connected to the input of the third gate driving circuit 144341 and the input of the fourth gate driving circuit 144342. The output of the third gate driving circuit 144341 is connected to the gate of the switch Q1A, and the output of the fourth gate driving circuit 144342 is connected to the gate of the switch Q2B.

[0171] It should be noted that the output of the third gate driving circuit 144341 and the output of the fourth gate driving circuit 144342 can be understood as two outputs of the second driving circuit 14434. The input of the third gate driving circuit 144341 and the input of the fourth gate driving circuit 144342 can be understood as two inputs of the second driving circuit 14434.

[0172] The sampling circuit 14423 corresponding to the output voltage can include a fifth operational amplifier OP5, a positive input terminal of the fifth operational amplifier OP5 being connected with an output terminal VOUT of the switched-capacitor conversion circuit, a negative input terminal of the fifth operational amplifier OP5 being connected with a low-voltage terminal of the battery BAT, an output terminal of the fifth operational amplifier OP5 being connected with a positive input terminal of a third operational amplifier 14433, and a negative input terminal of the third operational amplifier 14433 being configured to receive the first limit value VBAT_REG_REF. The fifth operational amplifier OP5 is configured to collect the output voltage to obtain a first value VBAT_SNS, and transmit the first value VBAT_SNS to the positive input terminal of the third operational amplifier 14433.

[0173] It can be learned from the above that, in the process of voltage conversion of the switched-capacitor converter, the sampling circuit 14423 corresponding to the output voltage collects the output voltage to obtain the first value VBAT_SNS. When the first value VBAT_SNS is greater than the first limit value VBAT_REG_REF, the third operational amplifier 14433 outputs a high level (i.e., a first control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342.

[0174] In the first working phase, the third gate drive circuit 144341 reduces the gate voltage of the switch Q1A in response to the high level, so that the switch Q1A works in the variable resistance region and the on-resistance of the switch Q1A is increased, to bear the mutation of the first value VBAT_SNS relative to the first limit value VBAT_REG_REF by the increase of the on-resistance, so as to stabilize the first value VBAT_SNS at the first limit value VBAT_REG_REF, avoiding the fluctuation of the input voltage being transmitted to the output terminal, and ensuring the stability of the output.

[0175] In the second working phase, the fourth gate drive circuit 144342 reduces the gate voltage of the switch Q1B in response to the high level, so that the switch Q1B works in the variable resistance region and the on-resistance of the switch Q1B is increased, to bear the mutation of the first value VBAT_SNS relative to the first limit value VBAT_REG_REF by the increase of the on-resistance, so as to stabilize the first value VBAT_SNS at the first limit value VBAT_REG_REF, avoiding the fluctuation of the input voltage being transmitted to the output terminal, and ensuring the stability of the output.

[0176] In the process of voltage conversion by the switched-capacitor converter, the sampling circuit 14423 corresponding to the output voltage collects the output voltage to obtain a first value VBAT SNS. The third operational amplifier 14433 outputs a low level (i.e., a second control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342 when the first value VBAT SNS is less than or equal to a first limit value VBAT REG REF.

[0177] In the first working phase, the third gate drive circuit 144341 increases the gate voltage of the switch Q1A in response to the low level, so that the switch Q1A works in the saturation region.

[0178] In the second working phase, the fourth gate drive circuit 144342 increases the gate voltage of the switch Q1B in response to the low level, so that the switch Q1B works in the saturation region.

[0179] FIG. 22 is a circuit diagram of a switched-capacitor conversion circuit based on the switched-capacitor converter in FIG. 4. As shown in FIG. 22, the switched-capacitor conversion circuit can include the switched-capacitor converter shown in FIG. 4, a loop compensation circuit, a sampling circuit 14422 corresponding to the output current, a load R, and a low-side sampling resistor RSENSE. The first switches include the switches Q1A and Q1B. The output end VOUT of the switched-capacitor conversion circuit is connected to one end of the load R, and the low-side sampling resistor RSENSE is connected between the other end of the load R and the ground GND.

[0180] The input end of the switched-capacitor converter is connected to the input end VIN of the switched-capacitor conversion circuit, and the output end of the switched-capacitor converter is connected to the output end VOUT of the switched-capacitor conversion circuit. The specific structure of the switched-capacitor converter has been described above and will not be repeated here.

[0181] The structure of the loop compensation circuit is different from that of the loop compensation circuit in FIG. 21 in that the connection relationship between the positive input end and the negative input end of the third operational amplifier 14433 is different, which will be described below.

[0182] The sampling circuit 14422 corresponding to the output current can include a fourth operational amplifier OP4, a positive input terminal of the fourth operational amplifier OP4 connected to a high voltage terminal of the low-side sampling resistor RSENSE, a negative input terminal of the fourth operational amplifier OP4 connected to a low voltage terminal of the low-side sampling resistor RSENSE, an output terminal of the fourth operational amplifier OP4 connected to a positive input terminal of the third operational amplifier 14433, and a negative input terminal of the third operational amplifier 14433 configured to receive the first limit value IBAT_REG_REF. The fourth operational amplifier OP4 is configured to collect the output current to obtain a first value IBAT_SNS, and transmit the first value IBAT_SNS to the positive input terminal of the third operational amplifier 14433.

[0183] In combination with the above, during the voltage conversion of the switched-capacitor converter, the sampling circuit 14422 corresponding to the output current collects the output current to obtain a first value IBAT_SNS. When the first value IBAT_SNS is greater than the first limit value IBAT_REG_REF, the third operational amplifier 14433 outputs a high level (i.e., a first control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342.

[0184] In the first working phase, the third gate drive circuit 144341 reduces the gate voltage of the switch Q1A in response to the high level, so that the switch Q1A works in the variable resistance region and the on-resistance of the switch Q1A increases, so as to partially bear the sudden change of the first value IBAT_SNS relative to the first limit value IBAT_REG_REF through the increase of the on-resistance, so as to stabilize the first value IBAT_SNS at the first limit value IBAT_REG_REF, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0185] In the second working phase, the fourth gate drive circuit 144342 reduces the gate voltage of the switch Q1B in response to the high level, so that the switch Q1B works in the variable resistance region and the on-resistance of the switch Q1B increases, so as to partially bear the sudden change of the first value IBAT_SNS relative to the first limit value IBAT_REG_REF through the increase of the on-resistance, so as to stabilize the first value IBAT_SNS at the first limit value IBAT_REG_REF, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0186] In the process of voltage conversion of the switched capacitor converter, the output current is collected by the sampling circuit 14422 corresponding to the output current to obtain a first value IBAT SNS. The third operational amplifier 14433 outputs a low level (i.e. a second control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342 when the first value IBAT SNS is less than or equal to a first limit value IBAT REG REF.

[0187] In the first working stage, the third gate drive circuit 144341 increases the gate voltage of the switch Q1A in response to the low level, so that the switch Q1A works in the saturation region.

[0188] In the second working stage, the fourth gate drive circuit 144342 increases the gate voltage of the switch Q1B in response to the low level, so that the switch Q1B works in the saturation region.

[0189] FIG. 23 is a circuit diagram of another switched capacitor conversion circuit based on the switched capacitor converter in FIG. 4. The switched capacitor conversion circuit shown in FIG. 23 is different from the switched capacitor conversion circuit in FIG. 22 in that the first switches are switches Q2A and Q2B, the output end of the third gate drive circuit 144341 is connected to the gate of the switch Q2A, and the output end of the fourth gate drive circuit 144342 is connected to the gate of the switch Q2B.

[0190] The difference between the working process of the switched capacitor conversion circuit in FIG. 23 and the switched capacitor conversion circuit in FIG. 22 is that the controlled first switches are different, and the other working processes are similar, which will not be described here.

[0191] FIG. 24 is a circuit diagram of another switched capacitor conversion circuit based on the switched capacitor converter in FIG. 4. The switched capacitor conversion circuit shown in FIG. 24 is different from the switched capacitor conversion circuit in FIG. 22 in that the first switches are switches Q5A and Q5B, the output end of the third gate drive circuit 144341 is connected to the gate of the switch Q5A, and the output end of the fourth gate drive circuit 144342 is connected to the gate of the switch Q5B.

[0192] The difference between the working process of the switched capacitor conversion circuit in FIG. 24 and the switched capacitor conversion circuit in FIG. 22 is that the controlled first switches are different, and the other working processes are similar, which will not be described here.

[0193] Figure 25 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 4. The switched-capacitor conversion circuit shown in Figure 25 differs from the switched-capacitor conversion circuit in Figure 22 in that the first switches are switches Q8A, Q8B, the output terminal of the third gate drive circuit 144341 is connected to the gate of switch Q8A, and the output terminal of the fourth gate drive circuit 144342 is connected to the gate of switch Q8B.

[0194] The difference between the operation of the switched-capacitor conversion circuit in Figure 25 and the switched-capacitor conversion circuit in Figure 22 is that the first switches controlled are different, and the other operation processes are similar, which will not be described here.

[0195] Figure 26 is a circuit diagram of a switched-capacitor conversion circuit based on the switched-capacitor converter in Figure 7. As shown in Figure 26, the switched-capacitor conversion circuit can include the switched-capacitor converter shown in Figure 7, a loop compensation circuit, a sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage, and a load R. The first switches include switches Q1A, Q1B. The load R is connected between the output terminal VOUT of the switched-capacitor conversion circuit and the ground GND.

[0196] The input terminal of the switched-capacitor converter is connected to the input terminal VIN of the switched-capacitor conversion circuit, the output terminal of the switched-capacitor converter is connected to the output terminal VOUT of the switched-capacitor conversion circuit, and the specific structure of the switched-capacitor converter has been described above and will not be described here.

[0197] The structure of the loop compensation circuit differs from the loop compensation circuit in Figure 21 in that the connection relationship between the positive input terminal and the negative input terminal of the third operational amplifier 14433 is different, which will be described below.

[0198] The sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage can include a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a sixth operational amplifier OP6, wherein:

[0199] The first resistor R1 and the second resistor R2 are connected in series and then connected between the input end of the switched capacitor converter and the positive input end of the sixth operational amplifier OP6, the third resistor R3 is connected between the connection point of the first resistor R1 and the second resistor R2 and the ground GND, the fourth resistor R4 is connected between the output end VOUT of the switched capacitor conversion circuit and the negative input end of the sixth operational amplifier OP6, the fifth resistor R5 is connected between the negative input end of the sixth operational amplifier OP6 and the ground GND, and the sixth resistor R6 is connected between the positive input end of the sixth operational amplifier OP6 and the output end of the sixth operational amplifier OP6. The output end of the sixth operational amplifier OP6 is connected with the positive input end of the third operational amplifier 14433, and the negative input end of the third operational amplifier 14433 is used to receive the first limit value VDROP_REG_REF. The sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage is used to collect the difference between the input voltage and the output voltage to obtain the first value VDROP_SNS, and transmit the first value VDROP_SNS to the positive input end of the third operational amplifier 14433.

[0200] It can be known in combination with the above that, in the process of voltage conversion of the switched capacitor converter, the sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage collects the difference between the input voltage and the output voltage to obtain the first value VDROP_SNS. When the first value VDROP_SNS is greater than the first limit value VDROP_REG_REF, the third operational amplifier 14433 outputs a high level (i.e. the first control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342.

[0201] In the first working phase, the third gate drive circuit 144341 reduces the gate voltage of the switch Q1A in response to the high level, so that the switch Q1A works in the variable resistance region and increases the on-resistance of the switch Q1A, to bear part of the mutation of the first value VDROP_SNS relative to the first limit value VDROP_REG_REF through the increase of the on-resistance, so as to stabilize the first value VDROP_SNS at the first limit value VDROP_REG_REF, avoid the fluctuation of the input voltage being transmitted to the output end, and ensure the stability of the output.

[0202] In the second working stage, the fourth gate drive circuit 144342 lowers the gate voltage of the switch Q1B in response to the high level, so that the switch Q1B works in the variable resistance region and the on-resistance of the switch Q1B increases, to partially bear the mutation of the first value VDROP SNS relative to the first limit value VDROP REG REF through the increase of the on-resistance, to stabilize the first value VDROP SNS at the first limit value VDROP REG REF, avoid the fluctuation of the input voltage being transmitted to the output, and ensure the stability of the output.

[0203] In the process of voltage conversion of the switched capacitor converter, the sampling circuit 14424 corresponding to the difference between the input voltage and the output voltage collects the difference between the input voltage and the output voltage to obtain the first value VDROP SNS. The third operational amplifier 14433 outputs a low level (i.e. the second control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342 when the first value VDROP SNS is less than or equal to the first limit value VDROP REG REF.

[0204] In the first working stage, the third gate drive circuit 144341 raises the gate voltage of the switch Q1A in response to the low level, so that the switch Q1A works in the saturation region.

[0205] In the second working stage, the fourth gate drive circuit 144342 raises the gate voltage of the switch Q1B in response to the low level, so that the switch Q1B works in the saturation region.

[0206] FIG. 27 is a circuit diagram of another switched capacitor conversion circuit based on the switched capacitor converter in FIG. 7. The switched capacitor conversion circuit shown in FIG. 27 is different from the switched capacitor conversion circuit in FIG. 26 in that the first switches are switches Q2A and Q2B, the output end of the third gate drive circuit 144341 is connected to the gate of the switch Q2A, and the output end of the fourth gate drive circuit 144342 is connected to the gate of the switch Q2B.

[0207] The difference between the working process of the switched capacitor conversion circuit in FIG. 27 and the switched capacitor conversion circuit in FIG. 26 is that the controlled first switches are different, and the other working processes are similar, which will not be described here.

[0208] FIG. 28 is a circuit diagram of still another switched capacitor conversion circuit based on the switched capacitor converter in FIG. 7. The switched capacitor conversion circuit shown in FIG. 28 is different from the switched capacitor conversion circuit in FIG. 26 in that the first switches are switches Q3A and Q3B, the output end of the third gate drive circuit 144341 is connected to the gate of the switch Q3A, and the output end of the fourth gate drive circuit 144342 is connected to the gate of the switch Q3B.

[0209] The difference between the operation process of the switched-capacitor conversion circuit in FIG. 28 and the switched-capacitor conversion circuit in FIG. 26 is that the first switch controlled is different, and other operation processes are similar, which will not be described here.

[0210] FIG. 29 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in FIG. 7. The difference between the switched-capacitor conversion circuit shown in FIG. 29 and the switched-capacitor conversion circuit in FIG. 26 is that the first switch is switch Q4A, switch Q4B, the output terminal of the third gate drive circuit 144341 is connected to the gate of switch Q4A, and the output terminal of the fourth gate drive circuit 144342 is connected to the gate of switch Q4B.

[0211] The difference between the operation process of the switched-capacitor conversion circuit in FIG. 29 and the switched-capacitor conversion circuit in FIG. 26 is that the first switch controlled is different, and other operation processes are similar, which will not be described here.

[0212] FIG. 30 is a circuit diagram of a switched-capacitor conversion circuit based on the switched-capacitor converter in FIG. 10. As shown in FIG. 30, the switched-capacitor conversion circuit can include the switched-capacitor converter shown in FIG. 10, a loop compensation circuit, an input current corresponding sampling circuit 14421, and a load R. The first switch includes switch Q1A and Q1B. The load R is connected between the output terminal VOUT of the switched-capacitor conversion circuit and the ground GND.

[0213] The input terminal of the switched-capacitor conversion circuit is connected to the input terminal VIN of the switched-capacitor conversion circuit, the output terminal of the switched-capacitor conversion circuit is connected to the output terminal VOUT of the switched-capacitor conversion circuit, and the specific structure of the switched-capacitor conversion circuit has been described above and will not be described here.

[0214] The structure of the loop compensation circuit is different from that of the loop compensation circuit in FIG. 21 in that the positive input terminal of the third operational amplifier 14433 is connected to the output terminal of the input current corresponding sampling circuit 14421. The negative input terminal of the third operational amplifier 14433 is used to receive the first limit value IBUS_REG_REF.

[0215] The input terminal of the input current corresponding sampling circuit 14421 is connected to the input terminal VIN of the switched-capacitor conversion circuit.

[0216] The input current corresponding sampling circuit 14421 is used to collect the input current to obtain the first value IBUS_SNS and transmit the first value IBUS_SNS to the positive input terminal of the third operational amplifier 14433.

[0217] In combination with the above, during the voltage conversion of the switch capacitor converter, the sampling circuit 14421 corresponding to the input current collects the input current to obtain the first value IBUS SNS. When the first value IBUS SNS is greater than the first limit value IBUS REG REF, the third operational amplifier 14433 outputs a high level (i.e., a first control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342.

[0218] In the first working phase, the third gate drive circuit 144341 lowers the gate voltage of the switch Q1A in response to the high level, so that the switch Q1A works in the variable resistance region and the on-resistance of the switch Q1A is increased, to partially bear the mutation of the first value IBUS SNS relative to the first limit value IBUS REG REF through the increase of the on-resistance, so as to stabilize the first value IBUS SNS at the first limit value IBUS REG REF, avoiding the transmission of the fluctuation of the input voltage to the output end, and ensuring the stability of the output.

[0219] In the second working phase, the fourth gate drive circuit 144342 lowers the gate voltage of the switch Q1B in response to the high level, so that the switch Q1B works in the variable resistance region and the on-resistance of the switch Q1B is increased, to partially bear the mutation of the first value IBUS SNS relative to the first limit value IBUS REG REF through the increase of the on-resistance, so as to stabilize the first value IBUS SNS at the first limit value IBUS REG REF, avoiding the transmission of the fluctuation of the input voltage to the output end, and ensuring the stability of the output.

[0220] In combination with the above, during the voltage conversion of the switch capacitor converter, the sampling circuit 14421 corresponding to the input current collects the input current to obtain the first value IBUS SNS. When the first value IBUS SNS is greater than the first limit value IBUS REG REF, the third operational amplifier 14433 outputs a high level (i.e., a first control signal) to the third gate drive circuit 144341 and the fourth gate drive circuit 144342.

[0221] In the first working phase, the third gate drive circuit 144341 lowers the gate voltage of the switch Q1A in response to the high level, so that the switch Q1A works in the variable resistance region and the on-resistance of the switch Q1A is increased, to partially bear the mutation of the first value IBUS SNS relative to the first limit value IBUS REG REF through the increase of the on-resistance, so as to stabilize the first value IBUS SNS at the first limit value IBUS REG REF, avoiding the transmission of the fluctuation of the input voltage to the output end, and ensuring the stability of the output.

[0222] In the second working phase, the fourth gate drive circuit 144342 lowers the gate voltage of the switch Q1B in response to the high level, so that the switch Q1B works in the variable resistance region and the on-resistance of the switch Q1B is increased, to partially bear the mutation of the first value IBUS SNS relative to the first limit value IBUS REG REF through the increase of the on-resistance, so as to stabilize the first value IBUS SNS at the first limit value IBUS REG REF, avoiding the transmission of the fluctuation of the input voltage to the output end, and ensuring the stability of the output.

[0223] Fig. 31 is a circuit diagram of another switched-capacitor conversion circuit based on the switched-capacitor converter in Fig. 10. The switched-capacitor conversion circuit shown in Fig. 31 differs from the switched-capacitor conversion circuit in Fig. 30 in that the first switches are switches Q2A, Q2B, the output terminal of the third gate drive circuit 144341 is connected to the gate of switch Q2A, and the output terminal of the fourth gate drive circuit 144342 is connected to the gate of switch Q2B.

[0224] The difference between the working process of the switched-capacitor conversion circuit in Fig. 31 and the switched-capacitor conversion circuit in Fig. 30 is that the first switches controlled are different, and the other working processes are similar, which will not be described here.

[0225] Fig. 32 is a circuit diagram of yet another switched-capacitor conversion circuit based on the switched-capacitor converter in Fig. 10. The switched-capacitor conversion circuit shown in Fig. 32 differs from the switched-capacitor conversion circuit in Fig. 30 in that the first switches are switches Q5A, Q5B, the output terminal of the third gate drive circuit 144341 is connected to the gate of switch Q5A, and the output terminal of the fourth gate drive circuit 144342 is connected to the gate of switch Q5B.

[0226] The difference between the working process of the switched-capacitor conversion circuit in Fig. 32 and the switched-capacitor conversion circuit in Fig. 30 is that the first switches controlled are different, and the other working processes are similar, which will not be described here.

[0227] In some embodiments, the present application also provides a switched-capacitor conversion circuit, which differs from the switched-capacitor conversion circuit in the above in that the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip.

[0228] Obviously, since the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip, compared with being distributed on different chips, the number of pins and the area of the switched-capacitor conversion circuit are reduced, the cost is low, and packaging is easy. In addition, since the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit need to be connected through metal traces on a PCB when they are distributed on different chips, the traces are long and have high loss, while in the present application, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip, and the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are connected through internal traces in the chip, reducing the traces and reducing the loss. It should be noted that the present application also has the same effect as the switched-capacitor conversion circuit in the above, which will not be described here.

[0229] In some embodiments, the application also provides a switched-capacitor conversion circuit, which is different from the switched-capacitor conversion circuit above in that the switched-capacitor conversion circuit further comprises a power switch.

[0230] The input terminal of the switched-capacitor converter is connected to the input terminal of the switched-capacitor conversion circuit through the power switch. The power switch can be a MOSFET or a BJT, and the embodiments of the application do not make special limitations on this.

[0231] The power switch is used to be turned on when the switched-capacitor converter performs voltage conversion, so as to transmit the input voltage to the input terminal of the switched-capacitor converter.

[0232] Based on this, the first switch is specifically one or more of the power switch and the switch in the switched-capacitor converter that is currently in the on state and has adjustable on resistance.

[0233] For example, the first switch can be understood as at least the following three cases:

[0234] First, the first switch can be a switch in the switched-capacitor converter that is currently in the on state and has adjustable on resistance. Since the first case has been described above, it will not be repeated here.

[0235] Second, the first switch is the power switch.

[0236] Next, taking the power switch as an example, the switched-capacitor conversion circuit is exemplarily described.

[0237] FIG. 33 is a circuit schematic diagram of a switched-capacitor conversion circuit comprising a first power switch. As shown in FIG. 33, the switched-capacitor conversion circuit can comprise a power switch QD, a switched-capacitor converter 1441, four sampling circuits, a loop compensation circuit, a battery BAT (i.e., a load), and a low-side sampling resistor RSENSE.

[0238] The first switch is the power switch QD, which is an N-type MOSFET. The circuit parameters include the input current, the output current, the output voltage, and the difference between the input voltage and the output voltage.

[0239] The output terminal VOUT of the switched-capacitor conversion circuit is connected to the positive electrode of the battery BAT, and the low-side sampling resistor RSENSE is connected between the negative electrode of the battery BAT and the ground GND.

[0240] The input terminal Vin1 of the switched-capacitor converter 1441 is connected to the input terminal VIN of the switched-capacitor conversion circuit, the output terminal Vout1 of the switched-capacitor converter 1441 is connected to the output terminal VOUT of the switched-capacitor conversion circuit, and the specific structure of the switched-capacitor converter 1441 has been described above and will not be repeated here.

[0241] The source of the power switch QD is connected with the input end Vin1 of the switched-capacitor converter 1441, the drain of the power switch QD is connected with the input end VIN of the switched-capacitor converter, and the gate of the power switch QD is used for receiving the driving signal GD.

[0242] The loop compensation circuit is different from the loop compensation circuit in FIG. 19 in that the structure of the first driving circuit 14432 is different. In FIG. 33, the input end of the first driving circuit 14432 is connected with the output end of the second operational amplifier 14431, and the output end of the first driving circuit 14432 is connected with the gate of the power switch QD.

[0243] The four sampling circuits are similar to the four sampling circuits in FIG. 19, which will not be described here again.

[0244] It can be known from the above that in the process of voltage conversion of the switched-capacitor converter, the four sampling circuits collect the corresponding circuit parameters to obtain four first values. When it is determined by the four first operational amplifiers (CF1-CF4), the four diodes (D1-D4), and the second operational amplifier 14431 that at least one of the four first values is greater than the corresponding first limit value, the second operational amplifier 14431 outputs a low level (i.e., the first control signal) to the first driving circuit 14432.

[0245] The first driving circuit 14432 reduces the gate voltage (i.e., the voltage of the driving signal GD) of the power switch QD in response to the low level, so that the power switch QD works in the variable resistance region and the on-resistance of the power switch QD is increased, so as to bear the mutation of the first value relative to the corresponding first limit value by the increase of the on-resistance, so as to stabilize the first value at the corresponding first limit value, avoid the fluctuation of the input voltage being transmitted to the output end, and ensure the stability of the output.

[0246] In the process of voltage conversion of the switched-capacitor converter, the four sampling circuits collect the corresponding circuit parameters to obtain four first values. When it is determined by the four first operational amplifiers (CF1-CF4), the four diodes (D1-D4), and the second operational amplifier 14431 that each of the four first values is less than or equal to the corresponding first limit value, the second operational amplifier 14431 outputs a high level (i.e., the second control signal) to the first driving circuit 14432.

[0247] The first driving circuit 14432 increases the gate voltage of the power switch QD in response to the high level, so that the power switch QD works in the saturation region.

[0248] Based on this, as shown in FIG. 34, before t1, there is fluctuation in the input voltage, and the fluctuation continues to increase over time, and the first value IBUS_SNS (i.e., the input current collected) also continues to increase, and before t1, the first value IBUS_SNS is less than or equal to the first limit value IBUS_REG_REF, so before t1, in combination with the drive signal GD, the power switch QD works in the saturation region, and the output voltage is approximately half of the input voltage, and the output voltage is stable.

[0249] At t1, the fluctuation in the input voltage continues to increase, so that the first value IBUS_SNS also continues to increase, and the first value IBUS_SNS is greater than the first limit value IBUS_REG_REF. At this time, the voltage at the control end of the power switch QD (i.e., the voltage of the drive signal GD) is reduced, so that the power switch QD works in the variable resistance region and increases the on-resistance of the power switch QD, so that the on-resistance is increased to partially bear the sudden change of the first value IBUS_SNS relative to the first limit value IBUS_REG_REF, and the first value IBUS_SNS is stabilized at the first limit value IBUS_REG_REF, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0250] From t1 to t2, the fluctuation in the input voltage first continues to increase and then decreases, and the first value IBUS_SNS is greater than the first limit value IBUS_REG_REF. Therefore, by reducing the voltage at the control end of the power switch QD, the power switch QD works in the variable resistance region and increases the on-resistance of the power switch QD, so that the on-resistance is increased to partially bear the sudden change of the first value IBUS_SNS relative to the first limit value IBUS_REG_REF, and the first value IBUS_SNS is stabilized at the first limit value IBUS_REG_REF, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output.

[0251] At t2 and after t2, the input voltage first continues to decrease and then tends to be stable, so that the first value IBUS_SNS first decreases and then tends to be stable, and the first value IBUS_SNS is less than or equal to the first limit value IBUS_REG_REF. At this time, by increasing the control voltage of the power switch QD, the power switch QD works in the saturation region, and the on-resistance of the power switch QD is reduced, thereby reducing the power consumption of the circuit and stabilizing the output.

[0252] The third, the first switch is a power switch and the second switch. Among them, the second switch is a switch in the switch capacitor converter which is currently in the on state and the on resistance of which is adjustable.

[0253] It should be noted that, in the case where the first switch is a power switch and the second switch, the working principle of the switched-capacitor conversion circuit is the same as above, and will not be repeated here.

[0254] Obviously, since each sampling circuit 1442 in the one or more sampling circuits is capable of sampling the circuit parameter to obtain a first value corresponding to the circuit parameter. Therefore, in the process of voltage conversion by the switched-capacitor converter 1441, when there is fluctuation in the input voltage, the first value collected by each sampling circuit 1442 in the one or more sampling circuits also carries the fluctuation information of the input voltage. In this way, when the fluctuation of the input voltage causes the first value to exceed the corresponding first limit value, the loop compensation circuit 1443 adjusts the voltage at the control end of the first switch (i.e., one or more of the power switch and the switch in the switched-capacitor converter 1441 that is currently in the on state and has an adjustable on resistance) to make the first switch work in the variable resistance region and increase the on resistance of the first switch, so as to partially bear the sudden change of the first value relative to the corresponding first limit value by increasing the on resistance, so as to stabilize each first value at the corresponding first limit value, avoiding the fluctuation of the input voltage being transmitted to the output end, and ensuring the stability of the output. In addition, since the first switch is one or more of the power switch and the switch in the switched-capacitor converter 1441 that is currently in the on state and has an adjustable on resistance, more ways are provided for the selection of the first switch. Furthermore, since the switched-capacitor converter 1441 is capable of converting the input voltage to the output voltage, the transformation of the voltage is realized. In addition, in the case where the first switch is the switch in the switched-capacitor converter that is currently in the on state and has an adjustable on resistance, since the first switch reuses the switch in the switched-capacitor converter, the area and cost of the circuit are reduced.

[0255] In some embodiments, the present application also provides a switched-capacitor conversion circuit, which is different from the above-mentioned switched-capacitor conversion circuit including a power switch in that the power switch, the switched-capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on the same chip.

[0256] Obviously, since the power switch, the switched-capacitor converter, the one or more sampling circuits and the loop compensation circuit are integrated on the same chip, compared with being distributed on different chips, pins and the area of the switched-capacitor converter are reduced, the cost is low, and packaging is easy. In addition, since when the power switch, the switched-capacitor converter, the one or more sampling circuits and the loop compensation circuit are distributed on different chips, the power switch, the switched-capacitor converter, the one or more sampling circuits and the loop compensation circuit need to be connected through metal traces on a PCB, the traces are long and the loss is high, while in the embodiment of the application, the power switch, the switched-capacitor converter, the one or more sampling circuits and the loop compensation circuit are integrated on the same chip, and the power switch, the switched-capacitor converter, the one or more sampling circuits and the loop compensation circuit are connected through internal traces in the chip, reducing the traces and reducing the loss.

[0257] It should be noted that the embodiment of the application also has the same effect as the switched-capacitor conversion circuit including the power switch described above, which will not be described here.

[0258] The embodiment of the application also provides a power supply device, which includes the switched-capacitor conversion circuit provided by any of the above embodiments.

[0259] The power supply device provided by the embodiment of the application can be a charger or a transformer, etc., or other power supply devices capable of voltage conversion, which is not specifically limited by the embodiment of the application.

[0260] The power supply device provided by the embodiment of the application includes the switched-capacitor conversion circuit provided by any of the above embodiments, has the same functional modules and beneficial effects as the switched-capacitor conversion circuit, which will not be described here.

[0261] The embodiment of the application also provides a chip, which includes the switched-capacitor conversion circuit provided by any of the above embodiments.

[0262] Exemplarily, integrating the switched-capacitor conversion circuit provided by any of the above embodiments into a chip can reduce the volume of the switched-capacitor conversion circuit, which is conducive to the miniaturization development of the switched-capacitor conversion circuit.

[0263] The chip provided by the embodiment of the application includes the switched-capacitor conversion circuit provided by any of the above embodiments, has the same functional modules and beneficial effects as the switched-capacitor conversion circuit, which will not be described here.

[0264] The electronic device includes the switch-capacitor conversion circuit or the chip provided by any of the above embodiments. The switch-capacitor conversion circuit or the chip is used for voltage conversion in the electronic device. The converted voltage can be used as a charging voltage of a battery, a power supply voltage of other elements in the electronic device, or the like, which is not specially limited in the embodiments of the present application. The electronic device includes, but is not limited to, a notebook computer, a netbook, a mobile phone, a tablet computer, an electronic reader, and the like.

[0265] The above disclosure is only specific embodiments of the present application, but the embodiments of the present application are not limited thereto. Any changes that can be thought of by those skilled in the art shall fall within the protection scope of the present application.

[0266] The "comprising" described in the present application does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" before the element does not exclude the presence of multiple such elements. The present application can be implemented by means of hardware including several distinct elements, and by means of a suitably programmed computer. In a claim enumerating several means, those means can be embodied by one and the same item of hardware. The use of the terms "first", "second", and "third", etc. do not denote any order. These terms can be construed to be terms of name. The steps in the above embodiments should not be understood as a limitation on the order of execution, unless otherwise specified.

[0267] The above description and the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features. The modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A switched capacitor conversion circuit, characterized in that: include: a switched capacitor converter, having an input end connected to the input end of the switched capacitor conversion circuit and an output end connected to the output end of the switched capacitor conversion circuit, for converting an input voltage into an output voltage; One or more sampling circuits, corresponding one to one with one or more circuit parameters, wherein each of the one or more sampling circuits is configured to collect the circuit parameter to obtain a first value corresponding to the circuit parameter; wherein the first value corresponds to a first limit value; a loop compensation circuit, configured to adjust the voltage of the control terminal of the first switch when the first value is greater than the corresponding first limit value, so as to make the first switch operate in a variable resistance region and increase the on-resistance of the first switch; The first switch is a switch in the switched capacitor converter that is currently in an on state and whose on-resistance is adjustable.

2. The switched capacitor conversion circuit according to claim 1, wherein: The switched capacitor converter, the one or more sampling circuits, and the loop compensation circuit are integrated on a same chip.

3. The switched capacitor conversion circuit according to claim 1, wherein: The switched capacitor conversion circuit further includes: a power switch; The input end of the switched capacitor converter is connected to the input end of the switched capacitor conversion circuit through the power switch; The power switch is configured to be turned on when the switched capacitor converter performs voltage conversion, so that the input voltage is transmitted to the input terminal of the switched capacitor converter; The first switch is one or more switches in the power switch and the switched capacitor converter that are currently in an on state and whose on-resistance is adjustable.

4. The switched capacitor conversion circuit according to claim 3, wherein: The power switch, the switched capacitor converter, the one or more sampling circuits and the loop compensation circuit are integrated on a same chip.

5. The switched capacitor converter circuit according to any one of claims 1 to 4, characterized in that: The loop compensation circuit is further configured to adjust the voltage at the control terminal of the first switch so that the first switch operates in a first operating range when the first value is less than or equal to the corresponding first limit value; Wherein, when the first switch is a metal-oxide semiconductor field effect transistor, the first working region is a saturation region; when the first switch is a bipolar transistor, the first working region is an amplification region.

6. The switched capacitor conversion circuit according to claim 5, wherein: The one or more circuit parameters include a plurality of circuit parameters, and the one or more first values ​​include a plurality of first values; The loop compensation circuit includes: a plurality of first operational amplifiers, a plurality of diodes, a second operational amplifier and a first driving circuit, wherein: The plurality of first operational amplifiers correspond one-to-one to the plurality of diodes, and the plurality of first operational amplifiers correspond one-to-one to the plurality of first values; A positive input terminal of a first operational amplifier among the plurality of first operational amplifiers is used to receive the first numerical value corresponding to the first operational amplifier, a negative input terminal of the first operational amplifier is used to receive the first limit value corresponding to the first numerical value corresponding to the first operational amplifier, and an output terminal of the first operational amplifier is connected to the anode of the diode corresponding to the first operational amplifier; The cathodes of the plurality of diodes are connected to the inverting input terminal of the second operational amplifier, the positive input terminal of the second operational amplifier is used to receive the second limit value, the output terminal of the second operational amplifier is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is connected to the control terminal of the first switch; The plurality of first operational amplifiers, the plurality of diodes, and the second operational amplifier are configured to output a first control signal when at least one of the one or more first values ​​is greater than the corresponding first limit value, or to output a second control signal when each of the one or more first values ​​is less than or equal to the corresponding first limit value; The first drive circuit is configured to adjust the voltage at the control terminal of the first switch in response to the first control signal, so that the first switch operates in the variable resistance region and increases the on-resistance of the first switch, or, in response to the second control signal, adjust the voltage at the control terminal of the first switch so that the first switch operates in the first operating region.

7. The switched capacitor conversion circuit according to claim 5, wherein: The one or more circuit parameters include a circuit parameter, and the one or more first values ​​include a first value; The loop compensation circuit includes: a third operational amplifier and a second driving circuit, wherein: The positive input terminal of the third operational amplifier is used to receive the first value, the negative input terminal of the third operational amplifier is used to receive the first limit value corresponding to the first value, the output terminal of the third operational amplifier is connected to the input terminal of the second drive circuit, and the output terminal of the second drive circuit is connected to the control terminal of the first switch; The third operational amplifier is configured to output a first control signal when the first value is greater than the corresponding first limit value, or output a second control signal when the first value is less than or equal to the first limit value; The second drive circuit is used to adjust the voltage of the control terminal of the first switch in response to the first control signal, so that the first switch operates in the variable resistance region and increases the on-resistance of the first switch, and, in response to the second control signal, adjust the voltage of the control terminal of the first switch so that the first switch operates in the first operating region.

8. The switched capacitor converter circuit according to any one of claims 1 to 4 or 6 to 7, characterized in that: The one or more circuit parameters include one or more of an input current, an output current, an output voltage, and a difference between an input voltage and an output voltage.

9. The switched capacitor conversion circuit according to claim 8, wherein: The sampling circuit corresponding to the output current includes: a fourth operational amplifier, wherein: The positive input terminal of the fourth operational amplifier is connected to the high voltage terminal of the low-side sampling resistor, the negative input terminal of the fourth operational amplifier is connected to the low voltage terminal of the low-side sampling resistor, and the output terminal of the fourth operational amplifier is used to output the first value corresponding to the output current; The low-side sampling resistor and the load are connected in series and then connected between the output end of the switch capacitor conversion circuit and the ground.

10. The switched capacitor conversion circuit according to claim 8, wherein: The sampling circuit corresponding to the output voltage includes: a fifth operational amplifier, wherein: The positive input terminal of the fifth operational amplifier is connected to the output terminal of the switched capacitor conversion circuit, the negative input terminal of the fifth operational amplifier is connected to the low voltage terminal of the load, and the output terminal of the fifth operational amplifier is used to output the first value corresponding to the output voltage; The load is connected between the output terminal of the switch capacitor conversion circuit and the ground.

11. The switched capacitor conversion circuit according to claim 8, wherein: The sampling circuit corresponding to the difference between the input voltage and the output voltage includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a sixth operational amplifier, wherein: The first resistor and the second resistor are connected in series and connected between the input terminal of the switched capacitor converter and the positive input terminal of the sixth operational amplifier. The third resistor is connected between the connection point of the first resistor and the second resistor and the ground. The fourth resistor is connected between the output terminal of the switched capacitor conversion circuit and the reverse input terminal of the sixth operational amplifier. The fifth resistor is connected between the reverse input terminal of the sixth operational amplifier and the ground. The sixth resistor is connected between the positive input terminal of the sixth operational amplifier and the output terminal of the sixth operational amplifier. The output terminal of the sixth operational amplifier is used to output the first numerical value corresponding to the difference between the input voltage and the output voltage.

12. The switched capacitor converter circuit according to any one of claims 1 to 4, 6 to 7, or 9 to 11, characterized in that: In the case where the switch in the switched capacitor converter is a metal-oxide semiconductor field effect transistor, the switch is a switch in which the body diode is in an off state; In a case where the switch in the switched capacitor converter is a bipolar transistor, the switch is a switch in the switched capacitor converter that is currently in an on state.

13. A power supply device, characterized in that: A switched capacitor conversion circuit is included; The switched capacitor conversion circuit comprises: a switched capacitor converter, having an input end connected to the input end of the switched capacitor conversion circuit and an output end connected to the output end of the switched capacitor conversion circuit, for converting an input voltage into an output voltage; One or more sampling circuits, corresponding one to one with one or more circuit parameters, wherein each of the one or more sampling circuits is configured to collect the circuit parameter to obtain a first value corresponding to the circuit parameter; wherein the first value corresponds to a first limit value; a loop compensation circuit, configured to adjust the voltage of the control terminal of the first switch when the first value is greater than the corresponding first limit value, so as to make the first switch operate in a variable resistance region and increase the on-resistance of the first switch; The first switch is a switch in the switched capacitor converter that is currently in an on state and whose on-resistance is adjustable.

14. The power supply device according to claim 13, characterized in that: The switched capacitor conversion circuit further includes: a power switch; The input end of the switched capacitor converter is connected to the input end of the switched capacitor conversion circuit through the power switch; The power switch is configured to be turned on when the switched capacitor converter performs voltage conversion, so that the input voltage is transmitted to the input terminal of the switched capacitor converter; The first switch is one or more switches in the power switch and the switched capacitor converter that are currently in an on state and whose on-resistance is adjustable.

15. The power supply device according to claim 13, characterized in that: The one or more circuit parameters include a plurality of circuit parameters, and the one or more first values ​​include a plurality of first values; The loop compensation circuit includes: a plurality of first operational amplifiers, a plurality of diodes, a second operational amplifier and a first driving circuit, wherein: The plurality of first operational amplifiers correspond one-to-one to the plurality of diodes, and the plurality of first operational amplifiers correspond one-to-one to the plurality of first values; A positive input terminal of a first operational amplifier among the plurality of first operational amplifiers is used to receive the first numerical value corresponding to the first operational amplifier, a negative input terminal of the first operational amplifier is used to receive the first limit value corresponding to the first numerical value corresponding to the first operational amplifier, and an output terminal of the first operational amplifier is connected to the anode of the diode corresponding to the first operational amplifier; The cathodes of the plurality of diodes are connected to the inverting input terminal of the second operational amplifier, the positive input terminal of the second operational amplifier is used to receive the second limit value, the output terminal of the second operational amplifier is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is connected to the control terminal of the first switch; The plurality of first operational amplifiers, the plurality of diodes, and the second operational amplifier are configured to output a first control signal when at least one of the one or more first values ​​is greater than the corresponding first limit value, or to output a second control signal when each of the one or more first values ​​is less than or equal to the corresponding first limit value; The first drive circuit is configured to adjust the voltage at the control terminal of the first switch in response to the first control signal, so that the first switch operates in the variable resistance region and increases the on-resistance of the first switch, or, in response to the second control signal, adjust the voltage at the control terminal of the first switch so that the first switch operates in the first operating region.

16. A chip, characterized in that: A switched capacitor conversion circuit is included; The switched capacitor conversion circuit comprises: a switched capacitor converter, having an input end connected to the input end of the switched capacitor conversion circuit and an output end connected to the output end of the switched capacitor conversion circuit, for converting an input voltage into an output voltage; One or more sampling circuits, corresponding one to one with one or more circuit parameters, wherein each of the one or more sampling circuits is configured to collect the circuit parameter to obtain a first value corresponding to the circuit parameter; wherein the first value corresponds to a first limit value; a loop compensation circuit, configured to adjust the voltage of the control terminal of the first switch when the first value is greater than the corresponding first limit value, so as to make the first switch operate in a variable resistance region and increase the on-resistance of the first switch; The first switch is a switch in the switched capacitor converter that is currently in an on state and whose on-resistance is adjustable.

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