Structured support for an energy storage micro-device

Abstract

A structured support for an energy storage micro-device, comprising: - a substrate; - micro-pillars disposed on one face of the substrate, each micro-pillar having a free surface; - nano-wires, said nano-wires being disposed on the free surface of at least a portion of the micro-pillars, and said face of the substrate being devoid of nano-wires.

Description

[0001] DESCRIPTION

[0002] TITLE: Architectural support for micro-energy storage device

[0003] Technical field

[0004] The present invention relates to an architectural support for a micro-energy storage device, a micro-energy storage device comprising said architectural support, and a method of manufacturing said architectural support.

[0005] State of the prior art

[0006] Miniaturized energy storage devices, also called micro energy storage devices or integrated energy storage devices, such as microbatteries, microcapacitors or microsupercapacitors, are electronic components with a small physical size.

[0007] Such miniaturization is essential in the current development of electronic devices, in particular those known as embedded, portable or smart, such as for example integrated circuits, implantable or portable medical devices, smartphones, tablets, smartwatches, navigation systems, laptops, sensors, in particular embedded, connected objects, in particular of the loT type (for Internet of Things in English), and practically any equipment requiring compact integrated circuits and increasingly smaller electronic devices.

[0008] The current development of miniaturized energy storage devices faces various problems.

[0009] First, due to their reduced surface area, micro-energy storage devices generally have a reduced energy density.

[0010] It is therefore essential to find solutions to increase energy density (i.e. the amount of energy that a micro-energy storage device can provide in a given space) in order to maintain high electrical performance in a small format, and to do so sustainably.

[0011] Furthermore, with the reduction in their dimensions, mechanical and thermal constraints can have a greater impact on the reliability and longevity of micro energy storage devices.

[0012] It is therefore necessary to develop more reliable and safer micro-energy storage devices, particularly those free from the risk of short circuits, explosions or leaks, especially when used in implantable medical devices or other critical applications.

[0013] Furthermore, manufacturing micro energy storage devices with high precision and high electrical performance can be difficult and expensive.

[0014] Manufacturing processes for micro-energy storage devices must therefore be adapted to avoid defects and guarantee consistent performance, while having reduced costs.

[0015] The invention aims to further improve micro-energy storage devices, in particular by improving their electrical performance, reliability, safety and manufacturing.

[0016] Statement of the invention

[0017] Architectural support for micro-energy storage devices

[0018] The invention thus relates, according to a first of its aspects, to an architectural support for a micro-energy storage device comprising:

[0019] - a substrate,

[0020] - micro-pillars arranged on one side of the substrate, each micro-pillar having a free surface,

[0021] - nanowires, said nanowires being arranged on the free surface of at least part of the micro-pillars.

[0022] The term “architectural support” means a support comprising a structure of its surface, i.e. surface structures, such as for example the presence of microstructures and / or nanostructures, in particular micro-pillars and / or nano-wires, in comparison with a support without structure of its surface, generally called a “planar or two-dimensional (2D) support”.

[0023] In the case where the architectural support would only comprise micro-pillars as surface structures (i.e. absence of nano-wires), the architectural support would be a so-called three-dimensional (3D) architectural support.

[0024] The architectural support according to the invention comprises both micro-pillars and nano-wires as surface structures. It is therefore a so-called four-dimensional (4D) architectural support.

[0025] The architectural support according to the invention is particularly advantageous insofar as the latter develops a large surface area, compared to a flat (2D) or three-dimensional (3D) support, due to the presence of the micro-pillars, on the one hand, and the presence of the nano-wires, on the other hand. Indeed, compared to a flat (2D) support, a three-dimensional (3D) architectural support makes it possible to increase the surface area developed by the support by a gain factor of between 10 and 100, in particular between 40 and 80 (the gain factor is also called “AEF” for Area Enlargement Factored). This gain factor is explained by the presence of the micro-pillars.

[0026] Compared to a three-dimensional (3D) architectural support, a four-dimensional (4D) architectural support, such as according to the invention, makes it possible to increase the surface area developed by the support by a gain factor of between 2 and 50, in particular between 5 and 15. This gain factor is explained by the additional presence of the nanowires.

[0027] Said face of the substrate may be devoid of nanowires.

[0028] This characteristic according to which said face of the substrate can be devoid of nano-wires can make it possible to simplify the manufacturing process of the support, in particular by eliminating a lithography step, and without significantly reducing the surface area developed by the support.

[0029] Indeed, the presence of nanowires on the face of the substrate only contributes marginally to the surface area developed by the support, in comparison with the nanowires arranged on the free surface of at least part of the micro-pillars.

[0030] Furthermore, when the support has nanowires on the face of the substrate, these nanowires present a risk of breakage, in particular when the support is used for the manufacture of a micro-energy storage device.

[0031] For example, the deposition of resin on the nanowires arranged on the face of the substrate during a lithography step can lead to damage or even breakage of these nanowires.

[0032] This may cause short circuits within the said micro energy storage device in which the medium is or will be integrated.

[0033] The characteristic according to which said face of the substrate can be devoid of nanowires can thus make it possible to limit, or even eliminate, this risk of short circuit, and thus improve the safety and reliability of said micro-energy storage device in which the support is or will be integrated.

[0034] The nanowires can be arranged on the free surface of each of the micro-pillars.

[0035] The nanowires can be arranged over the entire free surface of at least part of the micro-pillars, in particular over the entire free surface of each of the micro-pillars.

[0036] Alternatively, the nanowires are arranged only on a portion of the free surface of at least a portion of the micro-pillars, in particular only on a portion of the free surface of each of the micro-pillars. Each micro-pillar may comprise an upper face and one or more lateral faces.

[0037] The side face(s) are preferably substantially perpendicular to the face of the substrate.

[0038] The upper face is preferably substantially parallel to the face of the substrate.

[0039] In an exemplary embodiment, the nanowires are arranged only on the lateral face(s) of at least part of the micro-pillars, in particular only on the lateral face(s) of each of the micro-pillars.

[0040] This therefore means that, in this embodiment, the upper faces of the micro-pillars are devoid of nano-wires.

[0041] This can simplify the support manufacturing process, in particular by eliminating a lithography step, without significantly reducing the surface area developed by the support.

[0042] Indeed, the presence of nanowires on the upper faces of the micro-pillars only contributes marginally to the surface area developed by the support, in comparison with the nanowires arranged on the lateral faces of the micro-pillars.

[0043] Furthermore, when the support has nanowires on the upper faces of the micro-pillars, these nanowires present a risk of breakage, in particular when the support is used for the manufacture of a micro-energy storage device.

[0044] For example, the deposition of resin on the nanowires arranged on the upper faces of the micro-pillars during a lithography step can lead to damage, or even breakage, of these nanowires.

[0045] This may cause short circuits within the said micro energy storage device in which the medium is or will be integrated.

[0046] The characteristic according to which the nanowires can be arranged only on the lateral face(s) of at least part of the micro-pillars, in particular only on the lateral face(s) of each of the micro-pillars, can thus make it possible to limit, or even eliminate, this risk of short circuit, and thus improve the safety and reliability of said micro-energy storage device in which the support is or will be integrated.

[0047] Micro-pillars

[0048] In an exemplary embodiment, each micro-pillar is solid, in particular over all or part of its height. In an exemplary embodiment, each micro-pillar is hollow, in particular over all or part of its height. The presence of such micro-pillars can make it possible to further increase the surface area developed by the support.

[0049] Each micro-pillar may have a proximal end connected to the face of the substrate and a distal end.

[0050] In an exemplary embodiment, each micro-pillar is hollow over part of its height, in particular at its distal end.

[0051] In an exemplary embodiment, each micro-pillar comprises a first solid part which is connected to the face of the substrate and which continues with a second hollow part. The presence of such micro-pillars can make it possible to further increase the surface area developed by the support.

[0052] Preferably, each micro-pillar has an elongated shape.

[0053] Preferably, each micro-pillar extends from the face of the substrate, in particular in a rectilinear manner, in particular in a manner substantially perpendicular to the face of the substrate.

[0054] Each micro-pillar may have a cylindrical, conical, truncated cone or any other shape, preferably cylindrical.

[0055] The term "cylindrical shape" refers to any type of cylinder such as a right circular cylinder, a square cylinder, or a rectangular cylinder.

[0056] In an exemplary embodiment, each micro-pillar comprises a first cylindrical part which is connected to the face of the substrate and which continues with a second conical or truncated conical part.

[0057] Each micro-pillar may have a circular, elliptical or polygonal cross-section, for example triangular, square, rectangular, pentagonal, hexagonal, cross-shaped, star-shaped, etc.

[0058] In an exemplary embodiment, each micro-pillar has a circular cross-section, for example with a diameter of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

[0059] In an exemplary embodiment, each micro-pillar has a triangular, square or rectangular cross-section, for example with sides each having a length of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

[0060] In a preferred embodiment, each micro-pillar has a square-shaped cross-section, for example with sides each having a length of between 2 μm and 6 μm, in particular between 3 μm and 5 μm. A square-shaped cross-section can make it possible to maximize the lateral surface area developed by the micro-pillars, and thus maximize the surface area developed by the support.

[0061] In a preferred embodiment, each micro-pillar has a cylindrical shape and has a square or rectangular cross-section, preferably square, with, for example, sides each having a length of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

[0062] In this preferred embodiment, each micro-pillar has a top face and four side faces.

[0063] In this embodiment, the nanowires are arranged only on the lateral faces of at least a portion of the micropillars, in particular of each of the micropillars. Thus, in this preferred embodiment, the upper faces of the micropillars are devoid of nanowires.

[0064] Each micro-pillar can have a cross-section with a surface area of ​​between 2 pm 2 and 40 pm 2 , preferably between 4 pm 2 and 36 pm 2, and more preferably between 9 pm 2 and 25 pm 2 .

[0065] Each micro-pillar may have a length greater than or equal to 10 pm, preferably greater than or equal to 20 pm, more preferably greater than or equal to 30 pm, and even more preferably greater than or equal to 40 pm.

[0066] The terms "length" and "height" are equivalent.

[0067] Each micro-pillar may have a length less than or equal to 400 pm, preferably less than or equal to 350 pm, more preferably less than or equal to 300 pm, and even more preferably less than or equal to 250 pm.

[0068] Each micro-pillar may have a length ranging from 10 pm to 400 pm, preferably ranging from 20 pm to 350 pm, more preferably ranging from 30 pm to 300 pm, and even more preferably ranging from 40 pm to 250 pm.

[0069] In an exemplary embodiment, each micro-pillar has a length greater than 200 pm, preferably greater than 200 pm and less than or equal to 350 pm, more preferably greater than 200 pm and less than or equal to 300 pm, even more preferably greater than 200 pm and less than or equal to 250 pm.

[0070] The micro-pillars can be arranged on the face of the substrate in rows, in particular each rectilinear, in particular parallel to each other.

[0071] In an exemplary embodiment, each row of micro-pillars comprises a space between two adjacent micro-pillars whose length is between 2 pm and 6 pm, in particular between 3 pm and 5 pm. In an exemplary embodiment, two adjacent rows of micro-pillars are separated by a distance between 0 pm and 6 pm, in particular between 0 pm and 5 pm, or even between 1 and 5 pm.

[0072] In an exemplary embodiment, two adjacent rows of micro-pillars are arranged in a staggered pattern.

[0073] In a preferred embodiment, the substrate and the micro-pillars are formed as a single piece. This feature has the following advantages:

[0074] - provides improved mechanical resistance due to better cohesion of the support,

[0075] - avoids the risk of cracking or detachment of the micro-pillars. Indeed, the micro-pillars are “hollowed” into the substrate and are thus laterally protected (see figures 1 and 2) significantly increases the reliability and lifespan of a device comprising such an architectural support simplifies the manufacturing process and contributes to improving its reproducibility on an industrial scale.

[0076] For example, micro-pillars are obtained by a deep reactive ion etching technique (also called DRIE for Deep Reactive Ion Etching in English) of a wafer, for example made of silicon.

[0077] The substrate and the micro-pillars may comprise, or even be made of, a material suitable for microfabrication techniques, particularly for microelectronics.

[0078] The substrate and the micro-pillars may comprise, or even be made of, a semiconductor material or an insulating material, in particular a dielectric.

[0079] The substrate and micro-pillars may comprise, or even be made of, a ceramic material.

[0080] The substrate and the micro-pillars comprise, or are made of, silicon (Si), silica (SiC>2), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), silicon nitride (SisN4) and / or indium phosphide (InP), preferably silicon (Si).

[0081] Nano-wires

[0082] Each nanowire can contain a metal oxide or a mixture of metal oxides.

[0083] For example, each nanowire comprises silica (SiO2), zinc oxide (ZnO), titanium dioxide (TiO2), indium oxide (I n2O3), gallium oxide (Ga20s), bismuth oxide (Bi20s) and / or tin dioxide (SnC>2), preferably silica (SiC>2), zinc oxide (ZnO) and / or titanium dioxide (TiC>2), more preferably silica (SiC>2) and / or zinc oxide (ZnO), and even more preferably silica (SiO2).

[0084] Each nanowire may further comprise a metal or metal alloy, preferably capable of being deposited by an atomic layer deposition technique (also known as an ALD technique for Atomic Layer Deposition in English).

[0085] For example, each nanowire comprises platinum (Pt), gold (Au), silver (Ag), aluminum (Al) and / or gallium (Ga), preferably platinum (Pt), gold (Au) and / or silver (Ag), and more preferably platinum (Pt).

[0086] Preferably, each nanowire comprises silica (SiO2), and in particular platinum (Pt).

[0087] In an exemplary embodiment, each nanowire is made of silica (SiO2) and platinum (Pt).

[0088] Each nanowire may have a proximal end, a distal end, and a body connecting the proximal end to the distal end.

[0089] The body can be full.

[0090] The body may have an elongated shape, particularly a cylindrical shape.

[0091] The body may have a curved shape.

[0092] The body may have a circular or elliptical cross-section, preferably circular.

[0093] The proximal end can be connected to the free surface of a micro-pillar.

[0094] The distal end may have a convex shape, including a spherical shape, for example a sphere, half-sphere, or portion-sphere shape.

[0095] The body may comprise, or even consist of, a metal oxide or a mixture of metal oxides, preferably capable of being deposited by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by a low-pressure chemical vapor deposition technique (also called LPCVD technique for Low Pressure Chemical Vapor Deposition in English) or by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0096] For example, the body comprises, or is even made up of, silica (SiO2), zinc oxide (ZnO), titanium dioxide (TiO2), indium oxide (I n2O3), gallium oxide (Ga2Os), bismuth oxide (Bi2Os) and / or tin dioxide (SnO2), preferably silica (SiO2), zinc oxide (ZnO) and / or titanium dioxide (TiO2), more preferably silica (SiC>2) and / or zinc oxide (ZnO), and even more preferably silica (SiC>2).

[0097] In a preferred embodiment, the body comprises, or is even made of, silica (SiC>2).

[0098] The proximal end may comprise, or even consist of, a metal oxide or a mixture of metal oxides.

[0099] For example, the proximal end comprises, or is made of, silica (SiC>2), zinc oxide (ZnO), titanium dioxide (TiO2), indium oxide (I n2O3), gallium oxide (Ga2Os), bismuth oxide (Bi2Os) and / or tin dioxide (SnO2), preferably silica (SiO2), zinc oxide (ZnO) and / or titanium dioxide (TiO2), more preferably silica (SiO2) and / or zinc oxide (ZnO), and even more preferably silica (SiO2).

[0100] In a preferred embodiment, the proximal end comprises, or is made of, silica (SiO2).

[0101] The distal end may comprise, or even be made of, a metal or a metal alloy, preferably capable of being deposited by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0102] For example, the distal end comprises, or is made of, platinum (Pt), gold (Au), silver (Ag), aluminum (Al) and / or gallium (Ga), preferably platinum (Pt), gold (Au) and / or silver (Ag), and more preferably platinum (Pt).

[0103] In a preferred embodiment, the distal end comprises, or is made of, platinum (Pt).

[0104] Each nanowire may have a length greater than or equal to 100 nm, preferably greater than or equal to 200 nm, more preferably greater than or equal to 300 nm, even more preferably greater than or equal to 400 nm, and in particular greater than or equal to 500 nm.

[0105] In an exemplary embodiment, each nanowire has a length greater than or equal to 1 pm.

[0106] Each nanowire may have a length less than or equal to 10 pm, preferably less than or equal to 9 pm, more preferably less than or equal to 8 pm, even more preferably less than or equal to 7 pm, and in particular less than or equal to 6 pm.

[0107] In an exemplary embodiment, each nanowire has a length less than or equal to 5 pm. Each nanowire may have a length ranging from 100 nm to 10 pm, preferably ranging from 200 nm to 9 pm, more preferably ranging from 300 nm to 8 pm, even more preferably ranging from 400 nm to 7 pm, and in particular ranging from 500 nm to 6 pm.

[0108] In an exemplary embodiment, each nanowire has a length ranging from 1 pm to 5 pm.

[0109] Each nanowire may have a cross-section whose largest dimension is greater than or equal to 20 nm, preferably greater than or equal to 30 nm, more preferably greater than or equal to 40 nm, and even more preferably greater than or equal to 50 nm.

[0110] Each nanowire may have a cross-section whose largest dimension is less than or equal to 250 nm, preferably less than or equal to 240 nm, more preferably less than or equal to 230 nm, even more preferably less than or equal to 220 nm, and in particular less than or equal to 210 nm.

[0111] Each nanowire may have a cross-section whose largest dimension is between 20 nm and 250 nm, preferably between 30 nm and 240 nm, more preferably between 40 nm and 230 nm, and even more preferably between 50 nm and 220 nm.

[0112] In an exemplary embodiment, each nanowire has a cross-section whose largest dimension is between 20 nm and 200 nm, and preferably between 30 nm and 190 nm.

[0113] The density of nanowires can be between 10 million nanowires / mm 2 and 50 million nanowires / mm 2 , preferably between 10 million nanowires / mm 2 and 40 million nanowires / mm 2 , more preferably between 10 million nano-wires / mm 2 and 30 million nanowires / mm 2 , and even more preferably between 10 million nanowires / mm 2 and 25 million nanowires / mm 2 .

[0114] Such a density of nanowires is particularly advantageous insofar as it can allow particularly high gains to be obtained in terms of surface area developed by the support.

[0115] Each nanowire can be oriented randomly.

[0116] Nanowires can be entangled.

[0117] Each nanowire may comprise a first part which is connected to the free surface of a micro-pillar and which is rectilinear and orthogonal to said free surface, this first part continuing with a second part which is curved. Support

[0118] The support may comprise at least one layer of an electronically conductive material, in particular metallic.

[0119] The layer of electronically conductive material may be arranged on the nanowires and micro-pillars of the architectural support, in particular may surround or cover each nanowire and each micro-pillar, in particular may surround or cover the proximal end, the distal end and the body of each nanowire and the free surface of each micro-pillar.

[0120] The layer of electronically conductive material can form a current collector, in particular of a battery, or an electrode, in particular of a capacitor.

[0121] Preferably, the electronically conductive material is a material that can be deposited by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0122] The electronically conductive material may comprise, or even consist of, a metal, in particular a transition metal, or a metal alloy, in particular of transition metals.

[0123] For example, the electronically conductive material comprises, or is even made up of, platinum (Pt), gold (Au), silver (Ag), copper (Cu) or one of their mixtures, and preferably platinum (Pt).

[0124] The layer of electronically conductive material may have a thickness of between 10 and 50 nm, preferably between 15 nm and 45 nm, more preferably between 20 nm and 40 nm.

[0125] The layer of electronically conductive material can be deposited by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0126] The layer of electronically conductive material may be in direct contact with the nanowires and micropillars of the architectural support, in particular in direct contact with the proximal end, the distal end and the body of each nanowire and in direct contact with the free surface of each micropillar.

[0127] The support may further comprise at least one protective layer, in particular a thermal layer. The protective layer may be arranged on the nanowires and micropillars of the architectural support, in particular may surround or cover each nanowire and each micropillar, in particular may surround or cover the proximal end, the distal end and the body of each nanowire and the free surface of each micropillar.

[0128] The layer of electronically conductive material can be arranged on the protective layer.

[0129] The protective layer can cover the nanowires and micropillars of the architectural support.

[0130] The layer of electronically conductive material may cover or surround the protective layer.

[0131] The protective layer can be in direct contact with the nanowires and micropillars of the architectural support and in direct contact with the layer of electronically conductive material.

[0132] The protective layer can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0133] The protective layer may have a thickness ranging from 10 nm to 80 nm, preferably ranging from 20 nm to 70 nm, more preferably ranging from 30 nm to 60 nm, and even more preferably ranging from 35 nm to 55 nm.

[0134] The protective layer may include, or even be made of, an insulating material.

[0135] For example, the insulating material is a material that can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0136] The insulating material is preferably a ceramic material.

[0137] The insulating material may include, or even consist of, a metal oxide or a mixture of metal oxides.

[0138] For example, the insulating material contains, or is even made of, alumina (AI2O3).

[0139] The protective layer may protect the architectural support against high temperatures, in particular greater than or equal to 400°C, preferably greater than or equal to 500°C, more preferably greater than or equal to 600°C, and even more preferably greater than or equal to 700°C. Such temperature values ​​may be necessary, for example, to form on the architectural support a layer of a mixed metal oxide (e.g., LiNi0.5Mni.5O4 or BaTiOs) by ALD from several layers of different materials (e.g., MnO2, NiO and LiOH for LiNi0.sMni.sC; BaO and TiC>2 for BaTiOs), in particular deposited sequentially. Such heat treatments are crystallization annealings.

[0140] However, exposing the architectural support to such temperature values ​​may, for example, alter the structure and / or composition of the architectural support.

[0141] For example, exposure of the architectural support to such temperature values ​​can cause the diffusion of platinum (Pt) from the nanowires into the silicon (Si) of the micro-pillars and / or the substrate, thus forming a non-conductive SiPt alloy.

[0142] Thus, when the architectural support is exposed to such temperature values, the structure and / or composition of the architectural support can be preserved thanks to the presence of the protective layer.

[0143] The face of the substrate may have a square or rectangular shape, in particular with sides each having a length of between 50 pm and 20 mm, preferably between 100 pm and 2.5 mm.

[0144] The face of the substrate may have a surface area of ​​between 2500 pm 2 and 400 mm 2 , preferably between 10000 pm 2 and 6.25 mm 2 .

[0145] Such surface values ​​correspond to the face of the substrate without micro-pillars and nano-wires.

[0146] The micro energy storage device may be a microbattery, a microcapacitor, a microsupercapacitor or a hybrid device.

[0147] By “hybrid device” is meant a device comprising at least one battery electrode and at least one capacitor or supercapacitor electrode.

[0148] The micro-battery is preferably a solid-state micro-battery.

[0149] The micro-battery is preferably a lithium-ion (Li-ion) micro-battery.

[0150] The lithium-ion (Li-ion) micro-battery may include a positive electrode active material of the LMNO (Lithium Nickel Manganese Oxide) type.

[0151] The microcapacitor is preferably a metal-insulator-metal (MIM) microcapacitor.

[0152] Micro-device for energy storage comprising an architectural support The invention also relates, according to another of its aspects, to a micro-device for energy storage comprising an architectural support as defined above.

[0153] The micro energy storage device may be a microbattery, a microcapacitor, a microsupercapacitor or a hybrid device.

[0154] By “hybrid device” is meant a device comprising at least one battery electrode and at least one capacitor or supercapacitor electrode.

[0155] The micro-battery is preferably a solid-state micro-battery.

[0156] The micro-battery is preferably a lithium-ion (Li-ion) micro-battery.

[0157] The lithium-ion (Li-ion) micro-battery may include a positive electrode active material of the LMNO (Lithium Nickel Manganese Oxide) type.

[0158] The microcapacitor is preferably a metal-insulator-metal (MIM) microcapacitor.

[0159] The micro-device may comprise at least one layer of an electronically conductive material, in particular metallic.

[0160] The layer of electronically conductive material can be arranged on the architectural support, in particular covering the architectural support.

[0161] In particular, the layer of electronically conductive material may be arranged on the nanowires and micropillars of the architectural support, in particular may surround or cover each nanowire and each micropillar, in particular may surround or cover the proximal end, the distal end and the body of each nanowire and the free surface of each micropillar.

[0162] The layer of electronically conductive material can form a current collector, in particular of a battery, or an electrode, in particular of a capacitor.

[0163] Preferably, the electronically conductive material is a material that can be deposited by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0164] The electronically conductive material may comprise, or even consist of, a metal, in particular a transition metal, or a metal alloy, in particular of transition metals.

[0165] For example, the electronically conductive material comprises, or is made of, platinum (Pt), gold (Au), silver (Ag), copper (Cu) or a mixture thereof, and preferably platinum (Pt). The layer of electronically conductive material may have a thickness of between 10 and 50 nm, preferably between 15 nm and 45 nm, more preferably between 20 nm and 40 nm.

[0166] The layer of electronically conductive material can be deposited by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0167] The layer of electronically conductive material may be in direct contact with the architectural support, in particular in direct contact with the nanowires and micropillars of the architectural support, in particular in direct contact with the proximal end, the distal end and the body of each nanowire and in direct contact with the free surface of each micropillar.

[0168] The micro-device may also include at least one protective layer, in particular thermal.

[0169] The protective layer can be placed on the architectural support, in particular covering the architectural support.

[0170] In particular, the protective layer may be arranged on the nanowires and micropillars of the architectural support, in particular may surround or cover each nanowire and each micropillar, in particular may surround or cover the proximal end, the distal end and the body of each nanowire and the free surface of each micropillar, the nanowires and micropillars of the architectural support, in particular may surround or cover each nanowire and each micropillar, in particular may surround or cover the proximal end, the distal end and the body of each nanowire and the free surface of each micropillar.

[0171] The layer of electronically conductive material can be arranged on the protective layer.

[0172] The layer of electronically conductive material may cover or surround the protective layer.

[0173] The protective layer may be in direct contact with the architectural support, in particular in direct contact with the nanowires and micropillars of the architectural support, in particular in direct contact with the proximal end, the distal end and the body of each nanowire and in direct contact with the free surface of each micropillar.

[0174] The protective layer can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0175] The protective layer may have a thickness ranging from 10 nm to 80 nm, preferably ranging from 20 nm to 70 nm, more preferably ranging from 30 nm to 60 nm, and even more preferably ranging from 35 nm to 55 nm.

[0176] The protective layer may include, or even be made of, an insulating material.

[0177] For example, the insulating material is a material that can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0178] The insulating material is preferably a ceramic material.

[0179] The insulating material may include, or even consist of, a metal oxide or a mixture of metal oxides.

[0180] For example, the insulating material contains, or is even made of, alumina (AI2O3).

[0181] The protective layer can protect the architectural support against high temperatures, in particular greater than or equal to 400°C, preferably greater than or equal to 500°C, more preferably greater than or equal to 600°C, and even more preferably greater than or equal to 700°C.

[0182] Such temperature values ​​may be necessary, for example, to form a layer of a mixed metal oxide (e.g., LiNi0.5Mni,5O4 or BaTiOs) on the structured support by ALD from several layers of different materials (e.g., MnO2, NiO and LiOH for LiNi0.5Mni,5O4; BaO and TiC>2 for BaTiOs), in particular deposited sequentially. Such heat treatments are crystallization annealing.

[0183] However, exposing the architectural support to such temperature values ​​may, for example, alter the structure and / or composition of the architectural support.

[0184] For example, exposure of the architectural support to such temperature values ​​can cause the diffusion of platinum (Pt) from the nanowires into the silicon (Si) of the micro-pillars and / or the substrate, thus forming a non-conductive SiPt alloy.

[0185] Thus, when the architectural support is exposed to such temperature values, the structure and / or composition of the architectural support can be preserved thanks to the presence of the protective layer. Method of manufacturing an architectural support

[0186] The invention also relates, according to another of its aspects, to a method for manufacturing an architectural support as defined above, comprising at least the following steps: a) etching a wafer comprising a semiconductor or insulating material, in particular a dielectric material, whereby an architectural support is obtained comprising a substrate and micro-pillars arranged on one face of the substrate; b) deposition on the architectural support obtained in step a) of a layer of a material comprising a metal oxide or a mixture of metal oxides; c) deposition on the architectural support obtained in step b) of a layer of a material comprising a metal or a metal alloy; d) etching the layer of material comprising a metal or a metal alloy obtained in step c); then f) thermal annealing.

[0187] Step a) can be implemented using a deep reactive ion etching (DRIE) technique.

[0188] For example, the deep reactive ion etching technique is implemented using an “OXFORD Estrelas PlasmaLab Pro 100” reactor.

[0189] Step a) may be preceded by a lithography step, in particular photolithography.

[0190] The lithography step can be implemented using a resin, in particular a positive one, such as for example the “SPR220-7pm” resin.

[0191] For example, the lithography step is implemented using a resist thickness ranging from 6 pm to 9 pm, including a thickness of about 7.5 pm.

[0192] The lithography step may be preceded by a wafer cleaning step.

[0193] Step a) can be followed by a step of removing the resin used during the lithography step.

[0194] Step b) may be implemented by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by a low pressure chemical vapor deposition technique (also called LPCVD technique for Low Pressure Chemical Vapor Deposition in English) or by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English), and more preferably by a low pressure chemical vapor deposition technique (also called LPCVD technique for Low Pressure Chemical Vapor Deposition in English).

[0195] The layer of material comprising a metal oxide or a mixture of metal oxides may comprise, or even consist of, silica (SiO2), zinc oxide (ZnO), titanium dioxide (TiC>2), indium oxide (ln2C>3), gallium oxide (Ga2Os), bismuth oxide (Bi2Os) and / or tin dioxide (SnC>2), preferably silica (SiC>2), zinc oxide (ZnO) and / or titanium dioxide (TiO2), more preferably silica (SiO2) and / or zinc oxide (ZnO), and even more preferably silica (SiO2).

[0196] The layer of material comprising a metal oxide or a mixture of metal oxides may have a thickness ranging from 5 nm to 25 nm, preferably ranging from 10 nm to 20 nm, for example a thickness of approximately 15 nm.

[0197] The thickness of the material layer containing a metal oxide or a mixture of metal oxides can influence the length of the nanowires.

[0198] Step b) may be preceded by a step of cleaning the architectural support obtained in step a).

[0199] Step c) can be implemented by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0200] The layer of material comprising a metal or a metal alloy may comprise, or even consist of, platinum (Pt), gold (Au), silver (Ag), aluminum (Al) and / or gallium (Ga), preferably platinum (Pt), gold (Au) and / or silver (Ag), and more preferably platinum (Pt).

[0201] The layer of material comprising a metal or a metal alloy may have a thickness ranging from 5 nm to 25 nm, preferably ranging from 10 nm to 20 nm, for example a thickness of approximately 15 nm.

[0202] The thickness of the material layer containing a metal or metal alloy can influence the density and thickness of the nanowires.

[0203] For example, step c) is implemented by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English), for example at a temperature between 150°C and 550°C, preferably between 200°C and 500°C, more preferably between 200°C and 450°C, even more preferably between 200°C and 400°C, and in particular between 250°C and 350°C, using: at least one gas, preferably ozone (O3), and - at least one precursor, preferably a precursor comprising a metal, more preferably a precursor comprising platinum.

[0204] Preferably, the precursor is chosen from:

[0205] - trimethyl(methylcyclopentadienyl)platinum(IV) (MeCpPtMes),

[0206] - dimethyl(cyclooctadiene)platinum(ll) (Me2 tCOD), and

[0207] - one of their blends.

[0208] More preferably, the precursor is trimethyl(methylcyclopentadienyl)platinum(IV) (MeCpPtMes).

[0209] Step d) can be carried out using a reactive ion beam etching (RIBE) technique.

[0210] For example, the reactive ion beam etching technique is implemented using a "Meyer Burger lonSys 500" device.

[0211] For example, the reactive ion beam etching technique is implemented at a speed between 5 nm / min and 15 nm / min, preferably between 8 nm / min and 12 nm / min, more preferably between 9 nm / min and 11 nm / min, and in particular at an angle of 0°.

[0212] Step f) can be carried out in a rapid thermal annealing (RTA) furnace, in particular using temperature rise and fall rates of the order of 10°C / sec.

[0213] Step f) can be implemented with a first temperature level, in particular at 1000°C.

[0214] For example, the first stage lasts 1 minute, and is carried out under nitrogen.

[0215] Step f) can be implemented with a second temperature level, in particular at 1100°C, following the first temperature level.

[0216] For example, the second stage lasts 5 minutes, and is carried out under nitrogen.

[0217] The first temperature step may allow the layer of material comprising a metal or a metal alloy to pass from the solid state to the liquid state, so as to form drops of material comprising a metal or a metal alloy on the layer of material comprising a metal oxide or a mixture of metal oxides.

[0218] The second temperature step can allow the evaporation of the layer of material comprising a metal oxide or a mixture of metal oxides, and thus the growth of the nanowires.

[0219] The first temperature step can influence the density and thickness of the nanowires. The second step can influence the length of the nanowires.

[0220] The method according to the invention is particularly advantageous insofar as it does not require a lithography step after step c) and before step d). This makes it possible to simplify the manufacturing process while improving the mechanical resistance of the architectural support.

[0221] Indeed, thanks to the elimination of such a lithography step, the face of the substrate, and in particular the upper faces of the micro-pillars, are free of nano-wires.

[0222] The removal of these nanowires, which presented a risk of damage or even breakage, can thus improve the reliability and safety of the architectural support, without significantly reducing its developed surface area.

[0223] Brief description of the figures

[0224] Figure 1 A) illustrates a silicon substrate intended for the production of the architectural support according to the invention.

[0225] Figure 1 B) represents the step of deposition and exposure under UV of a photosensitive resin on the flat silicon substrate, allowing the subsequent definition of the micropillars by etching the substrate.

[0226] Figure 1 C) represents the successive steps of etching the silicon by the Bosch process, followed by the removal of the photosensitive resin by oxygen plasma cleaning (O2), resulting in a substrate comprising a plurality of micro-pillars extending from one face of said substrate.

[0227] Figure 1 D) represents an image obtained by scanning electron microscopy (SEM) showing a perspective view of a set of substantially parallel micro-pillars formed on the substrate by an etching technique (e.g. DRIE). This image shows the regular spatial distribution of the micro-pillars down to the base of the substrate.

[0228] Figure 2 A) illustrates the step of covering the architectural substrate: by a thin layer of silicon oxide (SiO2) obtained by low pressure chemical vapor deposition (LPCVD) or by atomic layer deposition (ALD) then, by a layer of platinum (Pt) deposited by ALD, covering the face of the substrate and the micro-pillars.

[0229] Figure 2 B) represents the platinum etching step by reactive ion etching (RIE), in order to remove the platinum layer present on the surface of the substrate while keeping this layer on the surface of the micro-pillars. Figure 2 C) illustrates the growth step of the SiO2 nanowires according to a vapor-liquid-solid (VLS) growth mechanism on the surface of the platinum-coated micro-pillars, leading to a significant increase in the specific surface area of ​​said micro-pillars.

[0230] Figure 3 A) illustrates a scanning electron microscopy (SEM) image of a set of substantially parallel micropillars, made on a substrate. These micropillars, with a high aspect ratio, are arranged in a regular and periodic manner. Each micropillar appears covered, on its lateral surface, with nanowires extending radially from the surface. The image makes it possible to visualize the homogeneity of the structuring at the microscopic scale, as well as the good distribution of the nanowires over the entire micropillar network.

[0231] Figure 3 B) illustrates a SEM image at a higher magnification than that of Figure 3 A) in close-up view of several micro-pillars from the same structure as that illustrated in Figure 3 A). This detailed view highlights the density and uniformity of the nanowire deposition on the lateral surface of the micro-pillars. The nanowires are oriented in a generally radial manner with respect to the longitudinal axis of the micro-pillars, and form a three-dimensional structure coating considerably increasing the specific surface area. This configuration is particularly suitable for electrochemical devices, such as micro-batteries or micro-supercapacitors.

Claims

CLAIMS 1. Architectural support for micro-energy storage device comprising: - a substrate, - micro-pillars arranged on one side of the substrate, each micro-pillar having a free surface, - nanowires, said nanowires being arranged on the free surface of at least a portion of the micropillars, said face of the substrate being devoid of nanowires, and the substrate and the micropillars being formed in one piece.

2. Architectural support according to claim 1, the nanowires being arranged only on a part of the free surface of at least a part of the micro-pillars.

3. Architectural support according to claim 2, each micro-pillar comprising an upper face and one or more lateral faces, the nano-wires being arranged only on the lateral face(s) of at least part of the micro-pillars.

4. Architectural support according to any one of the preceding claims, each micro-pillar having a cylindrical shape and comprising a cross-section of square or rectangular shape, preferably square, with in particular sides each having a length of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

5. Architectural support according to any one of the preceding claims, each micro-pillar having a length ranging from 10 pm to 400 pm, preferably ranging from 20 pm to 350 pm, more preferably ranging from 30 pm to 300 pm, and even more preferably ranging from 40 pm to 250 pm.

6. Architectural support according to any one of the preceding claims, the micropillars being arranged on the face of the substrate in rows, in particular each rectilinear, in particular parallel to each other.

7. Architectural support according to claim 6, each row of micro-pillars comprising a space between two adjacent micro-pillars whose length is between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

8. Architectural support according to claim 6 or 7, two adjacent rows of micropillars being separated by a distance of between 0 pm and 6 pm, in particular between 0 pm and 5 pm, or even between 1 and 5 pm.

9. Architectural support according to any one of claims 6 to 8, two adjacent rows of micro-pillars being arranged in a staggered pattern.

10. Architectural support according to any one of the preceding claims, the substrate and the micro-pillars comprising, or even being made of, a material suitable for microfabrication techniques, in particular for microelectronics. 1 1. Architectural support according to claim 10, the substrate and the micro-pillars comprising, or even being made of, a semiconductor material or an insulating material, in particular dielectric.

12. Architectural support according to claim 1 1, the substrate and the micro-pillars comprising, or even being made of, silicon (Si), silica (SiC>2), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), silicon nitride (SislX) and / or indium phosphide (InP), preferably silicon (Si).

13. Architectural support according to any one of the preceding claims, each nano-wire comprising a proximal end connected to the free surface of a micro-pillar, a distal end and a body connecting the proximal end to the distal end.

14. Architectural support according to claim 13, the body may have a cylindrical shape and have a cross-section of circular or elliptical shape, preferably circular.

15. Architectural support according to claim 13 or 14, the distal end having a convex shape, in particular spherical.

16. Architectural support according to any one of claims 13 to 15, the body comprising, or even consisting of, a metal oxide or a mixture of metal oxides, preferably capable of being deposited by a chemical vapor deposition technique, preferably by a low-pressure chemical vapor deposition technique or by an atomic layer deposition technique.

17. Architectural support according to claim 16, the body comprising, or even being made of, silica (SiO2), zinc oxide (ZnO), titanium dioxide (TiO2), oxide indium (I^Os), gallium oxide (Ga2Os), bismuth oxide (Bi20s) and / or tin dioxide (SnC>2), preferably silica (SiC>2), zinc oxide (ZnO) and / or titanium dioxide (TiC>2), more preferably silica (SiC>2) and / or zinc oxide (ZnO), and even more preferably silica (SiO2).

18. Architectural support according to any one of claims 13 to 17, the distal end comprising, or even being made of, a metal or a metal alloy, preferably capable of being deposited by an atomic layer deposition technique.

19. Architectural support according to claim 18, the distal end comprising, or even being made of, platinum (Pt), gold (Au), silver (Ag), aluminum (Al) and / or gallium (Ga), preferably platinum (Pt), gold (Au) and / or silver (Ag), and more preferably platinum (Pt).

20. Architectural support according to any one of the preceding claims, each nanowire having a length ranging from 100 nm to 10 pm, preferably ranging from 200 nm to 9 pm, more preferably ranging from 300 nm to 8 pm, even more preferably ranging from 400 nm to 7 pm, and in particular ranging from 500 nm to 6 pm.

21. Architectural support according to any one of the preceding claims, each nanowire having a cross-section whose largest dimension is between 20 nm and 200 nm, and preferably between 30 nm and 190 nm.

22. Architectural support according to any one of the preceding claims, the density of the nano-wires being between 10 million nano-wires / mm 2 and 50 million nanowires / mm 2 , preferably between 10 million nanowires / mm 2 and 40 million nanowires / mm 2 , more preferably between 10 million nano-wires / mm 2and 30 million nanowires / mm 2 , and even more preferably between 10 million nano-wires / mm 2 and 25 million nanowires / mm 2 .

23. Architectural support according to any one of the preceding claims, comprising at least one layer of an electronically conductive material, in particular metallic, said layer of electronically conductive material being arranged on the nano-wires and the micro-pillars of the architectural support.

24. Architectural support according to claim 23, the layer of electronically conductive material having a thickness of between 10 and 50 nm, preferably between 15 nm and 45 nm, more preferably between 20 nm and 40 nm.

25. Architectural support according to claim 23 or 24, comprising at least one protective layer, in particular thermal, said protective layer being arranged on the nano-wires and the micro-pillars of the architectural support, the layer of electronically conductive material being arranged on the protective layer.

26. Architectural support according to claim 25, the layer of insulating material having a thickness ranging from 10 nm to 80 nm, preferably ranging from 20 nm to 70 nm, more preferably ranging from 30 nm to 60 nm, and even more preferably ranging from 35 nm to 55 nm.

27. Architectural support according to any one of the preceding claims, the face of the substrate having a square or rectangular shape, with in particular sides each having a length of between 50 pm and 20 mm, preferably between 100 pm and 2.5 mm.

28. Micro-energy storage device comprising an architectural support according to any one of claims 1 to 27.

29. Micro-device according to claim 28, the energy storage micro-device being: - a micro-battery, in particular a solid-state micro-battery, in particular a lithium-ion micro-battery; - a micro-capacitor, in particular a metal-insulator-metal micro-capacitor; - a micro-supercapacitor; or - a hybrid device.

30. Method for manufacturing an architectural support according to any one of claims 1 to 30, comprising at least the following steps: a) etching a wafer comprising a semiconductor or insulating material, in particular a dielectric material, whereby an architectural support is obtained comprising a substrate and micro-pillars arranged on one face of the substrate; b) depositing on the architectural support obtained in step a) a layer of a material comprising a metal oxide or a mixture of metal oxides; c) depositing on the architectural support obtained in step b) a layer of a material comprising a metal or a metal alloy; d) etching the layer of material comprising a metal or a metal alloy obtained in step c); then f) thermal annealing.

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