Multi-threaded processor with power granularity and thread granularity

Abstract

A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.

Description

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[0017] Figure 1A shows a plurality of per-thread program counters 105 PC_T0 for thread_0, PC_T1 for thread_l, ..., PC_Tn for thread n, such that one program counter is separately operative for use with each thread. PC_T0 contains the current program counter value for thread 0, PC T1 contains the current program counter value for thread 1, etc., and the canonical sequence of thread identifiers from thread map register 103 indicate which thread program counter is to be retrieved.

[0018] Figure IB shows the thread map register 103 of figure 1, which comprises a sequence of thread identifiers TO 130A to Tn 132A executed canonically, and each thread location of thread map register 103 has a corresponding thread map valid register 101 location shown as 130B through 132B of figure IB, indicating whether the associated thread map register location is to be executed (indicated by '1') or not executed (indicated by '0'), such as by conditionally issuing an instruction to retrieve a program counter at prefetch stage 102 of figure 1 based on the corresponding location of the thread map register 101. The number of threads (each thread being a separate process executing in a CPU cycle of a particular stage) is m, limited by the number of register files 118 and program counters 105, and the thread map register 103 may support m threads in n thread map register locations (n>m) for control of the allocation of CPU bandwidth to thread. For greater n with fixed m,increased granularity of thread control is available. For example, a thread map with 16 entries may support 4 threads, each thread having granularity of 1 / 16 of the available CPU processing capacity and supporting anywhere from 0 / 16 to 16 / 16 of the available CPU processing capacity, subject to allocation of CPU processing capacity to the remaining threads.

[0019] Figure 2A shows an example 16 entry thread map register 103 of figure 1 over canonical cycle length 204 of figure 2 (using the length specified by thread map length register 109 of figure 1, the thread map register canonically repeating at the end of each 16 entries for the case where thread map register 109 contains the value 16). Execution of only threads 0 and 1 would occur if thread map register length was changed to 6, executing only thread map register locations 0 to 5 canonically. The present example of figure 2A is shown for 4 threads and sequential mapping, which may be suitable for applications without thread stalls, the case where a thread is unable to execute sequential cycles because of a delay in receiving a result from an external resource, for example. For n=16 thread map length and the values shown in 202A, the thread map register provides l / 16th resolution of processor application to each task. The processor can be used with one thread per thread map register location (number of threads m = number of thread map locations n), however this inflexibly provides a fixed allocation of time to each thread. In a preferred utilization, the number of thread identifiers m is smaller than the number of thread map register locations n, which provides that the allocation of a particular thread to a task may have the granularity p / n, where n is typically fixed and p is programmable as the number of cycles allocated to aparticular thread, and can be varied from 0 to n to allocate more or less computational resource to each thread by reallocating other thread map locations to a desired thread.

[0020] Figure 2A shows an example thread map register for a four thread processor in a 16 position thread map register 202, with threads 0, 1, 2, and 3 (TO, Tl, T2, T3, respectively), and processor capacity allocated to 12.5%, 25%, 50%, and 12.5%, to each respective thread using the thread map valid register 202B which has all thread map locations shown as valid (1) and thread map register length is 16. In this case, the thread execution sequence is as shown, two cycles of TO, four cycles of T2, eight cycles of T3, and two cycles of T3 in a canonical sequence. Thread map valid register 202C shows another example with the same thread map register 202A, where only the first thread identifier of each sequence is occupied, shown as TO Tl T2 T3 over 16 cycles. The advantage of sparse thread map 202C is that the additional execution cycles can be gained by writing additional '1' values only to the thread map valid register, so if a task has predictable load requirements, the thread map register can have thread map allocations which are configured for the high load requirement, and a dynamic adjustment can be made to the thread map valid register to change the number of execution cycles associated with the dynamic load thread without changing the thread map register, the unexecuted cycles resulting in reduced power consumption.

[0021] A problem arises where a particular thread must wait for an external resource to respond, known as a thread stall. In the example of figure 2A, the decode / execute stage 108 of figure 1 may require reading an externalshared memory or media access controller (MAC) not shown, and the delay in reading the external resource may require 4 clock cycles. In the case where the thread allocation 202A is shown in figure 2A and the threads accessing an external resource are TO and T3, or are otherwise subject to delays in reading or writing devices, TO will be in a thread stall at operation 208A, and T3 will be in a thread stall 214 at cycle 210. With the arrangement of thread identifiers shown in figure 2A, this will result in loss of an otherwise available CPU cycle for each thread stall.

[0022] Figure 2C shows an alternative thread map register 222 and thread map valid register 228, where the thread mapping uses the same time allocation of figure 2A, but with the thread sequence 220 rearranged for the same thread stall case as was shown in figure 2A. The rearrangement of TO to positions 0 and 7, and rearrangement of T3 to positions 1 and 8, is reflected in the arrangement of figure 2B. The TO thread is only stalled for thread stalls longer than 6 clock cycles 224, whereas the thread stall 212 is 4 clock cycles, so both occurrences of TO are executed with the arrangement of figure 2B, rather than one in figure 2A. Similarly, the T3 stall which causes the second T3 cycle of figure 2A to be deferred does not occur in figure 2B unless the thread stall has duration 226. A thread map valid register 230 is presented which is analogous to the single cycle thread execution of 202C. Alternatively, a thread stall can be avoided in a repeating sequence of the same thread identifier by writing '0' (not valid) to subsequent same thread identifier locations for a duration of expected latency, saving power over null or NOP instruction cycles of the stall interval.

[0023] In another example of the invention, the thread map register and / or the thread map valid register, or the thread map length register may be interactively changed according to process demands detected by a separate management process. Since the context from each stage is forwarded to a subsequent stage of figure 1, changes to the thread map register may be done at any time, subject to synchronous clocking requirements for the prefetch stage 102 to receive a deterministic threadJD and the associated per-thread program counter 105.

Claims

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12. The multi-thread processor of claim 10 where the corresponding location of the thread map register not be provided to the pre-fetch stage comprises the pre-fetch stage not taking action on the thread identifier.

13. The multi-thread processor of claim 10 where the thread map register, thread map valid register, and thread map length register are programmable registers.14.The multi-thread processor of claim 10 where each location of the thread map register has two or three bits for encoding a thread identifier, and each location of the thread map valid register is a single bit.

15. multi-thread processor comprising: a thread map register having a plurality of locations, each location for the storage of a thread identifier; a thread map valid register having a number of locations equal to a number of locations of the thread map register, each location of the thread map valid register indicating whether a corresponding thread identifier from the thread map register is to be executed or not executed; each thread identifier of the thread map register associated with a program counter register and a register file, the program counter register and register file coupled to at least one of the sequential stages: a prefetch stage, an instruction fetch stage, an instruction decode stage, a decode / execute stage, an execute stage, a load-store stage, and a writeback stage.The multi-thread processor of claim 15 where the corresponding location of the thread map register not executed comprises not delivering the pipeline clock to the pre-fetch stage. The multi-thread processor of claim 15 where the corresponding location of the thread map register not executed comprises the pre-fetch stage not taking action on the thread identifier. The multi-thread processor of claim 15 where the thread map register, thread map valid register, and thread map length register are programmable registers. The multi-thread processor of claim 15 where each location of the thread map register has two or three bits for encoding a thread identifier, and each location of the thread map valid register is a single bit.

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