Silicon-on-insulator semiconductor structure and method for manufacturing same

Abstract

The present invention relates to a silicon-on-insulator semiconductor structure and a method for manufacturing same. The structure comprises a lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor. The LDMOS field-effect transistor comprises: a substrate; a buried dielectric layer located on part of the substrate; a drift region located on the buried dielectric layer; a deep well located in the substrate and at least partially located below the buried dielectric layer; a drain region located above the buried dielectric layer; a source region located above the buried dielectric layer, the drift region being at least partially located between the source region and the drain region; and a gate. The conductivity type of the deep well is opposite to that of the substrate. For an nLDMOS, the drain region thereof is electrically connected to the deep well. For a pLDMOS, the source region thereof is electrically connected to the deep well. According to the present invention, the potential of the deep well having a conductivity type opposite to that of the substrate is led out and connected to the drain region of the nLDMOS / the source region of the pLDMOS, and the substrate is made to participate in vertical voltage withstanding by means of mutual depletion between the deep well and the substrate, thereby improving the breakdown voltage of a device.

Description

Silicon-on-insulator semiconductor structure and manufacturing method thereof TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a silicon-on-insulator semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the wide application of ultra-large scale integrated circuits in various fields, the development of high-voltage high-power semiconductor devices is increasingly required by the system. Silicon carbide devices have many advantages over silicon-based devices and have gradually replaced silicon-based devices in various application scenarios. The wide application of silicon carbide devices has also driven the development of gate drive chips. The traditional isolation method of silicon carbide device drive cannot realize monolithic integration, and faces the problems of size, cost and reliability, so the monolithic integrated gate drive chip is mostly realized based on the bulk silicon high-voltage BCD (Bipolar-CMOS-DMOS) process. However, the junction isolation and low substrate doping concentration between the substrate and the active layer of the bulk silicon device result in poor negative transient voltage resistance, which is not suitable for silicon carbide MOSFET gate drive. Compared with the bulk silicon structure, the silicon-on-insulator (SOI) structure adopts dielectric isolation, which completely isolates the electrical connection between the active layer and the substrate, so that the SOI device has advantages in latch-up resistance, anti-device crosstalk and integration density. The dielectric isolation feature makes it have stronger negative transient voltage resistance, so the SOI-based high-voltage gate drive chip can drive the silicon carbide device.

[0003] However, the conventional silicon-on-insulator integrated high-voltage device is difficult to achieve a breakdown voltage of 1200V and above. SUMMARY

[0004] Therefore, it is necessary to provide a silicon-on-insulator semiconductor structure with high breakdown voltage and a manufacturing method thereof.

[0005] A silicon-on-insulator semiconductor structure, comprising a lateral double-diffused metal-oxide-semiconductor field-effect transistor, the lateral double-diffused metal-oxide-semiconductor field-effect transistor comprising: a substrate; a buried dielectric layer on part of the substrate; a drift region on the buried dielectric layer; a deep well, the deep well being in the substrate and at least part of the deep well being below the buried dielectric layer; a drain region above the buried dielectric layer; a source region above the buried dielectric layer, the drift region being at least partially between the source region and the drain region; a gate; wherein the deep well is opposite in conductivity type to the substrate; the lateral double-diffused metal-oxide-semiconductor field-effect transistor comprises a NLDMOS and / or a PLDMOS; for the NLDMOS, its drain region is electrically connected to the deep well, and its drift region, source region and drain region have the same conductivity type; for the PLDMOS, its source region is electrically connected to the deep well, and its drift region, source region and drain region have the same conductivity type.

[0006] The silicon-on-insulator semiconductor structure described above, the potential of the deep well opposite in conductivity type to the substrate is led out and connected to the drain region of the NLDMOS / the source region of the PLDMOS, the substrate is made to participate in the vertical voltage resistance through mutual depletion of the deep well and the substrate, thereby improving the breakdown voltage of the device.

[0007] In one of the embodiments, for the NLDMOS, its source region is electrically connected to the substrate; for the PLDMOS, its drain region is electrically connected to the substrate.

[0008] In one of the embodiments, the lateral double-diffused metal-oxide-semiconductor field-effect transistor comprises a NLDMOS and a PLDMOS, the drift region in the NLDMOS is an N-type drift region, the drift region in the PLDMOS is a P-type drift region; the source region and the drain region in the NLDMOS are N-type regions, the source region and the drain region in the PLDMOS are P-type regions; the deep well is a deep N-well, and the substrate is a P-type substrate; the NLDMOS further comprises a P-type buried layer at least partially below the buried dielectric layer, the source region is electrically connected to the P-type buried layer, and the doping concentration of the P-type buried layer is greater than the doping concentration of the substrate.

[0009] In one of the embodiments, the SOI semiconductor structure further comprises: a junction termination region; a first isolation trench structure comprising insulating material disposed in a first trench, the first trench being a closed loop structure, the junction termination region, the N-type drift region and the P-type drift region being located outside the first trench, a bottom of the insulating material in the first trench being connected to the buried dielectric layer; a second isolation trench structure comprising insulating material disposed in a second trench, the second trench being a closed loop structure, the junction termination region, the N-type drift region and the P-type drift region being located inside the second trench, a bottom of the insulating material in the second trench being connected to the buried dielectric layer; an N-type region located inside the first trench, a portion of a top of the deep N-well being connected to a bottom of the N-type region, so as to be led out through the N-type region and electrically connected to a drain region of the NLDMOS and a source region of the PLDMOS; a P-type region located outside the second trench, a portion of a top of the substrate and a portion of a top of the P-type buried layer being connected to a bottom of the P-type region, so as to be led out through the P-type region and electrically connected to a source region of the NLDMOS and a drain region of the PLDMOS; wherein the drain region of the NLDMOS is disposed close to the first trench, and the source region of the NLDMOS is disposed close to the second trench, the drain region of the PLDMOS is disposed close to the second trench, and the source region of the PLDMOS is disposed close to the first trench.

[0010] In one of the embodiments, the SOI semiconductor structure further comprises an isolation structure located on two sides of the NLDMOS and on two sides of the PLDMOS, the isolation structure having insulating material, a first end of the isolation structure being in direct contact with the first isolation trench structure, a second end of the isolation structure being in direct contact with the second isolation trench structure, and a bottom of the isolation structure being in direct contact with the buried dielectric layer.

[0011] In one of the embodiments, the NLDMOS further comprises: a P-type body region located at a first side of the N-type drift region; an N-well located at a second side of the N-type drift region; wherein the source region of the NLDMOS is located in the P-type body region, and the drain region of the NLDMOS is located in the N-well; the PLDMOS further comprises: a P-well located at a first side of the P-type drift region; an N-type body region located at a second side of the P-type drift region; wherein the source region of the PLDMOS is located in the N-type body region, and the drain region of the PLDMOS is located in the P-well.

[0012] In one of the embodiments, the NLDMOS further comprises a P-type body lead-out region located in the P-type body region, a doping concentration of the P-type body lead-out region being greater than a doping concentration of the P-type body region, the P-type body lead-out region being located between the second trench and the source region of the NLDMOS.

[0013] In one of the embodiments, the PLDMOS further comprises an N-type body pull-up region in the N-type body region, the N-type body pull-up region has a doping concentration greater than that of the N-type body region, and the N-type body pull-up region is located between the first trench and the source region of the PLDMOS.

[0014] In one of the embodiments, the length of the deep N-well in the NLDMOS is 10% to 40% of the total length of the NLDMOS.

[0015] In one of the embodiments, the length of the P-type buried layer is 10% to 30% of the total length of the NLDMOS.

[0016] In one of the embodiments, the length of the deep N-well in the PLDMOS is 40% to 80% of the total length of the PLDMOS.

[0017] In one of the embodiments, the SOI semiconductor structure further comprises: a third isolation trench structure comprising an insulating material in a third trench, the third trench being a closed loop structure and located inside the first trench; an N-type pull-up region on the top of the N-type region between the first trench and the third trench, the N-type pull-up region having a doping concentration greater than that of the N-type region, and the deep well being pulled up through the N-type pull-up region; a floating high-voltage region inside the third trench; a fourth isolation trench structure comprising an insulating material in a fourth trench, the fourth trench being a closed loop structure and located outside the second trench; a P-type pull-up region on the top of the P-type region between the second trench and the fourth trench, the P-type pull-up region having a doping concentration greater than that of the P-type region, and the substrate and the P-type buried layer being pulled up through the P-type pull-up region; and a low-voltage region outside the fourth trench.

[0018] In one of the embodiments, the drift region is located in a top layer of silicon on the buried dielectric layer, and the thickness of the top layer of silicon is 6 microns to 18 microns.

[0019] A method for manufacturing a silicon-on-insulator semiconductor structure, comprising: providing a wafer having deep wells of a first conductive type formed in a substrate of a second conductive type, a top of the deep well being located at or near a first main surface of the wafer, the first conductive type and the second conductive type being opposite conductive types; forming a buried dielectric layer on a partial region of the first main surface; forming a drift region, a first conductive type region and a second conductive type region on the first main surface, the drift region being formed on the buried dielectric layer, the first conductive type region being formed on the deep well not formed with the buried dielectric layer, the second conductive type region being formed on the substrate not formed with the buried dielectric layer; forming a gate, a source region and a drain region of a lateral double-diffused metal oxide semiconductor field effect transistor above the buried dielectric layer, the drift region being at least partially located between the source region and the drain region; the drift region, the source region and the drain region having a same conductive type; wherein the lateral double-diffused metal oxide semiconductor field effect transistor comprises a NLDMOS and / or a PLDMOS; for the NLDMOS, the drain region is electrically connected with the deep well; for the PLDMOS, the source region is electrically connected with the deep well.

[0020] The method for manufacturing the silicon-on-insulator semiconductor structure above described leads out the potential of the deep well opposite to the conductive type of the substrate and connects it to the drain region of the NLDMOS / the source region of the PLDMOS, so that the substrate participates in the vertical voltage resistance through mutual depletion of the deep well and the substrate, thereby improving the breakdown voltage of the device.

[0021] In one of the embodiments, the buried dielectric layer comprises an oxygen buried layer, and the step of forming the buried dielectric layer on the partial region of the first main surface comprises: forming the oxygen buried layer through local oxygen ion implantation.

[0022] In one of the embodiments, the silicon-on-insulator semiconductor structure comprises a NLDMOS and a PLDMOS, the drift region in the NLDMOS is an N-type drift region, the drift region in the PLDMOS is a P-type drift region; the source region and the drain region in the NLDMOS are N-type regions, the source region and the drain region in the PLDMOS are P-type regions; the deep well is a deep N-well, and the substrate is a P-type substrate; before the step of forming the buried dielectric layer on the partial region of the first main surface, the method further comprises a step of forming a P-type buried layer connected with the P-type substrate, the P-type buried layer being located in the NLDMOS and below the buried dielectric layer, and a doping concentration of the P-type buried layer being greater than a doping concentration of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0023] For a better description and illustration of embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, presently described embodiments and / or examples, and the best mode presently contemplated of these inventions.

[0024] Fig. 1 is a schematic diagram of a silicon-on-insulator semiconductor structure in an embodiment of the present application;

[0025] Fig. 2 is a sectional view along line A-A' in Fig. 1;

[0026] Fig. 3 is a schematic diagram of the structure of the NLDMOS in Fig. 2;

[0027] Fig. 4 is a sectional view along line B-B' in Fig. 1;

[0028] Fig. 5 is a schematic diagram of the structure of the PLDMOS in Fig. 4;

[0029] Fig. 6 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor structure in an embodiment of the present application;

[0030] Fig. 7a is a schematic diagram of the sectional structure of the device after step S610 is completed, and Fig. 7b is a schematic diagram of the sectional structure of the device after a P-type buried layer 114 is formed;

[0031] Fig. 8a is a schematic diagram of the sectional structure of the PLDMOS region after a buried dielectric layer 22 is formed, and Fig. 8b is a schematic diagram of the sectional structure of the NLDMOS region after a buried dielectric layer 22 is formed;

[0032] Fig. 9a is a schematic diagram of the sectional structure of the PLDMOS region after an N-type region 16 is formed, and Fig. 9b is a schematic diagram of the sectional structure of the NLDMOS region after an N-type region 16 is formed;

[0033] Fig. 10a is a schematic diagram of the sectional structure of the PLDMOS region after step S630 is completed, and Fig. 10b is a schematic diagram of the sectional structure of the NLDMOS region after step S630 is completed;

[0034] Fig. 11a is a schematic diagram of the sectional structure of the PLDMOS region after a first isolation groove structure 32 and a second isolation groove structure 34 are formed, and Fig. 11b is a schematic diagram of the sectional structure of the NLDMOS region after a first isolation groove structure 32 and a second isolation groove structure 34 are formed;

[0035] Fig. 12a is a schematic diagram of the sectional structure of the PLDMOS region after a gate 262 is formed, and Fig. 12b is a schematic diagram of the sectional structure of the NLDMOS region after a gate 162 is formed;

[0036] Fig. 13 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor structure in another embodiment of the present application. DETAILED DESCRIPTION

[0037] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate alternative embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. In this specification, "connected" should be understood as "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0040] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0041] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It will also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0043] The semiconductor field terms used herein are technical terms commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish doping concentrations, P+ type represents a heavily doped P-type, P type represents a medium doped P-type, P- type represents a lightly doped P-type, N+ type represents a heavily doped N-type, N type represents a medium doped N-type, and N- type represents a lightly doped N-type.

[0044] The inventors believe that the main limiting factor for conventional silicon-on-insulator integrated high-voltage devices to achieve a breakdown voltage of 1200V and above is the vertical withstand voltage. Specifically, the presence of the buried oxide layer blocks the electrical connection between the active layer and the substrate, preventing them from being mutually depleted, so that the substrate cannot participate in the vertical withstand voltage, making the vertical withstand voltage of conventional silicon-on-insulator integrated high-voltage devices only about 600V.

[0045] Exemplarily, the following two schemes can be used to realize an integrated silicon-on-insulator high-voltage device of 1200V level: one scheme is to increase the thickness of the buried oxide layer. Since the critical breakdown field of the buried oxide layer is much higher than that of silicon material, and due to the difference in dielectric constant between silicon and silicon dioxide material, the electric field in the buried oxide layer is about 3 times that in silicon, so increasing the thickness of the buried oxide layer can significantly improve the vertical breakdown voltage of the device. However, this scheme has obvious disadvantages, because a too thick buried oxide layer will cause poor thermal conductivity, resulting in local lattice temperature rise of the device and causing degradation of the electrical parameters of the device. These degradation phenomena make the device reliability worse. At the same time, a thick buried oxide layer will also cause problems in process and cost, making it difficult to realize large-scale commercial application. The other scheme is to use an ultra-thin top silicon layer. Since the ultra-thin top silicon layer reduces the vertical ionization integration path of the carriers, the vertical critical breakdown field of the top silicon layer is significantly improved, so the electric field in the buried oxide layer is also significantly improved, and the breakdown voltage of the device is significantly increased. However, an excessively thin top silicon layer will cause a weak current-carrying capacity problem.

[0046] The present application designs an innovative silicon-on-insulator semiconductor structure, which uses a thick-film silicon-on-insulator high-low voltage compatible process platform, and can improve the off-state vertical breakdown voltage of the silicon-on-insulator integrated high-voltage device. The silicon-on-insulator semiconductor structure comprises a lateral double-diffused metal oxide semiconductor field effect transistor, which comprises:

[0047] a substrate;

[0048] a buried dielectric layer located on part of the substrate;

[0049] a drift region located on the buried dielectric layer;

[0050] a deep well, wherein the deep well is located in the substrate and at least part of the deep well is located below the buried dielectric layer.

[0051] a drain region above the buried dielectric layer;

[0052] a source region above the buried dielectric layer, at least part of the drift region being between the source region and the drain region;

[0053] a gate;

[0054] wherein the deep well is opposite in conductivity type to the substrate.

[0055] The lateral double-diffused metal-oxide-semiconductor field-effect transistor can be an NLDMOS, the drain region of which is electrically connected to the deep well, and the drift region, the source region and the drain region of which have the same conductivity type.

[0056] The lateral double-diffused metal-oxide-semiconductor field-effect transistor can also be a PLDMOS, the source region of which is electrically connected to the deep well, and the drift region, the source region and the drain region of which have the same conductivity type.

[0057] The lateral double-diffused metal-oxide-semiconductor field-effect transistor can further comprise both the aforementioned NLDMOS and the aforementioned PLDMOS.

[0058] The silicon-on-insulator semiconductor structure described above leads out the potential of the deep well opposite in conductivity type to the substrate and connects it to the drain region of the NLDMOS / the source region of the PLDMOS, and makes the substrate participate in the vertical voltage resistance through mutual depletion of the deep well and the substrate, thereby improving the breakdown voltage of the device.

[0059] In an embodiment of the present application, the source region of the NLDMOS is electrically connected to the substrate. In an embodiment of the present application, the drain region of the PLDMOS is electrically connected to the substrate.

[0060] In an embodiment of the present application, the buried dielectric layer is an oxygen buried layer.

[0061] Fig. 1 is a schematic diagram of a silicon-on-insulator semiconductor structure in an embodiment of the present application, the silicon-on-insulator semiconductor structure in the embodiment comprising an NLDMOS and a PLDMOS. Fig. 2 is a sectional view along line A-A' in Fig. 1, and Fig. 3 is a structural schematic diagram of the NLDMOS in Fig. 2. Fig. 4 is a sectional view along line B-B' in Fig. 1, and Fig. 5 is a structural schematic diagram of the PLDMOS in Fig. 4.

[0062] Referring to FIG. 2 and FIG. 3, in one embodiment of the present application, the drift region in the NLDMOS is an N-type drift region 142, the source region 152 and the drain region 154 are N-type regions, the deep well is a deep N-well 12, and the substrate 10 is a P-type substrate. The NLDMOS further comprises a P-type buried layer 114 located at least partially below the buried dielectric layer 22, the source region 152 is electrically connected to the P-type buried layer 114, and the P-type buried layer 114 is located in the substrate 10. The P-type buried layer 114 has a doping concentration greater than that of the substrate 10. The P-type buried layer 114 can be used to adjust the charge balance, ensuring that the N-type drift region 142 of the NLDMOS can be completely depleted, preventing the device from breaking down prematurely, and the P-type buried layer 114 can also assist the deep N-well 12 in depletion.

[0063] Referring to FIG. 4 and FIG. 5, in one embodiment of the present application, the drift region in the PLDMOS is a P-type drift region 242, the source region 252 and the drain region 254 are P-type regions, the deep well is a deep N-well 12, and the substrate 10 is a P-type substrate.

[0064] Referring to FIG. 1, in one embodiment of the present application, the silicon-on-insulator semiconductor structure further comprises a junction termination region. Referring to FIG. 2 to FIG. 5, the silicon-on-insulator semiconductor structure further comprises a first isolation groove structure 32, a second isolation groove structure 34, an N-type region 16, and a P-type region 18.

[0065] The first isolation groove structure 32 comprises an insulating material disposed in a first trench, the first trench being a closed loop structure, and the junction termination region, the N-type drift region 142, and the P-type drift region 242 are located outside the first trench (i.e., outside the closed loop structure of the first isolation groove structure 32). The bottom of the insulating material in the first trench is connected to the buried dielectric layer 22, i.e., the first isolation groove structure 32 and the buried dielectric layer 22 are connected together to form a surrounding insulating structure.

[0066] The second isolation groove structure 34 comprises an insulating material disposed in a second trench, the second trench being a closed loop structure, and the junction termination region, the N-type drift region 142, and the P-type drift region 242 are located inside the second trench (i.e., inside the closed loop structure of the second isolation groove structure 34). The bottom of the insulating material in the second trench is connected to the buried dielectric layer 22, i.e., the second isolation groove structure 34 and the buried dielectric layer 22 are connected together to form a surrounding insulating structure.

[0067] The N-type region 16 is located inside the first trench (i.e., inside the closed loop structure of the first isolation groove structure 32), and a portion of the top of the deep N-well 12 is connected to the bottom of the N-type region 16, thereby leading out through the N-type region 16 and electrically connected to the drain region 154 of the NLDMOS and the source region 252 of the PLDMOS.

[0068] The P-type region 18 is located outside the second trench (i.e. outside the second isolation groove structure 34), and a portion of the top of the P-type buried layer 114 is connected to the bottom of the P-type region 18, so as to be led out through the P-type region 18 (the substrate 10 is also led out through the P-type region 18) and electrically connected to the source region 152 of the NLDMOS and the drain region 254 of the PLDMOS.

[0069] In an embodiment of the present application, the P-type region 18 is an epitaxial layer. Further, the process platform of the present application can adopt a thick film process, i.e. the top layer of silicon in the SOI is a thick film. Specifically, the thickness of the epitaxial layer is 6-18 microns, and is formed by one-time epitaxy or multiple epitaxy. The problem of weak current capacity and difficult heat dissipation in the thin film process is avoided. The thick film SOI structure has the advantages of strong current capacity, compatible process flow with the bulk silicon process, and simultaneous integration of the NLDMOS and the PLDMOS.

[0070] The drain region 154 of the NLDMOS is arranged close to the first trench, and the source region 152 is arranged close to the second trench. The drain region 254 of the PLDMOS is arranged close to the second trench, and the source region 252 is arranged close to the first trench.

[0071] Referring to FIG. 1, in an embodiment of the present application, the silicon-on-insulator semiconductor structure further comprises an isolation structure 39 located on both sides of the NLDMOS and on both sides of the PLDMOS. The isolation structure 39 has an insulating material, one end of the isolation structure 39 is in direct contact with the first isolation groove structure 32, the other end is in direct contact with the second isolation groove structure 34, and the bottom of the isolation structure 39 is in direct contact with the buried dielectric layer 22, so as to achieve complete insulation and isolation between devices. Taking FIG. 1 as an example, the left and right sides of the NLDMOS are the isolation structure 39, the front and back are the first isolation groove structure 32 and the second isolation groove structure 34 respectively, and the bottom of the N-type drift region 142 is the buried dielectric layer 22, so as to achieve complete surrounding of the device by the insulating structure except for the top surface.

[0072] Referring to FIG. 1, in an embodiment of the present application, the silicon-on-insulator semiconductor structure further comprises a third isolation groove structure 36, a fourth isolation groove structure 38, a floating high-voltage region and a low-voltage region, so as to achieve a high-low voltage compatible process platform.

[0073] The third isolation trench structure 36 includes insulating material disposed in a third trench, which is a closed loop structure and is located inside the first trench (i.e., the third isolation trench structure 36 is a closed loop structure and is located inside the closed loop structure of the first isolation trench structure 32). A floating high voltage region is located inside the third trench. The floating high voltage region is isolated from the junction termination region by an N-isolation ring. The floating high voltage region is used to set a high voltage device. In one embodiment of the present application, the floating high voltage region is a 1200V floating high voltage region, i.e., used to set a high voltage device with a breakdown voltage of 1200V.

[0074] The fourth isolation trench structure 38 includes insulating material disposed in a fourth trench, which is a closed loop structure and is located outside the second trench (i.e., the fourth isolation trench structure 38 is a closed loop structure and is located outside the second isolation trench structure 34). A low voltage region is located outside the fourth trench. The low voltage region is isolated from the junction termination region by a P-isolation ring. The low voltage region is used to set a low voltage device, such as a CMOS device.

[0075] In the embodiment shown in FIG. 1, the LDMOS performs the function of level shifting, in which the NLDMOS implements the function of level upshift and the PLDMOS implements the function of level downshift.

[0076] Referring to FIGS. 2-4, in one embodiment of the present application, the silicon-on-insulator semiconductor structure further includes an N-type extraction region 17 and a P-type extraction region 19. The N-type extraction region 17 is located on top of the N-type region 16 between the first trench and the third trench (i.e., between the first isolation trench structure 32 and the third isolation trench structure 36). The N-type extraction region 17 has a higher doping concentration than the N-type region 16, and the deep N-well 12 extracts potential through the N-type extraction region 17. The P-type extraction region 19 is located on top of the P-type region 18 between the second trench and the fourth trench (i.e., between the second isolation trench structure 34 and the fourth isolation trench structure 38). The P-type extraction region 19 has a higher doping concentration than the P-type region 18, and the substrate 10 and the P-type buried layer 114 extract potential through the P-type extraction region 19.

[0077] Referring to FIG. 3, in one embodiment of the present application, the NLDMOS further includes a P-type body region 146 on one side of the N-type drift region 142 and an N-well 144 on the other side. The source region 152 of the NLDMOS is located in the P-type body region 146 and the drain region 154 is located in the N-well 144. The P-type body region 146 is located inside the second isolation trench structure 34 and the N-well 144 is located outside the first isolation trench structure 32. The doping concentration of the drain region 154 is higher than that of the N-well 144.

[0078] In one embodiment of the present application, the NLDMOS further comprises a P-body pull-out region 156 in the P-body region 146. The P-body pull-out region 156 has a doping concentration greater than that of the P-body region 146, and is located between the second isolation trench structure 34 and the source region 152 of the NLDMOS.

[0079] Referring to FIG. 5, in one embodiment of the present application, the PLDMOS further comprises a P-well 244 on one side of the P-drift region 242 and an N-body region 246 on the other side. The source region 252 of the PLDMOS is located in the N-body region 246, and the drain region 254 is located in the P-well 244. The P-well 244 is located inside the second isolation trench structure 34, and the N-body region 246 is located outside the first isolation trench structure 32. The doping concentration of the drain region 254 is greater than that of the P-well 244.

[0080] In one embodiment of the present application, the PLDMOS further comprises an N-body pull-out region 256 in the N-body region 246. The N-body pull-out region 256 has a doping concentration greater than that of the N-body region 246. The N-body pull-out region 256 is located between the first isolation trench structure 32 and the source region 252 of the PLDMOS.

[0081] In one embodiment of the present application, the doping concentration relationship in the device is: P-body pull-out region 156 > P-body region 146 / P-well 244 > P-buried layer 114 > P-drift region 242 > substrate 10; N-body pull-out region 256 > N-well 144 / N-body region 246 > deep N-well 12.

[0082] In one embodiment of the present application, the length of the deep N-well 12 in the NLDMOS is 10% to 40% of the total length of the device of the NLDMOS.

[0083] In one embodiment of the present application, the length of the P-buried layer 114 is 10% to 30% of the total length of the device of the NLDMOS.

[0084] In one embodiment of the present application, the length of the deep N-well 12 in the PLDMOS is 40% to 80% of the total length of the device of the PLDMOS. The total length L of the device of the NLDMOS / PLDMOS is the distance between the first isolation trench structure 32 and the second isolation trench structure 34, as shown in FIG. 5.

[0085] Referring to FIGS. 2 and 3, in one embodiment of the application, the NLDMOS further includes a field oxide layer 172 on the N-type drift region 142. The gate 162 extends from the P-type body region 146 proximate the source region 152 to the field oxide layer 172. In one embodiment of the application, the NLDMOS further includes an interlayer dielectric layer 74 on the surface of the device. The source region 152 is connected to the P-type body tap 156 and the P-type tap 19 by conductive material in the overlying contact hole (the contact hole extends through the interlayer dielectric layer 74) and a metal interconnect layer on the contact hole. The drain region 154 is connected to the N-type tap 17 by conductive material in the overlying contact hole and a metal interconnect layer on the contact hole.

[0086] Referring to FIGS. 4 and 5, in one embodiment of the application, the PLDMOS further includes a field oxide layer 272 on the P-type drift region 242. The gate 262 extends from the P-type body region 246 proximate the source region 252 to the field oxide layer 272. In one embodiment of the application, the PLDMOS further includes an interlayer dielectric layer 74 on the surface of the device. The source region 252 is connected to the N-type body tap 256 and the N-type tap 17 by conductive material in the overlying contact hole (the contact hole extends through the interlayer dielectric layer 74) and a metal interconnect layer on the contact hole. The drain region 254 is connected to the P-type tap 19 by conductive material in the overlying contact hole and a metal interconnect layer on the contact hole.

[0087] In one embodiment, the gates 162 and 262 are of polysilicon material, although in other embodiments, metals, metal nitrides, metal silicides, or the like can be used as the material for the gates 162 / 262. A gate dielectric layer can also be provided at the bottom of the gates 162 and 262, and can include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having dielectric constants from about 4 to about 20 (measured in vacuum), or can include higher dielectric constant dielectric materials having dielectric constants from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanates (BSTs), and lead zirconium titanates (PZTs).

[0088] Take NLDMOS in FIG. 2 as an example to illustrate the working principle of the high-voltage LDMOS device in the platform: when the device is reversely biased (the drain is positively biased, and the gate 162, the source and the substrate 10 are grounded), the PN junction formed by the substrate 10 and the deep N well 12 is reversely biased. As the external bias continuously increases, the space charge region of the P-type low-doped substrate 10 continuously expands downward. By setting appropriate substrate resistivity and deep N well 12 concentration, the breakdown voltage of the PN junction formed by the substrate 10 and the deep N well 12 can be greater than 1200V, so that the longitudinal withstand voltage of the LDMOS device can reach 1200V or more. In this way, the breakdown voltage of the silicon-on-insulator integrated high-voltage device can reach 1200V or more on a conventional SOI-based process platform, avoiding the adverse factors caused by thick buried oxide layers and ultra-thin top silicon. The working principle of the PLDMOS device is similar.

[0089] Based on all the above embodiments, the application introduces a deep N well 12 into a P-type substrate and leads the potential of the deep N well 12 from the surface, and participates in the longitudinal withstand voltage of the substrate 10 through the mutual depletion of the deep N well 12 and the substrate 10, thereby improving the longitudinal withstand voltage of the silicon-on-insulator integrated high-voltage device and making the breakdown voltage of the device reach 1200V or more without introducing too many complex processes. Based on the conventional thick-film SOI-based process platform, the application can avoid the adverse factors caused by thick buried oxide layers and ultra-thin top silicon.

[0090] The application correspondingly provides a manufacturing method of a silicon-on-insulator semiconductor structure, which can be used to manufacture the silicon-on-insulator semiconductor structure described in any of the above embodiments. FIG. 6 is a flowchart of the manufacturing method of the silicon-on-insulator semiconductor structure in an embodiment of the application, which includes the following steps:

[0091] S610, providing a wafer in which a deep well is formed in a substrate.

[0092] In an embodiment of the application, after step S610, a substrate 10 of a second conductivity type and a deep well of a first conductivity type are obtained, and the top of the formed deep well is located at the first main surface (i.e. the front surface) of the wafer or is close to the first main surface of the wafer. In an embodiment of the application, the silicon-on-insulator semiconductor structure includes NLDMOS and PLDMOS, the first conductivity type is N-type, the second conductivity type is P-type, the substrate 10 is a P-type substrate, and the deep well is a deep N well 12, as shown in FIG. 7a. The deep N well 12 can be formed by patterning (such as photolithography) and ion implantation (implanting N-type ions).

[0093] S620, forming a buried dielectric layer on the wafer.

[0094] In one embodiment of the present application, step S620 is followed by a step of forming a P-type buried layer 114 in the substrate 10, which is electrically connected to the source region 152. Referring to FIG. 7b, the P-type buried layer 114 is located in the NLDMOS region and is located below the buried dielectric layer 22.

[0095] In one embodiment of the present application, the buried dielectric layer 22 is an oxygen buried layer. Further, the oxygen buried layer can be formed in a specified region of the wafer by local oxygen ion implantation, and the oxygen buried layer is not formed in the region of the substrate 10 which is to be electrically connected to the upper layer. The cross-sectional structure of the PLDMOS region after the formation of the buried dielectric layer 22 is shown in FIG. 8a, and the cross-sectional structure of the NLDMOS region after the formation of the buried dielectric layer 22 is shown in FIG. 8b.

[0096] S630, forming a drift region, a first-conductivity-type region and a second-conductivity-type region on the wafer.

[0097] The drift region is formed on the buried dielectric layer 22, and the first-conductivity-type region is formed on the deep N-well 12 and the second-conductivity-type region is formed on the substrate 10 in the region where the buried dielectric layer 22 is not formed. In one embodiment of the present application, the first-conductivity-type region is the N-type region 16, and the second-conductivity-type region is the P-type region 18. In one embodiment of the present application, the P-type region 18 is an epitaxial layer, and the cross-sectional structure of the PLDMOS region after the formation of the P-type region 18 is shown in FIG. 9a, and the cross-sectional structure of the NLDMOS region after the formation of the P-type region 18 is shown in FIG. 9b. For the PLDMOS, part of the epitaxial layer on the buried dielectric layer 22 can be directly used as the P-type drift region 242. For the NLDMOS, the epitaxial layer on the buried dielectric layer 22 can be patterned (e.g., lithography) and ion implanted (N-type ions are implanted) to form the N-type drift region 142. In one embodiment of the present application, N-type ions are implanted into the epitaxial layer to form the N-type region 16 at the position where the N-type region 16 is needed. In one embodiment of the present application, the ion implantation for forming the N-type region 16 can be performed in the same step as the ion implantation for forming the N-type drift region 142.

[0098] In one embodiment of the present application, the cross-sectional structure of the PLDMOS region after step S630 is shown in FIG. 10a. In one embodiment of the present application, the cross-sectional structure of the NLDMOS region after step S630 is shown in FIG. 10b.

[0099] S640, forming a gate, a source region and a drain region above the buried dielectric layer.

[0100] For the NLDMOS, the drain region 154 is electrically connected to the deep N-well 12. Specifically, the deep N-well 12 can be led out from the surface of the device and then connected to the drain region 154 through a metal interconnection layer. For the PLDMOS, the source region 252 is electrically connected to the deep N-well 12. Specifically, the deep N-well 12 can be led out from the surface of the device and then connected to the source region 252 through a metal interconnection layer.

[0101] The manufacturing method of the above-mentioned silicon-on-insulator semiconductor structure leads out the potential of the deep N-well 12 of the opposite conductivity type to the substrate 10 and connects it to the drain region of the NLDMOS / the source region of the PLDMOS, so that the substrate participates in the longitudinal voltage resistance through the mutual depletion of the deep N-well 12 and the substrate 10, thereby improving the breakdown voltage of the device without introducing too much complex process.

[0102] In an embodiment of the present application, the steps of forming the first isolation groove structure 32 and the second isolation groove structure 34 are further included. Specifically, the first groove and the second groove can be formed by patterning (e.g. photolithography) and etching. The first groove and the second groove are closed loop structures, and the N-type drift region and the P-type drift region are located outside the first groove and inside the second groove, and the bottom of the first groove and the bottom of the second groove extend to the buried dielectric layer 22. Then, the first groove and the second groove are filled with insulating material to form the first isolation groove structure 32 and the second isolation groove structure 34.

[0103] In an embodiment of the present application, the cross-sectional structure of the PLDMOS region after the formation of the first isolation groove structure 32 and the second isolation groove structure 34 is shown in FIG. 11a. The step of forming the first isolation groove structure 32 and the second isolation groove structure 34 can be performed before the formation of the P-type region 18 and the P-type drift region 242, or after the formation of the P-type region 18 and the P-type drift region 242. In an embodiment of the present application, the cross-sectional structure of the NLDMOS region after the formation of the first isolation groove structure 32 and the second isolation groove structure 34 is shown in FIG. 11b. The step of forming the first isolation groove structure 32 and the second isolation groove structure 34 can be performed before the formation of the P-type region 18, or after the formation of the P-type region 18.

[0104] In one embodiment of the present application, the third isolation trench structure 36 and the fourth isolation trench structure 38 can be formed at the same time as the first isolation trench structure 32 and the second isolation trench structure 34. The third isolation trench structure 36 includes insulating material in a third trench, which is a closed loop structure and is inside the first trench (i.e., the third isolation trench structure 36 is a closed loop structure and is inside the first isolation trench structure 32). The fourth isolation trench structure 38 includes insulating material in a fourth trench, which is a closed loop structure and is outside the second trench (i.e., the fourth isolation trench structure 38 is a closed loop structure and is outside the second isolation trench structure 34).

[0105] In one embodiment of the present application, the isolation structure 39 can be formed on both sides of the NLDMOS and on both sides of the PLDMOS at the same time as the first isolation trench structure 32 and the second isolation trench structure 34. The isolation structure 39 has insulating material, one end of the isolation structure 39 directly contacts the first isolation trench structure 32, the other end of the isolation structure 39 directly contacts the second isolation trench structure 34, and the bottom of the isolation structure 39 directly contacts the buried dielectric layer 22, thereby achieving complete insulating isolation between devices.

[0106] In one embodiment of the present application, a portion of the epitaxial layer (P-type region 18) of the NLDMOS can be used as the P-type body region 146. In one embodiment of the present application, the N-type body region 246 can be formed at the same time as the N-type region 16 and the N-type drift region 142, i.e., the ion implantation step for forming the N-type body region 246 can be the same step as the ion implantation for forming the N-type region 16 and the N-type drift region 142.

[0107] In one embodiment of the present application, the steps of forming the N-well 144 and the P-well 244 are also included. The N-well 144 can be formed outside the first isolation trench structure 32 and the P-well 244 can be formed inside the second isolation trench structure 34, by means of patterning (e.g., photolithography) and ion implantation. The P-type body region 146 is located on one side of the N-type drift region 142, and the N-well 144 is located on the other side of the N-type drift region 142. The P-well 244 is located on one side of the P-type drift region 242, and the N-type body region 246 is located on the other side of the P-type drift region 242. In one embodiment of the present application, the N-well 144 can be formed in the same ion implantation step as the N-type body region 246, the N-type region 16, and the N-type drift region 142.

[0108] In one embodiment of the present application, the steps of forming the field oxide layer 172 on the upper surface of the N-type drift region 142 and the field oxide layer 272 on the upper surface of the P-type drift region 242 are also included. The field oxide layer 172 and the field oxide layer 272 can be formed in the same step by using a local thermal oxidation process.

[0109] In one embodiment of the present application, the steps of forming the gate 162 of the NLDMOS and the gate 262 of the PLDMOS are also included. The cross-sectional structure of the PLDMOS region after the formation of the gate 262 is shown in Fig. 12a, and the cross-sectional structure of the NLDMOS region after the formation of the gate 162 is shown in Fig. 12b.

[0110] In one embodiment of the present application, the steps of forming the source region 152, the drain region 154 and the P-type body tap region 156 of the NLDMOS are also included. The source region 152 and the P-type body tap region 156 are formed in the P-type body region 146, and the drain region 154 is formed in the N-well 144. The P-type body tap region 156 has a higher doping concentration than the P-type body region 146, and the P-type body tap region 156 is formed between the second isolation trench structure 34 and the source region 152 of the NLDMOS.

[0111] In one embodiment of the present application, the steps of forming the source region 252, the drain region 254 and the N-type body tap region 256 of the PLDMOS are also included. The source region 252 and the N-type body tap region 256 are formed in the N-type body region 246, and the drain region 254 is formed in the P-well 244. The N-type body tap region 256 has a higher doping concentration than the N-type body region 246. The N-type body tap region 256 is formed between the first isolation trench structure 32 and the source region 252 of the PLDMOS.

[0112] In one embodiment of the present application, the steps of forming the N-type tap region 17 and the P-type tap region 19 are also included. The N-type tap region 17 and the P-type tap region 19 can be formed by ion implantation. The N-type tap region 17 is formed on top of the N-type region 16 between the first trench and the third trench. The N-type tap region 17 has a higher doping concentration than the N-type region 16, and the deep N-well 12 is tapped through the N-type tap region 17. The P-type tap region 19 is formed on top of the P-type region 18 between the second trench and the fourth trench. The P-type tap region 19 has a higher doping concentration than the P-type region 18, and the substrate 10 and the P-type buried layer 114 are tapped through the P-type tap region 19.

[0113] Fig. 13 is a flow chart of a method of fabricating a silicon-on-insulator semiconductor structure according to another embodiment of the present application, including the following steps:

[0114] S710, forming a deep N-well in the substrate.

[0115] In one embodiment of the present application, the deep N-well 12 can be formed in the substrate 10 by patterning (e.g. photolithography) and ion implantation (implanting N-type ions), as shown in Fig. 7a. In one embodiment of the present application, the step of forming a P-type buried layer 114 in the substrate is also included, as shown in Fig. 7b.

[0116] S720, forming a buried oxide layer in a designated area on the front surface of the wafer by local oxygen ion implantation.

[0117] The buried oxide layer is formed as the buried dielectric layer 22, and the buried oxide layer is not formed in the area of the substrate 10 to be electrically connected to the upper layer. Referring to FIG. 8a and FIG. 8b.

[0118] S730, forming a P-type epitaxial layer on the front surface of the wafer.

[0119] The P-type epitaxial layer is grown above the buried oxide layer to form a thick top silicon. In an embodiment of the present application, the thickness of the P-type epitaxial layer is 6-18 microns. The P-type region 18 is part of the epitaxial layer. Referring to FIG. 9a and FIG. 9b.

[0120] S740, forming a trench isolation.

[0121] The trench isolation includes the first isolation trench structure 32, the second isolation trench structure 34, the third isolation trench structure 36, the fourth isolation trench structure 38, and the isolation structure 39. Part of the trench isolation can be referred to FIG. 10a and FIG. 10b.

[0122] S750, forming a drift region, a body region, and a well region.

[0123] For the PLDMOS, part of the P-type epitaxial layer on the buried dielectric layer 22 can be directly used as the P-type drift region 242 and the P-type body region 146. For the NLDMOS, the epitaxial layer on the buried dielectric layer 22 can be patterned (e.g., lithography) and ion implanted (implanting N-type ions) to form the N-type drift region 142, while forming the N-type region 16 and the N-type body region 246. The N-well 144 and the P-well 244 are formed by patterning (e.g., lithography) and ion implantation. Referring to FIG. 11a and FIG. 11b.

[0124] S760, forming a field oxide layer.

[0125] In an embodiment of the present application, a local thermal oxidation process is used to form the field oxide layer 272 on the upper surface of the N-type drift region 142 and the upper surface of the P-type drift region 242.

[0126] S770, forming a gate, a source region, a drain region, and a body tap region.

[0127] The cross-sectional structure of the PLDMOS region after forming the gate 262 is shown in FIG. 12a, and the cross-sectional structure of the NLDMOS region after forming the gate 162 is shown in FIG. 12b.

[0128] The source region 152 and the P-type body pull-up region 156 of the NLDMOS are formed in the P-type body region 146, and the drain region 154 is formed in the N-well 144. The P-type body pull-up region 156 has a higher doping concentration than the P-type body region 146, and the P-type body pull-up region 156 is formed between the second isolation trench structure 34 and the source region 152 of the NLDMOS.

[0129] The source region 252 and the N-type body pull-up region 256 of the PLDMOS are formed in the N-type body region 246, and the drain region 254 is formed in the P-well 244. The N-type body pull-up region 256 has a higher doping concentration than the N-type body region 246. The N-type body pull-up region 256 is formed between the first isolation trench structure 32 and the source region 252 of the PLDMOS.

[0130] In one embodiment of the present application, the step of forming the N-type pull-up region 17 and the P-type pull-up region 19 is further included. The N-type pull-up region 17 and the P-type pull-up region 19 can be formed by ion implantation. The N-type pull-up region 17 is formed on the top of the N-type region 16 between the first trench and the third trench.

[0131] S780, forming an interlayer dielectric layer, a contact hole, a source metal and a drain metal.

[0132] An interlayer dielectric layer 74, a contact hole, a source metal and a drain metal are formed. The SOI semiconductor structure after the above steps are completed can be seen in FIG. 3 and FIG. 5.

[0133] The manufacturing method of the SOI semiconductor structure of the present application is based on the same inventive concept as the SOI semiconductor structure, and the contents not specifically described in the manufacturing method of the SOI semiconductor structure can be referred to the introduction of the SOI semiconductor structure.

[0134] It should be understood that, although each step in the flowchart of the present application is shown in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0135] In the description of the specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the description, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0136] The technical features of the above-described embodiments can be combined arbitrarily, and for the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present application.

[0137] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A silicon-on-insulator semiconductor structure comprising a lateral double diffused metal oxide semiconductor field effect transistor, characterized in that, The lateral double-diffused metal oxide semiconductor field effect transistor comprises: a substrate; a buried dielectric layer on part of the substrate; a drift region on the buried dielectric layer; a deep well, the deep well being in the substrate and at least part of the deep well being below the buried dielectric layer; a drain region above the buried dielectric layer; a source region above the buried dielectric layer, the drift region being at least partially between the source region and the drain region; a gate; wherein the deep well is opposite in conductivity type to the substrate; the lateral double-diffused metal oxide semiconductor field effect transistor comprises an NLDMOS and / or a PLDMOS; for the NLDMOS, its drain region is electrically connected to the deep well, and its drift region, source region and drain region have the same conductivity type; for the PLDMOS, its source region is electrically connected to the deep well, and its drift region, source region and drain region have the same conductivity type.

2. The silicon-on-insulator semiconductor structure of claim 1, wherein, for the NLDMOS, its source region is electrically connected to the substrate; for the PLDMOS, its drain region is electrically connected to the substrate.

3. The silicon-on-insulator semiconductor structure of claim 2, wherein, the lateral double-diffused metal oxide semiconductor field effect transistor comprises an NLDMOS and a PLDMOS, the drift region in the NLDMOS is an N-type drift region, and the drift region in the PLDMOS is a P-type drift region; the source region and the drain region in the NLDMOS are N-type regions, and the source region and the drain region in the PLDMOS are P-type regions; the deep well is a deep N-well, and the substrate is a P-type substrate; the NLDMOS further comprises a P-type buried layer at least partially below the buried dielectric layer, the source region is electrically connected to the P-type buried layer, and the P-type buried layer has a doping concentration greater than that of the substrate.

4. The silicon-on-insulator semiconductor structure of claim 3, wherein the buried oxide layer has a thickness of about 50 A to about 200 A. further comprising: a junction termination region; a first isolation groove structure comprising an insulating material in a first groove, the first groove being a closed loop structure, the junction termination region, the N-type drift region and the P-type drift region being located outside the first groove, the bottom of the insulating material in the first groove being connected to the buried dielectric layer; a second isolation groove structure comprising an insulating material in a second groove, the second groove being a closed loop structure, the junction termination region, the N-type drift region and the P-type drift region being located inside the second groove, the bottom of the insulating material in the second groove being connected to the buried dielectric layer; an N-type region located inside the first groove, part of the top of the deep N-well being connected to the bottom of the N-type region, thereby leading out through the N-type region and being electrically connected to the drain region of the NLDMOS and the source region of the PLDMOS; a P-type region located outside the second groove, part of the top of the substrate and part of the top of the P-type buried layer being connected to the bottom of the P-type region, thereby leading out through the P-type region and being electrically connected to the source region of the NLDMOS and the drain region of the PLDMOS; The drain region of the NLDMOS is arranged close to the first trench, and the source region of the NLDMOS is arranged close to the second trench; the drain region of the PLDMOS is arranged close to the second trench, and the source region of the PLDMOS is arranged close to the first trench.

5. The silicon-on-insulator semiconductor structure of claim 4, wherein the buried oxide layer has a thickness of about 50 A to about 200 A. The isolation structure further comprises an insulating material, a first end of the isolation structure is in direct contact with the first isolation trench structure, a second end of the isolation structure is in direct contact with the second isolation trench structure, and a bottom of the isolation structure is in direct contact with the buried dielectric layer.

6. The silicon-on-insulator semiconductor structure of claim 3, wherein the buried oxide layer has a thickness of about 50 A to about 200 A. The NLDMOS further comprises: A P-type body region on a first side of the N-type drift region; An N-well on a second side of the N-type drift region; The source region of the NLDMOS is in the P-type body region, and the drain region of the NLDMOS is in the N-well; The PLDMOS further comprises: An N-well on a first side of the P-type drift region; A P-type body region on a second side of the P-type drift region; The source region of the PLDMOS is in the N-type body region, and the drain region of the PLDMOS is in the P-well.

7. The silicon-on-insulator semiconductor structure of claim 3, wherein the buried oxide layer has a thickness of about 50 A to about 200 A. The length of the deep N-well in the NLDMOS is 10% to 40% of the total length of the NLDMOS; and / or The length of the P-type buried layer is 10% to 30% of the total length of the NLDMOS; and / or The length of the deep N-well in the PLDMOS is 40% to 80% of the total length of the PLDMOS.

8. The silicon-on-insulator semiconductor structure of any of claims 4-7, wherein the buried oxide layer has a thickness of about 10 nm to about 20 nm. The third isolation trench structure further comprises an insulating material arranged in a third trench, the third trench is a closed ring structure and is located inside the first trench; The N-type pull-out region is located at the top of the N-type region between the first trench and the third trench, the doping concentration of the N-type pull-out region is greater than the doping concentration of the N-type region, and the deep well is pulled out through the N-type pull-out region; The floating high-voltage region is located inside the third trench; The fourth isolation trench structure further comprises an insulating material arranged in a fourth trench, the fourth trench is a closed ring structure and is located outside the second trench; The P-type pull-out region is located at the top of the P-type region between the second trench and the fourth trench, the doping concentration of the P-type pull-out region is greater than the doping concentration of the P-type region, and the substrate and the P-type buried layer are pulled out through the P-type pull-out region; The low-voltage region is located outside the fourth trench. The drift region is located in a top layer of silicon on the buried dielectric layer, and the thickness of the top layer of silicon is 6 microns to 18 microns.

9. The silicon-on-insulator semiconductor structure of claim 1, wherein, 10. A manufacturing method of a silicon-on-insulator semiconductor structure, comprising: providing a wafer having a deep well of a first conductivity type formed in a substrate of a second conductivity type, a top of the deep well being located at or close to a first main surface of the wafer, the first conductivity type and the second conductivity type being opposite conductivity types; forming a buried dielectric layer in a partial region of the first main surface; ​ forming a drift region, a first conductive type region and a second conductive type region on the first main surface, the drift region being formed on the buried dielectric layer, the first conductive type region being formed on the deep well on which the buried dielectric layer is not formed, and the second conductive type region being formed on the substrate on which the buried dielectric layer is not formed; forming a gate, a source region and a drain region of a lateral double-diffused metal oxide semiconductor field effect transistor above the buried dielectric layer, at least part of the drift region being located between the source region and the drain region; the drift region, the source region and the drain region having the same conductive type; wherein the lateral double-diffused metal oxide semiconductor field effect transistor comprises a NLDMOS and / or a PLDMOS; for the NLDMOS, the drain region is electrically connected with the deep well; for the PLDMOS, the source region is electrically connected with the deep well.

11. The method of manufacturing a silicon-on-insulator semiconductor structure according to claim 10, wherein the buried dielectric layer comprises an oxygen buried layer, and the step of forming the buried dielectric layer on the partial region of the first main surface comprises: forming the oxygen buried layer by local oxygen ion implantation.

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