Method for manufacturing semiconductor structure and semiconductor structure

Abstract

A method for manufacturing a semiconductor structure, and a semiconductor structure. The method comprises: providing a substrate (1), wherein the substrate (1) is provided with an active pillar (11) and an isolation layer (12) arranged at intervals in a first direction (X), and both the active pillar (11) and the isolation layer (12) extend in a second direction (Y), the first direction (X) being parallel to a surface of the substrate (1), the second direction (Y) being parallel to the thickness direction of the substrate (1), and the second direction (Y) being perpendicular to the first direction (X); removing part of the isolation layer (12) to form a first recess (201); depositing a first dielectric layer (302) on at least a side wall of the first recess (201), so as to form a second recess (202); forming a first metal layer (401), the first metal layer (401) at least directly covering the active pillar (11); performing heat treatment to form a conductive structure (501), wherein the first dielectric layer (302) covers a side wall of the conductive structure (501), and the conductive structure (501) extends in a third direction (Z), the third direction (Z) being perpendicular to the first direction (X) and the second direction (Y); and forming a second dielectric layer (601), wherein the second dielectric layer fills the second recess (202).

Description

Manufacturing method of semiconductor structure and semiconductor structure thereof

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410465795.7, filed on April 17, 2024, entitled "Manufacturing method of semiconductor structure and semiconductor structure thereof", the contents of which are incorporated herein in their entirety by reference. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a manufacturing method of semiconductor structure and semiconductor structure thereof. BACKGROUND

[0004] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory, compared with static memory, DRAM memory has the advantages of simple structure, low manufacturing cost and high capacity density. With the development of semiconductor industry, semiconductor devices are becoming highly integrated, i.e. miniaturization. Highly integrated semiconductor devices are changing from planar channel transistors to vertical channel transistors (VCT).

[0005] However, in the manufacturing process of vertical channel transistors, the performance and yield of semiconductor memory devices are still low. How to improve the performance and yield of semiconductor memory devices is a technical problem to be solved at present. SUMMARY

[0006] The present disclosure provides a manufacturing method of semiconductor structure and semiconductor structure thereof, which at least has the advantage of improving the performance and yield of semiconductor memory devices.

[0007] According to some embodiments of the present disclosure, the present disclosure provides a manufacturing method of semiconductor structure, comprising:

[0008] providing a substrate, the substrate has active pillars and isolation layers arranged at intervals along a first direction, the active pillars and the isolation layers both extend along a second direction, the first direction is parallel to the surface of the substrate, the second direction is parallel to the thickness direction of the substrate, and the second direction is perpendicular to the first direction;

[0009] removing part of the isolation layers to form first recesses;

[0010] depositing a first dielectric layer at least on the sidewalls of the first recesses to form second recesses;

[0011] forming a first metal layer, the first metal layer directly covers at least the active pillars;

[0012] performing a thermal treatment to form the electrically conductive structure, the first dielectric layer covering sidewalls of the electrically conductive structure, the electrically conductive structure extending along a third direction, the third direction being perpendicular to the first direction and the second direction;

[0013] forming a second dielectric layer, the second dielectric layer filling the second recess.

[0014] In some embodiments, forming the first dielectric layer specifically includes:

[0015] forming a first dielectric material layer, the first dielectric material layer covering sidewalls and a bottom of the first recess and a top of the active pillar;

[0016] removing the first dielectric material layer from the top of the active pillar, the remaining first dielectric material layer as the first dielectric layer.

[0017] In some embodiments, forming the first dielectric layer specifically includes:

[0018] forming a first dielectric material layer, the first dielectric material layer covering sidewalls and a bottom of the first recess and a top of the active pillar;

[0019] removing the first dielectric material layer from the top of the active pillar and the bottom of the first recess, the remaining first dielectric material layer as the first dielectric layer.

[0020] In some embodiments, the first metal layer fills the second recess and covers the top of the active pillar.

[0021] In some embodiments, after forming the first dielectric material layer and before forming the first metal layer, further comprising:

[0022] forming a second metal material layer, the second metal material layer covering the first dielectric material layer and filling the second recess, removing part of the second metal material layer and part of the first dielectric material layer to expose the top of the active pillar, the remaining second metal material layer as the second metal layer, the second metal layer being flush with the active pillar;

[0023] forming the first metal layer on the second metal layer and the top of the active pillar.

[0024] In some embodiments, after forming the first dielectric material layer and before forming the first metal layer, further comprising:

[0025] forming a third dielectric material layer, the third dielectric material layer covering the first dielectric material layer and filling the second recess, removing part of the third dielectric material layer and part of the first dielectric material layer to expose the top of the active pillar, the remaining third dielectric material layer as the third dielectric layer, the third dielectric layer being flush with the active pillar;

[0026] forming the first metal layer on the third dielectric layer and the top of the active pillar.

[0027] In some embodiments, after forming the electrically conductive structure and before forming the second dielectric layer, further comprising:

[0028] removing the first metal layer to re-expose the second recess.

[0029] In some embodiments, after forming the electrically conductive structure and before forming the second dielectric layer, further comprising:

[0030] removing the first metal layer and the second metal layer to re-expose the second recess.

[0031] In some embodiments, after forming the electrically conductive structure and before forming the second dielectric layer, further comprising:

[0032] removing the first metal layer and the third dielectric layer to re-expose the second recess.

[0033] In some embodiments, a dielectric constant of the first dielectric layer is less than a dielectric constant of the active pillar; a depth of the first recess is greater than a depth of the electrically conductive structure.

[0034] In some embodiments, the second dielectric layer has an air gap therein, a depth of the air gap in the second direction is greater than a depth of the electrically conductive structure.

[0035] In some embodiments, a temperature of forming the first dielectric layer is greater than a thermal treatment temperature, a resistivity of the electrically conductive structure is not greater than 20 μΩ·cm.

[0036] Another aspect of the present disclosure provides a semiconductor structure, comprising:

[0037] a substrate, the substrate having active pillars and isolation layers spaced apart along a first direction, the active pillars and the isolation layers both extending along a second direction, the first direction being parallel to a surface of the substrate, the second direction being parallel to a thickness direction of the substrate, the second direction being perpendicular to the first direction;

[0038] an electrically conductive structure, the electrically conductive structure being electrically connected with the active pillars, the electrically conductive structure extending along a third direction, the third direction being perpendicular to the first direction and the second direction;

[0039] a first recess between adjacent electrically conductive structures;

[0040] a second recess within the first recess;

[0041] a first dielectric layer between the first recess and the second recess and covering at least a sidewall of the electrically conductive structure;

[0042] a second dielectric layer filling the second recess and covering a top of the electrically conductive structure.

[0043] In some embodiments, a dielectric constant of the first dielectric layer is less than a dielectric constant of the active pillar; a depth of the first recess is greater than a depth of the electrically conductive structure.

[0044] In some embodiments, the conductive structure has a resistivity no greater than 20 μΩ-cm.

[0045] In some embodiments, the second dielectric layer has an air gap therein, the air gap having a depth in the second direction greater than a depth of the conductive structure.

[0046] The semiconductor structure and the manufacturing method thereof provided by some embodiments of the present disclosure, by removing part of the isolation layer to form a first recess; and depositing a first dielectric layer at least on the sidewall of the first recess to form a second recess; forming a first metal layer, the first metal layer directly covering at least the active pillar; performing a heat treatment to form a conductive structure, the first dielectric layer covering the sidewall of the conductive structure; first, the conductive structure is protected by the first dielectric layer covering the sidewall of the conductive structure, so that the morphology of the conductive structure is prevented from changing, second, the first dielectric layer is covered in advance in the process to prevent the conductive structure from changing from a low resistance state to a high resistance state, so that the resistance of the conductive structure itself is reduced, and third, the low dielectric constant of the first dielectric layer can reduce the parasitic capacitance between the conductive structures; the above problems are solved to improve the performance of the conductive structure and improve the yield of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0047] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are shown by way of illustration in the drawings and are not necessarily drawn to scale. Unless otherwise noted, the drawings provided herein are not to scale. The specific embodiments of the present disclosure will be described in sections below as being illustrated by the drawings in which like reference characters designate corresponding parts throughout the several views.

[0048] FIGS. 1A-1E are process flow diagrams of various steps in the preparation of a semiconductor structure in the related art;

[0049] FIGS. 2A-2J are process flow diagrams of one embodiment of a method of forming a semiconductor structure according to the present disclosure;

[0050] FIGS. 3A-3H are process flow diagrams of another embodiment of a method of forming a semiconductor structure according to the present disclosure;

[0051] FIGS. 4A-4H are process flow diagrams of yet another embodiment of a method of forming a semiconductor structure according to the present disclosure;

[0052] FIG. 5A is a schematic diagram of one embodiment of a semiconductor structure according to the present disclosure.

[0053] FIG. 5B is a schematic diagram of another embodiment of a semiconductor structure according to the present disclosure.

[0054] FIG. 5C is a schematic diagram of a semiconductor structure and wafer bonding structure according to the present application. DETAILED DESCRIPTION

[0055] The semiconductor structure and the forming method thereof according to the present application will be described in detail below with reference to the accompanying drawings.

[0056] As shown in FIGS. 1A-1E, the semiconductor device of the related art in the preparation process, as shown in FIG. 1A, a first metal layer 3 is formed on the active pillar 11 and the isolation layer 12, and after heat treatment, a conductive structure 4 is formed as shown in FIG. 1B. Due to the expansion of the metal layer in the process of reacting with the active pillar, the final conductive structure 4 has a large head morphology as shown in the figure. The existence of the large head morphology will affect the performance of the conductive structure itself and have an impact on the subsequent process. Secondly, as shown in FIG. 1C, in the process of forming a trench 5 by etching back part of the isolation layer 12, the side wall of the conductive structure 4 with large head morphology will be etched to form a defect A due to the lack of protection of the side wall of the conductive structure 4. Only one defect is shown here, but the defect A can exist on the side wall of each conductive structure 4. The existence of the defect A will affect the performance of the conductive structure 4. Thirdly, as shown in FIG. 1D, after the formation of the conductive structure 4, a first dielectric layer 6 is formed in the trench 5. In the process of forming the first dielectric layer 6, the defect A further forms a defect B. Since the formation temperature of the first dielectric layer 6 is higher than the heat treatment temperature, the conductive structure 4 will further react at high temperature, so that the material of the conductive structure 4 changes from a low resistance state to a high resistance state, i.e. the conductive structure 4 changes from a low resistance state to a high resistance state. The conductive structure 7 increases the resistance of the conductive structure 4 itself, affects the performance of the conductive structure 4, and increases the contact resistance between the metal and the semiconductor. Finally, as shown in FIG. 1E, a second dielectric layer 8 is formed on the first dielectric layer 6 to fill the trench 5. Since the dielectric constant of the first dielectric layer 6 is high, the parasitic capacitance between the conductive structure 4 and the conductive structure 4 will be large.

[0057] Therefore, the present application provides a semiconductor structure forming method and a semiconductor structure, which can protect the morphology of the conductive structure, reduce the existence of defects, and reduce the resistance of the conductive structure itself and the parasitic capacitance between the conductive structures.

[0058] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are presented in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0059] Fig. 2A-2J are process flow diagrams of one embodiment of the method for forming a semiconductor structure according to the present application. As shown in Fig. 2A and Fig. 2B, the method for forming a semiconductor structure according to the present application comprises the following steps: providing a substrate 1 having active pillars 11 and isolation layers 12 arranged along a first direction X, the active pillars 11 and the isolation layers 12 extending along a second direction Y, the first direction X being parallel to the surface of the substrate 1, the second direction Y being parallel to the thickness direction of the substrate 1, and the second direction Y being perpendicular to the first direction X; and removing part of the isolation layers 12 to form first recesses 201.

[0060] The substrate can be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); or can be a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI); or can be made of other materials such as a group III-V compound like gallium arsenide. In this embodiment, the substrate is made of silicon. The substrate can be doped with impurity ions as needed, and the impurity ions can be N-type or P-type.

[0061] The present application provides a method for forming the active pillars 11, which comprises the following steps, but is not limited thereto: forming a plurality of trenches in the semiconductor substrate by photolithography and etching; and filling the trenches with an isolation material to form the isolation layers 12, the isolation material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable isolation materials. In this embodiment, the isolation material is silicon oxide. The substrate separated by the isolation layers 12 is the active pillars 11. In this embodiment, as shown in Fig. 2A, the active pillars 11 and the isolation layers 12 are arranged along the first direction X, the first direction X being parallel to the surface of the substrate 1, and the active pillars 11 and the isolation layers 12 extending along the second direction Y, the second direction Y being parallel to the thickness direction of the substrate 1.

[0062] The top surface of the first recesses 201 is lower than the top surface of the active pillars 11, and the depth of the first recesses 201 can be set according to the specific process requirements.

[0063] Then, as shown in Fig. 2C-2E, a first dielectric layer 302 is deposited at least on the sidewalls of the first recesses 201 to form second recesses 202.

[0064] As shown in Fig. 2C and Fig. 2D, one embodiment of forming the first dielectric layer 302 comprises the following steps: forming a first dielectric material layer 301 covering the sidewalls and the bottom of the first recesses 201 and the top of the active pillars 11;

[0065] The first dielectric material layer 301 on the top of the active pillars 11 is removed, and the remaining first dielectric material layer 301 serves as the first dielectric layer 302, which covers the bottom of the first recesses 201 and the sidewalls of the active pillars 11 exposed by the first recesses 201.

[0066] As shown in FIGS. 2C and 2E, another specific method of forming the first dielectric layer 302 includes: forming a first dielectric material layer 301 covering the sidewalls and the bottom of the first recess 201 and the top of the active pillar 11;

[0067] The first dielectric material layer 301 on the top of the active pillar 11 and the bottom of the first recess 201 is removed, and the remaining first dielectric material layer 301 serves as the first dielectric layer 302 covering only the sidewalls of the active pillar 11 exposed by the first recess 201.

[0068] Specifically, the first dielectric material layer 301 includes but is not limited to the following methods: one of an atomic layer deposition (ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, a chemical vapor deposition (CVD) process, and a plasma enhanced chemical vapor deposition (PECVD) process can be used to form the first dielectric material layer 301.

[0069] As shown in FIG. 2D, the first dielectric material layer 301 on the top of the active pillar 11 is removed, and a chemical mechanical grinding (CMP) method can be used to grind and remove only the first dielectric material layer 301 on the top of the active pillar 11, leaving the first dielectric material layer 301 on the sidewalls and the bottom of the first recess 201; as shown in FIG. 2E, the first dielectric material layer 301 on the top of the active pillar 11 and the bottom of the first recess 201 is removed, and a dry etching process can be used to remove the first dielectric material layer 301 on the top of the active pillar 11 and the bottom of the first recess 201 by adjusting the etching angle, energy and dose, leaving only the first dielectric material layer 301 on the sidewalls of the first recess 201.

[0070] Then, as shown in FIG. 2F, a first metal layer 401 is formed, which at least directly covers the active pillar 11; specifically, the first metal layer 401 includes but is not limited to the following methods: one of an atomic layer deposition (ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, a chemical vapor deposition (CVD) process, and a plasma enhanced chemical vapor deposition (PECVD) process can be used to form the first metal layer 401. The first metal layer 401 fills the second recess 202 and covers the top of the active pillar 11. The first metal layer 401 includes but is not limited to one or more of tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), and nickel (Ni), and in this embodiment, the first metal layer 401 is preferably platinum-doped nickel (NiPt).

[0071] Then, as shown in FIG. 2G, a heat treatment is performed to form the conductive structure 501, the first dielectric layer 302 covers the sidewall of the conductive structure 501, and the conductive structure 501 extends along a third direction Z, which is perpendicular to the first direction X and the second direction Y. The specific process of performing the heat treatment to form the conductive structure includes but is not limited to the following method: the heat treatment can be a high-temperature rapid thermal processing (RTP) process. By using the RTP process, the first metal layer 401 reacts with the active pillar 11 to form a metal silicide layer, which has good conductive performance to form the conductive structure 501, and the conductive structure 501 is electrically connected to the active pillar 11.

[0072] Since the first dielectric layer 302 at least covers the sidewall of the active pillar 11, in the process of the reaction between the first metal layer 401 and the active pillar 11 to form the conductive structure 501, the first dielectric layer 302 protects the sidewall of the active pillar 11, preventing the large head morphology defect shown in FIG. 1C caused by the expansion of the reaction between the active pillar 11 and the first metal layer 401, so that the sidewall morphology of the conductive structure 501 is more perpendicular, which improves the performance of the conductive structure 501 and facilitates subsequent processes.

[0073] In addition, the temperature for forming the first dielectric layer 302 is greater than the heat treatment temperature, and the temperature for forming the first dielectric layer 302 is greater than 500°C, and the heat treatment temperature does not exceed 500°C. As shown in FIGS. 1C-1D, if the conductive structure is formed first and then the first dielectric layer is formed, since the temperature for forming the first dielectric layer is higher than the heat treatment temperature, the conductive structure will further react at high temperature, so that the material of the conductive structure changes from a low-resistance state to a high-resistance state, i.e., the conductive structure changes from a low-resistance state to a high-resistance state, which increases the resistance of the conductive structure itself and affects the performance of the conductive structure. However, in the present application, the formation of the first dielectric layer 302 is earlier than the formation process of the conductive structure 501, i.e., the first dielectric layer 302 has been formed before the formation of the conductive structure 501, and the reaction process of the first dielectric layer 302 with a higher temperature will not affect the formation of the conductive structure 501, so that the material of the conductive structure 501 will not change from a low-resistance state to a high-resistance state, which prevents the increase of the resistance of the conductive structure 501 itself, so that the performance of the conductive structure 501 itself is improved.

[0074] Specifically, the conductive structure 501 can be one or more of titanium silicide (TiSi), tantalum silicide (TaSi), nickel silicide (NiSi), cobalt silicide (CoSi), and preferably the conductive structure 501 is nickel silicide (NiSi); specifically, the thermal stability of NiSi is poor, and NiSi starts to agglomerate and transform from low-resistance NiSi to high-resistance NiSi2 when the temperature is higher than 500°C; the specific resistivity of NiSi is not greater than 20 μΩ·cm, and the specific resistivity of NiSi2 is between 24-30 μΩ·cm; the transformation of the NiSi film layer from low-resistance NiSi to high-resistance NiSi2 will seriously affect the metal-semiconductor contact characteristics, the contact resistance will increase sharply, and the device performance will decrease. Therefore, the first dielectric layer 302 with a relatively high reaction temperature is formed before the conductive structure 501, to prevent the transformation of the conductive structure 501 from low-resistance NiSi to high-resistance NiSi2, so that the resistance of the conductive structure 501 itself is reduced, the contact resistance of the metal-semiconductor is further reduced, and the device performance is improved.

[0075] Next, as shown in FIGS. 2H-2J, a second dielectric layer 601 is formed, and the second dielectric layer 601 fills the second groove 202.

[0076] Specifically, as shown in FIG. 2H, after the conductive structure 501 is formed and before the second dielectric layer 601 is formed, the first metal layer 401 is removed to re-expose the second groove 202. The first metal layer 401 can be removed by a wet etching process, or the first metal layer 401 on the top of the conductive structure 501 is removed by a CMP process first, and then the remaining first metal layer 401 is removed by a dry etching process; in the process of removing the first metal layer 401, the sidewall of the conductive structure 501 is protected by the first dielectric layer 302, which can prevent the sidewall of the conductive structure 501 from being etched and prevent the defect A shown in FIG. 1C, so that the performance of the conductive structure 501 is improved.

[0077] Specifically, as shown in FIGS. 2I-2J, the second dielectric layer 601 is filled in the re-exposed second groove 202, and the second dielectric layer 601 covers the top of the conductive structure in addition to filling the second groove 202; the second dielectric layer 601 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or other suitable isolation materials. In this specific embodiment, the second dielectric layer 601 is silicon oxide. Specifically, the formation of the second dielectric layer 601 includes but is not limited to the following methods: one of an atomic layer deposition (ALD) process, a plasma-enhanced atomic layer deposition (PEALD) process, a chemical vapor deposition (CVD) process, and a plasma-enhanced chemical vapor deposition (PECVD) process can be used to form the second dielectric layer 601.

[0078] Specifically, as shown in FIG. 2I, in one embodiment, if the first dielectric layer 302 covers the sidewall and the bottom of the first recess 201, the second dielectric layer 601 covers the first dielectric layer 302 on the sidewall and the bottom of the first recess 201, and the second dielectric layer 601 fills the second recess 202 and covers the top of the conductive structure 501; as shown in FIG. 2J, in another embodiment, if the first dielectric layer 302 only covers the sidewall of the first recess 201, the second dielectric layer 601 covers the first dielectric layer on the sidewall of the first recess 201, and the second dielectric layer 601 fills the second recess 202 and covers the top of the conductive structure 501.

[0079] Specifically, the second dielectric layer 601 can have an air gap or not have an air gap; preferably, as shown in FIGS. 2I-2J, the second dielectric layer 601 has an air gap 701, and the depth of the air gap 701 in the second direction Y is greater than the depth of the conductive structure 501. In this application, the depth of the first recess 201 is greater than the depth of the conductive structure 501, so that the depth of the air gap 701 in the second direction Y is greater than the depth of the conductive structure 501 is possible. The depth h of the conductive structure refers to the depth from the top surface of the conductive structure to the bottom of the conductive structure. As shown, the air gap 701 has a top B and a bottom C, the top B of the air gap 701 is lower than the top surface of the conductive structure 501 but higher than the bottom surface of the conductive structure 501, the bottom C of the air gap 701 is lower than the bottom surface of the conductive structure 501, and the depth H of the air gap 701 refers to the height from the direction parallel to the top surface of the conductive structure 501 to the bottom C of the air gap, as shown by H in FIGS. 2I-2J. Further, the size of the air gap 701 in the second direction Y accounts for 2 / 3-3 / 4 of the depth of the second recess 202, and the maximum size of the air gap in the first direction X accounts for 1 / 3-3 / 4 of the width of the second recess 202. Such arrangement makes the air gap 701 between the conductive structures 501, reducing the parasitic capacitance between the conductive structures 501. In addition, the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar, and the material of the first dielectric layer 302 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide or other suitable materials, and in the embodiment of this application, the first dielectric layer 302 can be carbon-doped silicon oxide; the main material of the active pillar is silicon, and the dielectric constant of silicon is between 11-12, the dielectric constant of carbon-doped silicon oxide is about 4.5, and the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar, so that the parasitic capacitance of this semiconductor structure is further reduced.

[0080] The embodiment of the present application improves the process, so that the first dielectric layer 302 with high reaction temperature is formed before the conductive structure 501, preventing the conductive structure 501 from transforming from low-resistance NiSi to high-resistance NiSi2, so that the resistance of the conductive structure 501 itself is reduced; and the existence of the first dielectric layer 302 can prevent the conductive structure 501 from having a large head morphology and further damage in the etching process; and the dielectric constant of the first dielectric layer 302 is less than that of the active pillar 11, so that the parasitic capacitance of the device is reduced; in order to further reduce the parasitic capacitance, an air gap can also be arranged between the conductive structures 501, since the relative dielectric constant of air is about 1, air can be used as a good dielectric to further reduce the parasitic capacitance between the conductive structures 501; through the above improvements, the performance of the semiconductor device can be improved and the yield of the device can be improved.

[0081] FIGS. 3A-3H are process flow diagrams of another specific embodiment of the semiconductor structure forming method of the present application; since some process steps of the present embodiment are the same as or corresponding to those of the previous embodiment, the same or corresponding parts can be referred to the previous embodiment, and the specific description can be made with reference to FIGS. 2A-2E. The semiconductor structure forming method of the present application comprises the following steps: providing a substrate 1 having active pillars 11 and isolation layers 12 arranged at intervals along a first direction X, the active pillars 11 and the isolation layers 12 extending along a second direction Y, the first direction X being parallel to the surface of the substrate 1, the second direction Y being parallel to the thickness direction of the substrate 1, and the second direction Y being perpendicular to the first direction X; removing part of the isolation layers 12 to form a first recess 201; depositing a first dielectric layer 302 at least on the sidewall of the first recess 201 to form a second recess 202; the specific method of forming the first dielectric layer 302 can comprise forming a first dielectric material layer 301 first, the first dielectric material layer 301 covering the sidewall and bottom of the first recess 201 and the top of the active pillar 11, as shown in FIGS. 2C and 2D; one specific method of forming the first dielectric layer 302 comprises: forming a first dielectric material layer 301, the first dielectric material layer 301 covering the sidewall and bottom of the first recess 201 and the top of the active pillar 11; removing the first dielectric material layer 301 on the top of the active pillar 11, and the remaining first dielectric material layer 301 serving as the first dielectric layer 302, the first dielectric layer 302 covering the bottom of the first recess 201 and the sidewall of the active pillar 11 exposed by the first recess 201. As shown in FIGS. 2C and 2E, another specific method of forming the first dielectric layer 302 comprises: forming a first dielectric material layer 301, the first dielectric material layer 301 covering the sidewall and bottom of the first recess 201 and the top of the active pillar 11; removing the first dielectric material layer 301 on the top of the active pillar 11 and the bottom of the first recess 201, and the remaining first dielectric material layer 301 serving as the first dielectric layer 302, the first dielectric layer 302 covering only the sidewall of the active pillar 11 exposed by the first recess 201. The above steps can be referred to FIGS. 2A-2E.

[0082] The main distinguishing part of still another embodiment of the present disclosure will be described in detail in conjunction with the accompanying drawings, such as FIGS. 3A-3C. After forming the first dielectric material layer 301 and before forming the first metal layer 801, the method further comprises: as shown in FIG. 3A, forming a second metal material layer 402', the second metal material layer 402' covering the first dielectric material layer 301 and filling the second recess 202; as shown in FIG. 3B, removing part of the second metal material layer 402' and part of the first dielectric material layer 301 to expose the top of the active pillar 11, the remaining second metal material layer 402' serving as the second metal layer 402, the second metal layer 402 being flush with the active pillar 11, and the remaining first dielectric material layer 301 serving as the first dielectric layer 302, the first dielectric layer 302 covering at least the sidewall of the active pillar 11. As shown in FIG. 3C, then forming the first metal layer 801 on the second metal layer 402 and the top of the active pillar 11. The first metal layer 801 and the second metal layer 402 can be the same or different materials, and the first metal layer 801 and the second metal layer 402 include but are not limited to one or more of the following materials: tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), nickel (Ni), and in this embodiment the first metal layer 801 is preferably platinum-doped nickel (NiPt).

[0083] Then as shown in FIG. 3D, heat treatment is performed to form the conductive structure 501. Since the first dielectric layer 302 covers at least the sidewall of the active pillar 11 exposed by the first recess, in the process of the first metal layer 801 reacting with the active pillar 11 to form the conductive structure 501, the first dielectric layer 302 protects the sidewall of the active pillar 11 from the large head topography defect shown in FIG. 1C caused by the active pillar 11 reacting and expanding with the first metal layer 801, so that the sidewall topography of the conductive structure 501 is relatively vertical, improving the performance of the conductive structure 501 and facilitating subsequent processes.

[0084] Since the temperature for forming the first dielectric layer 302 is greater than the heat treatment temperature, specifically, the temperature for forming the first dielectric layer 302 is greater than 500 ℃, and the heat treatment temperature is not more than 500 ℃. As shown in FIGS. 1C-1D, if the conductive structure is formed first and then the first dielectric layer is formed, since the temperature for forming the first dielectric layer is higher than the heat treatment temperature, the conductive structure will further react at high temperature, so that the material of the conductive structure changes from a low-resistance state to a high-resistance state, i.e., the conductive structure changes from a low-resistance state to a high-resistance state, so that the resistance of the conductive structure itself increases, affecting the performance of the conductive structure; but in the embodiment of the present application, the first dielectric layer 302 is formed before the formation of the conductive structure 501, i.e., the first dielectric layer 302 has been formed before the formation of the conductive structure 501, and the reaction process of the first dielectric layer 302 at a higher temperature will not affect the formation of the conductive structure 501, so that the material of the conductive structure 501 will not change from a low-resistance state to a high-resistance state, preventing the resistance of the conductive structure 501 from increasing, so that the performance of the conductive structure 501 is improved.

[0085] Specifically, the conductive structure 501 can be one or more of titanium silicide (TiSi), tantalum silicide (TaSi), nickel silicide (NiSi), and cobalt silicide (CoSi), and preferably the conductive structure 501 is nickel silicide (NiSi); specifically, NiSi has poor thermal stability, and starts to agglomerate and changes from low-resistance NiSi to high-resistance NiSi2 when the temperature is higher than 500 ℃; specifically, the resistivity of NiSi is not more than 20 μΩ·cm, and the resistivity of NiSi2 is between 24-30 μΩ·cm; the change of NiSi thin film from low-resistance NiSi to high-resistance NiSi2 will seriously affect the metal-semiconductor contact characteristics, causing the contact resistance to increase sharply and the device performance to decrease. Therefore, the first dielectric layer 302 with a higher reaction temperature is formed before the conductive structure 501, preventing the conductive structure 501 from changing from low-resistance NiSi to high-resistance NiSi2, so that the resistance of the conductive structure 501 itself is reduced, further reducing the contact resistance of the metal-semiconductor, and improving the performance of the device.

[0086] Then, as shown in FIGS. 3E and 3F, after the formation of the conductive structure 501, the first metal layer 801 and the second metal layer 402 are removed to expose the second recess 202. Specifically, as shown in FIG. 3E, a wet etching process can be used to remove the first metal layer 801 and the second metal layer 402, and as shown in FIG. 3F, after the removal of the first metal layer 801 and the second metal layer 402, part of the first dielectric layer 302 at the bottom of the second recess 202 can be further removed, and the remaining first dielectric layer 302 only covers the sidewall of the second recess 202. The first dielectric layer 302 covers the sidewall of the conductive structure 501, and the depth of the first dielectric layer 302 along the second direction Y is greater than the depth of the conductive structure 501 along the second direction Y.

[0087] Then, as shown in FIGS. 3G-3H, a second dielectric layer 601 is filled in the second recess, and the second dielectric layer 601 covers the top of the conductive structure 501 in addition to filling the second recess 202; as shown in FIG. 3G, the second dielectric layer 601 has the first dielectric layer 302 between the second dielectric layer 601 and the isolation layer 12, and as shown in FIG. 3H, the second dielectric layer 601 does not have the first dielectric layer 302 between the second dielectric layer 601 and the isolation layer 12, i.e., the second dielectric layer 601 directly contacts the isolation layer 12.

[0088] Specifically, the second dielectric layer 601 can have an air gap or can not have an air gap; preferably, as shown in FIGS. 3G-3H, the second dielectric layer 601 has an air gap 701, and the depth of the air gap 701 in the second direction Y is greater than the depth of the conductive structure 501. In the present application, the depth of the first recess 201 is greater than the depth of the conductive structure 501, so that the depth of the air gap 701 in the second direction Y is greater than the depth of the conductive structure 501 is possible. The depth h of the conductive structure refers to the depth from the top surface of the conductive structure to the bottom of the conductive structure. As shown, the air gap 701 has a top B and a bottom C, the top B of the air gap 701 is lower than the top surface of the conductive structure 501 but higher than the bottom surface of the conductive structure 501, the bottom C of the air gap 701 is lower than the bottom surface of the conductive structure 501, and the depth H of the air gap 701 refers to the height from the direction parallel to the top surface of the conductive structure 501 to the bottom C of the air gap, as shown by H in FIGS. 3G-3H. Further, the size of the air gap 701 in the second direction Y accounts for 2 / 3-3 / 4 of the depth of the second recess 202, and the maximum size of the air gap in the first direction X accounts for 1 / 3-3 / 4 of the width of the second recess 202. Such arrangement makes the air gap 701 between the conductive structures 501, reducing the parasitic capacitance between the conductive structures 501. In addition, the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar, and the material of the first dielectric layer 302 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide, or other suitable materials, and in the embodiments of the present application, the first dielectric layer 302 can be carbon-doped silicon oxide; the main material of the active pillar is silicon, and the dielectric constant of silicon is between 11-12, the dielectric constant of carbon-doped silicon oxide is about 4.5, and the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar, so that the parasitic capacitance of the semiconductor structure is further reduced.

[0089] The embodiment of the present application improves the process, so that the first dielectric layer 302 with high reaction temperature is formed before the conductive structure 501, preventing the conductive structure 501 from transforming from low-resistance NiSi to high-resistance NiSi2, so that the resistance of the conductive structure 501 itself is reduced; and the existence of the first dielectric layer 302 can prevent the conductive structure 501 from having a large head morphology and further damage in the etching process; and the dielectric constant of the first dielectric layer 302 is less than that of the active pillar 11, so that the parasitic capacitance of the device is reduced; in order to further reduce the parasitic capacitance, an air gap can be arranged between the conductive structures 501, since the relative dielectric constant of air is about 1, which can be used as a good dielectric to further reduce the parasitic capacitance between the conductive structures 501; through the above improvements, the performance of the semiconductor device can be improved and the yield of the device can be improved.

[0090] FIGS. 4A-4H are process flow diagrams of another specific embodiment of the semiconductor structure forming method of the present application; since some process steps of the present embodiment are the same as or corresponding to those of the above embodiments, the same or corresponding parts can be referred to the foregoing embodiments, and the specific embodiments can be referred to FIGS. 2A-2E. The semiconductor structure forming method of the present application comprises the following steps: providing a substrate 1 having active pillars 11 and isolation layers 12 arranged at intervals along a first direction X, the active pillars 11 and the isolation layers 12 extending along a second direction Y, the first direction X being parallel to the surface of the substrate 1, the second direction Y being parallel to the thickness direction of the substrate 1, and the second direction Y being perpendicular to the first direction X; removing part of the isolation layers 12 to form first grooves 201; depositing a first dielectric layer 302 at least on the sidewalls of the first grooves 201 to form second grooves 202; the specific method for forming the first dielectric layer 302 can comprise forming a first dielectric material layer 301 first, the first dielectric material layer 301 covering the sidewalls and bottom of the first grooves 201 and the top of the active pillars 11; the above steps can be referred to FIGS. 2A-2E.

[0091] The main difference of another embodiment of the present disclosure will be described in detail in combination with the drawings, as shown in FIGS. 4A-4C. After forming the first dielectric material layer 301 and before forming the first metal layer 801, it further comprises: as shown in FIG. 4A, forming a third dielectric material layer 901, the third dielectric material layer 901 covering the first dielectric material layer 301 and filling the second grooves 202; as shown in FIG. 4B, removing part of the third dielectric material layer 901 and part of the first dielectric material layer 301 to expose the top of the active pillars 11, the remaining third dielectric material layer 901 serving as a third dielectric layer 902, and the remaining first dielectric material layer 301 serving as a first dielectric layer 302, the third dielectric layer 902 being flush with the active pillars 11; the specific method can use a CMP process to remove part of the third dielectric material layer 901 and part of the first dielectric material layer 301. Then, as shown in FIG. 4C, the first metal layer 801 is formed on the third dielectric layer 902 and the top of the active pillars 11.

[0092] Then, as shown in FIG. 4D, a heat treatment is performed to form the conductive structure 501. Since the first dielectric layer 302 covers the sidewall of the active pillar 11, the first dielectric layer 302 protects the sidewall of the active pillar 11 from reacting with the first metal layer 801 to form the conductive structure 501, preventing the active pillar 11 from reacting with the first metal layer 801 to expand and form the large head topography defect shown in FIG. 1C, so that the sidewall topography of the conductive structure 501 is more perpendicular, improving the performance of the conductive structure 501 and facilitating subsequent processes.

[0093] Since the temperature at which the first dielectric layer 302 is formed is greater than the heat treatment temperature, specifically, the temperature at which the first dielectric layer 302 is formed is greater than 500°C, and the heat treatment temperature does not exceed 500°C. As shown in FIGS. 1C-1D, if the conductive structure is formed first and then the first dielectric layer is formed, since the temperature at which the first dielectric layer is formed is higher than the heat treatment temperature, the conductive structure will further react at high temperature, causing the material of the conductive structure to change from a low-resistance state to a high-resistance state, i.e., from a low-resistance conductive structure to a high-resistance conductive structure, increasing the resistance of the conductive structure itself and affecting the performance of the conductive structure; but in the embodiment of the present application, the formation of the first dielectric layer 302 is earlier than the formation of the conductive structure 501, i.e., the first dielectric layer 302 has been formed before the formation of the conductive structure 501, so the reaction process of the first dielectric layer 302 at a higher temperature will not affect the formation of the conductive structure 501, so that the material of the conductive structure 501 will not change from a low-resistance state to a high-resistance state, preventing the resistance of the conductive structure 501 from increasing, so that the performance of the conductive structure 501 is improved.

[0094] Specifically, the conductive structure 501 can be one or more of titanium silicide (TiSi), tantalum silicide (TaSi), nickel silicide (NiSi), and cobalt silicide (CoSi), and preferably the conductive structure 501 is nickel silicide (NiSi); specifically, NiSi has poor thermal stability and starts to clump when the temperature is higher than 500°C, and the low-resistance NiSi starts to change to high-resistance NiSi2, specifically, the resistivity of NiSi is not greater than 20 μΩ·cm, and the resistivity of NiSi2 is between 24-30 μΩ·cm; the change of the NiSi thin film from low-resistance NiSi to high-resistance NiSi2 will seriously affect the metal-semiconductor contact characteristics, the contact resistance will increase sharply, and the device performance will decrease. Therefore, the first dielectric layer 302 with a higher reaction temperature is formed before the conductive structure 501, preventing the conductive structure 501 from changing from low-resistance NiSi to high-resistance NiSi2, reducing the resistance of the conductive structure 501 itself, further reducing the contact resistance of the metal-semiconductor, and improving the performance of the device.

[0095] Then, as shown in FIG. 4E and FIG. 4F, after the conductive structure 501 is formed, the first metal layer 801 and the third dielectric layer 902 are removed to expose the second recess 202. Specifically, as shown in FIG. 4E, a wet etching process can be used to remove the first metal layer 801 and the third dielectric layer 902; in one embodiment, the first metal layer 801 can be removed by wet etching first, and then the third dielectric layer 902 can be removed by wet etching; in another embodiment, the first metal layer 801 can be removed by CMP, and then the third dielectric layer 902 can be removed by wet etching. As shown in FIG. 4F, after the first metal layer 801 and the third dielectric layer 902 are removed, part of the first dielectric layer 302 at the bottom of the second recess 202 can be further removed, and the remaining first dielectric layer 302 only covers the sidewall of the second recess 202. The first dielectric layer 302 covers the sidewall of the conductive structure 501, and the depth of the first dielectric layer 302 along the second direction Y is greater than the depth of the conductive structure 501 along the second direction Y.

[0096] Then, as shown in FIG. 4G-4H, the second dielectric layer 601 is filled in the second recess, and the second dielectric layer 601 covers the top of the conductive structure 501 in addition to filling the second recess; as shown in FIG. 4G, the second dielectric layer 601 has the first dielectric layer 302 between the second dielectric layer 601 and the isolation layer 12, and as shown in FIG. 4H, the second dielectric layer 601 does not have the first dielectric layer 302 between the second dielectric layer 601 and the isolation layer 12, i.e., the second dielectric layer 601 directly contacts the isolation layer 12.

[0097] The second dielectric layer 601 can have or not have an air gap. Preferably, as shown in FIGS. 4G-4H, the second dielectric layer 601 has an air gap 701, and the depth of the air gap 701 in the second direction Y is greater than the depth of the conductive structure 501. In the present application, the depth of the first recess 201 is greater than the depth of the conductive structure 501, so that the depth of the air gap 701 in the second direction Y is greater than the depth of the conductive structure 501. The depth h of the conductive structure refers to the depth from the top surface of the conductive structure to the bottom of the conductive structure. As shown, the air gap 701 has a top B and a bottom C, the top B of the air gap 701 is lower than the top surface of the conductive structure 501 but higher than the bottom surface of the conductive structure 501, the bottom C of the air gap 701 is lower than the bottom surface of the conductive structure 501, and the depth H of the air gap 701 refers to the height from the direction parallel to the top surface of the conductive structure 501 to the bottom C of the air gap, as shown by H in FIGS. 3G-3H. Further, the size of the air gap 701 in the second direction Y accounts for 2 / 3-3 / 4 of the depth of the second recess 202, and the maximum size of the air gap in the first direction X accounts for 1 / 3-3 / 4 of the width of the second recess 202. Such arrangement allows the air gap 701 to be between the conductive structures 501, thereby reducing the parasitic capacitance between the conductive structures 501. In addition, the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar, and the material of the first dielectric layer 302 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide, or other suitable materials. In the embodiments of the present application, the first dielectric layer 302 can be carbon-doped silicon oxide. The main material of the active pillar is silicon, and the dielectric constant of silicon is between 11 and 12. The dielectric constant of carbon-doped silicon oxide is about 4.5. The dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar, so that the parasitic capacitance of the semiconductor structure is further reduced.

[0098] The embodiments of the present application improve the process to form the first dielectric layer 302 before the conductive structure 501 at a relatively high reaction temperature, prevent the conductive structure 501 from converting from low-resistance NiSi to high-resistance NiSi2, and reduce the resistance of the conductive structure 501 itself. The presence of the first dielectric layer 302 can prevent the conductive structure 501 from having a large head morphology and further damage during the etching process. Further, the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar 11, so that the parasitic capacitance of the device is reduced. In order to further reduce the parasitic capacitance, an air gap can be provided between the conductive structures 501. Since the relative dielectric constant of air is about 1, air can be used as a good dielectric to further reduce the parasitic capacitance between the conductive structures 501. Through the above improvements, the performance of the semiconductor device can be improved, and the yield of the device can be improved.

[0099] FIG. 5A is a structural schematic diagram of a specific embodiment of a semiconductor structure of the present application.

[0100] The semiconductor structure comprises a substrate 1, the substrate 1 has active pillars 11 and isolation layers 12 arranged at intervals along a first direction X, the active pillars 11 and the isolation layers 12 both extend along a second direction Y, the first direction X is parallel to the surface of the substrate 1, the second direction Y is parallel to the thickness direction of the substrate 1, and the second direction Y is perpendicular to the first direction X; a conductive structure 501 is electrically connected with the active pillars 11, the conductive structure 501 extends along a third direction Z, and the third direction Z is perpendicular to the first direction X and the second direction Y. Specifically, the active pillars 11 are arranged at intervals along the first direction X and the third direction Z, and the active pillars 11 are isolated by the isolation layers 12. A first recess 201 is shown by a solid line in the enlarged view and is located between adjacent conductive structures 501; a second recess 202 is shown by a dashed line in the enlarged view and is located in the first recess 201; a first dielectric layer 302 is located between the first recess 201 and the second recess 202 and covers at least the sidewall of the conductive structure 501; and a second dielectric layer 601 fills the second recess 202 and covers the top of the conductive structure 501.

[0101] As shown in FIG. 5A, the first dielectric layer 302 is located at the bottom and the sidewall of the first recess 201. In a specific embodiment, the first dielectric layer 302 can be located only at the sidewall of the first recess 201.

[0102] Specifically, the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar 11; and the depth H1 of the first recess 201 is greater than the depth h of the conductive structure. The depth H1 of the first recess 201 refers to the depth from the direction parallel to the conductive structure 501 to the bottom of the first recess 201, and the depth h of the conductive structure refers to the depth from the top surface of the conductive structure to the bottom of the conductive structure. The resistivity of the conductive structure is not greater than 20 μΩ·cm, and the material of the conductive structure can be NiSi. The second dielectric layer 601 has an air gap 701, and the depth H of the air gap 701 in the second direction Y is greater than the depth h of the conductive structure 501. For other same or corresponding parts, refer to the corresponding description of the foregoing embodiments.

[0103] The presence of the first dielectric layer 302 can prevent the conductive structure 501 from appearing as a large head and further damage during the etching process; it can also prevent the conductive structure 501 from being converted from low-resistance NiSi to high-resistance NiSi2, so that the resistance of the conductive structure 501 itself is reduced; and the dielectric constant of the first dielectric layer 302 is less than the dielectric constant of the active pillar 11, so that the parasitic capacitance of the device is reduced. In order to further reduce the parasitic capacitance, an air gap can be provided between the conductive structures 501, since the relative dielectric constant of air is about 1, which can be used as a good dielectric to further reduce the parasitic capacitance between the conductive structures 501. Through the above improvements, the performance of the semiconductor device can be improved, and the yield of the device can be improved.

[0104] Fig. 5B is a structural schematic diagram of another embodiment of the semiconductor structure of the present application.

[0105] As shown in Fig. 5B, on the basis of Fig. 5A, the substrate 1 further comprises a word line structure 10, which is arranged around the active pillar 11, the active pillars 11 are arranged at intervals along the first direction X and the third direction Z, and the active pillars 11 are isolated by the isolation layer 12; one end of the active pillar 11 is electrically connected with the conductive structure 501, which can be a bit line structure, and the other end of the active pillar 11 is electrically connected with the capacitor structure 20, and the adjacent capacitor structures are isolated by the fourth dielectric layer 30. In this embodiment, the semiconductor structure can be a gate-all-around (GAA) structure or a vertical channel transistor (VCT) structure.

[0106] Fig. 5C is a structural schematic diagram of a memory device formed by bonding the semiconductor structure and a wafer.

[0107] As shown in Fig. 5C, the memory device comprises a first wafer 40 and a second wafer 50, the first wafer 40 has the semiconductor structure described above, and the second wafer 50 comprises a control circuit, and the first wafer 40 and the second wafer 50 are bonded to form the memory device.

[0108] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined in the claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, Comprising: providing a substrate (1) having active pillars (11) and isolation layers (12) spaced apart along a first direction (X), the active pillars (11) and the isolation layers (12) both extending along a second direction (Y), the first direction (X) being parallel to a surface of the substrate (1), the second direction (Y) being parallel to a thickness direction of the substrate (1), the second direction (Y) being perpendicular to the first direction (X); removing part of the isolation layers (12) to form first recesses (201); depositing a first dielectric layer (302) at least on sidewalls of the first recesses (201) to form second recesses (202); forming a first metal layer (401, 801) directly covering at least the active pillars (11); performing a thermal treatment to form electrically conductive structures (501), the first dielectric layer (302) covering sidewalls of the electrically conductive structures (501), the electrically conductive structures (501) extending along a third direction (Z), the third direction (Z) being perpendicular to the first direction (X) and the second direction (Y); forming a second dielectric layer (601) filling the second recesses (202).

2. The production method according to claim 1, wherein The forming of the first dielectric layer (302) specifically comprises: forming a first dielectric material layer (301) covering sidewalls and bottoms of the first recesses (201) and tops of the active pillars (11); removing the first dielectric material layer (301) from the tops of the active pillars (11), the remaining first dielectric material layer (301) serving as the first dielectric layer (302).

3. The production method according to claim 1, wherein The forming of the first dielectric layer (302) specifically comprises: forming a first dielectric material layer (301) covering sidewalls and bottoms of the first recesses (201) and tops of the active pillars (11); removing the first dielectric material layer (301) from the tops of the active pillars (11) and the bottoms of the first recesses (201), the remaining first dielectric material layer (301) serving as the first dielectric layer (302).

4. The manufacturing method of any one of claims 2 or 3, wherein: the first metal layer (401, 801) fills the second recesses (202) and covers the tops of the active pillars (11).

5. The production method according to any one of claims 2 or 3, wherein After forming the first dielectric material layer (301) and before forming the first metal layer (401, 801), further comprising: forming a second metal material layer (402') covering the first dielectric material layer (301) and filling the second recesses (202), removing part of the second metal material layer (402') and part of the first dielectric material layer (301) to expose the tops of the active pillars (11), the remaining second metal material layer (402') serving as a second metal layer (402), the second metal layer (402) being flush with the active pillars (11); Forming the first metal layer (401, 801) on the second metal layer (402) and on top of the active pillar (11).

6. The production method according to any one of claims 2 or 3, wherein After forming the first dielectric material layer (301) and before forming the first metal layer (401, 801), further comprising: forming a third dielectric material layer (901) covering the first dielectric material layer (301) and filling the second recess (202), removing part of the third dielectric material layer (901) and part of the first dielectric material layer (301) to expose top of the active pillar (11), the remaining third dielectric material layer (901) as a third dielectric layer (902) which is flush with the active pillar (11); forming the first metal layer (401, 801) on the third dielectric layer (902) and on top of the active pillar (11).

7. The production method according to claim 4, wherein After forming the conductive structure (501) and before forming the second dielectric layer (601), further comprising: removing the first metal layer (401, 801) to re-expose the second recess (202).

8. The production method according to claim 5, wherein After forming the conductive structure (501) and before forming the second dielectric layer (601), further comprising: removing the first metal layer (401, 801) and the second metal layer (402) to re-expose the second recess (202).

9. The production method according to claim 6, wherein After forming the conductive structure (501) and before forming the second dielectric layer (601), further comprising: removing the first metal layer (401, 801) and the third dielectric layer (902) to re-expose the second recess (202).

10. The production method according to claim 1, wherein The depth of the first recess (201) is greater than the depth of the conductive structure (501); the dielectric constant of the first dielectric layer (302) is less than the dielectric constant of the active pillar (11); the temperature for forming the first dielectric layer (302) is greater than the temperature of the heat treatment, and the resistivity of the conductive structure (501) is not greater than 20 μΩ·cm.

11. The production method according to claim 1, wherein The second dielectric layer (601) has an air gap (701), and the depth of the air gap (701) in the second direction (Y) is greater than the depth of the conductive structure (501).

12. A semiconductor structure, characterized by Comprising: a substrate (1) having active pillars (11) and isolation layers (12) spaced apart along a first direction (X), the active pillars (11) and the isolation layers (12) both extending along a second direction (Y), the first direction (X) being parallel to the surface of the substrate (1), the second direction (Y) being parallel to the thickness direction of the substrate (1), and the second direction (Y) being perpendicular to the first direction (X); a conductive structure (501) electrically connected to the active pillar (11), the conductive structure (501) extending along a third direction (Z), the third direction (Z) being perpendicular to the first direction (X) and the second direction (Y); a first recess (201) between adjacent conductive structures (501); a second recess (202) located in the first recess (201); a first dielectric layer (302) located between the first recess (201) and the second recess (202) and covering at least a sidewall of the conductive structure (501); a second dielectric layer (601) filling the second recess (202) and covering a top of the conductive structure (501).

13. The semiconductor structure of claim 12, wherein, The first dielectric layer (302) has a dielectric constant less than that of the active pillar (11); and the first recess (201) has a depth greater than that of the conductive structure (501).

14. The semiconductor structure of claim 12, wherein, The conductive structure (501) has a resistivity not greater than 20 μΩ·cm.

15. The semiconductor structure of claim 12, wherein, The second dielectric layer (601) has an air gap (701) therein, the air gap (701) having a depth in the second direction (Y) greater than that of the conductive structure (501).

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