Methods for controlling a converter, control devices for controlling a converter and converters

Abstract

The present disclosure relates to a method for controlling a converter comprising a converter section, and a series connection of a first and second capacitor unit. The converter section comprises a first and second power converter each comprising a first, second and third terminal. For controlling a conversion of a voltage at the first terminal of each power converter to a further voltage of lower or higher level at the second and third terminal of each power converter the method comprises: generating for each of controllable semiconductor switches of the first and second power converter a different duty cycle for switching the controllable semiconductor switch by computing a single duty cycle with regard to a maximum power point tracking, and computing the duty cycle for switching the controllable semiconductor switch using the single duty cycle and at least one of a first, second and third correction parameter.

Description

[0001] METHODS FOR CONTROLLING A CONVERTER, CONTROL DEVICES FOR CONTROLLING A CONVERTER AND CONVERTERS

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to methods for controlling a converter, control devices for controlling a converter and converters.

[0004] BACKGROUND

[0005] Solar energy may be translated into electrical energy by solar photovoltaic (PV) panels, e.g. PV arrays. The electrical energy translated from solar energy is in the form of direct current (DC) energy. Eventually, the DC electric energy is delivered to alternating current (AC) power systems by means of power electronic conversion systems. Consumption and loads may use the electrical energy in the form of AC energy. Examples of loads may comprise home appliances, industry motors, etc.

[0006] SUMMARY

[0007] A power converter system for converting DC power to AC power may comprise two stages. A first stage may comprise or be a DC-to-DC power converter stage. That is, one level of DC voltage or current may be converted to a lower or greater level of DC voltage or current. For example, a DC voltage or current may be converted to a lower or greater DC voltage or current (i.e. voltage or current of lower or higher level), respectively. The second stage may comprise or be a DC-to-AC power converter stage, which may be referred to as inverter stage. That is, DC power may be converted to AC power. For example, a DC voltage or current may be converted to an AC voltage or current, respectively. Optionally, the power converter system may be bidirectional. In this case, the second stage may be configured to be an AC-to-DC power converter stage. That is, AC power may be converted to DC power.

[0008] In case a PV system, such as a PV array or PV panel, is electrically connected to a DC-to-DC power converter stage, the DC- to-DC converter stage may be configured to boost an input DC voltage provided by the PV array or panel to a value higher at the output of the DC-to-DC converter stage. The terms “solar PV” and, thus, “solar PV system” may be used as synonyms for the terms “PV” and “PV system”, respectively.

[0009] In view of the above, this disclosure aims to provide a converter for a DC-to-DC conversion that is improved with regard to at least one of losses of semiconductor switches used in the converter for controlling the converter, costs and size. An objective of this disclosure is to provide such a converter that allows guaranteeing a maximum energy being harvested from a PV system, when the converter is directly connected with the PV system for converting the DC voltage provided by the PV system.

[0010] These and other objectives are achieved by the solution of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0011] Herein, the terms “electrically connect” and “connect” are used as synonyms. The term “controlled semiconductor switch” may be used as a synonym for the term “controllable semiconductor switch”. The term “controllable semiconductor switch” means a semiconductor switch comprising a control terminal, such as a transistor, a thyristor, triac etc. The controllable semiconductor switch may be controlled via the control terminal to switch between the conducting state (i.e. on-state) and the non-conducting state (i.e. off-state). Herein, controllable semiconductor switches may be power semiconductor transistors, such as an insulated- gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). Using MOSFET instead of IGBTS for the controllable semiconductor switches has the following advantages: The operation speed of a MOSFET is faster than the operation speed of a similar rated IGBT. Power losses of a MOSFET are typically lower than power losses of a similar rated IGBT.

[0012] Herein, controllable semiconductor switches may be transistors. A controllable semiconductor switch being a transistor may be an insulated-gate bipolar transistor (IGBT), a field-effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistors (BJT) or a junction gate field-effect transistor (JFET). Optionally, a controllable semiconductor switch may be a semiconductor switch with a diode associated to it. For example, a controllable semiconductor switch may be a transistor, such as a IGBT, with a diode connected in anti-parallel to the transistor. That is, in case a controllable semiconductor switch is a transistor, optionally a diode is connected in anti-parallel to the transistor. For example, a controllable semiconductor switch may be a transistor, such as a MOSFET, comprising an intrinsic body diode. The diode and intrinsic body diode are examples of an “uncontrollable semiconductor switch”, which may be referred to as “uncontrolled semiconductor switch”.

[0013] The term “uncontrollable semiconductor switch” means a semiconductor switch without a control terminal that allows a unidirectional current flow, that is a current flow in one direction. Examples of an “uncontrollable semiconductor switch” are a diode (may be referred to as “p-n semiconductor diode”), a pin diode, a Schottky diode, an intrinsic body diode of a respective device / transistor etc.

[0014] Herein, the terms “coil”, “choke” and “reactor” may be used as a synonym for the term “inductor”.

[0015] A first aspect of this disclosure provides a method for controlling a converter. The converter comprises a converter section, and a series connection of a first and second capacitor unit. The converter section comprises a first, second, third and fourth terminal for receiving DC voltages. The converter section comprises a first and second power converter each comprising a first, second and third terminal, a capacitor, a first switch unit comprising two semiconductor switches electrically connected in series between the second terminal of the power converter and a node, and a second switch unit comprising two semiconductor switches electrically connected in series between the node and the third terminal of the power converter. The node is electrically connected via an inductor to the first terminal of the power converter and the capacitor is electrically connected with a midpoint between the two semiconductor switches of the first switch unit and a midpoint between the two semiconductor switches of the second switch unit. The switches of the second switch unit of the first power converter and the switches of the first switch unit of the second power converter are controllable semiconductor switches. The first terminal of the first power converter is electrically connected with the second terminal of the converter section. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter section is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter section. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter section is electrically connected with the second terminal of the second capacitor unit. The method comprises measuring a current and a voltage at the first terminal and a voltage at the capacitor of each of the first and second power converter, and measuring a voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. For controlling a conversion of a voltage at the first terminal of each power converter to a further voltage of lower or higher level at the second and third terminal of each power converter the method comprises: generating for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch by: computing, using the measured current and voltage at the first terminal of the first power converter and the measured current and voltage at the first terminal of the second power converter, a single duty cycle with regard to a maximum power point tracking (MPPT); computing, using the measured voltages of the first and second capacitor unit and measured voltages of the capacitor of the first and second power converter, a first correction parameter for balancing the voltages of the first and second capacitor unit, a second correction parameter for balancing the voltages of the capacitor of the first power converter and capacitor of the second power converter, and a third correction parameter for keeping an average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter smaller than 50% of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit; and computing the duty cycle for switching the controllable semiconductor switch using the single duty cycle and at least one of the first, second and third correction parameter.

[0016] Computing the single duty cycle with regard to MPPT (i.e. performing an MPPT algorithm) for controlling the controllable semiconductor switches of the first and second power converter allows harvesting a maximum energy from electrical energy sources, e.g. voltage sources or current sources, that may be connected to the first, second, third and fourth terminal of the converter section. Such electrical sources may be PV systems, such as PV panels or PV arrays. For example, the first, second, third and fourth terminal of the converter section may be connected to PV systems, such as PV panels or PV arrays. In this case, computing the single duty cycle with regard to MPPT (i.e. performing the MPPT algorithm) for controlling the switches of the first and second power converter allows ensuring that the PV systems produce the maximum available energy. The first and third terminal may be configured to be electrically connected with a first electrical energy source (e.g. first voltage source) and the second and fourth terminal may be configured to be electrically connected with a second electrical energy source (e.g. second voltage source). The first and second electrical energy source may be a first and second PV system, the PV system comprising or being one or more PV panels and / or PV arrays. The first and second sources may be a first and second battery, optional rechargeable batteries. The term “battery energy storage (BES)” may be used as a synonym for the term “battery”. The converter controlled by the method of the first aspect allows providing a low loss MPPT operation. This allows an increase of an extraction of energy from energy sources, e.g. solar PV energy from PV systems, that may be connected to the first, second, third and fourth terminals of the converter section. In other words, this allows increasing PV yield due to low losses in the converter, e.g. low losses in the DC-to-DC conversion.

[0017] Computing the first correction parameter and / or second correction parameter (i.e. performing a balancing algorithm) for controlling the controllable semiconductor switches allows maintaining the electrical energies (e.g. voltages, such as DC voltages) of the first and second capacitor unit and / or the capacitor of the first power converter and capacitor of the second power converters, respectively, at controlled levels. This eliminates the need for any hardware for further control and balancing of the electrical energies of the first and second capacitor units and the capacitors of the first and second power converter. This allows reducing the size of the converter, increasing the energy efficiency of the conversion and reducing the overall costs for producing the converter.

[0018] Computing the third correction parameter allows keeping the average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter smaller than 50% of the total voltage across the first and second capacitor unit. This prevents charging the capacitor of the first and second power converter beyond its rated value.

[0019] Generating different duty cycles for switching the different controllable semiconductor switches allows a balancing of the capacitors of the first and second power converter and the first and second capacitor unit without the need of the converter comprising a hardware balancer. This allows saving significantly cost, weight, volume and losses. Especially, the duty cycles represent a control degree of freedom.

[0020] In case, a PV system (e.g. PV string) is connected with the first terminal of each of the first and second power converter, and the two PV systems are fairly similar and operate under similar conditions (which is the case in most of large-scale PV plants), operation at the single duty cycle allows ensuring both PV systems operating at or very close to their respective maximum power point (MPP). Once the set-point for duty cycle of the switches is determined in the form of the single duty cycle, the first aspect proposes computing correction factors on control objectives, such as balance of voltages of the first and second capacitor unit, balance of the voltages of the capacitors of the first and second power converter etc. These correction factors are used in combination with the computed single duty cycle (being the reference duty cycle) to obtain the different duty cycles of individual controllable semiconductor switches.

[0021] The method steps may be repeated (e.g. at a control frequency). The computed different duty cycles may be provided to control means, e.g. a modulator, for generating different control signals (e.g. PWM signals) for controlling the different controllable semiconductor switches of the first and second power converter of the converter section. Thus, the method of the first aspect allows both, operating PV systems at or very close to their respective MPP and balancing of voltages of the capacitors of the power converters and capacitor units, without a hardware balancer circuit, such as a hardware resonant balancer stage, being present in the converter. This translates to significant saving in the cost, weight, volume as well as incurred losses of the converter.

[0022] The converter may be a DC-to-DC converter. Optionally, the converter may be a DC-to-DC converter stage that feeds a DC- to-AC converter stage (i.e. an inverter stage). The converter may be configured to boost DC voltage(s) received at the first, second, third and fourth terminals of the converter, i.e. convert a received DC voltage to a voltage of higher level. The converter controlled by the method of the first aspect being a DC-to-DC converter stage and a DC-to-AC converter stage being fed by the converter may interface a PV system and a grid. That is, they may be used to convert the DC voltage / direct current provided by the PV system to an AC voltage / altemating current for the grid. The first and second capacitor unit may be referred to as “first DC link capacitor unit” and “second DC link capacitor unit”, respectively. Thus, the voltage of the first and second capacitor unit may be referred to as “first DC link voltage” and “second DC link voltage”, respectively. The sum of the voltage of the first and second capacitor unit may be referred to as ‘Total DC link voltage”.

[0023] The converter allows, due to its structure, a partial power processing for overall power conversion. In a partial power processing, a majority of the power from the source (feeding the converter) is directed to the load side (which provides power to a load when the load is connected to the converter) without any switching, while a small portion of the power is processed by means of the first power converter and second power converter of the converter. In this case, the first and second power converter may be partial power converters. The term “partially rated power converter” may be used as a synonym for the term “partial power converter”. The converter can maintain the voltage at the first and second capacitor unit at predefined level, maintain the voltage at the capacitor of the first and second power converter at predefined level as well as maintain the MPPT point of an input source to the first, second, third and fourth terminals of the converter. At all input variations of voltage source connectable to the first, second, third and fourth terminal of the converter section, first and second power converter operate a smaller portion of the total power, and therefore, may be implemented using low voltage and / or low current semiconductor devices, such as low voltage and / or low current controllable semiconductor switches. Such low voltage and / or low current semiconductor devices are lower in costs compared to semiconductor devices rated for higher voltage and / or higher current. Low voltage and / or low current semiconductor devices can be switched faster and at high frequencies compared to semiconductor devices rated for higher voltage and / or higher current. Therefore, size of passive elements (such as inductors and capacitors) used in the power converters can be reduced considerably. These devices dissipate lower losses resulting lower cooling and heatsink requirements. As a result, the converter controlled by the method of the first aspect is improved with regard to efficiency, costs and size. In addition, the converter is improved with regard to losses of semiconductor switches used in the converter for controlling the converter. Thus, the converter allows a scalability for higher voltage applications without compromising efficiency, size and cost. The terms “converter circuit”, “converter device” or “converter module” may be used as a synonym for the term “converter”. The components of the converter may be arranged in a housing of the converter.

[0024] Herein, a voltage at the first terminal of a power converter (e.g. first or second power converter) means a voltage between the first terminal of the power converter and a further terminal, e.g. a terminal of the converter. Herein, a voltage at the second and third terminal of a power converter (e.g. first or second power converter) means a voltage between the second and third terminal of the power converter.

[0025] Herein, measuring a voltage at the first terminal of each of the first and second power converter means measuring the voltage at the first terminal of each of the first and second power converter with regard to the fourth terminal or first terminal of the converter section, respectively. That is, measuring the voltage at the first terminal of the first power converter means measuring the voltage between the second and fourth terminal of the converter section (the first terminal of the first power converter is electrically connected with the second terminal of the converter section). Accordingly, measuring the voltage at the first terminal of the second power converter means measuring the voltage between the third and first terminal of the converter section (the first terminal of the second power converter is electrically connected with the third terminal of the converter section).

[0026] Herein, measuring a voltage at the capacitor of each of the first and second power converter means measuring the voltage between the two terminals of the capacitor of each of the first and second power converter.

[0027] Herein, controlling the controllable semiconductor switches means controlling switching of the controllable semiconductor switches. Herein, generating for a controllable semiconductor a duty cycle for switching the controllable semiconductor switch may mean or comprise generating a control signal having said duty cycle (and optionally providing the control signal to the controllable semiconductor switch) in order to control the controllable semiconductor switch. The control signal may be for example a pulse width modulated (PWM) signal. Thus, generating for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch means generating for each of the controllable semiconductor switches a different control signal, wherein the control signals differ from each other in that they have a different duty cycle. In other words, this means generating for each of the controllable semiconductor switches a control signal having a different duty cycle.

[0028] The duty cycle of the control signal, e.g. PWM signal, may determine the ratio between the on-time and the sum of the on-time and off-time for a respective controllable semiconductor switch being controlled by the control signal (and for which the duty cycle is generated). The sum of the on-time and off-time is the period (inverse of the frequency) of the control signal. The on- time is the time during which the controllable semiconductor switch is in the conducting state and the off-time is the time during which the controllable semiconductor switch is in the non-conducting state. The frequency (i.e. inverse period) of the control signal may be kept constant. That is, for controlling a respective controllable semiconductor switch with a control signal, the duty cycle of the control signal (i.e. the duty cycle generated for the respective controllable semiconductor switch) may be controlled (e.g. changed). Hereby, the frequency of the control signal and, thus, of switching the respective controllable semiconductor switch may be kept constant.

[0029] The passages “voltages of the capacitor of the first and second power converter” and “voltages of the capacitor of the first power converter and capacitor of the second power converter” are to be understood as synonyms. They refer to the “voltage of the capacitor of the first power converter and voltage of the capacitor of the second power converter”.

[0030] Optionally, the third correction parameter is for keeping an average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter at around a quarter of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit. The passage “at around a quarter” may be understood as “between 20% and 30%”. For example, the third correction parameter is for keeping an average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter at a quarter of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit.

[0031] The present disclosure is not limited to a specific type of MPPT algorithm. Thus, any known MPPT algorithm may be used.

[0032] The converter may be an MPPT-DC-to-DC converter. The converter may be configured to employ the MPPT algorithm to extract the most energy possible from a photovoltaic (PV) system. The maximum power point (MPP) is the voltage and current at which a PV system may generate its maximum power. In other words, the MPP is the operating point at which a PV system generates its maximum power at those environmental conditions.

[0033] The capacitor of each of the first and second power converter may be referred to as “flying capacitor”.

[0034] In an implementation form of the first aspect the converter comprises one or more additional converter sections. For controlling the controllable semiconductor switches of an additional converter section of the one or more additional converter sections the method may comprise measuring a current and a voltage at the first terminal and a voltage at the capacitor of each of the first and second power converter of the additional converter section. For controlling a conversion of a voltage at the first terminal of each power converter of the additional converter section to a further voltage of lower or higher level at the second and third terminal of each power converter of the additional converter section the method may comprise: generating for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter of the additional converter section a different duty cycle for switching the controllable semiconductor switch by: computing, using the measured current and voltage at the first terminal of the first power converter of the additional converter section and the measured current and voltage at the first terminal of the second power converter of the additional converter section, a single duty cycle with regard to a MPPT; computing, using the measured voltages of the first and second capacitor unit and measured voltages of the capacitor of the first and second power converter of the additional converter section, a first correction parameter for balancing the voltages of the first and second capacitor unit, a second correction parameter for balancing the voltages of the capacitor of the first power converter of the additional converter section and capacitor of the second power converter of the additional converter section, and a third correction parameter for keeping an average of the voltage of the capacitor of the first power converter of the additional converter section and the voltage of the capacitor of the second power converter of the additional converter section smaller than 50% of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit; and computing the duty cycle for switching the controllable semiconductor using the single duty cycle and at least one of the first, second and third correction parameter.

[0035] This allows, connecting additional electrical energy sources, such as additional voltage or current sources, to the converter. Therefore, the converter may be used for more than two electrical energy sources in order to provide a voltage and / or current conversion for the multiple sources. Each of the one or more additional converter sections may be implemented like the converter section. Thus, the description of the converter section is correspondingly valid for the one or more additional converter sections.

[0036] Herein, measuring a voltage at the first terminal of each of the first and second power converter of the additional converter section means measuring the voltage at the first terminal of each of the first and second power converter of the additional converter section with regard to the fourth terminal or first terminal of the additional converter section, respectively. That is, measuring the voltage at the first terminal of the first power converter of the additional converter section means measuring the voltage between the second and fourth terminal of the additional converter section (the first terminal of the first power converter of the additional converter section is electrically connected with the second terminal of the additional converter section). Accordingly, measuring the voltage at the first terminal of the second power converter of the additional converter section means measuring the voltage between the third and first terminal of the additional converter section (the first terminal of the second power converter of the additional converter section is electrically connected with the third terminal of the additional converter section).

[0037] Herein, measuring a voltage at the capacitor of each of the first and second power converter of the additional converter section means measuring the voltage between the two terminals of the capacitor of each of the first and second power converter of the additional converter section.

[0038] In an implementation form of the first aspect, computing the single duty cycle with regard to a MPPT comprises: computing a first duty cycle by inputting the measured current and voltage at the first terminal of the first power converter to a first MPPT controller, computing a second duty cycle by inputting the measured current and voltage at the first terminal of the second power converter to a second MPPT controller, and computing the single duty cycle by computing an average of the first and second duty cycle.

[0039] That is, when a PV system (e.g. PV string) is connected with the first terminal of each of the first and second power converter, individual reference duty cycles (may be referred to as first duty cycle and second duty cycle) may be calculated for the two PV systems with an MPPT algorithm.

[0040] As an alternative to computing the average of the first and second duty cycle for computing the single duty cycle, optionally the maximum of the first and second duty cycle or the minimum of the first and second duty cycle may be chosen (taken) as the single duty cycle.

[0041] In an implementation form of the first aspect, computing the first correction parameter comprises computing a difference between the measured voltage of the first capacitor unit and the measured voltage of the second capacitor unit and inputting the difference in a controller

[0042] In an implementation form of the first aspect, computing the second correction parameter comprises computing a difference between the measured voltage of the capacitor of the first power converter and the measured voltage of the capacitor of the second power converter and inputting the difference in a controller.

[0043] In an implementation form of the first aspect, computing the third correction parameter comprises: computing an average of the measured voltage of the capacitor of the first power converter and the measured voltage of the capacitor of the second power converter, computing a sum of the measured voltage of the first capacitor unit and the measured voltage of the second capacitor unit, subtracting the computed average from the sum and inputting the subtraction result to a controller.

[0044] Computing the average of the measured voltage of the capacitor of the first power converter and the measured voltage of the capacitor of the second power converter may be computing the average of the measured voltage of the capacitor of the first power converter scaled with a factor and the measured voltage of the capacitor of the second power converter scaled with the same factor. For example, the factor may equal to four.

[0045] In an implementation form of the first aspect, the semiconductor switches of the first switch unit of the first power converter and the semiconductor switches of the second switch unit of the second power converter are uncontrollable semiconductor switches. The method may comprise at least one of: computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the node of the first power converter using the single duty cycle, the second correction parameter and the third correction parameter, computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the third terminal of the first power converter using the single duty cycle, and the first correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the second terminal of the second power converter using the single duty cycle, and the first correction parameter, and computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the node of the second power converter using the single duty cycle, the second correction parameter and the third correction parameter.

[0046] In an implementation form of the first aspect, the semiconductor switches of the first switch unit of the first power converter and the semiconductor switches of the second switch unit of the second power converter are controllable semiconductor switches. For controlling a conversion of the voltage at the first terminal of each power converter to the further voltage of lower or higher level at the second and third terminal of each power converter the method may comprise not switching the controllable semiconductor switches of the first switch unit of the first power converter and the controllable semiconductor switches of the second switch unit of the second power converter. The method may further comprise at least one of: computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the node of the first power converter using the single duty cycle, the second correction parameter and the third correction parameter, computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the third terminal of the first power converter using the single duty cycle, and the first correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the second terminal of the second power converter using the single duty cycle, and the first correction parameter, and computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the node of the second power converter using the single duty cycle, the second correction parameter and the third correction parameter.

[0047] In an implementation form of the first aspect, the semiconductor switches of the first switch unit of the first power converter and the semiconductor switches of the second switch unit of the second power converter are controllable semiconductor switches. For controlling a conversion of a voltage at the second and third terminal of each power converter to a further voltage of lower or higher level at the first terminal of each power converter the method may comprise not switching the controllable semiconductor switches of the second switch unit of the first power converter and the semiconductor switches of the first switch unit of the second power converter. The method may further comprise at least one of: computing the duty cycle for switching a semiconductor switch of the first switch unit of the first power converter electrically connected with the node of the first power converter using the single duty cycle, the second correction parameter and the third correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the first power converter electrically connected with the second terminal of the first power converter using the single duty cycle and the first correction parameter, computing the duty cycle for switching a semiconductor switch of the second switch unit of the second power converter electrically connected with the third terminal of the second power converter using the single duty cycle and the first correction parameter, and computing the duty cycle for switching a semiconductor switch of the second switch unit of the second power converter electrically connected with the node of the second power converter using the single duty cycle, the second correction parameter and the third correction parameter.

[0048] In an implementation form of the first aspect, the first switch unit of each of the first and second power converter comprises a third semiconductor switch electrically connected between the second terminal of the power converter and an end of the series connection of the two semiconductor switches of the first switch unit. The second switch unit of each of the first and second power converter may comprise a third semiconductor switch electrically connected between the third terminal of the power converter and an end of the series connection of the two semiconductor switches of the second switch unit. The first and second power converter may each comprise a second capacitor that is electrically connected between the end of the series connection of the two semiconductor switches of the first switch unit and the end of the series connection of the two semiconductor switches of the second switch unit. The method may comprise measuring a voltage at the second capacitor of each of the first and second power converter. Generating for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch may comprise: computing, using the measured current and voltage at the first terminal of the first power converter and the measured current and voltage at the first terminal of the second power converter, a single duty cycle with regard to a MPPT; computing, using the measured voltages of the first and second capacitor unit and measured voltages of the capacitor (may be called “first capacitor”) and second capacitor of the first and second power converter, the first, second and third correction parameter and a fourth correction parameter for balancing the voltages of the second capacitor of the first power converter and second capacitor of the second power converter, the third correction parameter being a correction parameter for keeping an average of the voltage of the capacitor of the first power converter, the voltage of the second capacitor of the first power converter, the voltage of the capacitor of the second power converter and the voltage of the second capacitor of the second power converter smaller than 50% of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit; and computing the duty cycle for switching the controllable semiconductor using the single duty cycle and at least one of the first, second, third and fourth correction parameter.

[0049] Optionally, the third correction parameter is for keeping an average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter at around a third of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit and keeping an average of the voltage of the second capacitor of the first power converter and the voltage of the second capacitor of the second power converter at around two third of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit. The passage “at around a third” may be understood as “between 28% and 38%”. The passage “at around two third” may be understood as “between 61% and 71%”. For example, the third correction parameter is for keeping an average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter at a third of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit and keeping an average of the voltage of the second capacitor of the first power converter and the voltage of the second capacitor of the second power converter at two third of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit.

[0050] The capacitor and second capacitor of each of the first and second power converter may be referred to as “flying capacitor”, e.g. as “first flying capacitor” and “second flying capacitor”, respectively.

[0051] In an implementation form of the first aspect, computing the fourth correction parameter comprises computing a difference between the measured voltage of the second capacitor of the first power converter and the measured voltage of the second capacitor of the second power converter and inputting the difference in a controller.

[0052] In an implementation form of the first aspect, computing the third correction parameter comprises: computing an average of the voltage of the capacitor of the first power converter, the voltage of the second capacitor of the first power converter, the voltage of the capacitor of the second power converter and the voltage of the second capacitor of the second power converter, computing a sum of the measured voltage of the first capacitor unit and the measured voltage of the second capacitor unit, and subtracting the computed average from the sum and inputting the subtraction result to a controller.

[0053] Computing an average of the voltage of the capacitor of the first power converter, the voltage of the second capacitor of the first power converter, the voltage of the capacitor of the second power converter and the voltage of the second capacitor of the second power converter may be computing an average of the voltage of the capacitor of the first power converter scaled with a first factor, the voltage of the second capacitor of the first power converter scaled with a second factor, the voltage of the capacitor of the second power converter scaled with a first factor and the voltage of the second capacitor of the second power converter scaled with a second factor. The first factor may be greater than the second factor. Optionally, the second factor may equal to half the first factor. For example, the first factor may equal to three (3) and the second factor may equal to three halves (3 / 2).

[0054] In an implementation form of the first aspect, the semiconductor switches of the first switch unit of the first power converter and the semiconductor switches of the second switch unit of the second power converter are uncontrollable semiconductor switches. The method may comprise at least one of: computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the node of the first power converter using the single duty cycle, the second correction parameter, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the third semiconductor switch of the second switch unit of the first power converter using the single duty cycle, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching the third semiconductor switch of the second switch unit of the first power converter using the single duty cycle and the first correction parameter, computing the duty cycle for switching the third semiconductor switch of the first switch unit of the second power converter using the single duty cycle and the first correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the third semiconductor switch of the first switch unit of the second power converter using the single duty cycle, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the node of the second power converter using the single duty cycle, the second correction parameter, the third correction and the fourth correction parameter.

[0055] In an implementation form of the first aspect, the semiconductor switches of the first switch unit of the first power converter and the semiconductor switches of the second switch unit of the second power converter are controllable semiconductor switches. For controlling a conversion of the voltage at the first terminal of each power converter to the further voltage of lower or higher level at the second and third terminal of each power converter the method may comprise not switching the controllable semiconductor switches of the first switch unit of the first power converter and the semiconductor switches of the second switch unit of the second power converter. The method may further comprise at least one of: computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the node of the first power converter using the single duty cycle, the second correction parameter, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching a semiconductor switch of the second switch unit of the first power converter electrically connected with the third semiconductor switch of the second switch unit of the first power converter using the single duty cycle, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching the third semiconductor switch of the second switch unit of the first power converter using the single duty cycle and the first correction parameter, computing the duty cycle for switching the third semiconductor switch of the first switch unit of the second power converter using the single duty cycle and the first correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the third semiconductor switch of the first switch unit of the second power converter using the single duty cycle, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the second power converter electrically connected with the node of the second power converter using the single duty cycle, the second correction parameter, the third correction and the fourth correction parameter.

[0056] In an implementation form of the first aspect, the semiconductor switches of the first switch unit of the first power converter and the semiconductor switches of the second switch unit of the second power converter are controllable semiconductor switches. For controlling a conversion of a voltage at the second and third terminal of each power converter to a further voltage of lower or higher level at the first terminal of each power converter the method may comprise not switching the controllable semiconductor switches of the second switch unit of the first power converter and the semiconductor switches of the first switch unit of the second power converter. The method may further comprise at least one of: computing the duty cycle for switching a semiconductor switch of the first switch unit of the first power converter electrically connected with the node of the first power converter using the single duty cycle, the second correction parameter, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching a semiconductor switch of the first switch unit of the first power converter electrically connected with the third semiconductor switch of the first switch unit of the first power converter using the single duty cycle, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching the third semiconductor switch of the first switch unit of the first power converter using the single duty cycle and the first correction parameter, computing the duty cycle for switching the third semiconductor switch of the second switch unit of the second power converter using the single duty cycle and the first correction parameter, computing the duty cycle for switching a semiconductor switch of the second switch unit of the second power converter electrically connected with the third semiconductor switch of the second switch unit of the second power converter using the single duty cycle, the third correction parameter and the fourth correction parameter, computing the duty cycle for switching a semiconductor switch of the second switch unit of the second power converter electrically connected with the node of the second power converter using the single duty cycle, the second correction parameter, the third correction and the fourth correction parameter.

[0057] In order to achieve the method according to the first aspect of the disclosure, some or all of the implementation forms and optional features of the first aspect, as described above, may be combined with each other.

[0058] A second aspect of this disclosure provides a control device for controlling a converter. The converter comprises a converter section, and a series connection of a first and second capacitor unit. The converter section comprises a first, second, third and fourth terminal for receiving DC voltages. The converter section comprises a first and second power converter each comprising a first, second and third terminal, a capacitor, a first switch unit comprising two semiconductor switches electrically connected in series between the second terminal of the power converter and a node, and a second switch unit comprising two semiconductor switches electrically connected in series between the node and the third terminal of the power converter. The node is electrically connected via an inductor to the first terminal of the power converter and the capacitor is electrically connected with a midpoint between the two semiconductor switches of the first switch unit and a midpoint between the two semiconductor switches of the second switch unit. The switches of the second switch unit of the first power converter and the switches of the first switch unit of the second power converter are controllable semiconductor switches. The first terminal of the first power converter is electrically connected with the second terminal of the converter section. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter section is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter section. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter section is electrically connected with the second terminal of the second capacitor unit. The control device is configured to obtain a measured current and voltage at the first terminal and a measured voltage at the capacitor of each of the first and second power converter, and obtain a measured voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The control device is configured to, for controlling a conversion of a voltage at the first terminal of each power converter to a further voltage of lower or higher level at the second and third terminal of each power converter, generate for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch by: computing, using the measured current and voltage at the first terminal of the first power converter and the measured current and voltage at the first terminal of the second power converter, a single duty cycle with regard to a maximum power point tracking, MPPT; computing, using the measured voltages of the first and second capacitor unit and measured voltages of the capacitor of the first and second power converter, a first correction parameter for balancing the voltages of the first and second capacitor unit, a second correction parameter for balancing the voltages of the capacitor of the first power converter and capacitor of the second power converter, and a third correction parameter for keeping an average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter smaller than 50% of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit; and computing the duty cycle for switching the controllable semiconductor switch using the single duty cycle and at least one of the first, second and third correction parameter. The control device may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components.

[0059] The first and third terminal of the converter section may be configured to be electrically connected with a first electrical energy source (e.g. first voltage source or current source) and the second and fourth terminal of the converter section may be configured to be electrically connected with a second electrical energy source (e.g. second voltage source or current source).

[0060] The above description of the method according to the first aspect, especially the optional features and implementation forms of the first aspect, are correspondingly valid for the control device of the second aspect. The control device of the second aspect may be configured to perform the method of the first aspect.

[0061] The control device of the second aspect and its implementation forms and optional features achieve the same advantages as the method of the first aspect and its respective implementation forms and respective optional features.

[0062] A third aspect of this disclosure provides a converter. The converter comprises a converter section, and a series connection of a first and second capacitor unit. The converter section comprises a first, second, third and fourth terminal for receiving DC voltages. The converter section comprises a first and second power converter each comprising a first, second and third terminal, a capacitor, a first switch unit comprising two semiconductor switches electrically connected in series between the second terminal of the power converter and a node, and a second switch unit comprising two semiconductor switches electrically connected in series between the node and the third terminal of the power converter. The node is electrically connected via an inductor to the first terminal of the power converter and the capacitor is electrically connected with a midpoint between the two semiconductor switches of the first switch unit and a midpoint between the two semiconductor switches of the second switch unit. The switches of the second switch unit of the first power converter and the switches of the first switch unit of the second power converter are controllable semiconductor switches. The first terminal of the first power converter is electrically connected with the second terminal of the converter section. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter section is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter section. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter section is electrically connected with the second terminal of the second capacitor unit. The converter is configured to measure a current and a voltage at the first terminal and a voltage at the capacitor of each of the first and second power converter. The converter is configured to measure a voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The converter is configured to, for controlling a conversion of a voltage at the first terminal of each power converter to a further voltage of lower or higher level at the second and third terminal of each power converter, generate for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch by: computing, using the measured current and voltage at the first terminal of the first power converter and the measured current and voltage at the first terminal of the second power converter, a single duty cycle with regard to a maximum power point tracking, MPPT; computing, using the measured voltages of the first and second capacitor unit and measured voltages of the capacitor of the first and second power converter, a first correction parameter for balancing the voltages of the first and second capacitor unit, a second correction parameter for balancing the voltages of the capacitor of the first power converter and capacitor of the second power converter, and a third correction parameter for keeping an average of the voltage of the capacitor of the first power converter and the voltage of the capacitor of the second power converter smaller 50% of the sum of the voltage of the first capacitor unit and the voltage of the second capacitor unit; and computing the duty cycle for switching the controllable semiconductor switch using the single duty cycle and at least one of the first, second and third correction parameter.

[0063] The first and third terminal of the converter section may be configured to be electrically connected with a first electrical energy source (e.g. first voltage source or current source) and the second and fourth terminal of the converter section may be configured to be electrically connected with a second electrical energy source (e.g. second voltage source or current source).

[0064] The above description of the method according to the first aspect, especially the optional features and implementation forms of the first aspect, are correspondingly valid for the converter of the third aspect. The converter of the third aspect may be configured to perform the method of the first aspect.

[0065] The converter of the third aspect and its implementation forms and optional features achieve the same advantages as the method of the first aspect and its respective implementation forms and respective optional features.

[0066] A fourth aspect of this disclosure provides a method for controlling a converter. The converter comprises a converter section, and a series connection of a first and second capacitor unit. The converter section comprises a first, second, third and fourth terminal for receiving DC voltages. The converter section comprises a first and second power converter each comprising a first, second and third terminal, a first switch unit comprising a semiconductor switch connected between the second terminal of the power converter and a node, and a second switch unit comprising a semiconductor switch electrically connected in series between the node and the third terminal of the power converter. The node is electrically connected via an inductor to the first terminal of the power converter. The switch of the second switch unit of the first power converter and the switch of the first switch unit of the second power converter are controllable semiconductor switches. The first terminal of the first power converter is electrically connected with the second terminal of the converter section. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter section is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter section. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter section is electrically connected with the second terminal of the second capacitor unit. The method comprises measuring a current and a voltage at the first terminal of each of the first and second power converter. The method comprises measuring a voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. For controlling a conversion of a voltage at the first terminal of each power converter to a further voltage of lower or higher level at the second and third terminal of each power converter the method comprises: generating for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch by: computing, using the measured current and voltage at the first terminal of the first power converter and the measured current and voltage at the first terminal of the second power converter, a single duty cycle with regard to a maximum power point tracking, MPPT; computing, using the measured voltages of the first and second capacitor unit a correction parameter for balancing the voltages of the first and second capacitor unit; and computing the duty cycle for switching the controllable semiconductor switch using the single duty cycle and the correction parameter. The first and third terminal of the converter section may be configured to be electrically connected with a first electrical energy source (e.g. first voltage source or current source) and the second and fourth terminal of the converter section may be configured to be electrically connected with a second electrical energy source (e.g. second voltage source or current source).

[0067] Herein, measuring a voltage at the first terminal of each of the first and second power converter means measuring the voltage at the first terminal of each of the first and second power converter with regard to the fourth terminal or first terminal of the converter section, respectively. That is, measuring the voltage at the first terminal of the first power converter means measuring the voltage between the second and fourth terminal of the converter section (the first terminal of the first power converter is electrically connected with the second terminal of the converter section). Accordingly, measuring the voltage at the first terminal of the second power converter means measuring the voltage between the third and first terminal of the converter section (the first terminal of the second power converter is electrically connected with the third terminal of the converter section).

[0068] The method of the fourth aspect differs from the method of the first aspect in that the converter, especially the first and second power converter of the converter, being controlled by the method of the fourth aspect differs from the converter being controlled by the method of the first aspect. Thus, according to the method of the first aspect three correction parameters are computed, whereas according to the method of the fourth aspect a correction parameter is computed, which corresponds to the first correction parameter computed by the method of the first aspect.

[0069] The above description of the method according to the first aspect, especially the optional features and implementation forms of the first aspect, are correspondingly valid for the method of the fourth aspect.

[0070] The method of the fourth aspect and its implementation forms and optional features achieve the same advantages as the method of the first aspect and its respective implementation forms and respective optional features.

[0071] A fifth aspect of this disclosure provides a control device for controlling a converter. The converter comprises a converter section, and a series connection of a first and second capacitor unit. The converter section comprises a first, second, third and fourth terminal for receiving DC voltages. The converter section comprises a first and second power converter each comprising a first, second and third terminal, a first switch unit comprising a semiconductor switch connected between the second terminal of the power converter and a node, and a second switch unit comprising a semiconductor switch electrically connected in series between the node and the third terminal of the power converter. The node is electrically connected via an inductor to the first terminal of the power converter. The switch of the second switch unit of the first power converter and the switch of the first switch unit of the second power converter are controllable semiconductor switches. The first terminal of the first power converter is electrically connected with the second terminal of the converter section. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter section is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter section. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter section is electrically connected with the second terminal of the second capacitor unit. The control device is configured to obtain a measured current and voltage at the first terminal of each of the first and second power converter, and obtain a measured voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The control device is configured to, for controlling a conversion of a voltage at the first terminal of each power converter to a further voltage of lower or higher level at the second and third terminal of each power converter, generate for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch by: computing, using the measured current and voltage at the first terminal of the first power converter and the measured current and voltage at the first terminal of the second power converter, a single duty cycle with regard to a maximum power point tracking, MPPT; computing, using the measured voltages of the first and second capacitor unit a correction parameter for balancing the voltages of the first and second capacitor unit; and computing the duty cycle for switching the controllable semiconductor switch using the single duty cycle and the correction parameter.

[0072] The control device may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components.

[0073] The first and third terminal of the converter section may be configured to be electrically connected with a first electrical energy source (e.g. first voltage source or current source) and the second and fourth terminal of the converter section may be configured to be electrically connected with a second electrical energy source (e.g. second voltage source or current source).

[0074] The above description of the method according to the fourth aspect, especially the optional features and implementation forms of the fourth aspect, are correspondingly valid for the control device of the fifth aspect. The control device of the fifth aspect may be configured to perform the method of the fourth aspect.

[0075] The converter of the fifth aspect and its implementation forms and optional features achieve the similar advantages as the method of the first aspect and its respective implementation forms and respective optional features.

[0076] A sixth aspect of this disclosure provides a converter. The converter comprises a converter section, and a series connection of a first and second capacitor unit. The converter section comprises a first, second, third and fourth terminal for receiving DC voltages. The converter section comprises a first and second power converter each comprising a first, second and third terminal, a first switch unit comprising a semiconductor switch connected between the second terminal of the power converter and a node, and a second switch unit comprising a semiconductor switch electrically connected between the node and the third terminal of the power converter. The node is electrically connected via an inductor to the first terminal of the power converter. The switch of the second switch unit of the first power converter and the switch of the first switch unit of the second power converter are controllable semiconductor switches. The first terminal of the first power converter is electrically connected with the second terminal of the converter section. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter section is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter section. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter section is electrically connected with the second terminal of the second capacitor unit. The converter is configured to measure a current and a voltage at the first terminal of each of the first and second power converter. The converter is configured to measure a voltage between the first terminal and second terminal of the first capacitor unit and second capacitor unit. The converter is configured to, for controlling a conversion of a voltage at the first terminal of each power converter to a further voltage of lower or higher level at the second and third terminal of each power converter, generate for each of the controllable semiconductor switches of the second switch unit of the first power converter and the first switch unit of the second power converter a different duty cycle for switching the controllable semiconductor switch by: computing, using the measured current and voltage at the first terminal of the first power converter and the measured current and voltage at the first terminal of the second power converter, a single duty cycle with regard to a maximum power point tracking, MPPT; computing, using the measured voltages of the first and second capacitor unit a correction parameter for balancing the voltages of the first and second capacitor unit; and computing the duty cycle for switching the controllable semiconductor switch using the single duty cycle and the correction parameter.

[0077] The above description of the method according to the fourth aspect, especially the optional features and implementation forms of the fourth aspect, are correspondingly valid for the converter of the sixth aspect. The converter of the sixth aspect may be configured to perform the method of the fourth aspect.

[0078] The converter of the sixth aspect and its implementation forms and optional features achieve the same advantages as the method of the first aspect and its respective implementation forms and respective optional features.

[0079] Herein, when an electrical energy source is connected to two terminals of the converter section of a converter, a capacitor (may be referred to as input capacitor) may optionally be connected in parallel to the electrical energy source. That is, a first and second terminal of the capacitor may be connected to the aforementioned two terminals of the converter section.

[0080] The converter described with regard to the method of the first aspect, the converter described with regard to the control device of the second aspect and the converter of the third aspect correspond to each other. The converter described with regard to the method of the fourth aspect, the converter described with regard to the control device of the fifth aspect and the converter of the sixth aspect correspond to each other. The methods of the first and fourth aspects, control devices of the second and fifth aspects and converters of the third and sixth aspects allow a low cost MPPT DC-to-DC conversion. With regard to string inverters for interfacing a PV system (e.g. a PV array) to a grid, each string inverter comprising the converter described with regard to the first aspect, second aspect, fourth aspect or fifth aspect or the converter of the third aspect or sixth aspect as a DC- to-DC converter stage and an DC-to-AC converter stage, the methods of the first and fourth aspects, control devices of the second and fifth aspects and converters of the third and sixth aspects enable having a string level optimization, rather than multiple strings to be maintained at one MPPT. The methods of the first and fourth aspect, the converter described with regard to the control devices of the second and fifth aspect and the converters of the third and sixth aspect allow extension of PV strings, BES integration or any combination of both.

[0081] With the methods of the first and fourth aspects, control devices of the second and fifth aspects and the converters of the third and sixth aspects, it is possible to improve the efficiency, power density and the cost of a MPPT DC / DC converter, e.g. when used for PV systems. Moreover, a high electrical efficiency can be achieved as lower voltage semiconductor devices can be used and by means of the integration of control and driving circuits in close proximity to switching power cells thereby minimizing delays and latencies in the control loop.

[0082] For example, the methods and converters of this disclosure show only a negligible reduction of PV power extracted for 15% irradiation mismatch between PV systems connected as electrical energy sources with the converter compared to conventional converter solutions with a hardware balancer, while showing a significant improvement with regard to cost, weight and volume due to not requiring a hardware balancer for achieving the balancing effects described herein.

[0083] All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

[0084] BRIEF DESCRIPTION OF DRAWINGS

[0085] The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which:

[0086] FIG. 1 shows an example of a converter of this disclosure and an example of a control device of this disclosure for controlling a converter.

[0087] FIG. 2 shows an example of an implementation form of a method of this disclosure for controlling a converter of this disclosure, such as the converter of any one FIGs 1, 3, 4, 7, lO and l l.

[0088] FIG. 3 shows an example of an implementation form of the converter of FIG. 1.

[0089] FIG. 4 shows an example of an implementation form of the converter of FIG. 1.

[0090] FIG. 5 shows an example of an implementation form of the method of FIG. 2.

[0091] FIG. 6 shows an example of a time course of control signals having duty cycles generated by performing the method steps of FIG. 5.

[0092] FIG. 7 shows an example of an implementation form of the converter of FIG. 1.

[0093] FIG. 8 shows an example of an implementation form of the method of FIG. 2.

[0094] FIG. 9 shows an example of a time course of control signals having duty cycles generated by performing the method of FIG. 8.

[0095] FIG. 10 shows an example of an implementation form of the converter of FIG. 1.

[0096] FIG. 11 shows an example of an implementation form of the converter of FIG. 1.

[0097] FIG. 12 shows an example of an implementation form of the method of FIG. 2.

[0098] FIG. 13 shows an example of a converter of this disclosure.

[0099] Same elements shown in the Figures (FIGs) are labeled with the same reference sign, and may be implemented likewise.

[0100] DETAILED DESCRIPTION OF EMBODIMENTS

[0101] FIG. 1 shows an example of a converter of this disclosure and an example of a control device of this disclosure for controlling a converter. The converter of FIG. 1 is an example of the converter of the third aspect. Thus, the description of the converter of the third aspect is correspondingly valid for the converter of FIG. 1. The control device of FIG. 1 is an example of the control device of the second aspect. Thus, the description of the control device of the second aspect is correspondingly valid for the control device of FIG. 1.

[0102] As shown in FIG. 1, the converter 100 comprises a converter section 101, and a series connection of a first capacitor unit Cl and a second capacitor unit C2. The converter section 101 comprises a first terminal T 1 , second terminal T2, third terminal T3 and fourth terminal T4 for receiving DC voltages. The first, second, third and fourth terminal Tl, T2, T3, T4 of the converter section 101 may be referred to as first, second, third and fourth terminal Tl, T2, T3, T4 of the converter 100. As shown in FIG. 1, the first and third terminal Tl, T3 may be configured to be electrically connected with a first electrical energy source 200a (e.g. first voltage or current source) and the second and fourth terminal T2, T4 may be configured to be electrically connected with a second electrical energy source 200b (e.g. second voltage or current source). The converter section 101 comprises a first power converter la and second power converter lb. Each power converter of the first and second power converters la, lb comprises a first terminal X, second terminal Yl and third terminal Y2, a capacitor Cla, Clb (not shown in FIG. 1), a first switch unit SUla, SUlb comprising two semiconductor switches electrically connected in series between the second terminal Yl of the power converter la, lb and a node Nla, Nib (not shown in FIG. 1), and a second switch unit SU2a, SU2b comprising two semiconductor switches electrically connected in series between the node Nla, Nib and the third terminal Y2 of the power converter la, lb (not shown in FIG. 1). The node Nla, Nib is electrically connected via an inductor La, Lb to the first terminal X of the power converter la, lb and the capacitor Cla, Clb is electrically connected with a midpoint between the two semiconductor switches of the first switch unit SUla, SUlb and a midpoint between the two semiconductor switches of the second switch unit SU2a, SU2b (not shown in FIG. 1). The switches of the second switch unit SU2a of the first power converter la and the switches of the first switch unit SUlb of the second power converter lb are controllable semiconductor switches (not shown in FIG. 1). FIGs 4, 7, 10, 11 and 13 show examples of implementation forms of the first and second power converter la, lb of the converter 100. In case the first and second power converter la, lb are implemented in line with the example of FIG. 13, then the converter 100 is an example of the converter of the sixth aspect of this disclosure. Thus, in this case, the description of the converter of the sixth aspect is correspondingly valid for the converter 100.

[0103] As shown in FIG. 1, the first terminal X of the first power converter la is electrically connected with the second terminal T2 of the converter section 101. The second and third terminal Yl, Y2 of the first power converter la are electrically connected with a first and second terminal of the first capacitor unit Cl, respectively. The first terminal Tl of the converter section 101 is electrically connected with the first terminal of the first capacitor unit Cl . The first terminal X of the second power converter lb is electrically connected with the third terminal T3 of the converter section 101. The second and third terminal Yl, Y2 of the second power converter lb are electrically connected with a first and second terminal of the second capacitor unit C2, respectively. The fourth terminal T4 of the converter section 101 is electrically connected with the second terminal of the second capacitor unit C2. The second terminal of the first capacitor unit Cl is electrically connected with the first terminal of the second capacitor unit C2. As shown in FIG. 1 , the third terminal Y2 of the first power converter la is electrically connected with the second terminal Yl of the second power convert lb.

[0104] The converter 100 is configured to measure a current and a voltage at the first terminal X and a voltage at the capacitor Cla, Clb (not shown in FIG. 1) of each of the first and second power converter la, lb. That is, with regard to the first power converter la, the converter 100 is configured to measure a current II at the second terminal T2 of the converter section 101 and a voltage VI between the second terminal T2 and fourth terminal T4 of the converter section 101 (the first terminal X of the first power converter la is connected with the second terminal T2 of the converter section 101). With regard to the second power converter lb, the converter 100 is configured to measure a current 12 at the third terminal T3 of the converter section 101 and a voltage V2 between the third terminal T3 and first terminal Tl of the converter sectionlOl (the first terminal X of the second power converter lb is connected with the third terminal T3 of the converter section 101). With regard to the first power converter la, the converter 100 is configured to measure a voltage V_Cla between a first and second terminal of the capacitor Cla of the first power converter la. With regard to the second power converter lb, the converter 100 is configured to measure a voltage V_Clb between a first and second terminal of the capacitor Clb of the second power converter lb. The converter 100 is configured to measure a voltage between the first terminal and second terminal of the first capacitor unit Cl and second capacitor unit C2. That is, the converter 100 is configured to measure a voltage V_C1 between the first terminal and second terminal of the first capacitor unit Cl and a voltage V_C2 between the first terminal and second terminal of the second capacitor unit C2.

[0105] For measuring currents and voltages, such as the aforementioned currents and voltages, the converter 100 may comprise respective measuring circuit(s) and / or elements) (not shown). For example, for measuring current the converter 100 may comprise a resistor, such as a shunt resistor. For example, for measuring a voltage the converter 100 may comprise a voltage divider, such as two resistors electrically connected in series. The present disclosure is not limited to a specific way of measuring currents and voltages. Thus, with regard to measuring currents and voltages the converter 100 may be implemented in any known way.

[0106] The converter 100 is configured to, for controlling a conversion of a voltage at the first terminal X of each power converter la, lb to a further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb, generate for each of the controllable semiconductor switches of the second switch unit SU2a of the first power converter la and the first switch unit SUlb of the second power converter lb a different duty cycle for switching the controllable semiconductor switch by performing the steps described below.

[0107] Computing, using the measured voltages V_C1, V_C2 of the first and second capacitor unit Cl, C2, a first correction parameter 51 for balancing the voltages V_C1, V_C2 of the first and second capacitor unit Cl, C2 (and, thus, balancing the electrical energies of the first and second capacitor unit Cl, C2). In other words, the converter 100 may perform, using the measured voltages V_C1, V_C2 of the first and second capacitor unit Cl, C2, a balancing algorithm for balancing the voltages V_C1, V_C2 of the first and second capacitor unit Cl, C2. An example of how such computation of the first correction parameter 51 is performed is described with regard to FIG. 5.

[0108] Computing a second correction parameter 52 for balancing the voltages V_Cla, V_Clb of the capacitor Cla of the first power converter la and capacitor Clb of the second power converter lb. In other words, the converter 100 may perform, using the measured voltages V_C 1 a, V_C 1 b of the capacitor C 1 a, C 1 b of the first and second power converter la, 1 b, a balancing algorithm for balancing the voltages V_Cla, V_Clb of the capacitor Cla of the first power converter la and capacitor Clb of the second power converter lb. An example of how such computation of the second correction parameter 52 is performed is described with regard to FIG. 5.

[0109] Computing a third correction parameter 53 for keeping an average of the voltage V_Cla of the capacitor Cla of the first power converter la and the voltage V_Clb of the capacitor Clb of the second power converter lb smaller than 50% of the sum of the voltage V_C1 of the first capacitor unit Cl and the voltage V_C2 of the second capacitor unit C2. An example of how such computation of the third correction parameter 53 is performed is described with regard to FIGs 5 and 8.

[0110] Computing the duty cycle for switching the controllable semiconductor switch (i.e. the respective controllable switch) using the single duty cycle D and at least one of the first correction parameter 51 , second correction parameter 52 and third correction parameter 53. An example of how such computation of the duty cycle for switching the controlling the respective controllable semiconductor switch (i.e. the duty cycle of a control signal for controlling switching of the respective controllable switch) is performed is described with regard to FIGs 5 and 8.

[0111] Optionally additional steps (in addition to above described steps) may be performed by the converter 100 when generating for each of the controllable semiconductor switches of the second switch unit SU2a of the first power converter la and the first switch unit SUlb of the second power converter lb a different duty cycle for switching the controllable semiconductor switch in order to control a conversion of a voltage at the first terminal X of each power converter la, 1 b to a further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb.

[0112] With above described steps, the converter 100 may generate for each of the controllable semiconductor switches of the second switch unit SU2a of the first power converter la and the first switch unit SUlb of the second power converter lb a different duty cycle for switching the controllable semiconductor switch in order to control a conversion of a voltage at the first terminal X of each power converter la, lb to a further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb. That is, these steps allow the converter 100 to control a conversion of a voltage at the first terminal X of each power converter la, lb to a further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb. In other words, the converter 100 may control the controllable semiconductor switches the first power converter la and second power converter lb by providing to each of the aforementioned controllable semiconductor switches a respective control signal with a different duty cycle (i.e. the duty cycles of the control signals for controlling the controllable switches are different from each other).

[0113] For controlling the controllable switches and, thus, generating the different duty cycle (i.e. a control signal having a different duty cycle) for each of the controllable semiconductor switches of the converter section 101, the converter 100 may comprise a control unit (not shown in FIG. 1 ). The control unit may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components. The control unit is configured to provide control signals (e.g. pulse width modulated (PWM) signals) to the controllable semiconductor switches of the first and second power converter la, lb, especially to the control terminal of the controllable semiconductor switches, such that the control signals have a different duty cycle, i.e. differ from each other with regard to the duty cycle. The frequency (i.e. inverse period) of the control signal may be kept constant, i.e. switching of the controllable semiconductor switches may be controlled with control signals having a constant frequency, optionally same frequency. That is, for controlling a respective controllable semiconductor switch with a control signal, the control unit may be configured to control (e.g. change) the duty cycle of the control signal, wherein the control signals for controlling switching of the controllable semiconductor switches differ from each other with regard to the duty cycle. Hereby, the control unit may keep the frequency of the control signal constant. The control unit may be configured to perform above described steps.

[0114] Alternative to the converter 100, e.g. a control unit of the converter 100, being configured to control the controllable semiconductor switches of the first and second power converter la, lb, a control device 400 (e.g. external control device) may be used for this. This is indicated by the arrow between the box “400” indicating the control device and the box “100” indicating the converter 100. The box “400” may represent a housing of the control device 400. The box “100” may represent a housing of the converter 100. The control device 400 is an example of the control device of the second aspect.

[0115] The control device 400 is configured to obtain a measured current and voltage at the first terminal X of each of the first and second power converter la, lb and a measured voltage at the capacitor of each of the first and second power converter la. lb. That is, the control device 400 is configured to receive, with regard to the first power converter la of the converter 1, a current Il measured at the second terminal T2 of the converter section 101, a voltageVl measured between the second terminal T2 and fourth terminal T4 of the converter section 101 and a voltage V_Cla measured between the first and second terminal of the capacitor Cla of the first power converter la. The control device 400 is configured to receive, with regard to the second power converter 1 b of the converter section 101 , a current 12 measured at the third terminal T3 of the converter section 101 , a voltage V2 measured between the third terminal T3 and first terminal T1 of the converter section 101, and a voltage V_Clb measured between the first and second terminal of the capacitor Clb of the second power converter lb. The control device 400 is configured to obtain a measured voltage between the first terminal and second terminal of the first capacitor unit Cl and second capacitor unit C2. That is, the control device 400 is configured to obtain a voltage V_C1 measured between the first and second terminal of the first capacitor unit Cl and a voltage V_C2 measured between the first and second terminal of the second capacitor unit C2. The control device 400 may be configured to obtain the aforementioned currents and voltages from respective measurement circuit(s) and / or element(s) of the converter 100.

[0116] The control device 400 is configured to, for controlling a conversion of a voltage at the first terminal X of each power converter la, lb to a further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb, generate for each of the controllable semiconductor switches of the second switch unit SU2a of the first power converter la and the first switch unit SUlb of the second power converter lb a different duty cycle for switching the controllable semiconductor switch by performing the steps described above with regard to the converter 100. Especially, the control device 400 is configured to perform the above described steps of computing the single duty cycle D, computing the first correction parameter 51, computing the second correction parameter 52, computing the third correction parameter 52 and computing the duty cycle for switching the (respective) controllable semiconductor switch using the single duty cycle D and at least one of the first correction parameter 51, second correction parameter 52 and third correction parameter 53.

[0117] The above description of the optional control unit of the converter 100 is correspondingly valid for the control device 400. The control device 400 may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components.

[0118] The control device 400 is configured to provide control signals (e.g. pulse width modulated (PWM) signals) to the controllable semiconductor switches of the first and second power converter la, lb, especially to the control terminal of the controllable semiconductor switches. The frequency (i.e. inverse period) of the control signal may be kept constant. That is, for controlling a respective controllable semiconductor switch with a control signal, the control device 400 may be configured to control (e.g. change) the duty cycle of the control signal, wherein the control signals for controlling switching of the controllable semiconductor switches differ from each other with regard to the duty cycle. Hereby, the control device 400 may keep the frequency of the control signal constant. The control device 400 may be configured to control the duty cycle of the control signals for controlling the semiconductor switches by performing the steps described above with regard to the converter 100.

[0119] Herein, a description of the converter 100 (e.g. control unit of the converter), especially with regard to controlling controllable semiconductor switches, and a description of the control device 400 are valid for each other. Each of the first power converter la and second power converter lb of the converter section 101 of the converter 100 may be a partial power converter. The converter 100 may be unidirectional and each of the first, second, third and fourth terminal Tl, T2, T3, T4 of the converter section 101 of the converter 100 may be an input terminal. As shown in FIG. 1, the converter 100 may comprise a fifth terminal T5 and sixth terminal T6 that are configured to be electrically connected with an electrical load 300. The fifth terminal T5 is electrically connected with the first terminal of the first capacitor unit Cl and, thus, with the first terminal Tl of the converter section 101. The sixth terminal T6 is electrically connected with the second terminal of the second capacitor unit C2 and, thus, with the fourth terminal T4 of the converter section 101. Examples of implementation forms of the converter 100 being unidirectional (i.e. power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter 100) are shown in FIGs 4 and 7.

[0120] For example, the converter may be a DC-to-DC converter and the load 300 may be an DC-to-AC converter. In this case, the first and second electrical energy sources 200a, 200b may be PV systems, such as PV panel(s) and / or PV array(s). Optionally, the sources 200a, 200b may be two close strings in a PV park that are designed to generate similar DC power. The converter 100 being a DC-to-DC converter and the load 300 being a DC-to-AC converter may be used for converting DC power, e.g. DC voltage and / or current, provided by the first and second electrical energy sources 200a, 200b, e.g. PV systems, to AC power, e.g. AC voltage and / or a current, and provide the AC power to the grid. Optionally, the load 300 may be a DC load.

[0121] Alternatively, the converter 100 may be bidirectional. An example of an implementation form of the converter 100 being bidirectional is shown in FIG. 11. In this case, the first and second electrical energy sources 200a, 200b may be rechargeable battery energy storages (BES) and the load 300 may be configured to use electrical energy from the BES 200a, 200b (power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter 100) and charge the BES 200a, 200b with electrical energy (power flow from the terminals T5, T6 to the terminals Tl, T2, T3, T4 of the converter 100). Thus, the converter 100 being bidirectional supports discharging and charging of BES 200a, 200b.

[0122] As shown in FIG. 1 , a capacitor unit of the first and second capacitor unit C 1 , C2 may comprise or be a capacitor. F or example, as shown in FIG. 1 , each of the first and second capacitor unit C 1 , C2 may comprise or be a capacitor. Alternatively, a capacitor unit of the first and second capacitor unit C 1 , C2 may comprise or be multiple capacitors electrically connected in series and / or parallel. Optionally, each of the first and second capacitor unit Cl, C2 may comprise or be multiple capacitors electrically connected in series and / or parallel. Optionally, the first and second power converter la, lb may be implemented by the same power converter type. The power converters la, lb of the converter 100 may be implemented the same way. Optionally, at least one power converter of the converter 100 may be implemented differently. As outlined already above, examples of implementation forms of the power converters la, lb of the converter 100 are shown in FIGs 4, 7, 10, 11 and 13.

[0123] For further information on the converter 100 reference is made to FIGs 2 to 12. Especially, for further information on how the converter 100 (e.g. control unit of the converter) and the control device 400 may control controllable semiconductor switches references is made to FIGs 2, 5, 6, 8, 9 and 12.

[0124] FIG. 2 shows an example of an implementation form of a method of this disclosure for controlling a converter of this disclosure, such as the converter of any one FIGs 1, 3, 4, 7, 10 and 11. The method of FIG. 2 is an example of the method of the first aspect. Thus, the description of the method of the first aspect is correspondingly valid for the method of FIG. 2.

[0125] As shown in FIG. 2, the method comprises a step 1000 of measuring a current II, 12 and a voltage VI, V2 at the first terminal X and a voltage V_Cla, V_Clb at the capacitor Cla, Clb of each of the first and second power converter la, lb. The method comprises a step 2000 of measuring a voltage V_C1, V_C2 between the first terminal and second terminal of the first capacitor unit Cl and second capacitor unit C2. According to FIG. 2, the step 2000 follows the step 1000. This may be vice versa or the steps 1000 and 2000 may be performed simultaneously. For controlling a conversion of a voltage at the first terminal X of each power converter la, lb to a further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb the method comprises a step 3000 of generating for each of the controllable semiconductor switches of the second switch unit of the first power converter la and the first switch unit of the second power converter lb a different duty cycle for switching the controllable semiconductor switch. As shown in FIG. 2, the step 3000 may be performed by performing the following steps 3000a, 3000b and 3000c. The step 3000a comprises or is computing, using the measured current II and voltage VI at the first terminal X of the first power converter la and the measured current 12 and voltage V2 at the first terminal X of the second power converter lb, a single duty cycle D with regard to a maximum power point tracking (MPPT). The step 3000b comprises or is computing, using the measured voltages V_C1, V_C2 of the first and second capacitor unit Cl, C2 and measured voltages V_Cla, V_Clb of the capacitor Cla, Clb of the first and second power converter la, lb, a first correction parameter 51 for balancing the voltages V_C1, V_C2 of the first and second capacitor unit Cl, C2; a second correction parameter 52 for balancing the voltages V_Cla, V_Clb of the capacitor Cla of the first power converter la and capacitor Clb of the second power converter lb; and a third correction parameter 53 for keeping an average of the voltage V_Cla of the capacitor Cla of the first power converter la and the voltage V_Clb of the capacitor Clb of the second power converter lb smaller than 50% of the sum of the voltage V_C1 of the first capacitor unit Cl and the voltage V_C2 of the second capacitor unit C2. The correction parameters may be computed in any order and / or at least partly simultaneously. The step 3000c comprises or is computing the duty cycle for switching the (respective) controllable semiconductor switch (i.e. the different duty cycle of each controllable semiconductor switch) using the single duty cycle D and at least one of the first correction parameter 51, second correction parameter 52 and third correction parameter 53. According to FIG. 2, the step 3000b follows the step 3000a. This may be vice versa or the steps 3000a and 3000b may be performed simultaneously. The order of the steps shown in FIG. 2 is only by way of example and, thus, may be different as long as information used by a respective step is available. This is valid for any description of method steps herein. That is, when method steps are described herein, they may be performed in any order and / or at least partly simultaneously as long as information used by a respective step is available.

[0126] In an optional implementation form of the converter 100, the first switch unit SUla, SUlb of each of the first and second power converter la, lb comprises a third semiconductor switch electrically connected between the second terminal Yl of the power converter la, lb and an end of the series connection of the two semiconductor switches of the first switch unit SUla, SUlb. The second switch unit SU2a, SU2b of each of the first and second power converter la, lb may comprise a third semiconductor switch electrically connected between the third terminal Y2 of the power converter la, lb and an end of the series connection of the two semiconductor switches of the second switch unit SU1, SU2. In addition, the first and second power converter la, lb may each comprise a second capacitor C2a, C2b that is electrically connected between the aforementioned end of the series connection of the two semiconductor switches of the first switch unit SUla, SUlb and the aforementioned end of the series connection of the two semiconductor switches of the second switch unit SU2a, SU2b. An example of such optional implementation form is shown in FIG. 7.

[0127] In case the converter 100 has the aforementioned optional implementation form, the method may comprise a step of measuring a voltage V_C2a, V_C2b at the second capacitor of each of the first and second power converter (not shown in FIG. 2). The step 3000b may comprise computing a fourth correction parameter 54 for balancing the voltages V_C2a, V_C2b of the second capacitor C2a of the first power converter la and second capacitor C2b of the second power converter lb and the third correction parameter 53 may be a correction parameter for keeping an average of the voltage V_Cla of the capacitor Cla of the first power converter la, the voltage V_C2a of the second capacitor C2a of the first power converter la, the voltage V_Clb of the capacitor Clb of the second power converter lb and the voltage V_C2b of the second capacitor C2b of the second power converter lb smaller than 50% of the sum of the voltage V_C1 of the first capacitor unit Cl and the voltage V_C2 of the second capacitor unit C2. In the aforementioned case, the computation of step 3000b is performed using the measured voltages V_C 1 , V_C2 of the first and second capacitor unit Cl, C2 and measured voltages V_Cla, V_Clb, V_C2a, V_C2b of the capacitor Cla, Clb and second capacitor C2a, C2b of the first and second power converter la, lb. The passage “measured voltages V_Cla, V_Clb, V_C2a, V_C2b of the capacitor Cla, Clb and second capacitor C2a, C2b of the first and second power converter la, lb” means “measured voltage V_Cla of the capacitor Cla of the first power converter la, measured voltage V_C2a of the second capacitor C2a of the first power converter la, measured voltage V_Clb of the capacitor Clb of the second power converter lb and measured voltage V_C2b of the second capacitor C2b of the second power converter lb”. The correction parameters may be computed in any order and / or at least partly simultaneously. In the aforementioned case, the computation of step 3000c is computing the duty cycle for switching the (respective) controllable semiconductor switch (i.e. the different duty cycle of each controllable semiconductor switch) using the single duty cycle D and at least one of the first correction parameter 51, second correction parameter 52, third correction parameter 53 and fourth correction parameter 54. An example of an implementation form of the aforementioned optional case of performing the method of FIG. 2 is described with regard to FIGs 8 and 9.

[0128] The converter 100 (e.g. control unit of the converter) and the control device 400 of FIG. 1 may control controllable semiconductor switches by performing the method of FIG. 2.

[0129] For further information, especially examples of implementation forms of the steps and optional steps of the method of Figure 2 described above, reference is made to the description of the method of the first aspect as well as the description of FIGs 3 to 12, especially FIGs 5, 6, 8, 9 and 12.

[0130] FIG. 3 shows an example of an implementation form of the converter of FIG. 1. The converter 100 of FIG. 3 corresponds to the converter 100 of FIG. 1. Thus, the description of the converter 100 of FIG. 1 is correspondingly valid for the converter 100 of FIG. 3 and in the following mainly a difference, especially an optional feature, of the converter 100 of FIG. 3 with regard to the converter 100 of FIG. 1 is described.

[0131] As shown in FIG. 3, the converter 100 comprises one or more additional converter sections 101a. According to FIG. 3, two additional converter sections 101a are shown. This is only by way of example and, thus, only one additional converter section 101a or more than two additional converter sections 101a may be provided. For controlling the controllable semiconductor switches of an additional converter section (e.g. each additional converter section) of the one or more additional converter sections 101a the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 1) may perform the method steps described above with regard to the converter section 101 of the converter 100 of FIG. 1. That is, the description of the converter section 101 of the converter 100 of FIG. 1 is correspondingly valid for each additional converter section 101a of the converter 100 of FIG. 3. The optional features of the converter section 101 of the converter 100 of FIG. 1, which are described with regard to FIGs 2 and 4 to 12 are valid for each additional converter section 101a of the converter 100 of FIG. 3. The method steps described with regard to the method of Figure 2 may be adapted accordingly for providing a method for controlling a converter 100 of FIG. 3, i.e. a converter with one or more additional converter sections 101a.

[0132] The one or more additional converter sections 101a are implemented in line with the converter section 101 of the converter

[0133] 100. Thus, a description of the converter section 101, such as a description of the structure and control of the converter section

[0134] 101, is correspondingly valid for the one or more additional converter sections 101a. The description with regard to the sources 200a, 200b is correspondingly valid for the sources that may electrically connected with the one or more additional converter sections 101a.

[0135] The implementation form of FIG. 3 allows connecting multiple 2n electrical energy sources, such as PV systems and / or BES to the converter 100, wherein n is an integer that is greater than one (n > 1). The number of power converters of the converter section 101 and one or more additional converter sections 101a equals to the number of electrical energy sources that may be connected to the converter 100. In case n equals 1 (n = 1), the converter 100 corresponds to the implementation form of FIG. 1 for two electrical energy sources.

[0136] FIG. 4 shows an example of an implementation form of the converter of FIG. 1. The converter of FIG. 4 corresponds to the converter of FIG. 1. Thus, the description of the converter of FIG. 1 is correspondingly valid for the converter of FIG. 4 and in the following mainly the implementation of the converter section 101 of the converter 100 is described.

[0137] As shown in FIG. 4, the first power converter la comprises the capacitor Cla, the first switch unit SUla comprising two semiconductor switches Sila, S 12a electrically connected in series between the second terminal Y1 of the first power converter la and a node Nla, and a second switch unit SU2a comprising two semiconductor switches S21a, S22a electrically connected in series between the node Nla and the third terminal Y2 of the first power converter la. The node Nla of the first power converter la is electrically connected via an inductor La to the first terminal X of the first power converter la and the capacitor Cla is electrically connected with a midpoint (i.e. node) between the two semiconductor switches Sila, S12a of the first switch unit SUla and a midpoint (i.e. node) between the two semiconductor switches S21a, S22a of the second switch unit SU2a. The inductor La is part of the first power converter la.

[0138] The second power converter lb comprises the capacitor Cl b, the first switch unit SUlb comprising two semiconductor switches SI lb, S12b electrically connected in series between the second terminal Y1 of the second power converter lb and a node Nib, and a second switch unit SU2b comprising two semiconductor switches S21b, S22b electrically connected in series between the node Nib and the third terminal Y2 of the second power converter lb. The node Nib of the second power converter lb is electrically connected via an inductor Lb to the first terminal X of the second power converter lb and the capacitor Clb is electrically connected with a midpoint (i.e. node) between the two semiconductor switches SI lb, S12b of the first switch unit SUlb and a midpoint (i.e. node) between the two semiconductor switches S21b, S22b of the second switch unit SU2b. The inductor Lb is part of the second power converter lb.

[0139] The switches S21a, S22a of the second switch unit SU2a of the first power converter la and the switches SI lb, S12b of the first switch unit SUlb of the second power converter lb are controllable semiconductor switches. As shown in FIG. 4, they may be IGBTs, wherein a diode is connected in antiparallel to each IGBT. This is only by way of example and, thus, any other type of controllable semiconductor switch, e.g. any other type of transistor may be used. According to the example of FIG. 4, the semiconductor switches Sila, S12a of the first switch unit SUla of the first power converter la and the semiconductor switches S21b, S22b of the second switch unit SU2b of the second power converter lb are uncontrollable semiconductor switches. As shown in FIG. 4, they may be diodes. This is only by way of example and, thus, any other type of uncontrollable semiconductor switch may be used.

[0140] The first and second power converter la, lb of the converter 100 of Figure 4 may be referred to as three-level flying boost converters, i.e. converters having a three-level flying boost topology. Thus, the converter 100 may represent or comprise a back-to-back connection of two three-level flying boost converters.

[0141] FIG. 4 shows the inputs to the optional control device 400 for performing the above described control of the controllable semiconductor switches of the two power converters la, lb and the duty cycle D_Sx of the control signals (e.g. in the form of PWM signals) for controlling the controllable semiconductor switches of the two power converters la, lb. These inputs comprise a measured current II and voltage VI at the first terminal X of the first power converter la, a measured current 12 and voltage V2 at the first terminal X of the second power converter lb, a measured voltage V_Cla at the capacitor Cla of the first power converter la, a measured voltage V_Clb at the capacitor Clb of the second power converter lb, a measured voltage V_C1 between the first terminal and second terminal of the first capacitor unit Cl and a measured voltage V_C2 between the first terminal and second terminal of the second capacitor unit C2. The duty cycle for controlling the controllable semiconductor switches S21a, S22a of the second switch unit SU2a of the first power converter la are labelled as “D_S21a” and “D_S22a”, respectively. The duty cycle for controlling the controllable semiconductor switches SI lb, S 12b of the first switch unit SUlb of the second power converter lb are labelled as “D_S1 lb” and “D_S12b”, respectively. These inputs and outputs of the control device 400 are correspondingly valid in case the converter 100, especially a control unit of the converter 100, is configured to control controllable semiconductor switches of the two power converters la, lb.

[0142] The power converters la, lb of the converter section 101 of the converter 100 of FIG. 4 may have 1 / 2 of the semiconductor blocking voltage ratings to the full voltage across the first and second capacitor units Cl, C2 (e.g. the full DC link). That is, the switches used in the power converters la, lb may have 1 / 2 of the semiconductor blocking voltage rating compared to a converter that comprises instead of the switch units SUla, SUlb, SU2a, SU2b of the first and second power converters la, lb a series connection of four semiconductor switches that is electrically connected in parallel to the series connection of the first and second capacitor unit Cl, C2.

[0143] The converter 100 of FIG. 4 may optionally comprise the optional feature of one or more additional converter sections 101a described above with regard to FIG. 3. In this case, each additional converter sections 101a may be implemented in line with the converter section 101 of FIG. 4. The above description of FIG. 3 is correspondingly valid.

[0144] An example of controlling the controllable semiconductor switches of the converter 100 of FIG. 4 by generating different duty cycles for each of the controllable semiconductor switches is described with regard to FIGs 5 and 6.

[0145] FIG. 5 shows an example of an implementation form of the method of FIG. 2. The method steps of Figure 5 may be performed in case the converter to be controlled is implemented in line with the converter 100 of FIG. 4.

[0146] As shown in FIG. 5, computing the single duty cycle D with regard to a MPPT may comprise computing a first duty cycle D_MPP1 by inputting the measured current II and voltage VI at the first terminal X of the first power converter la to a first MPPT controller 400a. For example, the first MPPT controller 400a may be a string-level MPPT. This is only by way of example and, thus, may be different. That is, the present disclosure is not limited to a specific MPPT algorithm. Computing the single duty cycle D with regard to the MPPT may further comprise computing a second duty cycle D_MPP2 by inputting the measured current 12 and voltage V2 at the first terminal X of the second power converter lb to a second MPPT controller 400b. For example, the second MPPT controller 400b may be a string-level MPPT. This is only by way of example and, thus, may be different. That is, the present disclosure is not limited to a specific MPPT algorithm. Computing the single duty cycle D with regard to the MPPT may further comprise computing the single duty cycle D by computing an average 400c of the first and second duty cycle D_MPP1 and D_MPP2. This average computation is represented in FIG. 5 by the function “f(ul, u2)” in the box labelled with the reference sign “400c”. When the first and second electrical energy sources 200a, 200b are two PV systems (e.g. PV strings), the first and second MPPT controller 400a, 400b may compute, optionally estimate, the set point for the two PV systems based on actual measured values of the currents and voltages of the PV systems corresponding to the measured currents II, 12 and voltages VI, V2.

[0147] As shown in the box labelled with the reference sign “400d” in FIG. 5, computing the first correction parameter 51 may comprise computing a difference between the measured voltage V_C1 of the first capacitor unit Cl and the measured voltage V_C2 of the second capacitor unit C2 and inputting the difference in a controller. For example, the controller may be a proportional integral (PI) controller. This is only by way of example and, thus, a different controller type, such as a proportional controller may be used. As shown in the box labelled with the reference sign “400d” in FIG. 5, computing the second correction parameter 52 may comprise computing a difference between the measured voltage V_Cla of the capacitor Cla of the first power converter la and the measured voltage V_Clb of the capacitor Clb of the second power converter lb and inputting the difference in a controller. For example, the controller may be a proportional integral (PI) controller. This is only by way of example and, thus, a different controller type, such as a proportional controller may be used.

[0148] As shown in the box labelled with the reference sign “400d” in FIG. 5, computing the third correction parameter 53 may comprise computing an average of the measured voltage V_Cla of the capacitor Cla of the first power converter la and the measured voltage V_Clb of the capacitor Clb of the second power converter lb; computing a sum of the measured voltage V_C1 of the first capacitor unit Cl and the measured voltage V_C2 of the second capacitor unit C2, and subtracting the computed average from the sum and inputting the subtraction result to a controller. For example, the controller may be a proportional integral (PI) controller. This is only by way of example and, thus, a different controller type, such as a proportional controller may be used. The aforementioned average computation is represented in the box 400d of FIG. 5 by the function “f(inputs)”. The average computation may be done using an averaging function “f(inputs)” that takes moving average of all inputs.

[0149] As indicated in the box 400d of FIG. 5, computing the average of the measured voltage V_Cla of the capacitor Cla of the first power converter la and the measured voltage V_Clb of the capacitor Clb of the second power converter lb may optionally be computing the average of the measured voltage V_Cla of the capacitor Cla of the first power converter la scaled with a factor K and the measured voltage V_Clb of the capacitor Clb of the second power converter lb scaled with the factor K. For example, the factor K may equal to four. This is only by way of example and, thus, the factor may be different.

[0150] As shown in the box 400e of FIG. 5, generating for each of the controllable semiconductor switches S21a, S22a, S12b, SI lb of the second switch unit SU2a of the first power converter la and the first switch unit SUlb of the second power converter lb of the converter section 101 of the converter 100 of FIG. 4 a different duty cycle (duty cycle D_S21a, D_S22a, D_S12b, D_S1 lb, respectively) for switching the controllable semiconductor switch may comprise the steps described in the following. The duty cycle D_S21 a for switching the semiconductor switch S21 a of the second switch unit SU2a of the first power converter la electrically connected with the node Nla of the first power converter la may be computed using the single duty cycle D, the second correction parameter 52 and the third correction parameter 53. For example, the duty cycle D_S21a may be computed by adding to the duty cycle D the second correction parameter 52 and third correction parameter 53 (i.e. D+52+53).

[0151] The duty cycle D_S22a for switching the semiconductor switch S22a of the second switch unit SU2a of the first power converter la electrically connected with the third terminal Y2 of the first power converter la may be computed using the single duty cycle D and the first correction parameter 51. For example, the duty cycle D_S22a may be computed by adding the single duty cycle D and the first correction parameter 51 (i.e. D+51). The duty cycle D_S12b for switching the semiconductor switch S12b of the first switch unit SUlb of the second power converter lb electrically connected with the second terminal Y1 of the second power converter lb may be computed using the single duty cycle D, and the first correction parameter 51. For example, the duty cycle D_S12b may be computed by subtracting the first correction parameter 51 from the single duty cycle D (i.e. D-51). The duty cycle D_S1 lb for switching the semiconductor switch SI lb of the first switch unit SUlb of the second power converter lb electrically connected with the node Nib of the second power converter lb may be computed using the single duty cycle D, the second correction parameter 52 and the third correction parameter 53. For example, the duty cycle D_S1 lb may be computed by subtracting the second correction parameter 52 from the single duty cycle D and adding the third correction parameter 53 to the single duty cycle D (i.e. D-52+53). Figure 6 shows an example of control signals, e.g. PWM signals, for controlling the switches S21a, S22a, SI 2b and SI lb that have the duty cycle D_S21a, D_S22a, D_S12b and D_Sllb, respectively, as exemplarily described above. According to an alternative implementation form the duty cycles D_S21a and D_S22a may be computed as exemplarily described above for computing the duty cycles D_S1 lb and D_S12b, respectively, and the duty cycles D_S1 lb and D_S12b may be computed as exemplarily described above for computing the duty cycles D_S21a and D_S22a, respectively

[0152] FIG. 6 shows an example of a time course of control signals having duty cycles generated by performing the method steps of FIG. 5. As outlined above, Figure 6 shows an example of control signals, e.g. PWM signals, for controlling the switches S21a, S22a, SI 2b and SI lb that have the duty cycle D_S21a, D_S22a, D_S12b and D_S1 lb, respectively. Each vertical axis represents a level of the respective control signal. The control signals are PWM signals and, thus, vary between two signal levels “high” and “low”, i.e. between two values of the vertical axis. When the level of a control signal is at the high level, the switch controlled by said control signal is in the conducting state. Accordingly, when the level of the control signal is at the low level, the switch controlled by said control signal is in the non-conducting state. Each horizontal axis represents time, wherein FIG. 6 shows the control signals for a period Tswof the respective control signal and, thus, switching the respective switch. For each switch, the respective duty cycle (of the respective control signal) for controlling the switch is indicated in terms of the single duty cycle D and the first, second and third correction parameters 51, 52 and 53. In addition, FIG. 6 indicates for different time sections, especially different combinations of high and low levels of the control signals, charging and discharging of the capacitors Cla, Clb of the first and second power converters la, lb and capacitor units Cl, C2 of the converter 100.

[0153] As shown in FIG. 6, tum-on of the switches S22a and S12b to the conducting state (with corresponding switches S21a and SI lb turned-off in the non-conducting state respectively) are the only two intervals when one of the first and second capacitor unit Cl and C2 is individually connected to the electrical energy sources 200a, 200b. Therefore, these two intervals can be adjusted by the first correction factor 51 to achieve the balance of the voltages of the first and second capacitor units Cl and C2. However, as indicated in Fig. 6, this introduces a mismatch in the voltages of the capacitors Cla, Clb of the first and second power converter la, lb since these are being charged in these intervals (tum-on of the switches S22a and SI 2b to the conducting state). To compensate for that, the switching states in which the capacitors Cla, Clb of the first and second power converter la, lb are discharged i.e. tum-on intervals of switches S21a and SI lb being in the conducting state, are adjusted by the second correction factor 52. Because of the complementary nature, these correction factors are added to one switch duty cycle and subtracted from the other. The third correction factor 53 may be added to the duty cycles for switches S21a and SI lb to bring the average of the voltages of the capacitors Cla, Clb of the first and second power converter la, lb to a nominal value being smaller than 50% of the sum of the voltage of the first capacitor unit Cl and the voltage of the second capacitor unit C2.

[0154] FIG. 7 shows an example of an implementation form of the converter of FIG. 1. The converter of FIG. 7 corresponds to the converter of FIG. 4. Thus, the description of the converter of FIG. 4 is correspondingly valid for the description of the converter of FIG. 7 and in the following mainly a difference, especially optional feature, of the converter of FIG. 7 with regard to the converter of FIG. 4 is described.

[0155] As shown in FIG. 7, the first switch unit SUla of the first power converter la may comprise a third semiconductor switch SI 3a electrically connected between the second terminal Y1 of the first power converter la and an end El a of the series connection of the two semiconductor switches SI la, SI 2a of the first switch unit SUla. The first switch unit SUla of the second power converter lb may comprise a third semiconductor switch SI 3b electrically connected between the second terminal Y1 of the second power converter lb and an end Elb of the series connection of the two semiconductor switches SI lb, SI 2b of the first switch unit SUlb. The second switch unit SU2a of the first power converter la may comprise a third semiconductor switch S23a electrically connected between the third terminal Y2 of the first power converter la and an end E2a of the series connection of the two semiconductor switches S21a, S22a of the second switch unit SU2a. The second switch unit SU2b of the second power converter lb may comprise a third semiconductor switch S23b electrically connected between the third terminal Y2 of the second power converter lb and an end E2b of the series connection of the two semiconductor switches S21b, S22b of the second switch unit SU2b. The first power converter la may comprise a second capacitor C2a that is electrically connected between the end E 1 a of the series connection of the two semiconductor switches Sila, S 12a of the first switch unit SU 1 a and the end E2a of the series connection of the two semiconductor switches S21a, S22a of the second switch unit SU2a. The second power converter lb may comprise a second capacitor C2b that is electrically connected between the end Elb of the series connection of the two semiconductor switches SI lb, S12b of the first switch unit SUlb and the end E2b of the series connection of the two semiconductor switches S21b, S22b of the second switch unit SU2b.

[0156] The switches S21 a, S22a and third switch S 13a of the second switch unit SU2a of the first power converter 1 a and the switches Sl lb, S12b and the third switch SI 3b of the first switch unit SUlb of the second power converter lb are controllable semiconductor switches. As shown in FIG. 7, they may be IGBTs, wherein a diode is connected in antiparallel to each IGBT. This is only by way of example and, thus, any other type of controllable semiconductor switch, e.g. any other type of transistor may be used. According to the example of FIG. 7, the semiconductor switches Si la, S12a and the third switch S13a of the first switch unit SUla of the first power converter la and the semiconductor switches S21b, S22b and the third switch S23b of the second switch unit SU2b of the second power converter lb are uncontrollable semiconductor switches. As shown in FIG. 7, they may be diodes. This is only by way of example and, thus, any other type of uncontrollable semiconductor switch may be used.

[0157] The first and second power converter la, lb of the converter 100 of Figure 7 may be referred to as four-level flying boost converters, i.e. converters having a four-level flying boost topology. Thus, the converter 100 may represent or comprise a back- to-back connection of two four-level flying boost converters.

[0158] FIG. 7 shows the inputs to the optional control device 400 for performing the above described control of the controllable semiconductor switches of the two power converters la, lb and the duty cycle D_Sx of the control signals (e.g. in the form of PWM signals) for controlling the controllable semiconductor switches of the two power converters la, lb. These inputs comprise a measured current II and voltage VI at the first terminal X of the first power converter la, a measured current 12 and voltage V2 at the first terminal X of the second power converter lb, a measured voltage V_Cla at the capacitor Cla of the first power converter la, a measured voltage V_Clb at the capacitor Clb of the second power converter lb, a measured voltage V_C2a at the second capacitor C2a of the first power converter la, a measured voltage V_C2b at the second capacitor C2b of the second power converter lb, a measured voltage V_C1 between the first terminal and second terminal of the first capacitor unit Cl and a measured voltage V_C2 between the first terminal and second terminal of the second capacitor unit C2. The duty cycle for controlling the controllable semiconductor switches S21a, S22a, S23a of the second switch unit SU2a of the first power converter la are labelled as “D_S21a”, “D_S22a” and “D_S23a”, respectively. The duty cycle for controlling the controllable semiconductor switches Sl lb, S12b, SI 3b of the first switch unit SUlb of the second power converter lb are labelled as “D_S1 lb”, “D_S12b” and “D_S13b”, respectively. These inputs and outputs of the control device 400 are correspondingly valid in case the converter 100, especially a control unit of the converter 100, is configured to control controllable semiconductor switches of the two power converters la, lb.

[0159] The converter 100 of FIG. 7 may optionally comprise the optional feature of one or more additional converter sections 101a described above with regard to FIG. 3. In this case, each additional converter sections 101a may be implemented in line with the converter section 101 of FIG. 7. The above description of FIG. 3 is correspondingly valid. An example of controlling the controllable semiconductor switches of the converter 100 of FIG. 7 by generating different duty cycles for each of the controllable semiconductor switches is described with regard to FIGs 8 and 9.

[0160] FIG. 8 shows an example of an implementation form of the method of FIG. 2. The method steps of Figure 8 may be performed in case the converter to be controlled is implemented in line with the converter 100 of FIG. 7.

[0161] As shown in FIG. 8, computing the single duty cycle D with regard to a MPPT may be performed as outlined above with regard to FIG. 5. That is, computation of the single duty cycle D is independent of the number of switches of each switch unit SUla, SU2a, SUlb, SU2b of the two power converters la, lb.

[0162] As shown in the box labelled with the reference sign “400d” in FIG. 8, computing the first correction parameter 51 and second correction parameter 52 may be performed as outlined above with regard to FIG. 5.

[0163] In case of the converter 100 of FIG. 7, the third correction parameter 53 may be a correction parameter for keeping an average of the voltage V_Cla of the capacitor Cla of the first power converter la, the voltage V_C2a of the second capacitor C2a of the first power converter la, the voltage V_Clb of the capacitor Clb of the second power converter lb and the voltage V_C2b of the second capacitor C2b of the second power converter lb smaller than 50% of the sum of the voltage V_C1 of the first capacitor unit Cl and the voltage V_C2 of the second capacitor unit C2. As shown in the box labelled with the reference sign “400d” in FIG. 8, computing the third correction parameter 53 may comprise computing an average of the voltage V_Cla of the capacitor Cla of the first power converter la, the voltage V_C2a of the second capacitor C2a of the first power converter la, the voltage V_Clb of the capacitor Clb of the second power converter lb and the voltage V_C2b of the second capacitor C2b of the second power converter lb; computing a sum of the measured voltage V_C1 of the first capacitor unit Cl and the measured voltage V_C2 of the second capacitor unit C2, and subtracting the computed average from the sum and inputting the subtraction result to a controller. For example, the controller may be a proportional integral (PI) controller. This is only by way of example and, thus, a different controller type, such as a proportional controller may be used. The aforementioned average computation is represented in the box 400d of FIG. 8 by the function “f(inputs)”. The average computation may be done using an averaging function “f(inputs)” that takes moving average of all inputs.

[0164] As indicated in the box 400d of FIG. 8, computing the average of the voltage V_Cla of the capacitor Cla of the first power converter la, the voltage V_C2a of the second capacitor C2a of the first power converter la, the voltage V_Clb of the capacitor Clb of the second power converter lb and the voltage V_C2b of the second capacitor C2b of the second power converter lb may optionally be computing an average of the voltage V_C la of the capacitor C la of the first power converter la scaled with a first factor KI , the voltage V_C2a of the second capacitor C2a of the first power converter 1 a scaled with a second factor K2, the voltage V_Clb of the capacitor Clb of the second power converter lb scaled with a first factor KI and the voltage V_C2b of the second capacitor C2b of the second power converter lb scaled with a second factor K2. The first factor KI may be greater than the second factor K2. Optionally, the second factor K2 may equal to half the first factor KI . For example, the first factor KI may equal to three (KI = 3) and the second factor K2 may equal to three halves (K2 = 3 / 2). This is only by way of example and, thus, the factor may be different.

[0165] In addition, as shown in FIG. 8, a fourth correction parameter 54 for balancing the voltages V_C2a, V_C2b of the second capacitor C2a of the first power converter la and second capacitor C2b of the second power converter lb may be computed. As indicated in the box 400d of FIG. 8, computing the fourth correction parameter 54 may comprise computing a difference between the measured voltage V_C2a of the second capacitor C2a of the first power converter la and the measured voltage V_C2b of the second capacitor C2b of the second power converter lb and inputting the difference in a controller. For example, the controller may be a proportional integral (PI) controller. This is only by way of example and, thus, a different controller type, such as a proportional controller may be used.

[0166] As shown in the box 400e of FIG. 8, generating for each of the controllable semiconductor switches S21a, S22a, D23a, SI 3b, S12b, Sl lb of the second switch unit SU2a of the first power converter la and the first switch unit SUlb of the second power converter lb of the converter section 101 of the converter 100 of FIG. 7 a different duty cycle (duty cycle D_S21a, D_S22a, D_23a, D_S13b, D_S12b, D_S1 lb, respectively) for switching the controllable semiconductor switch may comprise the steps described in the following. The duty cycle D_S21a for switching the semiconductor switch S21a of the second switch unit SU2a of the first power converter la electrically connected with the node N1 a of the first power converter la may be computed using the single duty cycle D, the second correction parameter 52, the third correction parameter 53 and the fourth correction parameter 54. For example, the duty cycle D_S21a may be computed by adding to two times the single duty cycle D the second correction parameter 52, the third correction parameter 53 and the fourth correction parameter 54 (i.e. 2D+52+53+54).

[0167] The duty cycle D_S22a for switching the semiconductor switch S22a of the second switch unit SU2a of the first power converter la electrically connected with the third semiconductor switch S23a of the second switch unit SU2a of the first power converter la may be computed using the single duty cycle D, the third correction parameter 53 and the fourth correction parameter 54. For example, the duty cycle D_S22a may be computed by adding to the single duty cycle D the third correction parameter 53 and the fourth correction parameter 54 (i.e. D+53+54). The duty cycle D_S23a for switching the third semiconductor switch S23a of the second switch unit SU2a of the first power converter la may be computed using the single duty cycle D and the first correction parameter 51. For example, the duty cycle D_S23a may be computed by adding two times the single duty cycle D and the first correction parameter 51 (i.e. 2D+51).

[0168] The duty cycle D_S13b for switching the third semiconductor switch SI 3b of the first switch unit SUlb of the second power converter lb may be computed using the single duty cycle D, and the first correction parameter 51. For example, the duty cycle D_S13b may be computed by subtracting the first correction parameter 51 from two times the single duty cycle D (i.e. 2D-51). The duty cycle D_S12b for switching the semiconductor switch S 12b of the first switch unit SUlb of the second power converter lb electrically connected with the third semiconductor switch S13b of the first switch unit SUlb of the second power converter SU2b may be computed using the single duty cycle D, the third correction parameter 53 and the fourth correction parameter 54. For example, the duty cycle D_S12b may be computed by adding the third correction parameter 53 to the single duty cycle D and subtracting the fourth correction parameter 54 from the single duty cycle D (i.e. D+53-54). The duty cycle D_S1 lb for switching the semiconductor switch SI lb of the first switch unit SUlb of the second power converter lb electrically connected with the node Nib of the second power converter lb may be computed using the single duty cycle D, the second correction parameter 52, the third correction parameter 53 and the fourth correction parameter 54. For example, the duty cycle D_Sl lb may be computed by subtracting the second correction parameter 52 and fourth correction parameter 54 from two times the single duty cycle D and adding the third correction parameter 53 to two times the single duty cycle D (i.e. 2D-52+53- 54).

[0169] Figure 9 shows an example of control signals, e.g. PWM signals, for controlling the switches S21a, S22a, S23a, S13b, S12b and Sllb that have the duty cycle D_S21a, D_S22a, D_S23a, D_S13b, D_S12b and D_Sllb, respectively, as exemplarily described above. According to an alternative implementation form the duty cycles D_S21a, D_S22a and D_S23a may be computed as exemplarily described above for computing the duty cycles D_S1 lb, D_S12b and D_S13b, respectively, and the duty cycles D_S1 lb, D_S12b and D_S13b may be computed as exemplarily described above for computing the duty cycles D_S21a, D_S22a and D_S23a, respectively. FIG. 9 shows an example of a time course of control signals having duty cycles generated by performing the method steps of FIG. 8. As outlined above, Figure 9 shows an example of control signals, e.g. PWM signals, for controlling the switches S21a, S22a, S23a, S13b, S12b and SI lb that have the duty cycle D_S21a, D_S22a, D_S23a, D_S13b, D_S12b and D_S1 lb, respectively. Each vertical axis represents a level of the respective control signal. The control signals are PWM signals and, thus, vary between two signal levels “high” and “low”, i.e. between two values of the vertical axis. When the level of a control signal is at the high level, the switch controlled by said control signal is in the conducting state. Accordingly, when the level of the control signal is at the low level, the switch controlled by said control signal is in the non-conducting state.

[0170] Each horizontal axis represents time, wherein FIG. 9 shows the control signals for a period Tswof the control signals for switches S21a, S23a, S13b and SI lb and, thus, switching the respective switch. In the example of FIG. 9, it is assumed that the switching frequency for controlling and, thus, switching the switches S22a and S12b is greater (e.g. two times greater) than the switching frequency for controlling and, thus, switching the switches S21a, S23a, S13b and SI lb. This is only by way of example and may be different. For each switch the respective duty cycle (of the respective control signal) for controlling the switch is indicated in terms of the single duty cycle D and the first, second, third and fourth correction parameters 51, 52, 53 and 54. In addition, FIG. 9 indicates for different time sections, especially different combinations of high and low levels of the control signals, charging and discharging of the capacitors Cl a, Clb and second capacitors C2a, C2b of the first and second power converters 1 a, 1 b and capacitor units C 1 , C2 of the converter 100.

[0171] FIGs 10 and 11 each show an example of an implementation form of the converter of FIG. 1. The implementation form of the converter of Figure 10 is identical to the implementation form of the converter of FIG. 11. Figure 10 shows the converter with labelled terminals X, Y1 and Y2 of the first and second power converter la, lb, whereas FIG. 11 does not show this detail. The converter of Figures 10 and 11 correspond to the converter of FIG. 4. Thus, the description of the converter of FIG. 4 is correspondingly valid for the description of the converter of FIGs 10 and 11 and in the following mainly a difference, especially optional feature, of the converter of FIGs 10 and 11 with regard to the converter of FIG. 4 is described. In the following the converter of FIG. 10 is described, wherein this description is valid for the converter of FIG. 11.

[0172] The converter 100 of FIG. 10 differs from the converter 100 of FIG. 4 in that according to the example of FIG. 10 the semiconductor switches SI 2a, SI la of the first switch unit SUla of the first power converter la and the semiconductor switches S21b, S22b of the second switch unit SU2b of the second power converter lb are controllable semiconductor switches. As shown in FIG. 10, they may be IGBTs, wherein a diode is connected in antiparallel to each IGBT. This is only by way of example and, thus, any other type of controllable semiconductor switch, e.g. any other type of transistor may be used. Since all semiconductor switches of the first power converter la and second power converter lb of the converter section 101 of the converter 100 of FIG. 10 are controllable semiconductor switches, the converter 100 of FIG. 10 is a bidirectional converter. In this case, the first and second electrical energy sources 200a, 200b may be rechargeable battery energy storages (BES) and the load 300 may be configured to use electrical energy from the BES 200a, 200b (power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter 100) and charge the BES 200a, 200b with electrical energy (power flow from the terminals T5, T6 to the terminals Tl, T2, T3, T4 of the converter 100). Thus, the converter 100 being bidirectional supports discharging and charging of the BES 200a, 200b.

[0173] FIG. 12 shows how the different duty cycles of the control signals for controlling the switches of the converter section 101 of the converter 100 of FIG. 11 may be generated for achieving a charging mode (the BES 200a, 200b are being charged when connected with the terminals Tl, T2, T3 and T4 of the converter section 101) and a discharging mode (the BES 200a, 200b are being discharged when connected with the terminals Tl, T2, T3 and T4 of the converter section 101). The converter 100 of FIG. 10 may optionally comprise the optional feature of one or more additional converter sections 101a described above with regard to FIG. 3. In this case, each additional converter sections 101a may be implemented in line with the converter section 101 of FIG. 10. The above description of FIG. 3 is correspondingly valid.

[0174] FIG. 12 shows an example of an implementation form of the method of FIG. 2. The method steps of FIG. 12 correspond to the method steps of FIG. 5 and, thus, the description of FIG. 5 is correspondingly valid for the method steps of FIG. 12.

[0175] As shown in FIG. 12, computation of the single duty cycle D may be computed as outlined in the description of FIG. 5, wherein each of the first MPPT controller 400a and second MPPT controller 400b may be a battery controller. In Figure 12, the first duty cycle output by the first battery controller 400a and the second duty cycle output by the second battery controller 400b are labelled with the reference signs “DI” and “D2”, respectively. The computation of the first, second and third correction parameter 51, 52, 53, shown in the box “400d” of FIG. 12, may be performed as outlined with regard to FIG. 5.

[0176] In order to achieve a discharging of the BES 200a, 200b, i.e. a discharge mode, a conversion of the voltage at the first terminal X of each power converter la, lb to the further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb may be controlled. As shown in FIG. 12, for controlling the conversion of the voltage at the first terminal X of each power converter la, lb to the further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb the following steps may be performed by the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 1). The controllable semiconductor switches S12a, Sila of the first switch unit SUla of the first power converter la and the semiconductor switches S21b, S22b of the second switch unit SU2b of the second power converter lb are not switched. That is, the duty cycles D_S12a, D_S1 la, D_S21b, D_S22b for the switches S12a, Si la, S21b, S22b, respectively, are set to zero. The duty cycles D_S21a, D_S22a for the switches S21a, S22a, respectively, of the second switch unit SU2a of the first power converter la and the duty cycles D_S12b, D_S1 lb for the switches S12b, SI lb, respectively, of the first switch unit SUlb of the second power converter lb are computed as described with regard to FIG. 5. Thus, with regard thereto, reference is made to the description of FIG. 5.

[0177] In order to achieve a charging of the BES 200a, 200b, i.e. a charge mode, a conversion of a voltage at the second and third terminal Yl, Y2 of each power converter la, lb to a further voltage of lower or higher level at the first terminal X of each power converter la, lb may be controlled. As shown in FIG. 12, for controlling a conversion of a voltage at the second and third terminal Yl , Y2 of each power converter la, lb to a further voltage of lower or higher level at the first terminal X of each power converter la, lb the following steps may be performed by the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 1). The controllable semiconductor switches S21a, S22a of the second switch unit SU2a of the first power converter la and the semiconductor switches S12b, SI lb of the first switch unit SUlb of the second power converter lb are not switched. That is, the duty cycles D_S21a, D_S22a, D_S12b, D_S1 lb for the switches S21a, S22a, S12b, SI lb, respectively, are set to zero. The duty cycles D_S1 la, D_S12a for the switches Si la, S12a, respectively, may be computed as described in FIG. 5 for the duty cycle D_S21a for the switch S21a and the duty cycle D_S22a for the switch S22a, respectively. The duty cycles D_S22b, D_S21b for the switches S22b, S21b, respectively, may be computed as described in FIG. 5 for the duty cycle D_S12b for the switch S12b and the duty cycle D_S1 lb for the switch SI lb, respectively.

[0178] According to an optional implementation form of the converter 100 of FIG. 7, the converter 100 of FIG. 7 may be changed in that the semiconductor switches Si la, S12a and the third switch S13a of the first switch unit SUla of the first power converter la and the semiconductor switches S21b, S22b and the third switch S23b of the second switch unit SU2b of the second power converter lb are controllable semiconductor switches (not shown in the FIGs). These controllable semiconductor switches may be IGBTs, wherein a diode is connected in antiparallel to each IGBT. This is only by way of example and, thus, any other type of controllable semiconductor switch, e.g. any other type of transistor may be used. The aforementioned optional implementation form of the converter 100 of FIG. 7 is a bidirectional converter. The description of FIG. 7 is correspondingly valid for the aforementioned optional implementation form of the converter 100 of FIG. 7. In the following a discharge mode and charge mode of the aforementioned optional implementation form of the converter 100 of FIG. 7 is described.

[0179] In order to achieve a discharging of the BES 200a, 200b, i.e. a discharge mode, a conversion of the voltage at the first terminal X of each power converter la, lb to the further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb may be controlled. For controlling the conversion of the voltage at the first terminal X of each power converter la, lb to the further voltage of lower or higher level at the second and third terminal Yl, Y2 of each power converter la, lb the following steps may be performed by the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 1). The controllable semiconductor switches S13a, S12a, Si la of the first switch unit SUla of the first power converter la and the semiconductor switches S21b, S22b, S23b of the second switch unit SU2b of the second power converter lb are not switched. That is, the duty cycles D_S13a, D_S12a, D_Slla, D_S21b, D_S22b, D_S23b for the switches S13a, S12a, Sila, S21b, S22b, S23b, respectively, are set to zero. The duty cycles D_S21a, D_S22a, D_S23a for the switches S21a, S22a, S23a, respectively, of the second switch unit SU2a of the first power converter la and the duty cycles D_S13b, D_S12b, D_S1 lb for the switches S13b, S12b, SI lb, respectively, of the first switch unit SUlb of the second power converter lb are computed as described with regard to FIG. 8. Thus, with regard thereto, reference is made to the description of FIG. 8.

[0180] In order to achieve a charging of the BES 200a, 200b, i.e. a charge mode, a conversion of a voltage at the second and third terminal Yl, Y2 of each power converter la, lb to a further voltage of lower or higher level at the first terminal X of each power converter la, lb may be controlled. For controlling a conversion of a voltage at the second and third terminal Yl, Y2 of each power converter la, lb to a further voltage of lower or higher level at the first terminal X of each power converter la, lb the following steps may be performed by the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 1). The controllable semiconductor switches S21a, S22a, S23a of the second switch unit SU2a of the first power converter la and the semiconductor switches S13b, S12b, SI lb of the first switch unit SUlb of the second power converter lb are not switched. That is, the duty cycles D_S21a, D_S22a, D_S23a, D_S13b, D_S12b, D_Sl lb for the switches S21a, S22a, S23a, SI 3b, S12b, Sl lb, respectively, are set to zero. The duty cycles D_Slla, D_S12a, D_S13a for the switches Si la, S12a, SI 3a, respectively, may be computed as described in FIG. 8 for the duty cycle D_S23a for the switch S23a, the duty cycle D_S22a for the switch S22a and the duty cycle D_S21a for the switch S21a, respectively. The duty cycles D_S23b, D_S22b, D_S21b for the switches S23b, S22b, S21b, respectively, may be computed as described in FIG. 8 for the duty cycle D_S13b for the switch SI 3b, the duty cycle D_S12b for the switch SI 2b and the duty cycle D_S1 lb for the switch Sl lb, respectively.

[0181] The aforementioned optional implementation form of the converter 100 of FIG. 7 may optionally comprise the optional feature of one or more additional converter sections 101a described above with regard to FIG. 3. In this case, each additional converter sections 101a may be implemented in line with the converter section 101 of the aforementioned optional implementation form of the converter 100 of FIG. 7. The above description of FIG. 3 is correspondingly valid.

[0182] FIG. 13 shows an example of a converter of this disclosure. The converter of FIG. 13 is an example of the converter of the sixth aspect. Thus, the description of the converter of the sixth aspect is correspondingly valid for the converter of FIG. 13. The converter of FIG. 13 corresponds to the converter of FIG. 4, wherein the first and second power converters la, lb of the converter section 101 of the converter of FIG. 13 are differently implemented compared to the first and second power converters la, lb of the converter section 101 of the converter of FIG. 4. Thus, the description of FIGs 1, 3 and 4 is correspondingly valid for the converter 100 of FIG. 13 and in the following mainly the implementation form of the power converters la, lb of the converter section 101 of the converter 100 of FIG. 13 is described. As shown in FIG. 13, the converter section 101 of the converter 100 may comprise the first and second power converter la, lb each comprising the first terminal X, the second terminal Y1 and the third terminal Y2. The first power converter la comprises a first switch unit SUla comprising or being a semiconductor switch Si la connected between the second terminal Y1 of the first power converter la and a node Nla, and a second switch unit SU2a comprising or being a semiconductor switch S21a electrically connected between the node Nla and the third terminal Y2 of the first power converter la. The node Nla is electrically connected via an inductor La to the first terminal X of the first power converter la. The inductor La is part of the first power converter la. The second power converter lb comprises a first switch unit SUlb comprising or being a semiconductor switch SI lb connected between the second terminal Y1 of the second power converter lb and a node Nib, and a second switch unit SU2b comprising or being a semiconductor switch S21b electrically connected between the node Nib and the third terminal Y2 of the second power converter lb. The node Nib is electrically connected via an inductor Lb to the first terminal X of the second power converter lb. The inductor Lb is part of the second power converter lb.

[0183] The switch S21a of the second switch unit SU2a of the first power converter la and the switch SI lb of the first switch unit SUlb of the second power converter lb are controllable semiconductor switches. According to a first alternative, the switch SI la of the first switch unit SUla of the first power converter la and the switch S21b of the second switch unit SU2b of the second power converter lb are controllable semiconductor switches (as shown in FIG. 13). For example, as shown in FIG. 13, the controllable switches may be IGBTs, wherein a diode is connected in antiparallel to each IGBT. This is only by way of example and, thus, any other type of controllable semiconductor switch, e.g. any other type of transistor may be used. According to a second alternative, the switch SI la of the first switch unit SUla of the first power converter la and the switch S21b of the second switch unit SU2b of the second power converter lb are uncontrollable semiconductor switches (not shown in FIG. 13). For example, the uncontrollable semiconductor switches may be diodes. This is only by way of example and, thus, any other type of uncontrollable semiconductor switch may be used.

[0184] Compared to the power converters la, lb of the converter 100 of FIG. 4, the power converters la, lb of the converter 100 of FIG. 13 do not comprise the capacitor Cla, Clb. As a result, for generating different duty cycles for switching the controllable semiconductor switches of the converter 100 of FIG. 13, the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 4) for controlling the converter 100 may be configured to compute the single duty cycle D and the correction parameter 51 for balancing the voltages of the first and second capacitor unit Cl, C2. In above description, this correction parameter 51 is referred to as first correction parameter 51.

[0185] In above mentioned second alternative, the converter 100 is unidirectional. In this case, the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 4) may generate the duty cycle D_S21a for switching the controllable semiconductor switch S21a as outlined in the description of FIGs 5 and 6 for generating the duty cycle D_S22a for switching the controllable semiconductor switch S22a of the converter 100 of FIG 4. The converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 4) may generate the duty cycle D_S1 lb for switching the controllable semiconductor switch SI lb as outlined in the description of FIGs 5 and 6 for generating the duty cycle D_S12b for switching the controllable semiconductor switch S12ab of the converter 100 of FIG. 4. This allows controlling a conversion of a voltage at the first terminal X of each power converter la, lb to a further voltage of lower or higher level at the second and third terminal Y1 , Y2 of each power converter la, lb.

[0186] In above mentioned first alternative (shown in FIG. 13), the converter 100 is bidirectional and, thus, supports discharging and charging of the sources 200a, 200b being BES 200a, 200b. For achieving a charging mode and a discharging mode, the converter 100 (e.g. control unit of the converter) or the control device 400 (shown in FIG. 4) may generate the duty cycles D_S1 la, D_S21a, D_S1 lb and D_S21b for the controllable semiconductor switches SI la, S21a, SI lb and S21b, respectively, as outlined in the description of FIG. 12 for generating the duty cycles D_S12a, D_S22a, D_S12b and D_S22b for switching the switches S12a, S22a, S12b and S22b of the converter of FIG. 11, respectively.

[0187] The converter 100 of FIG. 13 may optionally comprise the optional feature of one or more additional converter sections 101a described above with regard to FIG. 3. In this case, each additional converter sections 101a may be implemented in line with the converter section 101 of FIG. 13. The above description of FIG. 3 is correspondingly valid.

[0188] Herein, any bidirectional converter according to this disclosure may be used with PV systems alone as electrical energy sources 200a, 200b, or with battery energy storages (BES) alone as electrical energy sources 200a, 200b, or with a combination of one or more PV systems and one or more BES as electrical energy sources 200a, 200b. When using PV systems alone as electrical energy sources 200a, 200b, it gives the possibility of condition monitoring of the PV systems through photo-luminescence. The PV systems may be energized at night (thanks to the bidirectional power flow capability of the converter) and high-resolution photos of the luminescent PV systems may be captured. Post-processing of these images allows identifying PV cells defects or degradation of the PV system. Balancing of the voltages of the capacitors of the first and second power converters of any converter according to this disclosure by adapting the individual duty cycles with correction factors remains valid even if the imbalance is induced by the imbalance of grid phase voltages, i.e. imbalance from the load side. Herein, the methods and converters according to this disclosure allow a scalability for higher voltage applications without compromising efficiency and costs. The methods and converters according to this disclosure allow having a well-protected system against ground faults and a low-cost MPPT DC-DC converter. This allows for string level optimization instead of numerous strings being maintained at a single MPPT (SOA). Moreover, methods and converters according to this disclosure allow extension of PV strings, BES integration or any combination of both.

[0189] The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. A method for controlling a converter (100), wherein the converter (100) comprises a converter section (101), and a series connection of a first and second capacitor unit (Cl, C2), wherein the converter section (101) comprises: a first, second, third and fourth terminal (T1 , T2, T3, T4) for receiving DC voltages, and a first and second power converter (la, lb) each comprising a first, second and third terminal (X, Yl, Y2), a capacitor (C l a: Clb), a first switch unit iSIJ Ia: SUlb) comprising two semiconductor switches (Si la, S I 2a: Sl lb, S12b) electrically connected in series between the second terminal (Yl) of the power converter (la; lb) and a node (Nla; Nib), and a second switch unit (SU2a; SU2b) comprising two semiconductor switches (S21a, S22a; S21b, S22b) electrically connected in series between the node (Nla; Nib) and the third terminal (Y2) of the power converter (la; lb), the node (Nla; Nib) being electrically connected via an inductor (La; Lb) to the first terminal (X) of the power converter (la; lb) and the capacitor (Cla; Clb) being electrically connected with a midpoint between the two semiconductor switches (Si la, SI 2a; Sl lb, SI 2b) of the first switch unit (SUla; SUlb) and a midpoint between the two semiconductor switches (S21a, S22a; S21b, S22b) of the second switch unit (SU2a; SU2b), wherein the switches (S21a, S22a) of the second switch unit (SU2a) of the first power converter (la) and the switches (SI 2b, SI lb) of the first switch unit (SUlb) of the second power converter (lb) are controllable semiconductor switches, the first terminal (X) of the first power converter (la) is electrically connected with the second terminal (T2) of the converter section (101), the second and third terminal (Yl, Y2) of the first power converter (la) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively, the first terminal (T 1 ) of the converter section ( 101 ) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (lb) is electrically connected with the third terminal (T3) of the converter section (101), the second and third terminal (Yl, Y2) of the second power converter (lb) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter section ( 101 ) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the method comprises: measuring (1000) a current (II; 12) and a voltage (VI; V2) at the first terminal (X) and a voltage (V_Cla; V_Clb) at the capacitor (Cla; Clb) of each of the first and second power converter (la, lb), and measuring (2000) a voltage (V_C 1 , V_C2) between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and for controlling a conversion of a voltage at the first terminal (X) of each power converter (la, lb) to a further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb) the method comprises: generating (3000) for each of the controllable semiconductor switches (S21a, S22a, S12b, Sl lb) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) a different duty cycle (D_S21a; D_S22a; D_S12b; D_S1 lb) for switching the controllable semiconductor switch by:computing (3000a), using the measured current (Il ) and voltage (VI ) at the first terminal (X) of the first power converter (la) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb), a single duty cycle (D) with regard to a maximum power point tracking, MPPT; computing (3000b), using the measured voltages ( V_C 1 , V_C2) of the first and second capacitor unit (C 1 , C2) and measured voltages (V_Cla, V_Clb) of the capacitor (Cl a, Clb) of the first and second power converter (la, lb), a first correction parameter (51) for balancing the voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2), a second correction parameter (52) for balancing the voltages (V_Cla, V_Clb) of the capacitor (Cl a) of the first power converter (la) and capacitor (Clb) of the second power converter (lb), and a third correction parameter (53) for keeping an average of the voltage (V_Cla) of the capacitor (Cl a) of the first power converter (la) and the voltage (V_Clb) of the capacitor (Clb) of the second power converter (lb) smaller than 50% of the sum of the voltage (V_C1) of the first capacitor unit (Cl) and the voltage (V_C2) of the second capacitor unit (C2); and computing (3000c) the duty cycle (D_S2 la; D_S22a; D_S12b; D_Sl lb) for switching the controllable semiconductor switch using the single duty cycle (D) and at least one of the first, second and third correction parameter (51, 52, 53).

2. The method according to claim 1 , wherein the converter (100) comprises one or more additional converter sections (101, 101a), and for controlling the controllable semiconductor switches of an additional converter section (101a) of the one or more additional converter sections (101, 101a) the method comprises: measuring a current (II; 12) and a voltage (VI; V2) at the first terminal (X) and a voltage (V_Cla; V_Clb) at the capacitor (Cla; Clb) of each of the first and second power converter (la, lb) of the additional converter section (101a), and for controlling a conversion of a voltage at the first terminal (X) of each power converter (la, lb) of the additional converter section ( 101 a) to a further voltage of lower or higher level at the second and third terminal ( Y 1 , Y2) of each power converter (la, lb) of the additional converter section (101a) the method comprises: generating for each of the controllable semiconductor switches (S21a, S22a, S12b, SI lb) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) of the additional converter section (101a) a different duty cycle (D_S21a; D_S22a; D_S12b; D_S1 lb) for switching the controllable semiconductor switch by: computing, using the measured current (Il ) and voltage (VI ) at the first terminal (X) of the first power converter (la) of the additional converter section (101a) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb) of the additional converter section (101a), a single duty cycle (D) with regard to a MPPT; computing, using the measured voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2) and measured voltages (V_Cla, V_Clb) of the capacitor (Cla, Clb) of the first and second power converter (la, 1 b) of the additional converter section ( 101 ), a first correction parameter (51) for balancing the voltages ( V_C 1 , V_C2) of the first and second capacitor unit (Cl, C2), a second correction parameter (52) for balancing the voltages (V_Cla, V_Clb) of the capacitor (Cla) of the first power converter (la) of the additional converter section (101a) and capacitor (Clb) of the second power converter (lb) of the additional converter section (101), and a third correction parameter (53) for keeping an average of the voltage (V_Cla) of the capacitor (Cla) of the first power converter ( 1 a) of the additional converter section (101a) and the voltage ( V_C 1 b) of the capacitor (Clb) of the second power converter (lb) of the additional converter section (101a) smaller than 50% of the sum of the voltage (V_C 1 ) of the first capacitor unit (Cl) and the voltage ( V_C2) of the second capacitor unit (C2); andcomputing the duty cycle (D_S21 a; l )_S22a: l )_S 12 b: D_S1 lb) for switching the controllable semiconductor using the single duty cycle (D) and at least one of the first, second and third correction parameter (51, 52, 53).

3. The method according to any one of the previous claims, wherein computing the single duty cycle (D) with regard to a MPPT comprises: computing a first duty cycle (D_MPP1) by inputting the measured current (II) and voltage (VI) at the first terminal (X) of the first power converter (la) to a first MPPT controller (400a), computing a second duty cycle (D_MPP2) by inputting the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb) to a second MPPT controller (400b), and computing the single duty cycle (D) by computing an average of the first and second duty cycle (D_MPP1, D_MPP2).

4. The method according to any one of the previous claims, wherein computing the first correction parameter (51 ) comprises: computing a difference between the measured voltage ( V_C 1 ) of the first capacitor unit (Cl) and the measured voltage (V_C2) of the second capacitor unit (C2) and inputting the difference in a controller.

5. The method according to any one of the previous claims, wherein computing the second correction parameter (52) comprises: computing a difference between the measured voltage (V_Cla) of the capacitor (Cl a) of the first power converter (la) and the measured voltage (V_Clb) of the capacitor (Clb) of the second power converter (lb) and inputting the difference in a controller.

6. The method according to any one of the previous claims, wherein computing the third correction parameter (53) comprises: computing an average of the measured voltage ( V_C 1 a) of the capacitor (C 1 a) of the first power converter (la) and the measured voltage (V_Clb) of the capacitor (Clb) of the second power converter (lb), computing a sum of the measured voltage (V_C1) of the first capacitor unit (Cl) and the measured voltage (V_C2) of the second capacitor unit (C2), subtracting the computed average from the sum and inputting the subtraction result to a controller.

7. The method according to any one of the previous claims, wherein the semiconductor switches (Si la, S12a) of the first switch unit (SUla) of the first power converter (la) and the semiconductor switches (S21b, S22b) of the second switch unit (SU2b) of the second power converter (lb) are uncontrollable semiconductor switches, and the method comprises at least one of: computing the duty cycle (D_S21a) for switching a semiconductor switch (S21a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the node (Nla) of the first power converter (la) using the single duty cycle (D), the second correction parameter (52) and the third correction parameter (53), computing the duty cycle (D_S22a) for switching a semiconductor switch (S22a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the third terminal (Y2) of the first power converter (la) using the single duty cycle (D), and the first correction parameter (51), computing the duty cycle (D_S12b) for switching a semiconductor switch (S12b) of the first switch unit (SUlb) of the second power converter (lb) electrically connected with the second terminal (Yl) of the second power converter (lb) using the single duty cycle (D), and the first correction parameter (51), andcomputing the duty cycle (D_Sl lb) for switching a semiconductor switch (SI lb) of the first switch unit (SU lb) of the second power converter (lb) electrically connected with the node (Nib) of the second power converter (lb) using the single duty cycle (D), the second correction parameter (52) and the third correction parameter (53).

8. The method according to any one of claims 1 to 6, wherein the semiconductor switches (Si la, S12a) of the first switch unit (SUla) of the first power converter (la) and the semiconductor switches (S21b, S22b) of the second switch unit (SU2b) of the second power converter (lb) are controllable semiconductor switches, and for controlling a conversion of the voltage at the first terminal (X) of each power converter (la, lb) to the further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb) the method comprises: not switching the controllable semiconductor switches (Si la, S12a) of the first switch unit (SUla) of the first power converter (la) and the controllable semiconductor switches (S21b, S22b) of the second switch unit (SU2b) of the second power converter (lb), and the method further comprises at least one of: computing the duty cycle (D_S21a) for switching a semiconductor switch (S21a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the node (Nla) of the first power converter(la) using the single duty cycle (D), the second correction parameter (52) and the third correction parameter (53), computing the duty cycle (D_S22a) for switching a semiconductor switch (S22a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the third terminal (Y2) of the first power converter (la) using the single duty cycle (D), and the first correction parameter (51), computing the duty cycle (D_S12b) for switching a semiconductor switch (S12b) of the first switch unit (SU lb) of the second power converter (lb) electrically connected with the second terminal (Yl) of the second power converter (lb) using the single duty cycle (D), and the first correction parameter (51), and computing the duty cycle (D_Sllb) for switching a semiconductor switch (SI lb) of the first switch unit (SU lb) of the second power converter (lb) electrically connected with the node (Nib) of the second power converter(lb) using the single duty cycle (D), the second correction parameter (52) and the third correction parameter (53).

9. The method according to any one of claims 1 to 6 and 8, wherein the semiconductor switches (Si la, S12a) of the first switch unit (SUla) of the first power converter (la) and the semiconductor switches (S21b, S22b) of the second switch unit (SU2b) of the second power converter (lb) are controllable semiconductor switches, and for controlling a conversion of a voltage at the second and third terminal (Yl, Y2) of each power converter (la, lb) to a further voltage of lower or higher level at the first terminal (X) of each power converter (la, lb) the method comprises: not switching the controllable semiconductor switches (S21a, S22a) of the second switch unit (SU2a) of the first power converter (la) and the semiconductor switches (SI lb, S12b) of the first switch unit (SUlb) of the second power converter (lb), and the method further comprises at least one of: computing the duty cycle (D_S1 la) for switching a semiconductor switch (Si la) of the first switch unit (SUla) of the first power converter (la) electrically connected with the node (Nla) of the first power converter (la) using the single duty cycle (D), the second correction parameter (52) and the third correction parameter (53),computing the duty cycle (D_S12a) for switching a semiconductor switch (S12a) of the first switch unit (SUla) of the first power converter (la) electrically connected with the second terminal (Yl) of the first power converter (la) using the single duty cycle (D) and the first correction parameter (51), computing the duty cycle (D_S22b) for switching a semiconductor switch (S22b) of the second switch unit (SU2b) of the second power converter (2b) electrically connected with the third terminal (Y2) of the second power converter (lb) using the single duty cycle (D) and the first correction parameter (51), and computing the duty cycle (D_S21b) for switching a semiconductor switch (S21b) of the second switch unit (SU2b) of the second power converter (lb) electrically connected with the node (Nib) of the second power converter (lb) using the single duty cycle (D), the second correction parameter (52) and the third correction parameter (53).

10. The method according to any one of claims 1 to 6, wherein the first switch unit (SUla; SUlb) of each of the first and second power converter (la, lb) comprises a third semiconductor switch (S 13a; S 13b) electrically connected between the second terminal ( Yl ) of the power converter (la; lb) and an end (Ela; Elb) of the series connection of the two semiconductor switches (Si la, S12a; SI lb, S12b) of the first switch unit (SUla; SUlb), the second switch unit (SU2a; SU2b) of each of the first and second power converter (la, lb) comprises a third semiconductor switch (S23a; S23b) electrically connected between the third terminal (Y2) of the power converter (la; lb) and an end (E2a; E2b) of the series connection of the two semiconductor switches (S21a, S22a; S21b, S22b) of the second switch unit (SU2a; SU2b), and the first and second power converter (la, lb) each comprise a second capacitor (C2a; C2b) that is electrically connected between the end (Ela; El b) of the series connection of the two semiconductor switches (Sila, SI 2a; SI lb, S12b) of the first switch unit (SUla; SUlb) and the end (E2a; E2b) of the series connection of the two semiconductor switches (S21a, S22a; S21b, S22b) of the second switch unit (SU2a; SU2b); wherein the method comprises: measuring a voltage (V_C2a; V_C2b) at the second capacitor (C2a; C2b) of each of the first and second power converter (la, lb), and generating for each of the controllable semiconductor switches (S21a, S22a, S23a, Sllb, S12b, S13b) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) a different duty cycle (D_S21a; D_S22a; D_S23a; D_Sllb; D_S12b; D_S13b) for switching the controllable semiconductor switch comprises: computing, using the measured current (II) and voltage (VI) at the first terminal (X) of the first power converter (la) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb), a single duty cycle (D) with regard to a MPPT; computing, using the measured voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2) and measured voltages (V_Cla, V_Clb, V_C2a, V_C2b) of the capacitor (Cla; Clb) and second capacitor (C2a; C2b) of the first and second power converter (la, lb), the first, second and third correction parameter (51, 52, 53) and a fourth correction parameter (54) for balancing the voltages (V_C2a) of the second capacitor (C2a; C2b) of the first power converter (la) and second capacitor (V_C2b) of the second power converter (C2b), the third correction parameter (53) being a correction parameter for keeping an average of the voltage (V_Cla)of the capacitor (Cla) of the first power converter (la), the voltage (V_C2b) of the second capacitor (C2a) of the first power converter (la), the voltage (V_Clb) of the capacitor (Clb) of the second power converter (lb) and the voltage (V_C2b) of the second capacitor (C2b) of the second power converter (lb) smaller than 50% of the sum of the voltage (V_C1) of the first capacitor unit (Cl) and the voltage (V_C2) of the second capacitor unit (C2); andcomputing the duty cycle l'I )_S21 a: l )_S22a: l )_S23a: l )_S I I b: l )_S 12b: D_S13b) for switching the controllable semiconductor using the single duty cycle (D) and at least one of the first, second, third and fourth correction parameter (51, 52, 53, 54).

11. The method according to claim 10, wherein computing the fourth correction parameter (54) comprises: computing a difference between the measured voltage (V_C2a) of the second capacitor (C2a) of the first power converter (la) and the measured voltage (V_C2b) of the second capacitor (C2b) of the second power converter (lb) and inputting the difference in a controller.

12. The method according claim 10 or 11 , wherein computing the third correction parameter (53) comprises: computing an average of the voltage (V_Cla) of the capacitor (Cl a) of the first power converter (la), the voltage (V_C2a) of the second capacitor (C2a) of the first power converter (la), the voltage (V_Clb) of the capacitor (Clb) of the second power converter (lb) and the voltage (V_C2b) of the second capacitor (C2b) of the second power converter (lb), computing a sum of the measured voltage (V_C1) of the first capacitor unit (Cl) and the measured voltage (V_C2) of the second capacitor unit (C2), subtracting the computed average from the sum and inputting the subtraction result to a controller.

13. The method according to any one of claims 10 to 12, wherein the semiconductor switches (Si la, S12a, SI 3a) of the first switch unit (SU la) of the firstpower converter (la) and the semiconductor switches (S21b, S22b, S23b) of the second switch unit (SU2b) of the second power converter (lb) are uncontrollable semiconductor switches, and the method comprises at least one of: computing the duty cycle (D_S21a) for switching a semiconductor switch (S21a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the node (Nla) of the first power converter(la) using the single duty cycle (D), the second correction parameter (52), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_S22a) for switching a semiconductor switch (S22a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the third semiconductor switch (S23a) of the second switch unit (SU2a) of the first power converter (la) using the single duty cycle (D), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_S23a) for switching the third semiconductor switch (S23a) of the second switch unit (SU2a) of the first power converter (la) using the single duty cycle (D) and the first correction parameter (51), computing the duty cycle (D_S 13b) for switching the third semiconductor switch (S 13b) of the first switch unit (SUlb) of the second power converter (lb) using the single duty cycle (D) and the first correction parameter (81), computing the duty cycle (D_S12b) for switching a semiconductor switch (S12b) of the first switch unit (SUlb) of the second power converter (lb) electrically connected with the third semiconductor switch (SI 3b) of the first switch unit (SUlb) of the second power converter (lb) using the single duty cycle (D), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_Sllb) for switching a semiconductor switch (SI lb) of the first switch unit (SUlb) of the second power converter (lb) electrically connected with the node (Nib) of the second power converter(lb) using the single duty cycle (D), the second correction parameter (52), the third correction (53) and the fourth correction parameter (54).

14. The method according to any one of claims 10 to 12, wherein the semiconductor switches (Sila, S12a, SI 3a) of the first switch unit (SU la) of the first power converter (la) and the semiconductor switches (S21b, S22b, S23b) of the second switch unit (SU2b) of the second power converter (lb) are controllable semiconductor switches, and for controlling a conversion of the voltage at the first terminal (X) of each power converter (la, lb) to the further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb) the method comprises: not switching the controllable semiconductor switches (Sila, S12a, SI 3a) of the first switch unit (SU la) of the first power converter (la) and the semiconductor switches (S21b, S22b, S23b) of the second switch unit (SU2b) of the second power converter (lb), and the method further comprises at least one of: computing the duty cycle (D_S21a) for switching a semiconductor switch (S21a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the node (Nla) of the first power converter(la) using the single duty cycle (D), the second correction parameter (52), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_S22a) for switching a semiconductor switch (S22a) of the second switch unit (SU2a) of the first power converter (la) electrically connected with the third semiconductor switch (S23a) of the second switch unit (SU2a) of the first power converter (la) using the single duty cycle (D), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_S23a) for switching the third semiconductor switch (S23a) of the second switch unit (SU2a) of the first power converter (la) using the single duty cycle (D) and the first correction parameter (51), computing the duty cycle (D_S 13b) for switching the third semiconductor switch (S13b) ofthe first switch unit (SUlb) of the second power converter (lb) using the single duty cycle (D) and the first correction parameter (81), computing the duty cycle (D_S12b) for switching a semiconductor switch (S12b) of the first switch unit (SUlb) of the second power converter (lb) electrically connected with the third semiconductor switch (SI 3b) of the first switch unit (SUlb) of the second power converter (lb) using the single duty cycle (D), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_Sllb) for switching a semiconductor switch (SI lb) of the first switch unit (SUlb) of the second power converter (lb) electrically connected with the node (Nib) of the second power converter(lb) using the single duty cycle (D), the second correction parameter (52), the third correction (53) and the fourth correction parameter (54).

15. The method according to any one of claims 10 to 12 and 14, wherein the semiconductor switches (Si la, S12a, S13a) of the first switch unit (SUla) of the first power converter (la) and the semiconductor switches (S21b, S22b, S23b) of the second switch unit (SU2b) of the second power converter (lb) are controllable semiconductor switches, and for controlling a conversion of a voltage at the second and third terminal (Yl, Y2) of each power converter (la, lb) to a further voltage of lower or higher level at the first terminal (X) of each power converter (la, lb) the method comprises: not switching the controllable semiconductor switches (S21a, S22a, S23a) of the second switch unit (SU2a) of the first power converter (la) and the semiconductor switches (SI lb, S12b, SI 3b) of the first switch unit (SUlb) of the second power converter (lb), and the method further comprises at least one of:computing the duty cycle (D_S1 la) for switching a semiconductor switch (Si la) of the first switch unit (SUla) of the first power converter (la) electrically connected with the node (Nla) of the first power converter (la) using the single duty cycle (D), the second correction parameter (52), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_S12a) for switching a semiconductor switch (S12a) of the first switch unit (SUla) of the first power converter (la) electrically connected with the third semiconductor switch (SI 3a) of the first switch unit (SUla) of the first power converter (la) using the single duty cycle (D), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_S 13a) for switching the third semiconductor switch (S 13a) of the first switch unit (SU 1 a) of the first power converter (la) using the single duty cycle (D) and the first correction parameter (51 ), computing the duty cycle (D_S23b) for switching the third semiconductor switch (S23b) of the second switch unit (SU2b) of the second power converter (lb) using the single duty cycle (D) and the first correction parameter (51), computing the duty cycle (D_S22b) for switching a semiconductor switch (S22b) of the second switch unit (SU2b) of the second power converter (lb) electrically connected with the third semiconductor switch (SI 3b) of the second switch unit (SU2b) of the second power converter (lb) using the single duty cycle (D), the third correction parameter (53) and the fourth correction parameter (54), computing the duty cycle (D_S21b) for switching a semiconductor switch (S21b) of the second switch unit (SU2b) of the second power converter (lb) electrically connected with the node (Nib) of the second power converter (lb) using the single duty cycle (D), the second correction parameter (52), the third correction (53) and the fourth correction parameter (54).

16. A control device for controlling a converter, wherein the converter (100) comprises a converter section (101), and a series connection of a first and second capacitor unit (Cl, C2), wherein the converter section (101) comprises: a first, second, third and fourth terminal (Tl, T2, T3, T4) for receiving DC voltages, and a first and second power converter (la, lb) each comprising a first, second and third terminal (X, Yl, Y2), a capacitor iC I a: Clb), a first switch unit (SUla; SUlb) comprising two semiconductor switches (Si la, S12a; SI lb, SI 2b) electrically connected in series between the second terminal (Yl) of the power converter (la; lb) and a node (Nla; Nib), and a second switch unit (SU2a; SU2b) comprising two semiconductor switches (S21a, S22a; S21b, S22b) electrically connected in series between the node (Nla; Nib) and the third terminal (Y2) of the power converter (la; lb), the node (Nla; Nib) being electrically connected via an inductor (La; Lb) to the first terminal (X) of the power converter (la; lb) and the capacitor (Cla; Clb) being electrically connected with a midpoint between the two semiconductor switches (Si la, SI 2a; SI lb, SI 2b) of the first switch unit (SUla; SUlb) and a midpoint between the two semiconductor switches (S21a, S22a; S21b, S22b) of the second switch unit (SU2a; SU2b), wherein the switches (S21a, S22a) of the second switch unit (SU2a) of the first power converter (la) and the switches (SI 2b, SI lb) of the first switch unit (SUlb) of the second power converter (lb) are controllable semiconductor switches, the first terminal (X) of the first power converter (la) is electrically connected with the second terminal (T2) of the converter section (101), the second and third terminal (Yl, Y2) of the first power converter (la) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively,the first terminal (T 1 ) of the converter section ( 101 ) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (lb) is electrically connected with the third terminal (T3) of the converter section (101), the second and third terminal (Yl, Y2) of the second power converter (lb) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter section (101) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the control device is configured to: obtain a measured current (II; 12) and voltage (VI ; V2) at the first terminal (X) and a measured voltage (V_Cla; V_Clb) at the capacitor (Cla; Clb) of each of the first and second power converter (la, lb), and obtain a measured voltage ( V_C 1 , V_C2) between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and the control device is configured to, for controlling a conversion of a voltage at the first terminal (X) of each power converter (la, lb) to a further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb), generate for each of the controllable semiconductor switches (S21a, S22a, S12b, SI lb) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) a different duty cycle (D_S21a; D_S22a; D_S12b; D_S1 lb) for switching the controllable semiconductor switch by: computing, using the measured current (Il ) and voltage (VI ) at the first terminal (X) of the first power converter (la) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb), a single duty cycle (D) with regard to a maximum power point tracking, MPPT; computing, using the measured voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2) and measured voltages (V_Cla, Clb) of the capacitor (Cla, Clb)of the first and second power converter (la, lb), a first correction parameter (51 ) for balancing the voltages (V_C 1 , V_C2) of the first and second capacitor unit (Cl, C2), a second correction parameter (52) for balancing the voltages (V_Cla, V_Clb) of the capacitor (Cla) of the first power converter (la) and capacitor (Clb) of the second power converter (lb), and a third correction parameter (53) for keeping an average of the voltage (V_Cla) of the capacitor (Cl a) of the first power converter (la) and the voltage (V_Clb) of the capacitor (Clb) of the second power converter (lb) smaller than 50% of the sum of the voltage (V_C1) of the first capacitor unit (Cl) and the voltage (V_C2) of the second capacitor unit (C2); and computing the duty cycle (D_S21a; D_S22a; D_S12b; D_S1 lb) for switching the controllable semiconductor switch using the single duty cycle (D) and at least one of the first, second and third correction parameter (51, 52, 53).

17. A converter comprising: a converter section (101), and a series connection of a first and second capacitor unit (Cl, C2), wherein the converter section (101) comprises: a first, second, third and fourth terminal (T1 , T2, T3, T4) for receiving DC voltages, and a first and second power converter (la, lb) each comprising a first, second and third terminal (X, Yl, Y2), a capacitor (Cla; Clb), a first switch unit (SUla; SUlb) comprising two semiconductor switches (Si la, S12a; SI lb, SI 2b) electrically connected in series between the second terminal (Yl) of the power converter (la; lb) and a node (Nla; Nib), and a second switch unit (SU2a; SU2b) comprising two semiconductor switches (S21a, S22a; S21b, S22b) electrically connected in series between the node (Nla; Nib) and the third terminal (Y2) of the power converter (la; lb), the node (Nla; Nib) being electrically connected via an inductor (La; Lb) to thefirst terminal (X) of the power converter (la; lb) and the capacitor (Cla; Clb) being electrically connected with a midpoint between the two semiconductor switches (Si la, SI 2a; SI lb, SI 2b) of the first switch unit (SUla; SUlb) and a midpoint between the two semiconductor switches (S21a, S22a; S21b, S22b) of the second switch unit (SU2a; SU2b), wherein the switches (S21a, S22a) of the second switch unit (SU2a) of the first power converter (la) and the switches (SI 2b, SI lb) of the first switch unit (SUlb) of the second power converter (lb) are controllable semiconductor switches, the first terminal (X) of the first power converter (la) is electrically connected with the second terminal (T2) of the converter section (101), the second and third terminal (Yl, Y2) of the first power converter (la) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively, the first terminal (T 1 ) of the converter section ( 101 ) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (lb) is electrically connected with the third terminal (T3) of the converter section (101), the second and third terminal (Yl, Y2) of the second power converter (lb) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter section (101) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the converter is configured to: measure a current (II; 12) and a voltage (VI; V2) at the first terminal (X) and a voltage (V_Cla; V_Clb) at the capacitor (Cla; Clb) of each of the first and second power converter (la, lb), and a voltage (V_C1, V_C2) between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and the converter is configured to, for controlling a conversion of a voltage at the first terminal (X) of each power converter (la, lb) to a further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb), generate for each of the controllable semiconductor switches (S21a, S22a, S12b, SI lb) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) a different duty cycle (D_S21a; D_S22a; D_S12b; D_Sl lb) for switching the controllable semiconductor switch by: computing, using the measured current (Il ) and voltage (VI ) at the first terminal (X) of the first power converter (la) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb), a single duty cycle (D) with regard to a maximum power point tracking, MPPT; computing, using the measured voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2) and measured voltages (V_Cla, Clb) of the capacitor (Cla, Clb) of the first and second power converter (la, lb), a first correction parameter (51 ) for balancing the voltages (V_C 1 , V_C2) of the first and second capacitor unit (Cl, C2), a second correction parameter (52) for balancing the voltages (V_Cla, V_Clb) of the capacitor (Cla) of the first power converter (la) and capacitor (Clb) of the second power converter (lb), and a third correction parameter (53 ) for keeping an average of the voltage ( V_C 1 a) of the capacitor (C 1 a) of the first power converter (la) and the voltage (V_Clb) of the capacitor (Clb) of the second power converter (lb) smaller 50% of the sum of the voltage (V_C 1 ) of the first capacitor unit (Cl) and the voltage ( V_C2) of the second capacitor unit (C2); and computing the duty cycle (D_S21a; D_S22a; D_S12b; D_S1 lb) for switching the controllable semiconductor switch using the single duty cycle (D) and at least one of the first, second and third correction parameter (51, 52, 53).

18. A method for controlling a converter (100), wherein the converter (100) comprises a converter section (101), and a series connection of a first and second capacitor unit (Cl, C2), wherein the converter section (101) comprises: a first, second, third and fourth terminal (Tl, T2, T3, T4) for receiving DC voltages, and a first and second power converter (la, lb) each comprising a first, second and third terminal (X, Yl, Y2), a first switch unit iSIJ I a: SUlb) comprising a semiconductor switch (Si la; SI lb) connected between the second terminal (Yl) of the power converter (la; lb) and a node (Nla; Nib), and a second switch unit (SU2a; SU2b) comprising a semiconductor switch (S21a; S21b) electrically connected in series between the node (Nla; Nib) and the third terminal (Y2) of the power converter (la; lb), the node (Nla; Nib) being electrically connected via an inductor (La; Lb) to the first terminal (X) of the power converter (la; lb), wherein the switch (S21a) of the second switch unit (SU2a) of the first power converter (la) and the switch (SI lb) of the first switch unit (SUlb) of the second power converter (lb) are controllable semiconductor switches, the first terminal (X) of the first power converter (la) is electrically connected with the second terminal (T2) of the converter section (101), the second and third terminal (Yl, Y2) of the first power converter (la) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively, the first terminal (T 1 ) of the converter section ( 101 ) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (lb) is electrically connected with the third terminal (T3) of the converter section (101), the second and third terminal (Yl, Y2) of the second power converter (lb) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter section (101) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the method comprises: measuring (1000) a current (II; 12) and a voltage (VI; V2) at the first terminal (X) of each of the first and second power converter (la, lb), and measuring (2000) a voltage ( V_C 1 , V_C2) between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and for controlling a conversion of a voltage at the first terminal (X) of each power converter (la, lb) to a further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb) the method comprises: generating for each of the controllable semiconductor switches (S21a, SI lb) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) a different duty cycle (D_S21a; D_S1 lb) for switching the controllable semiconductor switch by: computing, using the measured current (Il ) and voltage (VI ) at the first terminal (X) of the first power converter (la) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb), a single duty cycle (D) with regard to a maximum power point tracking, MPPT; computing, using the measured voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2) a correction parameter (51 ) for balancing the voltages (V_C 1 , V_C2) of the first and second capacitor unit (C 1 , C2); and computing the duty cycle (D_S21a; D_Sllb) for switching the controllable semiconductor switch using the single duty cycle (D) and the correction parameter (51).

19. A control device for controlling a converter (100), wherein the converter (100) comprises a converter section (101), and a series connection of a first and second capacitor unit (Cl, C2), wherein the converter section (101) comprises: a first, second, third and fourth terminal (T1 , T2, T3, T4) for receiving DC voltages, and a first and second power converter (la, lb) each comprising a first, second and third terminal (X, Yl, Y2), a first switch unit iSIJ I a: SUlb) comprising a semiconductor switch (Sila; SI lb) connected between the second terminal (Yl) of the power converter (la; lb) and a node (Nla; Nib), and a second switch unit (SU2a; SU2b) comprising a semiconductor switch (S21a; S21b) electrically connected in series between the node (Nla; Nib) and the third terminal (Y2) of the power converter (la; lb), the node (Nla; Nib) being electrically connected via an inductor (La; Lb) to the first terminal (X) of the power converter (la; lb), wherein the switch (S21a) of the second switch unit (SU2a) of the first power converter (la) and the switch (SI lb) of the first switch unit (SUlb) of the second power converter (lb) are controllable semiconductor switches, the first terminal (X) of the first power converter (la) is electrically connected with the second terminal (T2) of the converter section (101), the second and third terminal (Yl, Y2) of the first power converter (la) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively, the first terminal (Tl) of the converter section (101) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (lb) is electrically connected with the third terminal (T3) of the converter section (101), the second and third terminal (Yl, Y2) of the second power converter (lb) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter section (101) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the control device is configured to: obtain a measured current (Il ; 12) and voltage (VI ; V2) at the first terminal (X) of each of the first and second power converter (la, lb), and obtain a measured voltage (V_C1, V_C2) between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and the control device is configured to, for controlling a conversion of a voltage at the first terminal (X) of each power converter (la, lb) to a further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb), generate for each of the controllable semiconductor switches (S21a, SI lb) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) a different duty cycle (D_S21a; D_Sllb) for switching the controllable semiconductor switch by: computing, using the measured current (Il ) and voltage (VI ) at the first terminal (X) of the first power converter (la) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb), a single duty cycle (D) with regard to a maximum power point tracking, MPPT; computing, using the measured voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2) a correction parameter (51) for balancing the voltages ( V_C 1 , V_C2) of the first and second capacitor unit (C 1 , C2); and computing (3000c) the duty cycle (D_S21a; D_S1 lb) for switching the controllable semiconductor switch using the single duty cycle (D) and the correction parameter (51).

20. A converter (100) comprising: a converter section (101), and a series connection of a first and second capacitor unit (Cl, C2), wherein the converter section (101) comprises: a first, second, third and fourth terminal (Tl, T2, T3, T4) for receiving DC voltages, and a first and second power converter (la, lb) each comprising a first, second and third terminal (X, Yl, Y2), a first switch unit iSIJ I a: SUlb) comprising a semiconductor switch (Si la; SI lb) connected between the second terminal (Yl) of the power converter (la; lb) and a node (Nla; Nib), and a second switch unit (SU2a; SU2b) comprising a semiconductor switch (S21a; S21b) electrically connected between the node (Nla; Nib) and the third terminal (Y2) of the power converter (la; lb), the node (Nla; Nib) being electrically connected via an inductor (La; Lb) to the first terminal (X) of the power converter (la; lb), wherein the switch (S21a) of the second switch unit (SU2a) of the first power converter (la) and the switch (SI lb) of the first switch unit (SUlb) of the second power converter (lb) are controllable semiconductor switches, the first terminal (X) of the first power converter (la) is electrically connected with the second terminal (T2) of the converter section (101), the second and third terminal (Yl, Y2) of the first power converter (la) are electrically connected with a first and second terminal of the first capacitor unit (Cl), respectively, the first terminal (T 1 ) of the converter section ( 101 ) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (lb) is electrically connected with the third terminal (T3) of the converter section (101), the second and third terminal (Yl, Y2) of the second power converter (lb) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, and the fourth terminal (T4) of the converter section (101) is electrically connected with the second terminal of the second capacitor unit (C2); wherein the converter is configured to: measure a current (II; 12) and a voltage (VI; V2) at the first terminal (X) of each of the first and second power converter (la, lb), and measure a voltage ( V_C 1 , V_C2) between the first terminal and second terminal of the first capacitor unit (Cl) and second capacitor unit (C2), and the converter is configured to, for controlling a conversion of a voltage at the first terminal (X) of each power converter (la, lb) to a further voltage of lower or higher level at the second and third terminal (Yl, Y2) of each power converter (la, lb), generate for each of the controllable semiconductor switches (S21a, SI lb) of the second switch unit (SU2a) of the first power converter (la) and the first switch unit (SUlb) of the second power converter (lb) a different duty cycle (D_S21a; D_Sl lb) for switching the controllable semiconductor switch by: computing, using the measured current (Il ) and voltage (VI ) at the first terminal (X) of the first power converter (la) and the measured current (12) and voltage (V2) at the first terminal (X) of the second power converter (lb), a single duty cycle (D) with regard to a maximum power point tracking, MPPT; computing, using the measured voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2) a correction parameter (51) for balancing the voltages (V_C1, V_C2) of the first and second capacitor unit (Cl, C2); and computing (3000c) the duty cycle (D_S21a; D_S1 lb) for switching the controllable semiconductor switch using the single duty cycle (D) and the correction parameter (51).

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