Power converter with active filter circuit

Abstract

A power converter with a DC link with at least one DC link capacitor, an active rectifier circuit connected between AC terminals of the converter and the DC link, an active filter circuit connected between AC terminals of the converter and the DC link, wherein the active filter circuit comprises an auxiliary active rectifier circuit with auxiliary AC terminals and auxiliary DC terminals and an active filter inductor in each line between the converter AC terminals and the auxiliary AC terminals, the active filter circuit comprises a DC / DC-converter having first and second auxiliary DC terminals, the first auxiliary DC terminals being connected to the auxiliary DC terminals, wherein the DC / DC converter is configured to operate as an active common mode noise filter and the active filter circuit comprises a capacitive connection to a ground or neutral potential of the converter.

Description

[0001]202404936 Auslandsfassung 1 Description Power converter with Active Filter Circuit The present invention relates to a power converter, particularly a power converter for an electric drive, for example a power converter converting between a three-phase supply grid voltage and a three-phase voltage driving an electric motor. The power converter has an active filter circuit. Power converters need to fulfil EMC (electromagnetic compatibility) standards to be allowed to connect to the AC supply grid. Usually, passive filters are used to fulfil such standards. Passive filters are not very effective for changing grid conditions as they cannot be adjusted if additional noise appears in the grid which was not considered during design. Additionally, passive filters are typically designed for a worst-case scenario resulting in large components even though the converter will rarely ever encounter that worst-case scenario. Active filters can solve some of the problems of passive filters. They can adapt when grid conditions change, e.g. when additional noise appears from outside environments, allowing a remaining passive filter of the power converter to use much smaller components. It is an object of the present invention to provide an improved power converter having an improved active filter circuit. A power converter according to claim 1 provides a solution for this object. The power converter according to the invention comprises a DC link with at least one DC link capacitor and an active rectifier circuit connected between AC terminals of the converter and the DC link. It furthermore comprises an active filter circuit connected between AC terminals of the converter and the DC link. The active filter circuit comprises an auxiliary active rectifier circuit with auxiliary AC terminals and auxiliary DC terminals and an active filter inductor in each line between the converter AC terminals and the auxiliary AC terminals. The active filter circuit also comprises a DC / DC-converter having first and second auxiliary DC terminals, the first auxiliary DC terminals being connected to the auxiliary DC terminals of the auxiliary active rectifier circuit. The DC / DC converter is configured to operate as an active common mode noise filter. 202404936 Auslandsfassung 2 The active filter circuit comprises a capacitive connection to a ground or neutral potential of the converter. It is to be understood that the capacitive connection is based on specific circuit elements, i.e. capacitor elements. The capacitive connection is not meant to be consisting of stray capacitances. In other words, the capacitive connection comprises discrete capacitor elements, e.g. SMD elements. Preferentially, the auxiliary active rectifier circuit is configured to operate as an active DM noise filter circuit while the DC / DC converter is configured to operate as a common mode noise filter. Advantageously the proposed power converter’s active filter circuit is configured to not only reduce differential mode noise but also common mode noise thus reducing the size of a passive noise filter of the power converter. Further features that may be added alone or together in exemplary embodiments of the invention include: The power converter may comprise a passive filter circuit arranged in the AC lines connecting it to the grid. The passive filter circuit may comprise LCL-type filter parts designed to filter both differential and common mode noise. The auxiliary rectifier circuit is preferentially a 3-phase AC to DC converter. It can be a two-level converter comprising three parallel half-bridges of two semiconductor switches each. Depending on the grid voltage, it may be advantageous to use a different setup, particularly a multilevel converter. The DC / DC converter may comprise a parallel circuit comprising two half-bridges, each having two controllable semiconductor switches that are arranged in a series connection. DC / DC conversion between the terminals of the DC / DC converter is then effected by switching the semiconductor switches using a pulse width modulation scheme. Advantageously, this DC / DC converter has a simple and compact setup. This setup is particularly suited for reducing common mode noise as it allows two different semiconductor switch states to be used that have a different common mode voltage. 202404936 Auslandsfassung 3 The DC / DC converter may be connected in one of two ways with the other parts of the circuit. In a first alternative, the first auxiliary DC terminals are each connected across an inductance to one of the midpoints of the half-bridges. The outer terminals of the half-bridges form the second auxiliary DC terminals. This means that in this configuration, the DC / DC converter is connected to the auxiliary rectifier through the midpoints of the half-bridges. In a second alternative, the second auxiliary DC terminals are each connected across an inductance to one of the midpoints of the half-bridges. The outer terminals of the half-bridges form the first auxiliary DC terminals. This means that in this configuration the DC / DC converter is connected to the auxiliary rectifier through the outer terminals of the half-bridges. In a further embodiment of the power converter according to the second alternative, the second auxiliary DC terminals may be interconnected with a capacitor. In other words, the midpoints of the half-bridges of the DC / DC converter are interconnected across an LCL series connection of an inductor, a capacitor and an inductor. Depending on the configuration of the DC / DC converter, further configuration options may be used. In one embodiment of the invention, the second auxiliary DC terminals are connected to the DC link. This is preferentially a direct connection, i.e. with no other circuit elements interposed. As described above, if the second auxiliary DC terminals are connected to the midpoints of the half-bridges, inductive elements are arranged between the midpoints and the second auxiliary DC terminals, i.e. the inductive elements are present between the midpoints of the half-bridges and the DC link. In another embodiment of the power converter, the capacitive connection comprises, for each of the second auxiliary DC terminals of the DC / DC converter, a capacitor arranged between the respective terminal and ground or a neutral potential. In other words, in this embodiment, the capacitive connection is arranged at the second auxiliary DC terminals. When arranged at a DC node of the active filter circuit, the capacitive connection comprises one capacitor between each of the two DC lines and ground or the neutral potential. In another embodiment of the power converter, the capacitive connection comprises, for each of the first auxiliary DC terminals of the DC / DC converter, a capacitor arranged between the 202404936 Auslandsfassung 4 respective terminal and ground or a neutral potential. In other words, in this embodiment, the capacitive connection is arranged at the first auxiliary DC terminals. Since the first auxiliary DC terminals are connected, particularly directly connected, to the auxiliary DC terminals of the auxiliary rectifier, the capacitive connection is also arranged in direct connection to the auxiliary rectifier on its DC side. Alternatively, the capacitive connection may comprise, for each of the AC lines, a capacitor arranged between the respective line and ground or the neutral potential, connected to the line at a node between the auxiliary AC terminals and the active filter inductor, with a further inductor between the node and the auxiliary AC terminals. This means that in this embodiment, the capacitive connection is placed in an AC part of the active filter circuit and thus comprises three capacitors. In each line, the active filter inductor, the respective capacitor and the further inductor form an LCL configuration. In other words, the capacitive connection which is required to operate the DC / DC converter to counteract common mode noise generated in the active rectifier circuit and / or an inverted connected to the DC link may be connected to any point in the active filter circuit between the active filter inductors and the DC link of the power converter. This point may be in an AC section of the active filter circuit, “behind” the auxiliary rectifier from the viewpoint of the DC / DC converter, or in a DC section of the active filter circuit. In another embodiment of the power converter, a capacitor is connected between the auxiliary DC terminals, thus forming an auxiliary DC link. The semiconductor switches of the active rectifier circuit are preferentially selected to have a current rating that at least matches the nominal maximum current of the converter, as the active rectifier circuit is used to handle the full power of the power converter. Conversely, the semiconductor switches of the active filter circuit may be selected to have a current rating lower than the semiconductor switches of the active rectifier circuit as these switches only need to handle the approximate power of the noise generated in the active rectifier circuit which is much lower than the nominal power of the converter. Advantageously, this reduces the electrical losses generated by these switches. In typical applications, the power converter may comprise an inverter circuit connected between the DC link and load terminals. For example, the power converter may form an industrial drive 202404936 Auslandsfassung 5 circuit configured to supply an electrical motor with a three-phase AC voltage of variable frequency. The active rectifier circuit may be configured to perform switching operations with its semiconductor switches at a switching frequency of between 1 and 10 kHz, particularly between 2 and 4 kHz. In comparison to comparable power converters using only passive filters this is a low switching frequency. In such power converters a switching frequency in that range would typically be avoided to reduce the size of the passive filter components. Since the present power converter uses its active filter circuit to reduce at least part of the differential as well as common mode noise this low switching frequency can be used while keeping the passive filter components sufficiently small. Switching at such a low frequency reduces switching losses compared to a power converter operating its active rectifier switches at a higher frequency such as 16 kHz. The semiconductor switches of the active filter circuit in turn are configured to operate at a switching frequency of more than the active rectifier circuit, particularly above 10 kHz, particularly above 50 kHz. The incurred switching losses are comparatively low as the switches of the active filter are operated to only counteract the noise generated in the active rectifier circuit and possibly also an inverter connected to the DC link. The described configuration of the switches and their control circuit leads to an overall very efficient operation of the converter. The power semiconductor switches used are known in the technical field and may particularly be IGBTs (insulated gate bipolar transistors) or MOSFETs (metal-oxide semiconductor field- effect transistors). They may be silicon devices or wide bandgap devices such as SiC or GaN devices. Particularly the active rectifier circuit may use silicon devices while the active filter circuit may use wide bandgap devices which allow improved operation at higher switching frequencies. Control of the semiconductor switches of the active filter circuit may be based on measurements of the noise present at the AC terminals of the active rectifier circuit. Advantageously this allows the active filter circuit to react to changing noise environments that are generated outside the power converter and thus cannot be foreseen. 202404936 Auslandsfassung 6 Alternatively, control may be based on calculated noise based on the switching scheme of the active rectifier circuit. Advantageously this does not require high-speed measurements and filtering to create a suitable noise input signal. Additionally, the compensation of DM noise and CM noise may use different ways to determine noise. Particularly, DM noise may be measured while CM noise may be calculated. The switches may be operated to create a signal that is the inverse of the present noise as deduced by measurement or calculation from the PWM scheme. While the switches may be operated at different switching frequencies compared to the active rectifier circuit, operation of part or all switches of the power converter may still be synchronized. The converter may comprise an active rectifier, a DC voltage intermediate circuit, a load-side output converter and a DC / DC converter. The rectifier, the inverter and the DC / DC converter are connected to the DC voltage intermediate circuit. The DC / DC converter may further comprise two half-bridges, each with two semiconductor switches, which are connected in parallel to each other and to the DC DC link link. The DC / DC converter also has a specifiable compensation load that is connected between the center connections of the two half-bridges. The converter may also include a controller for the DC / DC converter, the controller being designed to determine a common-mode voltage to be compensated for by the rectifier and / or the load-side output converter. Finally, the controller is designed to operate the DC / DC converter in such a way that the common-mode voltage determined in this way is at least partially compensated. For this purpose, the controller is designed to operate the DC / DC converter with a first switching state and a second switching state, which is used alternately. The first switching state is selected from a first and second switching option, whereby the two upper switches of the half- backs are switched on at the first switching option and the two lower switches of the half-bridges are switched on at the second switching option. In the second switching state, on the other hand, diagonal switches of the half-bridges are switched on. The controller is also designed to determine first, second and third periods using the determined common-mode voltage and to use the first switching option in the first periods, the second 202404936 Auslandsfassung 7 switching option in the second periods and the second switching state in the third periods. The periods will be determined in such a way that the determined common-mode voltage is at least partially compensated. In an operating method according to an embodiment of the converter, a common-mode voltage to be compensated by the rectifier and / or the load-side output converter is determined and the DC / DC converter is operated in such a way that the common-mode voltage determined in this way is at least partially compensated. It is therefore advantageous to use a simple DC / DC converter to compensate for common mode voltages. This is available with regard to its hardware, i.e. the semiconductor switch as a standard component. According to the invention, its control is geared towards compensation and is simplified compared to operation as a load-side converter, since it does not have to set a specific voltage on the output side, but can be operated optimized for compensation. The compensating load is therefore not a load that can change depending on the application, but is an integral part of the power converter. This relieves the load on the other components of the power converter, as they do not have to use a special controller to compensate for CM interference. Rather, standard components suitable for the application, including the controller, can also be used here. Advantageously, there are degrees of freedom in the control of the DC / DC converter. Under the specification that exactly one of the two semiconductor switches of each of the half-bridges of the DC / DC converter is always switched on, there are four different switching options. In the two switching options that are part of the active switching state, the diagonally positioned semiconductor switching elements of the two half-bridges are switched on. In this switching option, the DC link voltage is applied at the output terminals, i.e. between the centers of the two half-bridges. However, there is no common-mode voltage for these two switching options. In the inactive switching state, the two upper semiconductor switching elements of the two half- bridges are switched on in the first switching option and the two lower semiconductor switching elements of the two half-bridges are switched on in the second switching option. This results in a common-mode voltage, the sign of which differs between the two switching options. The controller can therefore generate two non-zero common-mode voltages. These are used on the basis of the time periods in such a way that compensation of the common mode voltage is achieved by the active rectifier and / or output converter. 202404936 Auslandsfassung 8 The controller is designed to control the active rectifier in such a way that it switches between a number of rectifier switching states. It is also designed to control the load-side output converter in such a way that it switches between suitable switching states to generate output voltage / output current from the voltage of the intermediate circuit. In this process, different common-mode voltages are generated from each other. The active rectifier can be a two-point rectifier, which comprises three half-bridges connected in parallel, each with two semiconductor switching elements such as IGBTs or MOSFETs. The semiconductor switching elements can include intrinsic and also discrete parallel freewheeling diodes. However, the active rectifier can also have a different design. For example, the load-side output converter can be a three-phase inverter. For example, this can be constructed analogously to the active rectifier, i.e. have three parallel half-bridges, each with two semiconductor switches. Such an output converter can be used, for example, in a drive unit with an electric motor. Alternatively, the load-side output converter can also be a second DC / DC converter. This can, for example, create a non-galvanically isolated charger for an accumulator, such as the battery of an electrically powered vehicle. The DC DC link comprises one or more capacitors and is advantageously connected parallel to the external connections of the half-bridges of the active rectifier. The controller advantageously includes a programmable control module, such as a microcontroller. It is connected to a higher-level controller, from which it receives signals that determine the operating status for the power converter. The controller calculates switching times for the existing semiconductor switches and gives corresponding signals to gate driver units assigned to the semiconductor switches. The common mode voltage can be determined by means of a measurement. Alternatively, the common-mode voltage can also be calculated. The calculation can be made by the controller on the basis of the switching operations carried out by the controller. If a calculation is made, the common mode voltage is known in advance and without additional measuring equipment. If, on the other hand, a measurement is used, common-mode voltages can also be recorded and compensated for, which are not directly a result of the switching processes in the power converter. 202404936 Auslandsfassung 9 Preferably, the periods are parts of a respective leap period, the length of which is determined by the switching frequency. Accordingly, a rhythm of the switching processes is adhered to, which follows the switching periods. However, the length of the periods can vary from leap period to leap period, as the voltage applied by the converter to the load varies, for example if it is an AC voltage or the operating point changes. The time periods are preferably determined in such a way that the common mode voltage generated by the DC / DC converter is equal to a common mode voltage generated by the rectifier. In an advantageous design of the invention, the controller is designed to operate the DC / DC converter in such a way that in a first switching period only the first or second switching option is used and in a second switching period following the first switching option the remaining other switching option is used. In other words, in a first leap period, only the freewheel circuit in which the two upper semiconductor switches are switched on is used, and in the following leap period, only the freewheel circuit in which the two lower semiconductor switches are switched on is used. Alternatively, the switching options can also be reversed in this procedure, i.e. in a first switching period only the freewheel circuit is used, in which the two lower semiconductor switches are switched on and in the following switching period only the freewheel circuit where the two upper semiconductor switches are turned on. This switching pattern reduces the number of switching operations used in the DC / DC converter, reducing switching losses. At the same time, sufficient compensation of the common mode voltages by the DC / DC converter is still maintained. The compensating load can include a parallel connection of a resistor and a capacitance. Furthermore, between each of the center connections of the half-bridges of the DC / DC converter and a respective connection of the compensation load, a filter circuit with an inductor and a corresponding serially connected resistor can be arranged. The controller can be designed to control the DC / DC converter in such a way that at least part of the switching operations of the DC / DC converter and the active rectifier occur at the same time within a switching period. This also advantageously reduces or compensates for switching frequency components of the common mode voltage. 202404936 Auslandsfassung 10 The periods are preferably determined from the duration of the switching periods of the DC / DC converter, i.e. the switching frequency, the DC link voltage and an instantaneous value for the common-mode voltage generated by the active rectifier. An output voltage to be set, on the other hand, does not have to be taken into account advantageously, since the load operated by the DC / DC converter is only a dummy load. The switching period duration and the DC link voltage are advantageous or are known to the controller. The instantaneous value for the common-mode voltage generated by the active rectifier can be determined from available control data. This allows the controller to calculate the proportions from known and existing data and perform this calculation again for each switching period, so that the proportions in each switching period are adjusted to the instantaneous value of the common-mode voltage. The instantaneous value for the common-mode voltage generated by the rectifier can be determined as a value averaged over a switching period of the rectifier. This advantageously determines a single value for a switching period, which can also be used to control the DC / DC converter during a switching period. This avoids setting values for the common mode voltage that vary within a switching period. The instantaneous value can be determined using the switching period duration, the DC link voltage and proportions of the switching period duration assigned to the switching states of the active rectifier and / or the output converter. The instantaneous level of the common-mode voltage can be advantageously determined and determined by these values. The DC link voltage and the switching period of the active rectifier are known in the controller. The proportions of the switching period are determined in the controller, as they are needed to control the rectifier. It is advisable if the time periods for the DC / DC converter are arranged in such a way that there are always third periods between the first and second periods, so that there are times in the active switching state between times in which the DC / DC converter is in one of the inactive switching options and thus generates a common-mode voltage. This avoids direct switching, and possibly multiple switching between the switching options of the first state. The active rectifier and the DC / DC converter can be operated at the same switching frequency. The load-side output converter can also be operated with this switching frequency. The 202404936 Auslandsfassung 11 switching frequency used is much higher than the fundamental frequency of the AC input voltage. For example, the switching frequency can be 16 kHz, 25 kHz, or 48 kHz or more. --- In a further advantageous method of operation for a power converter which comprises an active rectifier, a DC voltage intermediate circuit and a DC / DC converter, the active rectifier is controlled in such a way that it performs a change between a plurality of rectifier switching states. Furthermore, the DC / DC converter is controlled to generate a DC output voltage from the voltage of the DC link in such a way that it alternates between a first switching state and a second switching state at a switching frequency. A first of the two switching states has a plurality of switching options for representing the switching state, in which different common-mode voltages are generated from each other. In a period in which the first switching state is present, a first switching option is used for a first part of the period and a second switching option for the remaining, second part of the period, whereby the proportions are determined in such a way that the common mode voltage generated by the DC / DC converter is equal to a common mode voltage generated by the rectifier. The control device is designed to control the active rectifier in such a way that it switches between a number of rectifier switching states. It is also designed to control the DC / DC converter in such a way that, in order to generate a DC output voltage from the voltage of the intermediate circuit with a switching frequency, it alternates between a first switching state and a second switching state, whereby a first of the two switching states comprises a plurality of switching options for representing the switching state, in which different common-mode voltages are generated from each other. The DC / DC converter is still controlled in such a way that in periods in which the first switching state is present, a first switching option is used for a first part of the period and a second switching option for the remaining, second part of the period. The control device determines the proportions in such a way that the common-mode voltage generated by the DC / DC converter is equal to a common-mode voltage generated by the rectifier. In the first switching state, which represents an off-switching position, in the first switching option, the two upper semiconductor switching elements of the two half-bridges are switched 202404936 Auslandsfassung 12 on, and in the second switching option, the two lower semiconductor switching elements of the two half-bridges are switched on. This offers the advantageous degree of freedom, which consists of the fact that there are two different switching options for the first switching state, which differ in the generated common-mode voltage. The active rectifier can be a two-point rectifier, which comprises three half-bridges connected in parallel, each with two semiconductor switching elements such as IGBTs or MOSFETs. The semiconductor switching elements can include intrinsic and also discrete parallel freewheeling diodes. However, the active rectifier can also have a different design. The control device advantageously includes a programmable control module, such as a microcontroller. It is connected to a higher-level controller, from which it receives signals that determine the operating status for the power converter. The control device calculates times for switching operations for the semiconductor switching elements of the rectifier and the DC / DC converter and transmits corresponding signals to gate driver units assigned to the semiconductor switching elements. Advantageous designs of the operating method and power converter according to the invention emerge from the dependent claims. The embodiment of the independent claims can be combined with the features of one of the subclaims or, preferably, with those of several subclaims. Accordingly, the following features may also be provided: The proportions of the period during which the first and second switching options are used are preferably determined from the switching period of the DC / DC converter, the DC link voltage, the DC output voltage and an instantaneous value for the common-mode voltage generated by the active rectifier. The switching period duration and the DC link voltage are advantageous or are known to the control device. The DC output voltage, i.e. the charging voltage in the case of a battery of an electrically powered vehicle, is also known to the controller, as it has to set this charging voltage. The instantaneous value for the common-mode voltage generated by the active rectifier can be determined from available control data. This allows the control device to calculate the proportions from known and existing data and perform this calculation again for each switching period, so that the proportions in each switching period are adjusted to the instantaneous value of the common-mode voltage. 202404936 Auslandsfassung 13 The instantaneous value for the common-mode voltage generated by the rectifier can be determined as a value averaged over a switching period of the rectifier. This advantageously determines a single value for a switching period, which can also be used to control the DC / DC converter during a switching period. This avoids setting values for the common mode voltage that vary within a switching period. The instantaneous value can be determined using the switching period duration, the DC link voltage and proportions of the switching period duration assigned to switching states of the active rectifier. The instantaneous level of the common-mode voltage can be advantageously determined and determined by these values. The DC link voltage and the switching period of the active rectifier are known in the control device. The proportions of the switching period of the rectifier are determined in the controller, as they are required for the control of the rectifier. It is appropriate for the first part of the period and the second part of the period to be separated in time by placing a second period between them in which the second switching state is used. This avoids direct switching, and possibly multiple switching between the switching options of the first state. Embodiments of the present invention are now described with reference to the accompanying drawings to which the invention is not limited. The illustrations of the drawings are in schematic form. It is noted that in different figures, similar or identical elements use the same reference signs. Figure 1 illustrates a first embodiment of a power converter with a combined active DM and CM noise filter circuit, Figure 2 illustrates a second embodiment of a power converter with a combined active DM and CM noise filter circuit, Figure 3 illustrates a third embodiment of a power converter with a combined active DM and CM noise filter circuit, Figure 4 illustrates a fourth embodiment of a power converter with a combined active DM and CM noise filter circuit, 202404936 Auslandsfassung 14 Figure 5 illustrates a fifth embodiment of a power converter with a combined active DM and CM noise filter circuit, Figure 6 illustrates a sixth embodiment of a power converter with a combined active DM and CM noise filter circuit, Figure 7 shows simulated results for the differential mode noise and noise reduction for the first embodiment of the power converter, Figure 8 shows simulated results for the common mode noise and noise reduction for the first embodiment of the power converter. Figure 9 shows switching states of the active rectifier within a switching period, Figure 10 to 16 show switching states in the DC / DC converter to compensate for common-mode voltages. Fig 1 shows a power converter 10 according to a first embodiment of the invention. Power converter 10 comprises an active rectifier circuit 12 (also called AFE = active front end) which in turn comprises three parallel half-bridges, each having two power semiconductor switches connected in series. The three midpoints between the switches of each of the half-bridges form AC terminals of the active rectifier circuit 12 while the interconnected endpoints of each of the half-bridges form DC terminals of the active rectifier circuit 12. The DC terminals of the active rectifier circuit 12 are connected to a DC link 14 having in this embodiment a single capacitor element. The DC terminals of the active rectifier circuit 12 and thus the DC link 14 are furthermore connected to a load 16. The load is shown as a simplified element in the figures but load 16 may be active or passive. For example, load 16 may comprise a three-phase inverter connecting to an electric motor, thus forming an industrial drive system. The AC terminals of the active rectifier circuit 12 are connected to a three-phase supply voltage such as three-phase grid 20 across a passive EMI filter 22. The power converter 10 further comprises an active filter circuit 30 which is connected on the AC side to grid 20 and on the DC side to DC link 14. The active filter circuit 30 comprises active filter inductors 26, an auxiliary active rectifier circuit 40 and an active DC / DC converter 50. The 202404936 Auslandsfassung 15 active filter inductors 26 are arranged in each of the AC lines between the auxiliary active rectifier circuit 40 and the grid 20. The auxiliary rectifier circuit 40 is built similarly to the active rectifier circuit 12, i.e. it comprises three parallel half-bridges of two controllable power semiconductor switches each. In other embodiments it may be using a different topology, such as a three-level topology. The outer terminals of the half-bridges form DC terminals 41a, b of the auxiliary rectifier circuit 40 and the midpoints of the half-bridges form AC terminals 42a...c of the auxiliary rectifier circuit 40. The active DC / DC converter 50 comprises two parallel half-bridges of two controllable power semiconductor switches each. DC / DC converter 50 has two outer DC terminals 51a, b formed by the connected outer terminals of the half-bridges and two inner DC terminals 52a, b formed by the midpoints of the two half-bridges. In the first embodiment according to figure 1 the outer DC terminals 51a, b of the active DC / DC converter 50 are connected to DC link 14. The inner DC terminals 52a, b are connected across an inductor to the DC terminals 41a, b of the auxiliary rectifier circuit 40. Additionally, a capacitor 43 is connected between the DC terminals 41a, b of the auxiliary rectifier circuit 40 forming an auxiliary DC link. Finally, the DC terminals 41a, b of the auxiliary rectifier circuit 40 are connected to ground across CM (common mode) path capacitors 32a, b. The power converter 10 is configured to operate the switches of the active rectifier circuit 12 with a frequency of between 2 and 4 kHz, i.e. with a reduced frequency compared to typical operating frequencies of such power converters. The switches of the active filter circuit 30 are operated at a higher frequency, e.g.16 kHz. While the switches of the active rectifier circuit 12 are controlled to handle the load current, the switches of the active filter circuit 30 are controlled to only operate to reduce the noise that the switches of the active rectifier circuit 12 produce at its AC terminals, i.e. toward the grid 20. Operation of the switches of the active filter circuit 30 may be based on an estimation of the generated DM and CM noise based on the control scheme (pulse width modulation) of the active rectifier circuit 12. In an alternative embodiment, operation of the switches of the active filter circuit 30 may be based on a measurement of the noise between the AC terminals of active rectifier circuit 12 and the grid 20. 202404936 Auslandsfassung 16 The auxiliary filter circuit 40 is operated to generate a voltage at its AC terminals that equals the reverse of the DM noise that is present to compensate that part of the noise. The active DC / DC filter 50 is operated to generate a voltage at the DC terminals of auxiliary filter circuit 40 that is the reverse of the present CM noise. The terminals that form the “output” terminals of the DC / DC converter 50 vary across embodiments as will be seen from the following description of other embodiments. The embodiment shown in figure 2 is generally similar and comprises the same elements as the embodiment of figure 1. The connection of the elements is changed with respect to the configuration of the first embodiment. In the embodiment according to figure 2, instead of the inner terminals 52a, b the outer terminals 51a, b of the active DC / DC converter 50 are connected to the DC terminals 41a, b of the auxiliary acting rectifier 40. The inner DC terminals 52a, b are connected to the DC link 14 across inductances. The operation of the power converter 10 and particularly the active filter circuit 30 follows the same principles as given for the first embodiment according to figure 1. Figure 3 shows a third embodiment of the invention. This embodiment is similar in its configuration to the first embodiment according to figure 1. Contrary to the first embodiment, the third embodiment does not use two CM path capacitors 32a, b connected to the DC terminals 41a, b of the auxiliary active rectifier 40. Instead, three CM path capacitors 34a…c are used in this embodiment. These are connected to the AC lines at nodes between the AC terminals 42a...c of the auxiliary active rectifier 40 and the inductor 26. Further inductances 35a…c are arranged between the AC terminals 42a...c and those nodes. Figure 4 shows a fourth embodiment of the invention. This embodiment incorporates the changes of the second and third embodiment over the first embodiment. In the embodiment according to figure 4, the outer terminals 51a, b of the active DC / DC converter 50 are connected to the DC terminals 41a, b of the auxiliary acting rectifier 40. The inner DC terminals 52a, b are connected to the DC link 14 across inductances. Also, three CM path capacitors 34a…c are used. These are connected to the AC lines at nodes between the AC terminals 42a...c of the auxiliary active rectifier 40 and the inductor 26. Further inductances 35a…c are arranged between the AC terminals 42a...c and those nodes. Figure 5 shows a fifth embodiment of the invention. The embodiment shown in figure 5 is generally similar to the second embodiment of figure 2, i.e. the outer terminals 51a, b of the 202404936 Auslandsfassung 17 active DC / DC converter 50 are connected to the DC terminals 41a, b of the auxiliary acting rectifier 40. In addition, the DC terminals 41a, b of the auxiliary rectifier circuit 40 are connected to ground across CM (common mode) path capacitors 32a, b. Contrary to the second embodiment of figure 2, the DC terminals 41a, b of the auxiliary active rectifier 40 are connected to the DC link 14. The inner DC terminals 52a, b of the active DC / DC converter are connected across an LCL structure 55, i.e. a series connection of an inductor, capacitor and inductor. Figure 6 shows a sixth embodiment of the invention. The embodiment shown in figure 6 is generally similar to the fifth embodiment of figure 5, i.e. the outer terminals 51a, b of the active DC / DC converter 50 are connected to the DC terminals 41a, b of the auxiliary acting rectifier 40. In contrast to the fifth embodiment, the CM path capacitors 32a, b are now arranged to take the place of the capacitor of the LCL structure connected to the inner DC terminals 52a, b of the DC / DC converter. In other words, each of the inner DC terminals 52a, b is connected to ground across an inductance and capacitor series. Figures 7 and 8 show simulated results for the first embodiment of the invention according to figure 1. In Fig.7 the differential mode noise and noise compensation at the grid is shown by looking at one phase current. In this simulation, the active rectifier 12 is operated at a comparatively low switching frequency, resulting in comparatively high noise output which is seen in the current trace 71. The output of the differential mode active filter, i.e. the auxiliary active rectifier 40 produces compensating noise as seen in the current trace 73. The resulting current seen by the grid is shown as current trace 72. The differential mode noise is reduced substantially. To achieve a similar result without the use of an active filter circuit 30 the active rectifier 12 would need to operate at a much higher switching frequency and would require an additional higher output inductance. The comparatively high switching frequency would increase the switching losses significantly as the active rectifier 12 is handling high power. Figure 8 shows simulation results for the common mode noise current as the sum of the three- phase current. Trace 81 shows the common mode noise current at the output of the active rectifier 12. Trace 82 shows the common mode noise at the grid, i.e. including the effects of the active filter circuit 40. 202404936 Auslandsfassung 18 A component of contact voltages arises as a beat of common-mode voltages at three times the fundamental frequency, i.e. in this example at 150 Hz, starting from a fundamental frequency (mains frequency) of 50 Hz and is caused by the switching processes of the active rectifier 12. The time-dependent common-mode voltage uCM0 is defined for the active rectifier 12 as: uCM0 = (uR0 + uS0 + uT0) / 3 In doing so, uR0, uS0, and uT0 Components of the common mode voltage. These components are either +UDC / 2 or –UDC / 2, depending on whether the upper or lower switching element of the respective half-bridge is switched on. In sum, therefore, for the common-mode voltage uCM0= + / -UDC / 2 if all upper or all lower switching elements are switched on or + / -UDC / 6 when a mixture of upper and lower switching elements is switched on in the active rectifier 12. If the switching state with the upper switch on is denoted as 1 and the switching state with the lower switch on is called 0 and the switching states for the three half-bridges are written one after the other, the possible total states referred to as vectors result as follows: Vector Switching statesCommon Mode RST Voltage / UDC V0 000 -1 / 2V1 100 -1 / 6V2 110 +1 / 6V3 010 -1 / 6V4 011 +1 / 6V5 001 -1 / 6V6 101 +1 / 6V7 111 +1 / 2The currently used switching state changes several times within a leap period, as described below. The exact course of the switching operations depends on the selected pulse width modulation for the active rectifier 12, and similarly, the course of the beating of the common- mode voltage with three times the frequency of the mains voltage is determined by the implementation of PWM. 202404936 Auslandsfassung 19 For the concrete example of a symmetrical space vector PWM, the result is a progression within a leap period, which is shown in a simplified way in Figure 9. Figure 9 shows the individual components of the common-mode voltages andR0, uS0, and uT0 as well as the total common- mode voltage andCM0 over the time of a leap period. The switching period of the length T = 1 / f with f = 48 kHz is divided into switch-on times, which area, tb and t0. In reality, these are not the same length and depend on the current operating point of the rectifier 12. They result from the pulse width modulation used. In general terms, the leap period consists of two zero vectors V0 and V0' and two active vectors Vaand Vbtogether. In the case of the 1st sector, these are vectors V7and V0and V1and V2. The switch-on times ta, tband τ0of the vectors are recalculated by the PWM unit of the rectifier 12 for each period. The behavior of the third harmonic depends on the DC link voltage and the selected PWM. It can be used well as a short-term mean valueCM,x of a switching period can be calculated from the control data of the respective converter. It is assumed that the control system according to Figure 9 determines the switch-on times ταand τβfor the two active vectors and τ0for the zero vector(s). For the short-term CM mean of the symmetric Space Vector PWM, the following applies: Where S stands for the sector in the pulse width modulation of the active rectifier 12. For a discontinuous Space Vector PWM, on the other hand, the following applies: Depending on the desired compensation, the compensator must set the following CM counter- voltage: 202404936 Auslandsfassung 20^ത^^^^^,^^^^^^^^ = −^^^^^^^^ ∙ ^ത^^^^^,^^^^^^, compensation of the AFE^ത^^^^^,^^^^^^^^ = −^^^^ ∙ Load converter compensation^ത^^^^^,^^^^^^^^ = −^^^^^^^^ ∙ ൫^ത^^^^^,^^^^^^ compensation of AFE and load converterThe weighting factor g expresses that the size ratios between the parasitic capacitances and, if applicable, filter capacitances and the coupling capacitors of the compensator must be taken into account. Furthermore, the resulting CM equivalent circuit diagram of the specific application including the inductive components is included. For the switching operations of the second DC / DC converter 36, a scheme can be drawn up in a similar way to the active rectifier 12, which, however, only contains four different states. since there are only two half-bridges. The common mode voltage uCM,DCresults for the second DC / DC converter 36 as follows: uCM,DC = (uA0 + uB0) / 2 The following switching states are possible with the DC / DC converter: Condition Switching statesCommon Mode Output Associated AB Voltage andCMDC voltage uOFF switching time DC0 10 0 +UDC tonDC1 00 -1 / 2 UDC 0 tOff 1DC2 11 +1 / 2 hDC 0 tRev 2DC3 01 0 -UDC tonThe DC / DC converter 50 forms only one common-mode voltage amplitude in the two DC outputs, i.e. when both half-bridges are switched up or down at the same time. If the time-out of a switching period is evenly applied to the switching states DC1and DC2the DC-DC converter does not produce a common-mode voltage for this switching period on average. An uneven distribution, on the other hand, produces a corresponding common-mode voltage value, which exists on average over the switching period. This can be used to counteract and compensate for the low-frequency common-mode beat of the active rectifier 12. The average value of the CM voltage generated by the compensator is general: 202404936 Auslandsfassung 21 In order to operate the compensator with the lowest possible switching losses, it is advisable to use only one freewheel state per period, depending on the average CM value to be compensated: ^ത^ ^^^^^^,1^^^^,^^^^^^^^ = −^^^^^^2 ∙^^^^^^^^^^^^for ūCM,Comp < 0 Since the compensator at the output only operates the compensation load 39, i.e. a pseudo- load, the selected output voltage can beOFFcan be arbitrary and thus be made dependent on the CM voltage to be compensated:^^^^^^ = ^^^^^^ ∙ ^^^^^^ If the switching operations of the active rectifier 12 and / or the load converter and the compensator are synchronized, this can be used to compensate for the switching frequency portion of the common mode disturbances. For synchronization, the off-states DC1and DC2of the DC / DC converter 50 into smaller intervals TOFF10, TOFF1x, TOFF20, TOFF2xin order to be able to counteract each common-mode voltage jump of the rectifier 12 with a common-mode voltage change of the DC / DC converter 50. Dabei ist TOFF10+ TOFF1x= TOFF1and TOFF20+ TOFF2x= TOFF2. Figure 10 shows an example of how this synchronization is performed. The switch-on times τa, τb and τ0 for the sake of simplicity. In real implementation, however, these are typically of different lengths of time and subject to constant change. As can be seen from Figure 10, each switching process of the rectifier 12 is assigned a switching process of the DC / DC converter 50, so that the switching frequency jumps in the 202404936 Auslandsfassung 22 common-mode voltage are at least reduced. It may be that the amplitude of the jumps is not the same, for example, a jump in the common-mode voltage of the rectifier can be 12 of 1 / 3 UDC a jump of the DC / DC converter 50 of 1 / 2 UDC . It is important to understand that the active rectifier 12 and the DC / DC converter 50 work in opposite directions due to the chosen common-mode definition in relation to the leakage current in the PE conductor. In order to compensate for the switching frequency portion of the current in the PE conductor, the synchronized voltage changes therefore always take place in the same direction. Depending on the operating point of the converter, this results in eight modes for the second DC / DC converter 50, i.e. the compensator between which the control device changes. If the total downtime of the DC / DC converter 50 cannot be achieved within the zero vector phase τ0of the AFE, the remaining downtime of the DC / DC converter 50 must be reduced to the switching times ta and tb of the active rectifier 12 vectors. The operating mode is selected on the basis of the size ratios between the switching times of the second DC / DC converter (TOFF10, TOFF1x, TOFF20, TOFF2x) and the AFE (ta, tband t0). Table 1: Size ratios for odd sectors (S1, S3, S5) Fashion TOff,20 TOff,10 TOff,2x Toff,1x0 < t0 / 2 < t0 / 2 < tb 01 < t0 / 2 ≥ t0 / 2 < tb < ta2 ≥ t0 / 2 < t0 / 2 < tb 03 ≥ t0 / 2 ≥ t0 / 2 < tb < ta4 ≥ t0 / 2 ≥ t0 / 2 ≥ tb < ta5 ≥ t0 / 2 ≥ t0 / 2 < tb ≥ ta6 < t0 / 2 ≥ t0 / 2 ≥ tb < ta7 < t0 / 2 ≥ t0 / 2 < tb ≥ taTable 2: Size ratios for even sectors (S2, S4, S6) Fashion TOff,20 TOff,10 TOff,2x Toff,1x0 < t0 / 2 < t0 / 2 < ta 0 202404936 Auslandsfassung 23 1< t0 / 2 ≥ t0 / 2 < ta < tb2 ≥ t0 / 2 < t0 / 2 < ta 03 ≥ t0 / 2 ≥ t0 / 2 < ta < tb4 ≥ t0 / 2 ≥ t0 / 2 ≥ ta < tb5 ≥ t0 / 2 ≥ t0 / 2 < ta ≥ tb6 < t0 / 2 ≥ t0 / 2 ≥ ta < tb7 < t0 / 2 ≥ t0 / 2 < ta ≥ tbThe calculation of the individual switch-on times of the freewheel phases is carried out in accordance with Tables 3, 4 and 5. Table 3: Switch-on times for odd sectors (S1, S3, S5) Fashion TOff,20 TOff,2x Toff,2y0 = tOff2-tb / 2 = tb / 2 -1 = t0 / 2 = tOff2-t0 / 2 -2 = tOff2-tb / 2 = tb / 2 -3 = t0 / 2 = tOff2-t0 / 2 -4 = t0 / 2 = tb * 0,95 = tOff2-tOff,20-tOff,2x5 = t0 / 2 = tOff2-t0 / 2 -6 = tOff2-tb / 2 = tb * 0,95 = tOff2-tOff,20-tOff,2x7 = tOff2-tb / 2 = tb / 2 -Table 4: Switch-on times for even sectors (S2, S4, S6) Fashion TOff,20 TOff,2x Toff,2y0 = tOff2-ta / 2 = ta / 2 -1 = t0 / 2 = tOff2-t0 / 2 -2 = tOff2-ta / 2 = ta / 2 -3 = t0 / 2 = tOff2-t0 / 2 -4 = t0 / 2 = ta * 0,95 = tOff2-tOff,20-tOff,2x5 = t0 / 2 = tOff2-t0 / 2 -6 = tOff2-ta / 2 = ta * 0,95 = tOff2-tOff,20-tOff,2x7 = tOff2-ta / 2 = ta / 2 - 202404936 Auslandsfassung 24 Table 5: Other switch-on times for all sectors Fashion TOff,10 Toff,1x Toff,1y0 = tOff1 - -1 = t0 / 2 = tOff1-t0 / 2 -2 = tOff1 - -3 = t0 / 2 = tOff1-t0 / 2 -4 = t0 / 2 = tOff1-t0 / 2 -5 = t0 / 2 = tOff1-t0 / 2 = tOff1-tOff,10-toff,1x6 = t0 / 2 = tOff1-t0 / 2 -7 = t0 / 2 = tOff1-t0 / 2 = tOff1-tOff,10-toff,1xAnother example is described below using Figure 11. In this embodiment, a reduction in the number of switching operations of the DC / DC converter 50 within a cycle period is achieved compared to the previous example, in other words it is a simpler method that achieves similar results in terms of compensation. In this case, the lower off state DC2symmetrically to the center of the bar period. The upper off state is divided evenly between the beginning and end of the cycle period. This means that the CM voltage time surfaces produced by the DC / DC converter 50 are aligned parallel to the maximum or minimum amplitude of the common mode voltage of the AFE. This achieves partial compensation of the switching frequency portion of the common mode voltage. The third harmonic is compensated by reducing the switch-on time of upper and lower off states DC1and DC2unevenly divided, as shown in Figure 11. If the duty cycle of the two freewheel circuits is evenly distributed, the compensation is limited to switching frequency components. A further reduction in switching operations can be achieved if only one DC1DC2per cycle period. Such a switching pattern is shown in Figure 12. The upper and lower off states DC1,DC2 are used alternately per cycle period of the rectifier 12. The switching pattern of the second DC / DC converter is thus repeated every two cycle periods of the rectifier 12. Here, too, for optimal synchronization with the rectifier 12, the upper DC1 symmetrically aligned to the center of the period and the lower state of DC2 divided into the beginning and end of the cycle period. 202404936 Auslandsfassung 25 As in the preceding example, the third harmonic is compensated by adjusting the times of the upper and lower states of DC1DC2 unevenly divided. Figure 13 shows a diagram with which a simplified CM compensation is achieved in an embodiment according to Figure 1. The assumption is made here that the load DC-DC converter 14 only uses its lower freewheel circuit. The switch-on time is at the beginning of TSW, the switch-off time at the end of the clock period. The DC / DC converter 50 is operated synchronized with the active rectifier 12 for compensation, i.e. the same clock frequency and phase are used. The duty cycle of the compensation voltage is calculated as follows: ;^^^^^^^^2 = 0 Figure 14 shows a circuit diagram that allows for simplified compensation of the summed common-mode voltage of both the rectifier 12 and the load-side DC / DC converter 14. The assumption is made here that the switch-off time of the load-side DC / DC converter 14 is symmetrically around the midpoint of the cycle period TSW. Rectifier 12 and load-side DC / DC converter 14 operate at the same clock frequency and their phase to each other is synchronized. The negative half-wave of the common-mode voltage of the rectifier 12 is thus synchronized with the lower freewheeling circuit of the load-side DC / DC converter 14, which already leads to a partial compensation of the resulting common-mode voltage. The common-mode voltage to be equalized by the DC / DC converter 50is obtained by including formulas introduced above and:^ത^^^^^,^^^^^^ = ^ത^^^^^,^^^^^^^^^^ − ^ത^^^^^,^^^^^^^^ 202404936 Auslandsfassung 26 Here, the switch-on times of the second DC / DC converter are also arranged symmetrically around the center of the clock period, whereby the switch-on time per clock period is divided into two by a switch-off time with the lower freewheel circuit. In the remaining part of the cycle period, the upper freewheel circuit is used. --- Figure 15 shows a switching state diagram for the DC / DC converter 50, in which TDC each of the DC1 and DC2 is used in equal parts (TOFF1 = TOFF2 = TOFF / 2). In this case, there is no average common-mode voltage. This control is therefore the starting point and suitable for the case where the instantaneous amplitude of the common-mode voltage e = 0. In addition, the assumption has been made for figure 15 that UBAT = 0.5 UDC, i.e. theON= dOFF= 0.5. In other words, the leap period T dividesDCevenly to ON and OFF times, i.e. TOFF= 0.5 TDCand TOFF1 = TOFF2 = 0.25 TDC. If UBAT = 0.4 UDC, then theON = 0.4 and dOFF = 0.6. In order not to generate a common mode voltage on average, T would then beOFF1 = TOFF2 = TOFF / 2 = dOFF * TDC / 2 = 0.3 TDC. If e is not 0, then a suitable common-mode voltage is set so that the time periods TOFF1and TOFF2for the receivables, where the cumulative time for the state (dOFF* TDC= TOFF= TOFF1+ TOFF2), as it is fixed by the battery voltage. The share dCMat the period duration that should be used to generate the required level of common mode voltage is dCM= e / (0.5 * UDC). The frequency of the beat is very low at 150 Hz compared to the switching frequency of, for example, 1 / TDC= 48 kHz. Therefore, for each leap period, the common-mode beat has a practically fixed instantaneous voltage value e, which can be negative or positive. Depending on the sign of the common mode voltage, the off state must be DC1 or DC2 for the share dCM at the period duration. The remaining share for the state dOFF,RES = dOFF – dCM Splits evenly between the two balances DC1 and DC2. 202404936 Auslandsfassung 27 This results in the following times for the two states for a positive common-mode voltage to be balanced: ^^ = ൫^^^^^^ + 0,5 For a negative common-mode voltage to be balanced, the two balances are to be swapped, i.e. the following times are obtained for the two states: ^^^^^^^^1 = ൫^^1^^^^^^ − ^^^^^^^^ + 2^^^^^^ + 0,5 ∙ ^^^^^^^^,^^^^^^൯ ∙ ^^^^^^ =2∙ ^^^^^^ ∙^^^^^^Figure 16 shows a diagram for the DC / DC converter 14, in which TDC the off-states DC1 and DC2 can be used in different parts. The value of e shown in Figure 16 corresponds approximately to e = -1 / 6 * UDC. The switch-off time TOFF2 for the DC state2 shortens as a result and the switch-off time TOFF1for the DC state1is extended by the same amount, so that TOFF= dOFF* TDC= TOFF1+ TOFF2Applies. The result is the curve of the DC output voltage. Furthermore, Figure 5 shows the common-mode voltage generated in the DC / DC converter 14. As can be seen from the hatching under the course of the common-mode voltage, the diagram shown causes T on average over the switching periodDCa common-mode voltage that counteracts the common-mode beat caused by the active rectifier 12. 202404936 Auslandsfassung 28 List of reference numbers10 power converter12 active rectifier14 DC link16 load20 grid22 passive filter circuit26 active filter circuit inductors30 active filter circuit32a, b CM path capacitors34a…c CM path capacitors39 compensation load40 auxiliary active rectifier41a, b auxiliary DC terminals of the auxiliary active rectifier42a...c auxiliary AC terminals of the auxiliary active rectifier43 auxiliary DC link capacitor50 DC / DC converter51a, b outer DC terminals of the acting DC / DC converter52a, b inner DC terminals of the acting DC / DC converter55 LCL structure71 one phase current at the AC terminals of the active rectifier circuit72 one phase current at the grid73 one phase current at the AC terminals of the active filter circuit81 current sum at the AC terminals of the active rectifier circuit82 current sum at the grid

Claims

202404936 Auslandsfassung 29 1. A power converter (10) with - a DC link (14) with at least one DC link capacitor, - an active rectifier circuit (12) connected between AC terminals of the converter (10) and the DC link (14), - an active filter circuit (30) connected between AC terminals of the converter (10) and the DC link (14), wherein - the active filter circuit (30) comprises an auxiliary active rectifier circuit (40) with auxiliary AC terminals (42a…c) and auxiliary DC terminals (41a, b) and an active filter inductor (26) in each line between the AC terminals of the converter (10) and the auxiliary AC terminals (42a..c), - the active filter circuit (30) comprises a DC / DC-converter (50) having first and second auxiliary DC terminals, the first auxiliary DC terminals being connected to the auxiliary DC terminals (41a, b), wherein the DC / DC converter (50) is configured to operate as an active common mode noise filter, - the active filter circuit (30) comprises a capacitive connection to a ground or neutral potential of the converter (10).

2. The power converter (10) of claim 1, wherein the DC / DC converter (50) comprises a parallel circuit comprising two half-bridges, each having two controllable semiconductor switches.

3. The power converter (10) of claim 2, wherein the first auxiliary DC terminals are each connected across an inductance to one of the midpoints (52a, b) of the half-bridges and the outer terminals (51a, b) of the half-bridges form the second auxiliary DC terminals.

4. The power converter (10) of claim 2, wherein the second auxiliary DC terminals are each connected across an inductance to one of the midpoints (52a, b) of the half-bridges and the outer terminals (51a, b) of the half-bridges form the first auxiliary DC terminals.

5. The power converter (10) of claim 4, wherein the midpoints (52a, b) of the half-bridges are interconnected across a LCL series connection (55) of an inductor, a capacitor and an inductor.

6. The power converter (10) of any of the preceding claims, wherein the second auxiliary DC terminals are connected to the DC link (14).202404936 Auslandsfassung 30 7. The power converter (10) of any of the preceding claims, wherein the capacitive connection comprises, for each of the second auxiliary DC terminals of the DC / DC converter, a capacitor (32a, b) arranged between the respective terminal and ground.

8. The power converter (10) of any of the preceding claims, wherein the capacitive connection comprises, for each of the first auxiliary DC terminals of the DC / DC converter, a capacitor (32a, b) arranged between the respective terminal and ground.

9. The power converter (10) of any of the preceding claims with a capacitor (43) connected between the auxiliary DC terminals forming an auxiliary DC link.

10. The power converter (10) of any of the preceding claims, wherein the capacitive connection comprises, for each of the AC lines, a capacitor (34a…c) arranged between the respective line and ground, connected to the line at a node between the auxiliary AC terminals (42a…c) and the active filter inductor (26), with a further inductor between the node and the auxiliary AC terminals (42a…c).

11. The power converter (10) of any of the preceding claims, wherein the semiconductor switches (44a…f) of the active rectifier circuit (12) are selected to have a current rating that at least matches the nominal maximum current of the converter (10).

12. The power converter (10) of any of the preceding claims, wherein the semiconductor switches of the active filter circuit (30) are selected to have a current rating lower than the semiconductor switches (44a…f) of the active rectifier circuit (12).

13. The power converter (10) of any of the preceding claims, comprising an inverter circuit connected between the DC link (14) and load terminals.

14. The power converter (10) of any of the preceding claims, wherein the active rectifier circuit (12) is configured to operate at a switching frequency of between 1 and 10 kHz, particularly between 2 and 4 kHz.

15. The power converter (10) of any of the preceding claims, wherein the auxiliary active rectifier circuit (40) is configured to operate at a switching frequency of above 10 kHz, particularly above 50 kHz.

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