Method of reactive ion etching silicon and articles thereof

Abstract

Described herein is method of reactive ion etching an amorphous silicon surface by depositing a silicon and carbon-containing passivating layer to improve etching. Also disclosed is an amorphous silicon layer having a nanostructured surface, wherein at least one of the nanostructured features has an aspect ratio greater than 1.

Description

METHOD OF REACTIVE ION ETCHING SILICON AND ARTICLES THEREOFU.S. GOVERNMENT RIGHTSUlis disclosure was made with Government support under Grant Number FA8650-22-D-5406 awarded by DOD. The Government has certain rights in this disclosure.TECHNICAL FIELD

[0001] A method for reactive ion etching of silicon using a passivation layer comprising silicon and carbon is disclosed along with the resulting articles.BRIEF DESCRIPTION OF DRAWINGS

[0002] Unless otherwise noted, the schematic drawings below are for illustrative proposes only and are not drawn to scale.

[0003] Fig. 1 is a schematic cross-sectional view of a masked substrate according to one embodiment of the present disclosure.

[0004] Fig. 2 is a schematic cross-sectional view of an etched masked substrate according to one embodiment of the present disclosure.

[0005] Fig. 3 is an enlarged schematic view of a cross-section of an etched masked substrate depicting undercutting.

[0006] Fig. 4 is schematic perspective view of an etched surface.

[0007] Fig. 5 is a plot of the diameter ratio versus etch depth for Comparative Example 1 and Examples 1 and 2.SUMMARY

[0008] Reactive ion etching (RIE) can be used to pattern nanostructured features onto a substrate, wherein a mask is placed over the substrate and the portions of the substrate not covered by the mask are etched away and the portions of substrate covered by the mask are not etched. However, when performing deep etching of a silicon substrate, undercutting can occur, which is believed to be due to a high percentage of free radicals present. Undercutting is where the substrate covered by the mask is also etched away, which can lead to undesirable tapered (i.e. , nonvertical) sidewalls.

[0009] One way to control the build-up of free radicals and achieve deep vertical sidewalls during etching is to lower the pressure during etching either through reducing the gas precursor flowrate or through increasing pumping speed. However, utilizing low' pressure as a method to correct undercut can reduce mask selectivity (i.c. , the etch rate of the silicon relative to the etch rate of the mask material) and thus, is not ideal.

[0010] In one aspect, a method for etching a surface is described. The method comprising: (a) placing a patterned mask over an amorphous silicon layer to form a masked substrate: (b) reactive ion etching the masked substrate to create a patterned etched amorphous silicon layer; (c) depositing a silicon and carbon-containing thin layer on the patterned etched amorphous silicon layer: and (d) removing the patterned mask to expose a structured surface on the amorphous silicon layer.

[0011] In another aspect, a nanostructured substrate is described. The nanostructured substrate comprises an amorphous silicon layer comprising a surface having a plurality of features protruding therefrom, wherein at least at least a portion of the plurality of features has a ratio of height to a minimum dimension orthogonal to the height greater than 1 and wherein at least a portion of the plurality of features comprise a silicon and carbon-containing thin layer on their sidewall.

[0012] The above summary is not intended to describe each embodiment. The details of one or more embodiments of the invention are also set forth in the description below. Other features, objects, and advantages will be apparent from the description and from the claims.DETAILED DESCRIPTION

[0013] As used herein and in tire appended claims, the singular forms “a." “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a” or “the” component may include one or more of the components and equivalents thereof known to those skilled in the art. Further, the term “and / or” means one or all the listed elements or a combination of any two or more of the listed elements.

[0014] Relative terms such as top, bottom, side, upper, lower, horizontal, vertical, and the like may be used herein and, if so, are from the perspective observed in the drawing. These terms are used only to simplify the description, however, and not to limit the scope of tire invention in any way.

[0015] Reference throughout this specification to “one embodiment,” “certain embodiments,” “one or more embodiments” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases such as “in one or more embodiments,” “in certain embodiments,” “In some embodiments” or “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention.

[0016] As used herein, the term “plasma” means a partially ionized gaseous or fluid state of matter containing reactive species which include electrons, ions, neutral molecules, free radicals, and other excited state atoms and molecules. Visible light and other radiation are typically emitted from the plasma as the species forming the plasma relax from various excited states to lower, or ground, states The plasma usually appears as a colored cloud in the reaction chamber.

[0017] As used herein, the term “or” is generally employed in its sense including “and / or” unless the content clearly dictates otherwise. The phrase “and / or” is used to indicate one or both stated cases may occur, for example A and / or B includes, (A and B) and (A or B).

[0018] As used herein, recitation of ranges by endpoints includes all numbers subsumed within that range (e.g., 1 to 10 includes 1 .4, 1 .9, 2.33, 5.75, 9.98, etc.).

[0019] As used herein, recitation of “at least one” includes all numbers of one and greater (e.g., at least 2, at least 4, at least 6, at least 8, at least 10, at least 25, at least 50, at least 100. etc.).

[0020] As used herein, “comprises at least one of’ A, B, and C refers to element A by itself, element B by itself, element C by itself, A and B, A and C, B and C, and a combination of all three.

[0021] The process as disclosed herein may be especially advantageous for manufacturing substrates with nanometer sized features. Generally, these feature sizes are manufactured in mass using lithographic techniques such as lithographic nanopatterning using reactive ion etching. Undercutting can be especially problematic when trying to etch deep nanometer sized features, wherein a desired cylinder-shaped feature may be etched into a cone.

[0022] The present description provides a method for passivating the surface of amorphous silicon to minimize undercutting of the vertical sidewalls of an etched feature during reactive ion etching (RIE).

[0023] The substrates to be patterned via RIE have an amorphous silicon layer. This amorphous silicon layer may comprise pure silicon, doped silicon, or hydrogenated silicon. As used herein, amorphous refers to the silicon lacking long range order and crystalline structure. Amorphous silicon does not have a measurable Tg and / or lacks grain structure as determined by electron microscopy.

[0024] Dopants for silicon can include boron, phosphorous, aluminum, nitrogen, indium, and gallium. Typically, the dopants are used in small amounts, generally no more than 0.2, 0.1, 0.05, or even 0.01 wt% based on the weight of the amorphous silicon. In some embodiments, the amorphous silicon layer comprises bulk silicon with an epitaxal layer that is lightly doped.

[0025] In some embodiments, the amorphous silicon layer comprises a hydrogenated amorphous silicon, which comprises silicon and hydrogen.

[0026] In some embodiments, the amorphous silicon layer is disposed on a support layer. In these embodiments, the support layer can be a material providing mechanical support to the amorphous silicon layer during processing and / or is a material that is more resistant to etching than the amorphous silicon, which can act as a backstop to the etching process. Exemplary' support materials include polyolefins (such as polyethylene, polypropylene, cyclic olefin copolymers, etc.), polyesters (such as polyethylene terephthalate (PET)), polystyrene, acrylonitrile butadiene styrene, polyvinyl chloride, poly vinylidene chloride, polycarbonate, polyacrylates, thermoplastic polyurethanes, polyvinyl acetate, polyamide, polyimide, poly(methyhnethacrylate), polyethylene naphthalate, polystyrene acrylonitrile, triacetate cellulose, nylon, silicone-polyoxamide polymers, fluoropolymers, and thermoplastic elastomers.

[0027] In some embodiments, the thickness of the amorphous silicon layer to be etched can be at least 200, 300, or even 400 nm and at most 500, 1000, 1500, 2000, 3000, 4000, or even 5000 nm. In some embodiments, the amorphous silicon layer is etched through its thickness down to a support layer.

[0028] A mask is used to pattern the amorphous silicon layer. The patterned mask can be made using techniques known in the art including lithography such as photolithography or nanoimprint lithography.The mask comprises a plurality of openings patterned to provide a desired geometry. Exemplary openings may include circles, squares, rectangles, quadrilaterals, or other designs. In some embodiments, the mask has at least some openings that are less than 5, 4, 3, 2, 1.5, 1, 0.9, 0.8, 0.5, 0.2, or even 0.1 micrometers in one dimension (in other words, length, width, diameter, etc.). Based on the technique used to make the mask, the openings are generally at least 50 nm in dimension.

[0029] Show’ll in Fig. 1 is a masked substrate according to one embodiment of the present disclosure. Masked substrate 10 comprises amorphous silicon layer 14 on top of support layer 16. Patterned mask 12 is disposed on top of amorphous silicon layer 14.

[0030] In some embodiments, the patterned mask is made with a photolithographic process, where the mask comprises open areas, where the energized plasma ions can pass through, and covered areas, which block the energized plasma ions. Generally, these masks are prepared separately and then placed over the amorphous silicon layer. The mask is generally made from a material that is resistant to the RIE process. In other words, the material can effectively block energized plasma ions from reaching the main surface of the amorphous silicon layer. This can include so-called hardtnask materials such as carbon, carbon-containing material (e g. , diamond-like-catbon (DLC)), semiconductor oxides and nitrides, such as aluminum oxide, chrome oxide, silicon nitride (SiN), silicon dioxide (SiO?) or silicon oxynitride (SiOxNy) and metal nitrides, such as titanium nitride (TiN), to name a few.

[0031] In another embodiment, as exemplified below, the patterned mask is made via a nanoimprint lithography process on top of the amorphous silicon layer. In this instance, as depicted by arrow 13 in Fig. 1, a small amount of mask material is present between the feature to be etched and amorphous silicon layer. During RIE, this sacrificial layer of material is etched away, exposing the underlying silicon, which is continued to be etched. These masking materials can made from coatings comprising silicone acrylates, for example. Generally, these masking materials are not as resistant to RIE etching as the hardmask materials. The thickness of the etch resistant mask is selected to withstand each reactive ion etching process that is performed so that the top surface of the amorphous silicon layer remains protected from etchant materials throughout the etching process. This necessary thickness of the mask is dependent upon, among other things, the selectivity of the materials (in other words the etch rate of the mask versus the etch rate of the amorphous silicon layer), in one example, the reactive ion etching processes have a selectivity of mask etch to the amorphous silicon layer etch of at least 1 :1, 2: 1 , or even 3: 1 and at most 5: 1, 8:1 or even 10: 1.

[0032] In some embodiments, the mask can be at least twice as thick as the depth the amorphous silicon layer is etched,

[0033] After providing the patterned mask atop the amorphous silicon layer, the masked substrate is then exposed to RIE, which is a process known in the art. The reactive ion etching step can be any dry etching technique wherein a chemically reactive plasma is generated by an electromagnetic field, which accelerates high-energy plasma ions towards the main surface of the masked substrate. The high-energy plasma ions collide with the exposed portions of die amorphous silicon layer, and thus remove the silicon material through the first set of openings on the mask.

[0034] For example, the reaction chamber is filled with an etching gas to etch the amorphous silicon layer. In some embodiments, the mask may comprise a thin layer of material, which is first etched away before etching the amorphous silicon. Exemplary’ etching gases include: SFg, CF4, and NF3.

[0035] The flow rate of the gas, process pressure, and amount of time the masked substrate is exposed to the reaction gas will vary depending on the desired etching.

[0036] In some embodiments, the pressure range in the etching process is 3 to 400 millitorr, radiofrequency power density is 0.25 to I W / cnr, and a rf frequency of 13.56 megahertz.

[0037] In some embodiments, an inert gas. such as argon, is passed through reaction chamber during etching.

[0038] In some embodiments., the masked substrate is held at a temperature of at least 20°C to at most 150°C during the etching process.

[0039] Shown in Fig. 2 is masked substrate 20 after an initial etching with RIE, wherein the portions of the layer of amorphous silicon 24 not covered by tire patterned mask 22 are beginning to be etched away.

[0040] Shown in Fig. 3 is an enlarged section of masked substrate 30 showing patterned mask 32 and tire etched away layer of amorphous silicon 34. Also shown in this figure are d, the depth of etch, w:, the width at the top of the unelched feature, and wr, the width of at the base of the unetched feature. Tn an ideal RIE etch, the ratio of w:to wv is 1 .0, corresponding io vertical sidewalls of the feature. However, as discussed above, as the depth of etch increases, the sidewalls of the features start to become etched as well leading to undercutting and a decrease in the ratio of wsto wb.

[0041] In the present disclosure, it has been discovered that a passivation layer comprising silicon and carbon can be used to mitigate this undercutting, improving the ratio of wt to wt, as compared to not using a passivation layer. In some embodiments, the ratio of the width at the top of the feature (e.g., diameter) versus the width at the base of the feature (e.g., diameter) is at least 0.6, 0.7, 0.8, 0.9 or even 0,95.

[0042] The passivation layer of the present disclosure is a silicon and carbon-containing layer. The silicon and carbon-containing layer is a thin layer, for example having an average thickness on the sidewalls of the features of at least 5, 10, 15, or even 20 nm and no more than 100, 80, 70, 60, 50, 40, or even 30 nm. Such thickness may be measured using techniques known in the art. such as cross-sectioning the sample and examining by electron microscopy.

[0043] In some embodiments, the silicon and carbon-containing thin layer is amorphous.

[0044] The silicon and carbon-containing thin layer is carbon-rich, comprising at least 30, 40, 45, 50 or even 55 atomic percent of carbon.

[0045] In some embodiments, the silicon and carbon-containing thin layer is SiCxOy, wherein x is a value between 1 .0 to 1.8 (inclusive) and y is a value between 0.3 to 1 . 1 (inclusive). In some embodiments, the silicon and carbon-containing thin layer comprises at least 25, 30, or even 40 atomic percent carbon and at most 45, 50, 55, 60, or even 65 atomic percent carbon, in some embodiments, the silicon and carbon-containing thin layer comprises at least 20 or even 25 atomic percent silicon and at most 35 or even 40 atomic percent silicon. In some embodiments, the silicon and carbon-containing thinlayer comprises at least 10, 15, or even 20 atomic percent oxygen and at most 25, 30, or even 35 atomic percent oxygen. The percentages reported can be on a hydrogen free basts. “Hydrogen free basis” refers to the atomic composition of a material as established by a method such as XPS or Electron Spectroscopy for Chemical Analysis (ESCA), which does not detect hydrogen even if large amounts are present in tire thin films.

[0046] In some embodiments, the silicon and carbon-containing thin layer is substantially free of fluorine atoms since a fluorine- free compound is used for passivation. As used herein substantially free, means that the silicon and carbon-containing thin layer comprises less than 5, 2, or even 1 atomic percent fluorine, or even there is no detectable amount of fluorine atoms.

[0047] In some embodiments, the silicon and carbon-containing thin layer consists essentially of silicon, carbon, oxygen, and optionally hydrogen. As used herein, the phrase consisting essentially of means that the silicon and carbon-containing thin layer comprises less than 5, 2, or even 1 atomic percent of other atoms, which may be present due to impurities in the compounds used for forming the passivation layer and / or impurities from the plasma or chamber material.

[0048] The passivation layer comprising a silicon and carbon-containing thin layer can be formed by the addition of a gas selected from hexamethyidisiioxatie or tetramethylsilane, which is added to tire reaction chamber and deposited onio the etched silicon surface using for example, a plasma enhanced chemical vapor deposition process (PECVD).

[0049] In the present disclosure, the etching of the masked substrate is either simultaneously or sequentially exposed to a passivating gas to provide a thin layer upon the etched surface.

[0050] In some embodiments, the masked substrate is first etched with RIE to expose sidewalls of the etched feature. Then the chamber is switched to a plasma chemical vapor deposition mode to deposit a silicon and carbon-containing thin passivation layer on tire etched surface. Then the chamber is switched back to RIE mode and the masked substrate is further etched. This process of etching then depositing a thin film layer is repeated until the desired etch depth, d, is achieved.

[0051] In another embodiment, the masked substrate is first etched with RIE to expose sidewalls of the etched feature. Then, the passivating gas is added into the chamber such that etching and deposition of the passivating film occurs simultaneously until the desired etch depth is achieved. In some embodiments, this method may be preferable due to simplicity and / or throughput.

[0052] In some embodiments, the flow proportional of the etching gas and the passivating gas is between 2:3 to 5:6 (inclusive).

[0053] After etching the layer of amorphous silicon to the desired depth, the patterned mask is removed, leaving the etched substrate comprising a series of features which were covered by the patterned mask. Typically, there is a passivating layer comprising a silicone and carbon-containing thin layer upon the etched surfaces.

[0054] Shown in Fig. 4 is perspective view of structured amorphous silicon layer 41 . The amorphous silicon layer has been etched revealing features 25A and 25B. The feature has height, h, and a width andlength at the top of the feature, wtand lt, respectively. The feature has a width and length at the base of the feature, wb and lb, respectively. As used herein “nanometer sized” refers to a feature having an average dimension of at least 1, 2, 5, 10, 20, 25, or even 50 nm (nanometer) and at most 0.1, 0.2, 0.5, 0.8, 0.9, 1 , 2, 3, 4, or even 5 micrometers. Ideally, the present disclosure is directed toward nanostructured surfaces, wherein the smallest dimension of an etched feature (in other words, length or width) is nanometer sized. Also shown in Fig. 4 is pitch, p, which is the distance between features (center to center).

[0055] In some embodiments, the height, h, of the etched features of the amorphous silicon layer is on average at least 10, 25, 50, 100, 150, or even 200 nm; and at most 0.5, 0.8, 1, 1.5, 2, 2.5, 3, 4, or even 5 pm (micrometers). In some embodiments, the resulting feature, which was masked during the process has a width at the top of the feature (wt) of at least 10, 25, 50, 100, 150, or even 200 nm; and at most 0.5, 0.8, 1 , 1.5, 2, 2.5, 3, 4, or even 5 pm. In some embodiments, the resulting feature, which was masked during the process has a length at the top of the feature (lt) of at least 10, 25, 50, 100, 150, or even 200 nm; and at most 0.5, 0.8, 1 , 1.5, 2, 2.5, 3, 4, or even 5 pm.

[0056] Ideally, the etchect substrates ot the present disclosure nave etched features with veiticat sidewalls. For example, wt / wb (or li / lt.) = 0.9 or even more preferably 1. In certain embodiments, the features have an aspect ratio of height (h) to span at the top of the feature at least 0.25, 0.5, 0.75, or even 1 and at most 1.5, 2, 2.5, 3, 4, 5, 6, 8, or even 10. By “span” is meant the shortest dimension at the top of the feature orthogonal to the height. Thus, span can refer to wtor L. The features may comprise shapes including, but are not limited to, rectangular, triangular and trapezoidal prisms; fins, cylindrical and truncated-cone shaped pillars, etc. The features may be placed with regular or randomized pitch, orientation, and shapes, dependent on application-functionality7and determined article design. The pitch is the distance between adjacent features (center-to-center). In some cases, the features have a pitch that is less than half of a predetermined wavelength of electromagnetic radiation (such as visible light, IR, etc.).

[0057] In some embodiments, the structured amorphous silicon layers of the present disclosure may be used in infrared (IR) metasurfaces. IR metasurfaces are planar devices composed of subwavelength structures (i.c., meta-atoms) and can steer the polarization, phase, and amplitude of electromagnetic waves at the wavelengths between 0.700 micrometers and 300 micrometers. Their ability to control the properties of electromagnetic waves, particularly polarization, in the longer IR wavelength region allows these materials to play7an important role for various applications including optical sensing, thermal imaging, and free-space wireless communication.EXAMPLES

[0058] Unless otherwise noted, all parts, percentages, ratios, etc. in the examples and the rest of the specification are by weight, and all reagents used in the examples were obtained, or are available, from general chemical suppliers such as, for example, Sigma- Aldrich Company, Saint Louis, Missouri, or may be synthesized by conventional methods.

[0059] These abbreviations arc used in the following examples: °C = degree Celsius, cP =CcntiPoisc, = centimeter, gsm = grams per square meter, ft = feet, fpm = feet per minute kHz = kilohertz, kW = kilowatt, pm= micrometer, m = meter, min = minute, mm = millimeter, MHz = megahertz, mPa = megapascal, mtorr = milli Torr, seem = standard cubic centimeters per minute, W = Watts, and wt = weight.Table 1. Materials List

[0060] Preparation of the Tooling Film

[0061] Resin A was prepared by combining and mixing PHOTOMER 6210, SR351, SR238 andIRGACURE TPO in respective weight ratios of 60 / 20 / 20 / 0.5. After all components were added, the resin composition was blended by warming to approximately 50 °C and mixing for 12 hours on a roller mixer. Mixture appeared homogeneous.

[0062] Nano structured film was prepared by die coating Resin A onto a 125 pm thick polyester film (available from Dupont as ST5O5). The coated side of the film was pressed against a patterned nanostructured nickel surface that was attached to a steel roller controlled at 60 °C using a rubber covered roller at a speed of 15.2 m / min. The pattern comprised a series of holes with a depth of 2.7 micrometers and a diameter of approximately 1.2 micrometers arranged in a square array with a pitch of 1 .86micrometers. The coating thickness of Resin A on the film was sufficient to fully wet the nickel surface and form a rolling bead of resin as the coated film was pressed against the nanostructured nickel surface. The film was exposed to radiation from two UV lamp systems (obtained under the trade designation “F600” from Fusion UV Systems, Gaithersburg, MD) fitted with D bulbs both operating at 142 W / 'cm, while in contact with the nanostructured mold surface. The resulting nanostruc Lured film was peeled from the nanostructured mold surface and then the nanostructured surface of the film was exposed to radiation from a UV lamp system (obtained under the trade designation “F600” from Fusion UV Systems) fitted with a D bulb operating at 142 W / cm.

[0063] Release Treating the Tooling Film

[0064] The tooling film from above was release treated as follows: PECVD was performed in a homebuilt parallel plate capacitively coupled plasma reactor. The chamber has a central cylindrical pow’ered electrode with a surface area of about 1.70 nr. After loading the tooling film into the chamber, the reactor chamber was pumped down to a base pressure of less than 1 mtorr. Process gas was introduced into the chamber at the designated flow rates detailed below. Treatment (surface functionalization or deposition) was performed by coupling RF power into the reactor at a frequency of 13.56 MHz and an applied power as described below. The treatment time was controlled by translating the tooling film through the reaction zone at 30.0 feet per minute (9.1 meters per minute). The tooling film was treated with two machine passes- the first is an oxygen plasma treatment step to functionalize the surface, followed by deposition of the release layer from HMDSO. The first pass used 1000 seem of oxygen with a pressure of 10.3 mtorr at 2000 watts. Then the second machine pass was with an open flow’ of HMDSO in the chamber (in other words, the HMDS was not metered in, but instead allowed to fill the chamber) at 6.0 mtorr at 1000 w’atts. This resulted in a tooling film coated with an HMDSO (or release) layer. Additional information regarding materials and processes for applying cylindrical PECVD and further details around the reactor used can be found in U.S. Pat. No. 8460568 (David et al.).

[0065] Amorphous silicon layer 1

[0066] A sputter deposition of silicon onto a ST5O5 PET substrate was done in a custom-built Mill Lane Engineering roll-to-roll sputter coating system using boron-doped silicon sputter targets in an argon atmosphere. The sputter sources were 5 inch (12.7 cm) x 15 inch (38. 1 cm) magnetron sources from Material Science (Canton, MI). There were multiple sputter sources (three total) surrounding a cooled drum that cooled the substrate when performing the sputter deposition. The sputtering process was as follows: the ST5O5 PET substrate was placed in the chamber and the chamber was pumped to a base pressure of less than 2x10-sTorr, and argon was introduced into the sputter chamber at a flow rate of 200 seem. The pumping w’as then throttled by closing off various cryopumps to achieve a process pressure of 15.1 mtorr. A 20kHz pulsed DC pow’er supply was used for the sputtering process at an applied power of 4kW. The deposition time (thickness) was controlled by translating the film over the cooled drum and through the sputter zone(s) at 3 feet per minute (91 cm / rnin) for multiple machine passes until the desired thickness was achieved. Folio-wing the sputter deposition process, the argon gas flow, applied pow'er, and film translation w'ere stopped, and the chamber wras returned to atmospheric pressure.

[0067] Amorphous silicon layer 2

[0068] A plasma enhanced chemical vapor deposition ( PECVD) of silicon onto a ST505 PET substrate was performed in a home-built parallel plate capacitively coupled plasma reactor. The chamber has a central cylindrical powered electrode with a surface area of 1.24 nr. After placing the ST505 PET film on the powered electrode, the reactor chamber was pumped down to a base pressure of less than 1 mTorr. SiH4 / Ar was introduced into the chamber at a flow rate of 4000 seem. Deposition was carried out by coupling RF power into the reactor at a frequency of 13.56 MHz and an applied power of 4000 watts, for deposition time of 80 minutes. During deposition, the powered electrode was rotated at a linear speed of 1 fpm (30 cm / min) to simulate a roll-to-roll process. Following deposition, the RF power and the gas supply were stopped, and the chamber was returned to atmospheric pressure. Additional information regarding materials and processes for applying cylindrical PECVD and further details around this kind of reactor can be found in U.S. Pat. No. 8460568.

[0069] Resin Solution 1 for Mask

[0070] Resin Solution 1 was prepared by weighing an appropriate amount of TEGO RC 702 into a container, and then adding a 50 / 50 (by mass) mixture of MEK / IPA to achieve a concentration of 15% TEGO RC 702 (by mass).

[0071] Resin Solution 2 for Mask

[0072] PE-6 was prepared by weighing an appropriate amount of TEGO RC 702 and K90 into a container to achieve a concentration of 0.5% K90 (by mass), and then adding a 50 / 50 (by mass) mixture of MEK / IPA to achieve a concentration of 15% TEGO RC 702 (by mass).

[0073] Preparation of an Amorphous silicon layer with the Nanoscale Patterned Mask

[0074] The resin solution as designated in Table 2 was coated 15.3 cm wide with a 0.127 mm shim and pumped with a Harvard syringe pump al a rate of 5.3 seem onto the release treated tooling film (described above). The coating was dried at ambient conditions for 4 minutes, then laminated in a nip to the designated amorphous silicon layer. The nip consisted of a 90-durometer rubber roll and a steel roll set at 54 °C. The nip was engaged by two Bimba air cylinders pressed by 0.27 MPa. The dried resin solution and the amorphous silicon layer remain in contact for approximately 1.5 m, where they are cured with a fusion D bulb, and subsequently peeled from the release treated tooling film, leaving the amorphous silicon layer with a patterned mask atop having nano-structured posts. See Table 2 for the amorphous silicon layer and resin solution used for each mask / amorphous silicon sample.Table 2

[0075] General Method for Reactive Ion Etching (RIE) and PECVD

[0076] RIE and PECVD was performed in a home-built parallel plate capacitively coupled plasma reactor. The chamber has a central cylindrical powered electrode with a surface area of about 1.70 rrr. After loading the designated mask / amorphous silicon sample into the chamber, the reactor chamber was pumped down to a base pressure of less than 1 mtorr. Process gas was introduced into the chamber at the flow rates detailed in the preparative example section below. Treatment (etching or deposition) was performed by coupling RF power into the reactor at a frequency of 13.56 MHz and an applied power of 7500 watts (about 0.44 W / cm2). The treatment time was controlled by translating the film samples through the reaction zone at speeds detailed in the example / comparative example below. The operating pressure during treatment is detailed in the example / comparative example below. For some samples, a plurality of steps were completed in which case the process gas flow, applied power, and film translation were stopped, and the chamber was returned to a base pressure of less than 1 mtorr before proceeding to the subsequent step. Following the treatments), the process gas flow, applied power, and film translation were stopped, and the chamber was returned to atmospheric pressure. Additional information regarding materials and processes for applying cylindrical PECVD and further details around the reactor used can be found in U.S. Pat. No. 8460568.

[0077] Scanning Electron Microscopy (SEM) Imaging

[0078] For imaging, cross-sections of the sample were cut. Samples were mounted on aluminum examination stubs and coated with AuPd by DC sputtering in a coater (Denton Vacuum Desk IV from Denton Vacuum, Mooresto’wn, NJ) to ensure conductivity. Examinations were performed in a Hitachi S4700 Field Emission Scanning Electron Microscope. Where applicable, feature dimensions were measured in ImageJ using tire reference scale bar generated by the S4700 microscope.

[0079] The etch depth (d) was measured along with the diameter across tire top of the amorphou s silicon layer (wt). The diameter across the base of the amorphous silicon layer (wb) was also measured and tire diameter ratio (wt / Wb) was determined.

[0080] Comparative Example 1

[0081] Mask-silicon substrate combination 1 was sectioned into multiple pieces. The General Method for RIE and PECVD was used to etch the mask-silicon substrate combination. Detailed in Table 3 are the various samples made and the conditions they were run at. Shown in Table 3 are the various run conditions at each step and the resulting SEM measurements.Table 3N / A =not applicable

[0082] Comparative Example 2

[0083] Mask-silicon substrate combination 2 was sectioned into multiple pieces. The General Method for RIE and PECVD was used to etch the mask-silicon substrate combination. Detailed in Table 4 are the various samples made and the conditions they were run at. Shown in Table 4 are the various run conditions at each step and the resulting SEM measurements.Table 4

[0084] Example 1

[0085] Mask-silicon substrate combination 1 was sectioned into multiple pieces. The General Method for RIE and PECVD was used to etch the mask-silicon substrate combination. Detailed in Table 5 below are the sequential steps used. When the samples w'ere passivated with the HMDSO under “open” conditions, this refers to the HMDSO flowing directly unmetered into the chamber for the given time. At given steps, a portion of tire sample was pulled and was imaged by SEM. Shown in Table 5 are the various run conditions at each step and tire resulting SEM measurements. For example, in Step 1, the sample is etched to initially remove the surface layer of the amorphous silicon. In Step 2, the sample is further etched to remove more of the amorphous silicon. In Step 3, the sample is then passivated with a thin silicon film. In Step 4, the passivated sample is then etched NF3 and the impact on etching as determined by SEM is shown.Table 5| Step | Process Conditions | SEM measurements |

[0086] Example 2

[0087] Mask-silicon substrate combination 1 was sectioned into multiple pieces. The General Method for RIE and PECVD was used to etch the mask-silicon substrate combination similar to Example 1, except the residence time of the HMDSO was shortened. Detailed in Table 6 below are the sequential steps used. At given steps, a portion of tire sample was pulled and was imaged by SEM. Shown in Table 6 are the various run conditions at each step and the resulting SEM measurements.Table 6

[0088] Example 3

[0089] Mask-silicon substrate combination 2 was sectioned into multiple pieces. The General Method for RIE and PECVD was used to etch the mask-silicon substrate combination similar to Example 1. Detailed in Table 7 below are the sequential steps used. At given steps, a portion of the sample was pulled and was imaged by SEM. Shown in Table 7 are the various run conditions at each step and the resulting SEM measurements.Table 7

[0090] Shown in Fig. 5 is the etch depth versus diameter ratio for Comparative Example 1 and Examples 2 and 3.

[0091] Foreseeable modifications and alterations of this invention will be apparent to those skilled in tire ai t without departing from tire scope and spirit of this invention. This invention should not be restricted to the embodiments that are set forth in this application for illustrative purposes. To the extent that there is any conflict or discrepancy between this specification as written and the disclosure in any document mentioned or incorporated by reference herein, this specification as written will prevail.

Claims

What is claimed is:

1. A method for etching a surface comprising:(a) placing a patterned mask over an amorphous silicon layer to form a masked substrate;(b) reactive ion etching the masked substrate to create a patterned etched amorphous silicon;(c) depositing a silicon and carbon-containing thin layer on the patterned etched amorphous silicon; and(d) removing the patterned mask to expose a structured amorphous silicon layer.

2. The method of claim 1, wherein the amorphous silicon layer is disposed on a support layer.

3. The method of any one of the previous claims, wherein the amorphous silicon layer comprises doped silicon, a hydrogenated silicon, or combinations thereof.

4. The method of any one of the previous claims, wherein steps b and c are sequential.

5. The method of any one of claims 1-3, wherein steps b and c are simultaneous.

6. The method of any one of the previous claims, wherein the silicon and carbon-containing thin layer comprises a dense random covalent system comprising on a hydrogen-free basis at least about 30 atomic percent carbon, at least about 25 atomic percent silicon.

7. The method of any one of the previous claims, wherein the silicon and carbon-containing thin layer is formed from the deposition of hexamethyldisiloxane, tetramethylsilane, or combinations thereof.

8. The method of any one of the previous claims, wherein plasma enhanced chemical vapor deposition is used to form the silicon and carbon-containing thin layer.

9. The method of any one of the previous claims, wherein the masked substrate is reactive ion etched until a desired etch depth is achieved.

10. A nanostructured substrate comprising an amorphous silicon layer comprising a surface having a plurality of features protruding therefrom, wherein at least at least a portion of the plurality of features has a ratio of height to a minimum dimension orthogonal to the height greater than 1 and wherem at least a portion of the plurality of features comprise a silicon and carbon-containing thin layer on their sidewall.11 . The nanostructured substrate of claim 10, wherein a ratio of a width across a top ( wt) versus a width across a base (wb) of at teas! a portion of the plurality of features is at least 0.6.

12. The nanostructured substrate of any one of claims 10-11, wherein at least a portion of the plurality of features has a height of between 10 nm and 5 pm.

13. The nanostructured substrate of any one of claims 10-12, wherein at least a portion of the plurality of features has a length and / or width between 10 nm and 5 ,um.

14. The nanostructured substrate of any one of claims 10-13, wherein at least a portion of the plurality of features has vertical side walls.

15. The nanostructured substrate of any one of claims 10-14, wherein the silicon and carbon- containing thin layer on the sides of at least a portion of the plurality of features have a thickness of at least 5 nm and no more than 100 nm.

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