Method for producing metal oxide layer

Abstract

The present invention provides a metal oxide layer with high carrier mobility and a method for producing the same. The method for producing a metal oxide layer comprises: a first step for forming a crystal part; a second step for forming a metal oxide layer having an amorphous structure on the crystal part; and a third step for performing a heat treatment to induce crystal growth of the metal oxide layer using the crystal part as a nucleus. The metal oxide layer contains indium. The crystal orientation of the crystal part is <001>, and the metal oxide layer after the heat treatment has crystal grains with a crystal orientation of <111>.

Description

Method for producing a metal oxide layer

[0001] 1. Field of the Invention One embodiment of the present invention relates to a metal oxide layer, a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a metal oxide layer and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] Examples of oxide semiconductors that can be used for the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin-film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization for the active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022) N. Preissler et al. , “Electrical transport, electrothermal transport, and effective electronic mass in single-crystalline In▲2▼O▲3▼ films”, Phys. Rev. B, 88, 085305 (2013) Takashi Koida, "High Mobility Transparent Conductive Film", National Research and Development Agency, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a metal oxide layer having high carrier mobility.An object of one embodiment of the present invention is to provide a novel metal oxide layer.An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, a memory device, or a display device to which the metal oxide layer is applied.

[0010] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a method for forming a metal oxide layer, the method including: a first step of forming a crystal portion; a second step of forming a metal oxide layer having an amorphous structure on the crystal portion; and a third step of performing heat treatment to grow crystals of the metal oxide layer using the crystal portion as nuclei. The metal oxide layer contains indium.

[0013] In the above-mentioned method for producing a metal oxide layer, it is preferable that in the first step, a crystal portion is formed on a layer having a groove portion, in the second step, a metal oxide layer is formed so as to cover the groove portion, and in the third step, crystals of the metal oxide layer are grown so as to follow the groove portion.

[0014] One embodiment of the present invention is a method for forming a metal oxide layer, the method including: a first step of forming a crystal portion; and a second step of forming a single-crystal metal oxide layer on the crystal portion using the crystal portion as a seed crystal. The metal oxide layer contains indium. In the first step, grooves are provided, and the crystal portion is formed on a layer having a curved surface at an upper end of the groove. In the second step, the metal oxide layer is formed to cover the groove.

[0015] One embodiment of the present invention is a method for forming a metal oxide layer, the method including: a first step of forming a crystal portion; a second step of forming a metal oxide layer having an amorphous structure on the crystal portion; and a third step of performing heat treatment to cause crystal growth of the metal oxide layer using the crystal portion as a nucleus. The metal oxide layer contains indium. In the first step, grooves are provided, and the crystal portion is formed on a layer having curved surfaces at the upper ends of the grooves. In the second step, the metal oxide layer is formed to cover the grooves. In the third step, the metal oxide layer is caused to crystal grow along the grooves.

[0016] In the above-described method for forming a metal oxide layer, in the second step, the metal oxide layer is preferably formed under conditions in which the substrate temperature is 100° C. or higher and 300° C. or lower. In particular, the metal oxide layer is preferably formed under conditions in which the substrate temperature is 150° C. or higher and 250° C. or lower.

[0017] In the method for producing a metal oxide layer, the curved surface preferably has a portion with a radius of curvature of 1 nm or more and 500 nm or less.

[0018] In the method for producing a metal oxide layer, the curved surface preferably has a portion whose radius of curvature is larger than the thickness of the metal oxide layer.

[0019] In the method for producing a metal oxide layer, the layer preferably contains an insulating material, or the layer preferably contains a conductive material.

[0020] In the method for producing a metal oxide layer, the layer preferably has a curved surface at the bottom of the groove.

[0021] In the above-described method for forming a metal oxide layer, it is preferable that the metal oxide layer be formed by a sputtering method using a gas containing hydrogen as a sputtering gas.

[0022] In the above method for forming a metal oxide layer, the heat treatment preferably includes a first heat treatment and a second heat treatment performed in this order, and the temperature of the second heat treatment is preferably higher than that of the first heat treatment.

[0023] In the above method for forming a metal oxide layer, the first heat treatment is preferably performed in an atmosphere containing hydrogen and nitrogen.

[0024] In the above method for forming a metal oxide layer, the hydrogen concentration in the metal oxide layer is preferably reduced by performing second heat treatment.

[0025] In the above-described method for forming a metal oxide layer, the metal oxide layer after the heat treatment preferably has crystal grains in the portions overlapping with the crystal portions.

[0026] In the above method for producing a metal oxide layer, the crystal grains preferably have a crystal orientation of <111>.

[0027] In the above method for producing a metal oxide layer, the crystal orientation of the crystal portion is preferably <001>.

[0028] In the method for forming a metal oxide layer, the crystalline portion preferably contains indium, gallium, and zinc, and has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereof, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereof.

[0029] In the above method for producing a metal oxide layer, the crystalline portion preferably contains indium oxide.

[0030] One embodiment of the present invention is a method for manufacturing a semiconductor device, including: a first step of forming a crystal portion on a first insulating layer; a second step of forming a metal oxide layer having an amorphous structure on the crystal portion; a third step of performing heat treatment to cause crystal growth of the metal oxide layer using the crystal portion as a nucleus; a fourth step of forming a second insulating layer to cover the metal oxide layer; and a fifth step of forming a conductive layer on the second insulating layer. The metal oxide layer contains indium.

[0031] In the above-described method for manufacturing a semiconductor device, it is preferable that in a first step, a crystal portion is formed on an insulating layer having a groove portion, in a second step, a metal oxide layer is formed so as to cover the groove portion, and in a third step, the metal oxide layer is crystal-grown so as to follow the groove portion.

[0032] In the above-described method for manufacturing a semiconductor device, it is preferable that the metal oxide layer be formed by a sputtering method and that a gas containing hydrogen be used as a sputtering gas.

[0033] In the above-described method for manufacturing a semiconductor device, the heat treatment is preferably performed by performing a first heat treatment and a second heat treatment in this order, and the temperature of the second heat treatment is preferably higher than that of the first heat treatment.

[0034] In the above-described method for manufacturing a semiconductor device, the first heat treatment is preferably performed in an atmosphere containing hydrogen and nitrogen.

[0035] In the above method for manufacturing a semiconductor device, the hydrogen concentration in the metal oxide layer is preferably reduced by performing second heat treatment.

[0036] In the above-described method for manufacturing a semiconductor device, the metal oxide layer after the heat treatment preferably has crystal grains in a portion overlapping with the crystal portion.

[0037] In the above-described method for manufacturing a semiconductor device, the crystal grains preferably have a crystal orientation of <111>.

[0038] In the above-described method for manufacturing a semiconductor device, the crystal portion preferably has a crystal orientation of <001>.

[0039] In the above-described method for manufacturing a semiconductor device, the crystal portion preferably contains indium, gallium, and zinc, and has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereof, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereof.

[0040] According to one embodiment of the present invention, a metal oxide layer having high carrier mobility can be provided. According to one embodiment of the present invention, a novel metal oxide layer can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device, a memory device, or a display device to which the metal oxide layer is applied can be provided.

[0041] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0042] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0043] FIGS. 1A to 1D are schematic perspective views showing an example of a semiconductor device. FIG. 2 is a diagram illustrating the carrier concentration dependence of the mobility of indium oxide, as disclosed in Non-Patent Document 2. FIGS. 3A and 3B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 3C is a cross-sectional view illustrating an indium oxide film. FIGS. 4A to 4E are diagrams illustrating the crystal structure of a metal oxide. FIGS. 5A to 5D are schematic cross-sectional views showing an example of a semiconductor device. FIG. 6A is a schematic cross-sectional view showing an example of a semiconductor device. FIGS. 6B and 6C are schematic perspective views showing an example of a semiconductor device. FIGS. 7A to 7D are schematic cross-sectional views showing an example of a semiconductor device. FIG. 8A is a schematic cross-sectional view showing an example of a semiconductor device. FIGS. 8B and 8C are schematic perspective views showing an example of a semiconductor device. FIGS. 9A to 9C and 9E are schematic perspective views showing an example of a semiconductor device. FIGS. 9D and 9F are schematic cross-sectional views showing an example of a semiconductor device. FIGS. 10A and 10C are schematic perspective views showing an example of a semiconductor device. FIG. 10B is a schematic cross-sectional view showing an example of a semiconductor device. FIGS. 11A, 11C, and 11E are schematic perspective views showing an example of a semiconductor device. FIGS. 11B, 11D, and 11F are schematic cross-sectional views showing an example of a semiconductor device. FIGS. 12A, 12C, and 12E are schematic perspective views showing an example of a method for manufacturing a semiconductor device. FIGS. 12B, 12D, and 12F are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 13A, 13C, and 13E are schematic perspective views showing an example of a method for manufacturing a semiconductor device. FIGS. 13B, 13D, and 13F are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 14A to 14E are schematic perspective views showing an example of a semiconductor device. FIGS. 15A, 15B, and 15D are schematic perspective views showing an example of a method for manufacturing a semiconductor device. FIG. 15C is a schematic cross-sectional view showing an example of a semiconductor device. FIG. 16 is a schematic cross-sectional view showing an example of a semiconductor device. 17A to 17C are perspective schematic views showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a semiconductor device. FIGS. 18B to 18D are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a plan view showing an example of a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing an example of a semiconductor device.FIG. 20A is a plan view showing an example of a semiconductor device. FIGS. 20B and 20C are cross-sectional views showing an example of a semiconductor device. FIGS. 21A to 21D are cross-sectional views showing an example of a semiconductor device. FIG. 22A is a plan view showing an example of a semiconductor device. FIGS. 22B to 22D are cross-sectional views showing an example of a semiconductor device. FIG. 23A is a plan view showing an example of a semiconductor device. FIGS. 23B to 23D are cross-sectional views showing an example of a semiconductor device. FIG. 24A is a plan view showing an example of a semiconductor device. FIGS. 24B and 24C are cross-sectional views showing an example of a semiconductor device. FIG. 25A is a plan view showing an example of a semiconductor device. FIGS. 25B and 25C are cross-sectional views showing an example of a semiconductor device. FIG. 26A is a plan view showing an example of a semiconductor device. FIGS. 26B to 26D are cross-sectional views showing an example of a semiconductor device. FIG. 27A is a plan view showing an example of a semiconductor device. FIGS. 27B and 27C are cross-sectional views showing an example of a semiconductor device. FIG. 28A is a plan view showing an example of a semiconductor device. FIGS. 28B to 28D are cross-sectional views showing an example of a semiconductor device. FIG. 29A is a plan view showing an example of a memory device. FIGS. 29B and 29C are cross-sectional views showing an example of a memory device. FIGS. 30A to 30C are cross-sectional views showing an example of a memory device. FIG. 31A is a plan view showing an example of a memory device. FIGS. 31B and 31C are cross-sectional views showing an example of a memory device. FIGS. 32A and 32B are cross-sectional views showing an example of a memory device. FIG. 33A is a plan view showing an example of a memory device. FIG. 33B is a cross-sectional view showing an example of a memory device. FIG. 34 is a cross-sectional view showing an example of a memory device. FIG. 35 is a cross-sectional view showing an example of a memory device. FIG. 36 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 37A to 37G are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 38A and 38B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 39 is a block diagram illustrating a CPU. FIGS. 40A and 40B are perspective views of a semiconductor device. FIGS. 41A and 41B are perspective views of a semiconductor device. FIG. 42 is a conceptual diagram illustrating layers of a memory device. 43A and 43B are diagrams showing an example of an electronic component, and FIGS. 44A to 44C are diagrams showing an example of a mainframe computer.FIG. 44D is a diagram showing an example of space equipment. FIG. 44E is a diagram showing an example of a storage system applicable to a data center. FIGS. 45A to 45F are diagrams showing an example of electronic equipment. FIGS. 46A to 46G are diagrams showing an example of electronic equipment. FIGS. 47A to 47F are diagrams showing an example of electronic equipment. FIG. 48 is a diagram showing a cross-sectional TEM image of a sample according to an example. FIGS. 49A1 and 49B1 are STEM images of an indium oxide film. FIGS. 49A2 and 49B2 are EDX mapping images of an indium oxide film. FIGS. 50A and 50B are cross-sectional STEM images according to an example. FIG. 51 is a cross-sectional STEM image according to an example. FIG. 52 shows the measurement results of EDX analysis. FIGS. 53A and 53B are cross-sectional STEM images of an indium zinc oxide film.

[0044] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0045] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0046] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0047] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0048] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0049] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0050] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0051] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0052] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0053] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0054] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0055] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0056] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0057] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0058] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0059] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0060] 1A to 14E, a semiconductor device according to one embodiment of the present invention and a method for manufacturing the semiconductor device will be described. The semiconductor device according to one embodiment of the present invention includes a transistor having a semiconductor layer.

[0061] <Configuration of Semiconductor Device> Figures 1A to 1D are perspective schematic diagrams of a semiconductor device. Figure 1B is a perspective schematic diagram of a portion of Figure 1A cut along the YZ plane including the dashed dotted line. In Figures 1A and 1B, the X direction, Y direction, and Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in Figures 1A and 1B, the directions do not necessarily have to match between these. In the subsequent figures, the X direction, Y direction, and Z direction do not necessarily have to match between the respective figures.

[0062] 1A and 1B , a semiconductor device according to one embodiment of the present invention includes an insulating layer 20, a semiconductor layer 30, an insulating layer 50 over the semiconductor layer 30, and a conductive layer 60 over the insulating layer 50. The semiconductor device according to one embodiment of the present invention may also include a layer 29.

[0063] 1C shows an insulating layer 20 and a semiconductor layer 30, which are components of the semiconductor device. As shown in Fig. 1C, the insulating layer 20 has a groove 91. The semiconductor layer 30 is provided so as to extend along a part of the bottom and a part of the sidewall of the groove 91.

[0064] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0065] In the transistor according to one embodiment of the present invention, the conductive layer 60 functions as a gate electrode, and the insulating layer 50 functions as a gate insulating layer. The semiconductor layer 30 has a channel formation region. At least part of a region of the semiconductor layer that overlaps with the conductive layer 60 with the insulating layer 50 interposed therebetween functions as the channel formation region.

[0066] A transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in a semiconductor layer 30 including a channel formation region. That is, the transistor can be referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 30 includes a metal oxide, the semiconductor layer 30 can be referred to as a metal oxide layer.

[0067] An OS transistor has an oxygen vacancy (V Ｏ The presence of oxygen vacancies and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region is made i-type (intrinsic) or substantially i-type.

[0068] Furthermore, when an excessive amount of oxygen is supplied to the semiconductor layer 30, electron traps due to the excess oxygen are formed in the insulating layer 50. This makes the OS transistor more susceptible to positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0069] Therefore, in the semiconductor device of one embodiment of the present invention, the impurity concentration in the semiconductor layer 30 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the semiconductor layer 30. Furthermore, it is preferable to reduce the amount of excess oxygen in the semiconductor layer 30.

[0070] Indium oxide is preferably used for the semiconductor layer 30. In this case, the semiconductor layer 30 contains indium and oxygen. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 30, the transistor can achieve a large on-state current and high frequency characteristics.

[0071] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. In polycrystalline films, crystal grain boundaries are observed.

[0072] The crystallinity of the semiconductor layer 30 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these techniques may be used for analysis.

[0073] The crystal grains can be confirmed, for example, in a high-resolution transmission electron microscope (TEM) image. Furthermore, the crystal grain boundaries can sometimes be confirmed, for example, in a high-resolution TEM image. That is, the crystal grains and the crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring the TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0074] The indium oxide film is preferably a single crystal. Since a single crystal does not have grain boundaries, carrier scattering at the grain boundaries can be suppressed, resulting in a transistor with high field-effect mobility and high reliability.

[0075] The indium oxide film may be polycrystalline or amorphous containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed in the channel formation region or that the grain boundary components are small. For example, by locating one crystal grain in the channel formation region, a structure in which no crystal grain boundaries are observed in the channel formation region can be achieved. Even in such a structure, the same effects as in a structure in which the indium oxide film is single crystal can be achieved.

[0076] Two or more crystal grains may be located in the channel formation region. For example, when first and second crystal grains are located in the channel formation region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, a crystal grain boundary may not be observed at the boundary between the first crystal grain and the second crystal grain. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, the formation of a crystal grain boundary between the first crystal grain and the second crystal grain can be suppressed. Therefore, even in this configuration, the same effect as in a configuration in which the indium oxide film is single crystal can be achieved. Note that the coincidence or substantially coincidence of the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain may be confirmed, for example, by a high-resolution TEM image. Specifically, in a high-resolution TEM image, it can be confirmed that the lattice fringes of the first crystal grains and the lattice fringes of the second crystal grains are continuously connected at the boundary between the first crystal grains and the second crystal grains.

[0077] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0078] The crystal orientation can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Alternatively, it can be evaluated by a pattern (also called an FFT pattern) obtained by performing fast Fourier transform (FFT) processing on a TEM image. The FFT pattern reflects the same reciprocal lattice space information as the diffraction pattern.

[0079] For example, when the difference in angle between the FFT patterns of the first crystal grain and the second crystal grain is −5 degrees or more and 5 degrees or less, preferably −3 degrees or more and 3 degrees or less, and more preferably −2 degrees or more and 2 degrees or less, it can be said that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. Note that, for example, the angle of the FFT pattern in the

[111] orientation refers to the acute angle between an approximate line connecting one or both of the spots resulting from the (222) plane and the central spot and a reference line (for example, a line extending in the vertical direction).

[0080] The degree of polycrystallinity of an indium oxide film can be evaluated by the grain size of the crystal grains. The grain size can be calculated, for example, by calculating the area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area as the diameter of the circle. The diameter in this case is sometimes called the area-equivalent diameter or the like.

[0081] The degree of polycrystallinity of an indium oxide film can also be evaluated by the extension length of the grain boundaries. The extension length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification at which the grain boundaries can be observed, and calculating the total length of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary extension length of 0 nm can be considered to be single crystalline. Furthermore, the longer the extension length of the grain boundaries, the more grain boundary components there are.

[0082] The extension length of the grain boundaries in the indium oxide film is preferably 0 nm or more and 1500 nm or less, more preferably 0 nm or more and 1000 nm or less, and even more preferably 0 nm or more and 800 nm or less. By having the indium oxide film with an extension length of the grain boundaries in the above range in the semiconductor layer 30, a configuration in which no crystal grain boundaries are observed or the grain boundary components are small can be realized in the channel formation region. Note that, unless otherwise specified in this specification, the area of ​​the field of view used to calculate the extension length of the grain boundaries is 90 nm square.

[0083] The thickness of the semiconductor layer 30 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, even more preferably 2.5 nm to 20 nm, even more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. The semiconductor layer 30 may have at least a portion with a thickness as described above. For example, the channel formation region of the semiconductor layer 30 may have a thickness as described above. Increasing the thickness of the semiconductor layer 30 can increase the on-current of the transistor. On the other hand, if the thickness of the semiconductor layer 30 is too thick, the extension length of the grain boundaries increases, which may result in a decrease in the on-current of the transistor due to carrier scattering at the grain boundaries. Furthermore, reducing the thickness of the semiconductor layer 30 can prevent the threshold voltage from decreasing, enabling the transistor to be a normally-off transistor. Furthermore, keeping the thickness of the semiconductor layer 30 within the above range can improve the crystallinity of the semiconductor layer 30. By increasing the crystallinity of the semiconductor layer 30, the semiconductor layer 30 can have crystal grains.

[0084] When a metal oxide contains indium and zinc, the metal oxide may have a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0085] In an oxide semiconductor layer with high crystallinity, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film with high permeability to one or both of hydrogen and oxygen compared to, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film with low barrier properties against one or both of hydrogen and oxygen compared to, for example, an IGZO film.

[0086] The indium oxide film is formed by heat treatment at a heating temperature of 400° C. for 8 hours, and the oxygen concentration is 1×10 ２０ atoms / cm ３ 2 x 10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ Furthermore, the indium oxide film can transmit, for example, 1×10 ２０ atoms / cm ３ 2 x 10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ It is preferable that the following oxygen has the property of diffusing within the crystal grains.

[0087] Oxygen in the indium oxide film diffuses through the crystal grains and grain boundaries, and V present in the crystal grains or grain boundaries is removed. Ｏ Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0088] The permeability of the membrane to oxygen and hydrogen can be evaluated by calculation using a method called Nudged Elastic Band (NEB). Specifically, the permeability can be evaluated by calculating the migration barrier of oxygen atoms and hydrogen atoms using the NEB method. The smaller the migration barrier value, the easier it is for the atoms to move (permeate).

[0089] An example of the calculation results is shown in Table 1. ２ O ３ is a crystal model of indium oxide, and IGZO shown in Table 1 is a crystal model of In—Ga—Zn oxide. Note that the excess oxygen shown in Table 1 refers to oxygen that is not located at the oxygen site of the crystal lattice or oxygen that is located between the lattices.

[0090]

[0091] From Table 1, it can be seen that the barriers to the movement of oxygen, hydrogen, and excess oxygen are large in the In-Ga-Zn oxide crystal model and small in the indium oxide crystal model. This suggests that oxygen and hydrogen move more easily (permeate more easily) in indium oxide than in In-Ga-Zn oxide. It also suggests that the indium oxide film has higher permeability to oxygen atoms and hydrogen atoms than the In-Ga-Zn oxide film. Therefore, it is presumed that the indium oxide film is a film into which hydrogen and oxygen are easily supplied and from which hydrogen and oxygen are easily discharged. In addition, the V generated in the +GBT test Ｏ It is expected that this will have the effect of filling the gap with oxygen, thereby enabling the realization of highly reliable transistors.

[0092] From the above, as shown in FIG. 3C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ) is present, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses into an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in an indium oxide film than in an IGZO film. In this way, since the oxygen vacancies in an indium oxide film are more easily reduced in a film than in an IGZO film, by applying such an indium oxide film to a transistor, a transistor exhibiting extremely high reliability can be realized.

[0093] Furthermore, as shown in FIG. 3C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or, as mentioned above, reacts with the oxygen contained in the film and is released as water molecules.

[0094] The content of the first element in the semiconductor layer 30 is preferably low. Furthermore, the concentration of the first element in the semiconductor layer 30 is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. That is, in the semiconductor layer 30, the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium is preferably low, the concentrations of two selected from boron, carbon, aluminum, silicon, zinc, and gallium are more preferably low, and the concentrations of all of boron, carbon, aluminum, silicon, zinc, and gallium are even more preferably low. The concentration of the first element in the semiconductor layer 30 is, for example, preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. The preferred concentration of the first element in the semiconductor layer 30 can also be said to be the preferred concentration of the first element in the channel formation region.

[0095] Furthermore, as will be described later, by using a precursor that has been distilled one or more times, it is possible to set the concentration of the first element in the semiconductor layer 30 to 0.01 atomic % (100 ppm) or less, 0.0001% (1 ppm) or less, 0.00001% (0.1 ppm or 100 ppb) or less, or 0.0000001% (0.001 ppm or 1 ppb) or less. In other words, the content (purity) of indium excluding oxygen in the semiconductor layer 30 can be set to 99.99 atomic % or more (4N), 99.9999 atomic % or more (6N), 99.99999 atomic % or more (7N), or 99.9999999 atomic % or more (9N), which may enable the formation of a semiconductor layer 30 having a purity comparable to the purity (10N) of silicon used in the semiconductor layer.

[0096] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be improved.

[0097] When the semiconductor layer 30 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, a transistor having a semiconductor layer 30 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer 30, the variation in threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability against positive bias application. Note that the same phenomenon as when the semiconductor layer 30 contains zinc atoms may occur.

[0098] Furthermore, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms, so that by reducing the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability from decreasing.

[0099] Furthermore, impurities such as the first element contained in the indium oxide film can become crystal nuclei. Reducing the impurities in the indium oxide film as much as possible reduces the number of crystal nuclei, which can promote the growth of large crystal grains, as described below.

[0100] Furthermore, when the indium oxide film is a polycrystalline film, the first element segregates at the grain boundaries to form an oxide containing the first element. Since the oxide has insulating properties, the on-state current or field-effect mobility of the transistor may be reduced. By reducing the first element in the indium oxide film as much as possible, the on-state current or field-effect mobility of the transistor can be increased.

[0101] Furthermore, by reducing the impurities in the indium oxide film, it is possible to suppress impurity scattering. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer 30 within the above-mentioned preferable range, the field-effect mobility of the transistor can be increased to 100 cm ２ / (V·s) or more, preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0102] In addition, in Non-Patent Document 2, the upper limit of the Hall mobility calculated assuming that the main causes of scattering in indium oxide are ionized impurities and polar optical phonons is 270 cm ２ / (V·s) (see Figure 2).

[0103] Here, the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO will be explained. Ｘ ) and FIG. 3B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0104] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 3B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 3A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 3A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 3A.

[0105] 3B, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0106] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0107] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0108] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, tantalum, tungsten, molybdenum, tin, silicon, germanium, zirconium, hafnium, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0109] In this way, indium oxide, a region with a low carrier concentration is used as a channel formation region of a transistor, and a region with a high carrier concentration is used as a source region and a drain region of the transistor. That is, indium oxide can be said to be an oxide capable of valence electron control. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that is not usually conceived. By using this technical concept, a transistor that has high mobility, low off-current, and is capable of normally off operation can be realized.

[0110] The concentration of the first element can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), or the like. The evaluation can be performed using, for example, ion beam spectroscopy (EDX), energy dispersive X-ray spectroscopy (EDX), or inductively coupled plasma atomic emission spectroscopy (ICP-AES).

[0111] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may cause oxygen vacancies. This may result in fluctuations in electrical characteristics and reduced reliability. On the other hand, hydrogen present at the grain boundaries may terminate dangling bonds present at the grain boundaries, improving the electrical characteristics and reliability of the transistor. Therefore, it is preferable that the hydrogen concentration in the indium oxide film be reduced, but it may be higher than the concentration of the first element in some cases.

[0112] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide, which has a wider band gap than silicon, for the semiconductor layer 30, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0113] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in an OS transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide with a small effective mass of electrons for the semiconductor layer of a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0114] Here, single crystal indium oxide (here, In ２ O ３ The effective masses of electrons and holes shown in Table 2 are values ​​calculated by first-principles electronic structure calculations.

[0115]

[0116] As shown in Table 2, the effective mass of electrons in indium oxide is small. Therefore, by using indium oxide, which has a small effective mass of electrons, for the semiconductor layer 30, it is possible to realize a transistor with a large on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also referred to as f characteristics). Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in, for example, silicon. Therefore, from the perspective of the effective mass of electrons, the f characteristics of a transistor using indium oxide in the channel formation region are higher than the f characteristics of a Si transistor.

[0117] As shown in Table 2, the effective mass of holes in indium oxide is large. Therefore, by using indium oxide, which has a large effective mass of holes, for the semiconductor layer 30, a transistor with an extremely small off-state current can be realized. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, in terms of the effective mass of holes, the off-state current of a transistor using indium oxide for a channel formation region is sufficiently smaller than the off-state current of a Si transistor.

[0118] In a transistor using indium oxide for the semiconductor layer 30, the off-state current value per 1 μm of channel width at room temperature (25° C.) is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８ It is possible to make it less than A / μm.

[0119] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency (fT) of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature (25° C.).

[0120] The indium oxide film may contain one or more metal elements having a large period number in the periodic table, provided that the film has crystallinity. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction. Therefore, by including a metal element having a large period number in the periodic table, the field-effect mobility of the transistor may be improved. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium).

[0121] FIG. 1B shows an example in which the semiconductor layer 30 has a single-layer structure. The semiconductor layer 30 can also have a stacked structure of two or more layers. For example, when the semiconductor layer 30 has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 30 described above as the first semiconductor layer, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can mainly function as a current path (channel). In other words, the first semiconductor layer has a channel formation region on the surface on the second semiconductor layer side and in the vicinity thereof.

[0122] The above-described configuration can reduce carriers trapped at the interface of the first semiconductor layer and its vicinity. Also, the channel can be located away from the surface of the insulating layer 50, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0123] Examples of metal oxides that can be used for the second semiconductor layer include indium gallium oxide (In—Ga oxide), In—Zn oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin oxide containing silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0124] The In-Zn oxide used in the second semiconductor layer can specifically have a composition of In:Zn=1:1 (atomic ratio) or thereabouts, In:Zn=2:1 (atomic ratio) or thereabouts, or In:Zn=4:1 (atomic ratio) or thereabouts. Furthermore, the IGZO used in the second semiconductor layer can specifically have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabouts, In:Ga:Zn=1:3:2 (atomic ratio) or thereabouts, or In:Ga:Zn=1:3:4 (atomic ratio) or thereabouts.

[0125] The crystallinity of the metal oxide included in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may include at least one of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0126] 1D shows insulating layer 20 and layer 29, which are components of the semiconductor device. As shown in Fig. 1D, an island-shaped layer 29 is provided in contact with insulating layer 20. In Fig. 1D, layer 29 is provided outside groove portion 91 so as to be in contact with the upper surface of insulating layer 20. Semiconductor layer 30 is provided so as to cover layer 29.

[0127] The layer 29 has crystals. The layer 29 functions as a seed or nucleus when a process for increasing the crystallinity of the semiconductor layer 30 is performed. In other words, the layer 29 functions as a seed or nucleus when the semiconductor layer 30 grows crystals. In this specification and the like, the layer 29 or the crystals contained in the layer 29 can be referred to as a seed crystal or a crystal nucleus. Furthermore, since the layer 29 has crystals, the layer 29 can be referred to as a crystalline portion.

[0128] The crystal structure of indium oxide is cubic (bixbyite type). When indium oxide is used for the semiconductor layer 30, the layer 29 preferably has, for example, hexagonal or trigonal crystals. In this case, the layer 29 has crystals with a <001> crystal orientation relative to the surface or surface on which the layer 29 is formed, thereby forming the semiconductor layer 30 having crystals with a <111> crystal orientation. When the crystals of the layer 29 have a <001> crystal orientation relative to the surface or surface on which the layer 29 is formed, the c-axis of the crystals is perpendicular or approximately perpendicular to the surface or surface on which the layer 29 is formed. Note that a hexagonal or trigonal crystal can sometimes be referred to as a crystal with a layered structure. Therefore, the above structure can be considered as a structure in which the semiconductor layer 30 having cubic crystals is formed on the layer 29 having crystals with a layered structure. That is, it can also be considered as a stacked structure manufactured using a heteroepitaxial growth technique or a technique similar to heteroepitaxial growth.

[0129] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0130] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of a film containing the crystal or the surface on which the crystal is formed. For example, a crystal with a crystal orientation of <100> is said to be a crystal whose (100) plane is parallel to the surface of a film containing the crystal or the surface on which the crystal is formed.

[0131] Specifically, layer 29 can be made of zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide. Layer 29 preferably uses In—Ga—Zn oxide. In this case, layer 29 contains indium, gallium, zinc, and oxygen. Specifically, layer 29 preferably has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereabout. Metal oxides with these compositions are suitable for layer 29 because they easily form a layered structure. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0132] In—Ga—Zn oxide, In—Sn—Zn oxide, and the like are likely to have a CAAC structure. When an oxide having a CAAC structure is used for layer 29, the c-axis of the crystals of layer 29 is perpendicular or approximately perpendicular to the surface of layer 29 or the surface on which layer 29 is formed. In other words, the crystal orientation of the crystals of layer 29 with respect to the surface of layer 29 or the surface on which layer 29 is formed is <001>. Therefore, by using an oxide that is likely to have a CAAC structure for layer 29, the controllability of the crystal orientation of the crystals of layer 29 can be improved.

[0133] Here, the crystal structures of metal oxides are shown in Figures 4A to 4E. Figure 4A is a diagram of the crystal structure of In-Ga-Zn oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio], viewed from a direction perpendicular to the c-axis. Figure 4B is a diagram of the plane indicated by the dashed line in Figure 4A, viewed from the c-axis direction. Figure 4C is a diagram of the plane indicated by the dashed line in Figure 4A, viewed from the c-axis direction. Figure 4D is a diagram of the plane indicated by the dashed line in Figure 4A, viewed from the c-axis direction. Mx in Figures 4A, 4C, and 4D represents Ga atoms or Zn atoms. Note that in Figure 4A, the plane indicated by the dashed line, the plane indicated by the dashed line, and the plane indicated by the dashed line are sometimes collectively referred to as the c-plane. Figure 4E is a diagram of the crystal structure of indium oxide, viewed from a direction perpendicular to the (111) plane.

[0134] The distance between metal atoms on the c-plane (arrows shown in each of FIGS. 4B to 4D) is said to be 0.330 nm. The In-In distance on the (111) plane (arrows shown in FIG. 4E) is said to be 0.334 nm and 0.385 nm. This shows that the arrangement of metal atoms on the c-plane of the CAAC structure and the (111) plane of indium oxide are similar. Therefore, an oxide that easily has a CAAC structure can be suitably used as layer 29.

[0135] When an oxide that easily has a CAAC structure is used for the layer 29, the semiconductor layer 30 can be formed having crystals with a <111> crystal orientation. Note that when the layer 29 is provided in a region that does not overlap with the groove 91 of the insulating layer 20, the crystal orientation of the crystal grains of the semiconductor layer 30 located in the region that does not overlap with the groove 91 of the insulating layer 20 can be <111>.

[0136] 5A and 5B show cross-sectional views of the insulating layer 20 and the semiconductor layer 30 at and near the upper end of the groove 91. The layer 29, the insulating layer 50, and the conductive layer 60 are omitted in FIGS. 5A and 5B. When the crystal growth rate in the semiconductor layer 30 in a direction parallel to the <111> orientation is faster than the crystal growth rate in a direction perpendicular to the <111> orientation, the <111> orientation of the crystal grains in the semiconductor layer 30 tends to be perpendicular or approximately perpendicular to the substrate surface (not shown), as shown in FIG. 5A. Depending on the crystal orientation and position of the layer 29 functioning as a seed crystal, the <111> orientation of the crystal grains may be horizontal to the substrate surface, as shown in FIG. 5B. For example, when the layer 29 is provided on top of the insulating layer 20, as shown in FIG. 5C, the <111> orientation of the crystal grains tends to be perpendicular to the substrate surface. On the other hand, as shown in FIG. 5D, when layer 29 is provided along the side surface of insulating layer 20, the <111> orientation of the crystal grains tends to be parallel to the substrate surface.

[0137] Here, the anisotropy of the effective mass of electrons in indium oxide is small. For example, in indium oxide, the effective mass of electrons in the

[100] direction, the effective mass of electrons in the

[110] direction, and the effective mass of electrons in the

[111] direction are approximately the same, ranging from 0.17 to 0.19. Therefore, regardless of the crystal orientation of the crystal grains located in the channel formation region, high field-effect mobility can be obtained.

[0138] Layer 29 can also be made of an oxide having a cubic crystal structure. Having the same crystal structure as semiconductor layer 30 allows epitaxial growth of semiconductor layer 30 using layer 29 as a seed or nucleus, thereby improving the crystallinity of semiconductor layer 30. Note that oxides containing Group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, Group 3 elements in the crystals are primarily present as trivalent cations. Therefore, layer 29 preferably contains at least one element capable of becoming a trivalent cation. The element capable of becoming a trivalent cation contained in layer 29 is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0139] For example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. can be used for the layer 29. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0140] It is also preferable that the difference (also referred to as lattice mismatch) between the lattice constant or the length of the unit lattice vector of the crystal nucleus and the lattice constant or the length of the unit lattice vector of the crystal of the semiconductor layer 30 is small. By using an oxide that reduces the lattice mismatch for the layer 29, the crystallinity of the semiconductor layer 30 can be improved.

[0141] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) with respect to the crystals of the formed film is calculated by the following formula (1). Hereinafter, the lattice mismatch Δa of the crystals of the formed film with respect to the crystals of the formed film may be simply referred to as the lattice mismatch Δa of the formed film with respect to the formed film.

[0142]

[0143] In formula (1), L １ is the lattice constant or the length of the unit lattice vector of the crystal of the formed film, and L ２ is the lattice constant or the length of the unit lattice vector of the crystal of the film to be formed.

[0144] The lattice mismatch Δa of the crystal grains in the semiconductor layer 30 with respect to the crystal nuclei is preferably −10% to 10%, more preferably −5% to 5%, and even more preferably −3% to 3%. By using a material that reduces the lattice mismatch with the semiconductor layer 30 for the layer 29, the crystallinity of the semiconductor layer 30 can be improved.

[0145] For example, the lattice constant of indium oxide crystal (bixbyite type) is said to be 1.01194 nm. The lattice constant of yttrium oxide crystal (bixbyite type) is said to be 1.05976 nm. Therefore, the lattice mismatch of indium oxide crystal with yttrium oxide crystal is −4.5%. Therefore, when indium oxide is used for the semiconductor layer 30, yttrium oxide can be used for the layer 29.

[0146] For example, the lattice constant of erbium oxide crystal (bixbyite type) is said to be 1.0582 nm. Therefore, the lattice mismatch of indium oxide crystal with erbium oxide crystal is −4.4%. Therefore, when indium oxide is used for semiconductor layer 30, erbium oxide can be used for layer 29.

[0147] For example, Zr, which is an example of yttrium zirconium oxide, ０．９ Y０．１ O １．９５ The lattice constant of the crystal (fluorite type) is 0.51481 nm (see ICSD coll.code.248790). ０．９ Y ０．１ O １．９５ The lattice mismatch of indium oxide crystal with indium oxide crystal is −1.7%. Therefore, when indium oxide is used for the semiconductor layer 30, yttrium zirconium oxide can be suitably used for the layer 29. Note that yttrium zirconium oxide contains yttrium, zirconium, and oxygen.

[0148] Adding yttrium or yttrium oxide to zirconium oxide, that is, increasing the yttrium content in yttrium zirconium oxide to greater than 0 atomic%, can stabilize the crystalline structure of zirconium oxide. However, if the content is too high, the crystalline structure of yttrium zirconium oxide may change from a cubic system to another system, so it is preferable that the content is not too high. Therefore, for example, the yttrium content in yttrium zirconium oxide is preferably 2 atomic% or more and 15 atomic% or less, and more preferably 5 atomic% or more and 10 atomic% or less.

[0149] Alternatively, indium oxide may be used for the layer 29. By using indium oxide for the layer 29, the semiconductor layer 30 can be homoepitaxially grown using the layer 29 as a seed or nucleus, and the crystallinity of the semiconductor layer 30 can be improved.

[0150] There are no particular limitations on the material that can be used for layer 29. Layer 29 may be made of an insulating material, a semiconductor material, or a conductive material. When a semiconductor material is used for layer 29, layer 29 may be considered as part of semiconductor layer 30.

[0151] 6A shows a cross-sectional view of the insulating layer 20 in the groove 91 when the upper end portion thereof has a curved surface. Also, FIG. 6B shows a perspective view of FIG. 6A, and FIG. 6C shows a perspective view of the insulating layer 20 and the layer 29. The curved upper end portion of the insulating layer 20 provides a gentle continuity between the upper surface of the insulating layer 20 and the side surface of the groove 91. This reduces the likelihood of distortion at the upper end portion of the insulating layer 20 during crystal growth of the semiconductor layer 30, thereby enabling the production of a semiconductor layer 30 with fewer crystal defects. This allows for the realization of a highly reliable transistor.

[0152] The radius of curvature R1 of the upper end of the insulating layer 20 in the groove 91 can be 1 nm or more and 500 nm or less, preferably 1 nm or more and 300 nm or less, more preferably 1 nm or more and 200 nm or less, and even more preferably 1 nm or more and 100 nm or less. The radius of curvature R1 is preferably larger than the thickness of the semiconductor layer 30. Note that the radius of curvature R1 is preferably smaller than at least the thickness of the insulating layer 20.

[0153] Furthermore, by also having a curved surface at the bottom of the groove 91, a semiconductor layer 30 with fewer crystal defects can be obtained, as described above. While FIG. 6A illustrates an example in which a portion of the insulating layer 20 located at the bottom of the groove 91 has a curved surface, the curved surface is not limited to the insulating layer 20 and can be another insulating layer or conductive layer. The radius of curvature R2 of the curved surface of the layer located at the bottom of the groove 91 (here, the insulating layer 20) can be 1 nm or more and 500 nm or less, preferably 1 nm or more and 300 nm or less, more preferably 1 nm or more and 200 nm or less, and even more preferably 1 nm or more and 100 nm or less. The radius of curvature R1 is preferably greater than the thickness of the semiconductor layer 30. It is preferable that the radius of curvature R1 be smaller than at least half the width of the groove 91.

[0154] 7A and 7B show cross-sectional views of the vicinity of the upper end of the insulating layer 20 when the upper end has a curved surface. FIGS. 7A and 7B correspond to FIGS. 5A and 5B, respectively. As shown in FIGS. 7A and 7B, since the upper end of the insulating layer 20 has a curved surface, crystal growth proceeds smoothly regardless of the crystal structure, and a semiconductor layer 30 having good crystallinity throughout the semiconductor layer 30 can be formed. FIGS. 7C and 7D correspond to FIGS. 5C and 5D, respectively, and show an example in which layer 29 is provided.

[0155] 8A to 8C show an example in which a pair of layers 40 are provided on top of an insulating layer 20. The layer 40 is separated by a groove 91. The upper end of the layer 40 at the groove 91 has a curved surface. Also, in FIGS. 8A to 8C, a layer 70 is provided at the bottom of the groove 91. The layer 70 has a curved surface at the bottom of the groove 91. As described above, the layer on which the semiconductor layer 30 is formed can be a layer other than the insulating layer 20. In this case, it is preferable that the layer on which the semiconductor layer 30 is formed has a curved surface. The layers 40 and 70 can be made of a conductive material, a semiconductor material, or an insulating material. For example, when the layers 40 and 70 are made of a conductive material, the layer 40 can function as one of a source electrode and a drain electrode, and the layer 70 can function as the other.

[0156] 1D shows an example in which layer 29 is circular in plan view. However, the present invention is not limited to this. In plan view, layer 29 can be, for example, a circle or a substantially circle such as an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. Furthermore, when sputtered particles are used as layer 29, layer 29 may be triangular or hexagonal in plan view.

[0157] 9A , the layer 29 may have a tapered shape. For example, the angle formed between the top surface of the insulating layer 20 outside the groove 91 and the side surface of the layer 29 may be less than 90°, preferably 30° or more and less than 90°. By forming the layer 29 in a tapered shape, the coverage of the semiconductor layer 30 can be improved and defects such as voids can be reduced. Furthermore, the crystal growth of the semiconductor layer 30 can be promoted.

[0158] 1D shows an example in which island-shaped layer 29 is provided. However, the present invention is not limited to this. For example, as shown in FIG. 9B, layer 29 may have a region extending in a direction perpendicular to the Z direction. Alternatively, for example, as shown in FIGS. 9C and 9D, layer 29 may be provided so as to cover the upper surface of insulating layer 20 outside groove portion 91.

[0159] Furthermore, a layer may be provided between the insulating layer 20 and the layer 29. Figures 9E and 9F illustrate a configuration in which a layer 40 is provided between the insulating layer 20 and the layer 29. In other words, the configurations shown in Figures 9E and 9F can be said to be a configuration in which the layer 40 is provided in the configurations shown in Figures 9C and 9D . Note that the layer 40 may be made of a conductive material, a semiconductor material, an insulating material, or a stack of two or more of these materials. For example, when a conductive material is used as the layer 40, the layer 40 contacts the semiconductor layer 30 (not shown) at least on the side surface of the groove 91, and therefore can function as a source electrode or a drain electrode.

[0160] 1D shows an example in which layer 29 is provided in contact with the upper surface of insulating layer 20 outside groove 91. However, the present invention is not limited to this. For example, as shown in FIGS. 10A and 10B, layer 29 may be provided so as to fill an opening provided in insulating layer 20. This allows the upper surface of insulating layer 20 outside groove 91 to be flat, thereby improving the crystallinity of semiconductor layer 30. Note that layer 29 filled in the opening may have an extending region (see FIG. 10C).

[0161] 9C and 9D show an example in which the layer 29 is provided outside the groove 91. However, the present invention is not limited to this. For example, as shown in FIGS. 11A and 11B, a portion of the layer 29 may be provided on the bottom of the groove 91. Alternatively, as shown in FIGS. 11C and 11D or 11E and 11F, the layer 29 may be provided in contact with at least a portion of the sidewall of the groove 91.

[0162] By providing the layer 29 in contact with at least a portion of the sidewall of the groove 91, it is possible to form a semiconductor layer 30 having crystal grains whose <111> orientation coincides or substantially coincides with the direction perpendicular to the sidewall of the groove 91. Note that, in the semiconductor layer 30, if the crystal growth rate in the direction perpendicular to the <111> orientation is faster than the crystal growth rate in the direction parallel to the <111> orientation, the <111> orientation of the crystal grains in the semiconductor layer 30 tends to be parallel or substantially parallel to the substrate surface (not shown), as shown in FIG.

[0163] The thickness of layer 29 is preferably thin. For example, the thickness of layer 29 is preferably thinner than the thickness of semiconductor layer 30. Specifically, layer 29 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm. By reducing the thickness of layer 29, the step between layer 29 and insulating layer 20 is reduced. This improves the coverage of semiconductor layer 30 and reduces defects such as voids. Furthermore, crystal growth of semiconductor layer 30 can be promoted. Layer 29 may be layered or granular.

[0164] The insulating layer 50 preferably has a function of supplying oxygen to the semiconductor layer 30. The insulating layer 50 preferably has a region containing oxygen that is desorbed by heating (hereinafter, may be referred to as excess oxygen), for example. When the insulating layer having the region containing excess oxygen is in contact with the semiconductor layer 30, oxygen can be supplied to the semiconductor layer 30. The oxygen supplied to the semiconductor layer 30 repairs oxygen vacancies, and the amount of oxygen vacancies in the semiconductor layer 30 can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0165] The insulating layer 50 preferably has a function of capturing or fixing oxygen (also referred to as gettering). As described above, an indium oxide film is a film through which oxygen easily moves. Therefore, when the insulating layer 50 has the function of capturing or fixing oxygen, excess oxygen in the semiconductor layer 30 can be diffused to the insulating layer 50 and the oxygen can be captured or fixed. Therefore, the OS transistor can suppress positive drift degradation in a +GBT stress test caused by excess oxygen. Examples of insulating materials having a function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and an oxide containing hafnium and silicon (hafnium silicate).

[0166] Aluminum oxide, hafnium oxide, hafnium zirconium oxide, and hafnium silicate have the function of capturing or fixing hydrogen. As described above, an indium oxide film is a film through which hydrogen easily moves. Therefore, since the insulating layer 50 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 30 can be diffused into the insulating layer 50 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 30 (particularly the hydrogen concentration in the channel formation region) can be reduced.

[0167] FIG. 1B shows an example in which the insulating layer 50 has a single-layer structure. The insulating layer 50 can have a stacked structure of two or more layers. When the insulating layer 50 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically aluminum oxide) applicable to the insulating layer 50 described above as the layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 50. With such a structure, oxygen can be supplied to the semiconductor layer 30, and the amount of oxygen vacancy can be reduced. Furthermore, excess oxygen in the semiconductor layer 30 can be discharged to the insulating layer 50. Furthermore, hydrogen in the semiconductor layer 30 can be captured or fixed.

[0168] The insulating layer 20 preferably has a function of supplying oxygen to the semiconductor layer 30. For example, the insulating layer 20 preferably has a region containing excess oxygen. The insulating layer 50 preferably has a function of capturing or fixing oxygen. With such a configuration, oxygen is pushed into the semiconductor layer 30 from the insulating layer 20 side, reducing the amount of oxygen vacancy in the semiconductor layer 30, and further, excess oxygen in the semiconductor layer 30 is pulled from the insulating layer 50 side, reducing the excess amount of oxygen in the semiconductor layer 30. Therefore, a semiconductor device with good reliability can be provided.

[0169] Furthermore, it is preferable to use a material for the insulating layer 20 that has a smaller thermal expansion coefficient than the metal oxide used for the semiconductor layer 30. For example, a material for the insulating layer 20 that has a smaller thermal expansion coefficient than indium oxide can be used. Specifically, the thermal expansion coefficient of the insulating layer 20 is 0.01×10 −６ K −１ 5.5 x 10 −６ K −１ Preferably, 0.01 x 10 or less −６ K −１ Above 5.0 x 10 −６ K −１ Preferably, it is less than 0.01 × 10 −６ K −１ Above 3.0 x 10 −６ K −１ More preferably, 0.01 x 10 or less −６ K −１ Above 1.0 x 10 −６ K −１ The following is even more preferable. With this configuration, the semiconductor layer 30 containing indium oxide is in contact with or located near the insulating layer 20, which has a small thermal expansion coefficient, and tensile stress is applied to the indium oxide when the temperature drops, making the indium oxide energetically unstable. As a result, the indium oxide becomes a cubic crystal, which is more energetically stable. This promotes crystal growth, allowing the formation of cubic crystals with large grain sizes. Silicon oxide is suitable for the insulating layer 20 because it has a smaller thermal expansion coefficient than indium oxide.

[0170] The thermal expansion coefficients of oxide semiconductors and insulators are shown in Table 3. In Table 3, IGZO and indium oxide (In ２ O ３ ) as an insulator, and silicon oxide (SiO ２ ), silicon nitride (Si ３ N ４ ), and yttria-stabilized zirconia (YSZ).

[0171]

[0172] 1B shows an example in which the insulating layer 20 has a single layer structure. However, the insulating layer 20 can have a stacked structure of two or more layers. When the insulating layer 20 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically silicon oxide) applicable to the insulating layer 20 described above as the layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 20. By using such a structure, the crystallinity of the semiconductor layer 30 can be improved.

[0173] It is preferable to use a highly conductive material such as tungsten for the conductive layer 60. It is also preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the conductive layer 60. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 60.

[0174] Furthermore, the conductive layer 60 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. For example, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. Indium gallium zinc oxide containing nitrogen may also be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an insulating layer outside the transistor may be captured.

[0175] In this embodiment, an example in which the groove portion 91 extends in the X direction is shown. However, the present invention is not limited to this. In a plan view, the groove portion 91 may be, for example, a circle or a substantially circle such as an ellipse, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. The circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0176] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below. The example of the manufacturing method of a semiconductor device described here also includes a method for manufacturing a semiconductor layer.

[0177] 12A, 12C, 12E, 13A, 13C, and 13E are schematic perspective views of the semiconductor device, and FIGS. 12B, 12D, 12F, 13B, 13D, and 13F are cross-sectional views of the semiconductor device as viewed from the X direction.

[0178] The layers constituting the semiconductor device (insulating layer 20, layer 29, semiconductor layer 30, insulating layer 50, conductive layer 60, etc.) can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. In particular, it is preferable to form the semiconductor layer 30 and the insulating layer 50 using the ALD method.

[0179] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings or grooves with high aspect ratios.

[0180] Some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Quantitative determination of these elements can be performed using XPS or SIMS. When the ALD method is used, the amount of carbon and chlorine contained in the film may be lower by adopting a high substrate temperature during film formation and / or by performing an impurity removal process, compared to when the ALD method is used without these procedures.

[0181] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0182] In a film forming apparatus using the ALD method, a first source gas (sometimes called a precursor, precursor, or metal precursor) and a second source gas (sometimes called a reactant, reactant, oxidizer, or non-metal precursor) for the reaction are alternately introduced into a chamber, and film formation is performed by repeating the introduction of these source gases. Note that the introduction of the source gases can be switched by, for example, switching the respective switching valves (sometimes called high-speed valves). In addition, when introducing the source gases, nitrogen (N ２ An inert gas such as argon (Ar), argon (Ar), or helium (He) may be introduced into the chamber together with the source gas as a carrier gas. By using a carrier gas, even if the source gas has low volatility or a low vapor pressure, it is possible to suppress the source gas from being adsorbed inside the piping and the valve, and to introduce the source gas into the chamber. This also improves the uniformity of the film formed, which is preferable.

[0183] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0184] First, as shown in Figures 12A and 12B, an insulating layer 20 is formed on a substrate (not shown). The upper surface of the insulating layer 20 is preferably flat. By flattening the upper surface of the insulating layer 20, the crystallinity of the semiconductor layer 30 to be formed later can be improved. For example, this can promote lateral growth of the crystals of the semiconductor layer 30 in the first heat treatment described below.

[0185] The insulating layer 20 can be formed by, for example, a sputtering method in an atmosphere containing oxygen. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas, the hydrogen concentration in the insulating layer 20 can be reduced. Furthermore, by forming the insulating layer 20 by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the insulating layer 20. Oxygen is supplied from the insulating layer 20 to the semiconductor layer 30 by heat or the like applied after the formation of the semiconductor layer 30, and oxygen vacancies and defects in which hydrogen has entered the oxygen vacancies (hereinafter referred to as V ＯThis can reduce the amount of heat generated by the heat transfer mechanism (sometimes referred to as H).

[0186] Heat treatment is preferably performed before forming the layer 29. The heat treatment is performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0187] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm (0.001%) or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the heat treatment as described above, impurities such as hydrogen or water contained in the insulating layer 20 or the like can be reduced before the semiconductor layer 30 is formed.

[0188] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb (1×10 −３ ppm) or less, and 0.1 ppb (1 x 10 −４ ppm) or less, and 0.05 ppb (5 × 10 −５ By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 20 and the like as much as possible.

[0189] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0190] Furthermore, it is preferable to perform a process of supplying oxygen before forming the layer 29. This supplies oxygen to the insulating layer 20, and oxygen can be supplied from the insulating layer 20 to the semiconductor layer 30 by heat or the like applied after the formation of the semiconductor layer 30.

[0191] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 20 by forming an oxide film (preferably a metal oxide film) by sputtering in an oxygen-containing atmosphere. The formed oxide film may be removed immediately after deposition or may be left as it is. When the formed oxide film is left as it is, the oxide film can be used as part of the semiconductor layer 30. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound gas containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0192] Subsequently, a layer 29 is formed on the insulating layer 20 (FIGS. 12A and 12B). The layer 29 functions as a seed or nucleus for crystal growth of the semiconductor layer 30. Therefore, the layer 29 can be called a seed layer, a seed crystal, or the like.

[0193] There is no particular limitation on the method for forming the layer 29. For example, the layer 29 can be formed by forming a film that will become the layer 29 and processing the film. The film can be formed by a sputtering method, a CVD method, a vacuum deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0194] The layer 29 can be formed by a sputtering method. Forming the layer 29 by a sputtering method can improve the crystallinity of the layer 29. Furthermore, forming the layer 29 by a sputtering method in an atmosphere containing oxygen can add oxygen to the insulating layer 20.

[0195] In addition, if a sputtering target has multiple crystal grains, and the crystal grains have a layered structure and have interfaces that are prone to cleavage, bombarding the sputtering target with ions can cleave the crystal grains, resulting in plate-shaped or pellet-shaped sputtering particles. Plate-shaped or pellet-shaped sputtering particles deposited on the insulating layer 20 may be used as layer 29. For example, if the crystal grains contain indium, gallium, zinc, and oxygen and have a hexagonal or trigonal crystal structure, the crystal grains are prone to cleavage along the {001} plane. Therefore, the plate-shaped or pellet-shaped sputtering particles are deposited on the insulating layer 20 so that the {001} plane is parallel to the surface of the insulating layer 20. Therefore, by using plate-shaped or pellet-shaped sputtering particles as layer 29, a semiconductor layer 30 having crystals with a <111> crystal orientation can be formed.

[0196] 12A and 12B, the insulating layer 20 is processed to form grooves 91. The grooves 91 extend in the X direction. When forming the grooves 91, a portion of the insulating layer 20 can be processed using an etching process. In particular, dry etching is preferable because it is suitable for fine processing.

[0197] 9C and 9D can be formed by forming groove 91 without processing the film that will become layer 29. This reduces the number of steps required to fabricate a semiconductor device compared to when the film is processed.

[0198] Furthermore, by forming films that will become layers 40 and 29 in this order on insulating layer 20 and then forming grooves 91, the structure shown in FIGS. 9E and 9F can be fabricated.

[0199] 10A and 10B or the layer 29 shown in Fig. 10C can be formed by forming an opening in the insulating layer 20, filling the opening with a film that will become the layer 29, and polishing the film by CMP or the like until the surface of the insulating layer 20 is exposed. This allows the upper surface of the insulating layer 20 outside the groove 91 to be flat.

[0200] 11A and 11B can be formed by forming a film that will become layer 29 by sputtering after forming groove 91. This reduces the number of manufacturing steps for the semiconductor device compared to processing the film. Alternatively, layer 29 shown in FIGS. 11C and 11D can be formed by removing a portion of layer 29 shown in FIGS. 11A and 11B by anisotropic etching such as dry etching.

[0201] Alternatively, after forming the groove portion 91, a film that will become the layer 29 is formed using a film formation method with good coating properties, such as the ALD method, and then a portion of the film is removed by anisotropic etching, such as dry etching, to form the layer 29 shown in Figures 11E and 11F.

[0202] As described above, by forming layer 29 before forming semiconductor layer 30, the thermal effect on semiconductor layer 30 can be reduced, and the grain size of the crystals in semiconductor layer 30 can be reduced and an increase in the grain boundaries can be suppressed.

[0203] Next, as shown in FIGS. 12C and 12D , a semiconductor layer 30 is formed to cover the layer 29 and the groove 91. The semiconductor layer 30 is preferably formed using a sputtering method. A noble gas (typically argon) or a simple gas such as oxygen, or a mixture of a noble gas and oxygen, can be used as the sputtering gas. The proportion of the noble gas (typically argon) in the entire sputtering gas is, for example, 50% to 100%, preferably 70% to 100%, and more preferably 90% to 100%. By increasing the proportion of the noble gas (typically argon) in the entire sputtering gas, a semiconductor layer 30 with low crystallinity can be formed. Furthermore, a semiconductor layer 30 with many dangling bonds can be formed. This increases the etching rate of the semiconductor layer 30. This facilitates processing of the semiconductor layer 30, thereby improving the productivity of semiconductor devices. The semiconductor layer 30 with low crystallinity has, for example, an amorphous structure.

[0204] The sputtering gas is hydrogen (H ２ ) can also be included. By introducing hydrogen when forming the semiconductor layer 30 by sputtering, it is possible to form a semiconductor layer 30 with low crystallinity. Furthermore, when forming the semiconductor layer 30, it is possible to suppress the generation of crystal nuclei or promote the annihilation of crystal nuclei. Note that if there are many crystal nuclei, the grown crystals collide with each other, suppressing the increase in grain size. In other words, the crystals will have a small grain size. However, by suppressing the generation of crystal nuclei and annihilating some of the crystal nuclei in the film to reduce the number of crystal nuclei, and then performing the first heat treatment described below, it is possible to promote crystal growth from fewer crystal nuclei and increase the crystal grain size in the semiconductor layer 30.

[0205] The semiconductor layer 30 can also be formed by sputtering in an atmosphere containing oxygen. In this case, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the semiconductor layer 30 can be reduced. For example, oxygen or a mixed gas of oxygen and a noble gas may be used as the sputtering gas.

[0206] Alternatively, the semiconductor layer 30 may be formed using an ALD method. A first precursor and a first oxidizing agent can be used to form the semiconductor layer 30. The first precursor preferably contains indium. In this case, an indium oxide film is formed as the semiconductor layer 30. That is, an oxide film containing a single element other than oxygen is formed. Note that when the first precursor contains indium, a thermal ALD method can be used as the ALD method.

[0207] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0208] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0209] It is preferable to use a precursor with a low impurity concentration, i.e., a high purity, in the method for forming the semiconductor layer 30. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, it is possible to reduce the impurities in the semiconductor layer 30.

[0210] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor layer 30 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor layer 30 can be reduced, thereby improving the crystallinity of the semiconductor layer 30.

[0211] Furthermore, as the precursor used in this embodiment, it is preferable to use a precursor purified by performing distillation (also referred to as rectification or precision distillation) two or more times. By using such a precursor, it is easy to form a metal oxide film with few impurities, which is preferable. By performing distillation multiple times, it is possible to further suppress impurities originating from the starting materials used in the precursor production from remaining in the precursor, which is preferable. Note that the present invention is not limited to the above, and a precursor purified by one distillation, i.e., simple distillation, may also be used. By using simple distillation, it is possible to reduce production costs, which is preferable.

[0212] By performing distillation one or more times, the aluminum content of the indium-containing precursor can be reduced to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less. By using the indium-containing precursor, it is possible to form an indium oxide film having a purity similar to that of silicon (10N) used in the semiconductor layer.

[0213] As the first oxidant, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used. The first oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the first oxidizing agent, the amount of hydrogen mixed into the insulating layer 20 can be reduced. Note that the first oxidizing agent can contain at least one of water and hydrogen peroxide. This allows the formation of a semiconductor layer 30 with low crystallinity.

[0214] In this specification and the like, unless otherwise specified, when ozone, oxygen, or water is used as an oxidizing agent, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, or ion state.

[0215] The pulse time for introducing the first oxidizing agent is preferably 0.1 seconds or more and 30 seconds or less, more preferably 0.3 seconds or more and 15 seconds or less, and even more preferably 0.3 seconds or more and 10 seconds or less. By shortening the pulse time for introducing the first oxidizing agent and reducing the amount of the first oxidizing agent introduced, more hydrogen contained in the first precursor remains in the film. By leaving more hydrogen in the film, it is possible to suppress the generation of crystal nuclei and eliminate some of the crystal nuclei in the film, thereby reducing the number of crystal nuclei in the film.

[0216] Here, the substrate heating temperature when introducing the first precursor into the reaction chamber is preferably set to a temperature corresponding to the decomposition temperature of the first precursor. Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, the substrate heating temperature can be, for example, 100°C to 350°C, preferably 150°C to 300°C. When providing layer 29, the substrate heating temperature can be set to room temperature (25°C) to 300°C, preferably room temperature to 200°C, and more preferably room temperature to 150°C. By lowering the substrate heating temperature, the crystallinity of semiconductor layer 30 during film formation can be reduced.

[0217] When the semiconductor layer 30 has a stacked structure, the semiconductor layer 30 can also be formed using, for example, a sputtering method and an ALD method. For example, when the semiconductor layer 30 has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer can be formed by an ALD method and the second semiconductor layer can be formed by a sputtering method. Since the ALD method is a film formation method with superior coverage compared to the sputtering method, forming the first semiconductor layer by the ALD method can improve the coverage of the semiconductor layer 30. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio. Furthermore, forming the second semiconductor layer by a sputtering method can improve productivity.

[0218] Alternatively, the first semiconductor layer may be formed by sputtering, and the second semiconductor layer may be formed by ALD. Even if pinholes or discontinuities are formed in the first semiconductor layer formed by sputtering, the overlapping portions can be filled with the second semiconductor layer formed by ALD, which has good coverage.

[0219] Next, the semiconductor layer 30 is processed into a desired shape. In Figures 12E and 12F, the semiconductor layer 30 is processed into an island shape to form a plurality of semiconductor layers 30. Specifically, the semiconductor layer 30 is processed so that the plurality of semiconductor layers 30 are spaced apart in the X direction.

[0220] It is preferable to supply the second element to the semiconductor layer 30 (this can also be referred to as adding or injecting the second element) before processing the semiconductor layer 30. This supplies the second element to the semiconductor layer 30. By supplying the second element to the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be reduced. This makes it easier to process the semiconductor layer 30, and can increase the productivity of semiconductor devices.

[0221] As the second element, it is preferable to use one or more of hydrogen and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0222] Plasma treatment can be suitably used to supply the second element. In the case of plasma treatment, the second element can be supplied by generating plasma in a gas atmosphere containing the second element to be supplied and performing plasma treatment. Devices that can be used to generate the plasma include dry etching devices, ashing devices, plasma CVD devices, and high-density plasma CVD devices. By supplying the second element at an accelerated rate, the collision energy when the second element is supplied to the semiconductor layer 30 increases, and the crystallinity of the semiconductor layer 30 can be more effectively reduced, which is preferable.

[0223] The supply of the second element is not limited to the above-described method, and for example, ion implantation can also be used. The ion implantation method can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied second element. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that a method in which ions are mass-separated before supplying them is sometimes called an ion implantation method, and a method in which ions are supplied without mass separation is sometimes called an ion doping method.

[0224] A gas containing the second element can be used as the source gas. When argon is used as the second element, argon gas can be used as the source gas. When argon and hydrogen are used as the second element, a mixed gas of argon gas and hydrogen gas can be used as the source gas. Alternatively, a mixed gas of a gas containing the second element and another gas can be used. Note that the source material used to supply the second element is not limited to a gas, and a solid or liquid can also be heated and vaporized for use.

[0225] Subsequently, a first heat treatment is performed. The first heat treatment is performed using, for example, hydrogen (H ２ ) and nitrogen (N ２ ), and hydrogen (H２ ) and nitrogen (N ２ ) is more preferably carried out in an atmosphere containing the hydrogen gas. In this case, the hydrogen flow ratio is preferably 3% or more and 15% or less, and more preferably 5% or more and 10% or less. The hydrogen flow ratio refers to the ratio of the flow rate of hydrogen gas to the total gas flow rate. The temperature of the first heat treatment is preferably 120°C or more and 300°C or less, more preferably 120°C or more and 250°C or less, and more preferably 120°C or more and 200°C or less. The time period of the first heat treatment is preferably 1 hour or more and 8 hours or less.

[0226] The first heat treatment promotes epitaxial growth and lateral growth of crystal grains in the semiconductor layer 30, using the layer 29 as a seed or nucleus, thereby improving the crystallinity of the semiconductor layer 30. In particular, using a material with a low thermal expansion coefficient for the insulating layer 20 can promote crystal growth. For example, crystal grains are formed in the semiconductor layer 30 overlapping the layer 29, and the lateral growth of these crystal grains can cause the semiconductor layer 30 to grow along the groove 91. That is, as shown in FIGS. 13A and 13B , the layer 29 acts as a seed or nucleus, causing the crystals to grow laterally, resulting in the expansion of region 31c. Region 31c has higher crystallinity than region 31a. As the treatment time progresses, region 31c further expands along the surface to be formed ( FIGS. 13C and 13D ). Finally, upon completion of the first heat treatment, region 31c expands throughout the entire semiconductor layer 30 ( FIGS. 13E and 13F ). In this manner, the crystallinity of the semiconductor layer 30 can be improved. Indium oxide with improved crystallinity due to the lateral growth of crystals from crystal nuclei can be called Lateral Growth Indium Oxide (LGIO).

[0227] Furthermore, by using silicon oxide, which has a small thermal expansion coefficient, for the insulating layer 20, tensile stress is applied to the indium oxide from the bottom and sidewalls of the groove 91 when the temperature is lowered, and this can promote crystal growth of the semiconductor layer 30.

[0228] Subsequently, a second heat treatment is performed. The second heat treatment is preferably performed in an atmosphere containing nitrogen and oxygen (typically, a nitrogen:oxygen volume ratio of 4:1). The temperature of the second heat treatment is preferably higher than the temperature of the first heat treatment. For example, the temperature is preferably 300° C. or higher and 400° C. or lower, more preferably 300° C. or higher and 350° C. or lower. The time period of the second heat treatment is preferably 1 hour or higher and 4 hours or lower.

[0229] The gas used in the second heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the semiconductor layer 30 as much as possible.

[0230] The heat treatment used for the second heat treatment is not particularly limited, and for example, an electric furnace, an RTA apparatus, or the like can be used.

[0231] By performing the first heat treatment at a temperature lower than that of the second heat treatment, the generation of crystal nuclei can be suppressed, thereby promoting the enlargement of the crystal grain size. Since the first heat treatment is performed in a reducing atmosphere, the amount of oxygen vacancies in the semiconductor layer 30 increases. Therefore, by performing the second heat treatment, oxygen is supplied to the semiconductor layer 30, and the supplied oxygen can repair (null) the oxygen vacancies. Furthermore, by performing the first heat treatment at a temperature lower than that of the second heat treatment, impurities may remain in the semiconductor layer 30. Therefore, by performing the second heat treatment at a temperature higher than that of the first heat treatment, the impurity concentration in the semiconductor layer 30 can be reduced. Furthermore, the hydrogen concentration in the semiconductor layer 30 can be reduced. Furthermore, by performing the second heat treatment, the crystal grains in the semiconductor layer 30 can be made larger.

[0232] As described above, by performing the first heat treatment and the second heat treatment in this order, the crystal growth of the semiconductor layer 30 can be achieved, and the amount of oxygen vacancies and impurities in the semiconductor layer 30 can be reduced.

[0233] Note that microwave plasma treatment may be performed after the formation of the semiconductor layer 30. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30 can be reduced. Furthermore, a crystalline region of the semiconductor layer 30 may grow.

[0234] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0235] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the semiconductor layer 30 can be reduced. Examples of impurities include carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on the semiconductor layer 30 in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the semiconductor layer 30 in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may enhance the crystallinity of the semiconductor layer 30.

[0236] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0237] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0238] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. The oxygen flow rate ratio (O ２ / (O ２ If the oxygen flow rate ratio (O + Ar) is too high, the discharge becomes unstable. ２ / (O ２ +Ar)) is preferably greater than 0% and less than or equal to 50%, more preferably greater than 0% and less than or equal to 40%, and even more preferably greater than 0% and less than or equal to 30%.

[0239] In microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋ ) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２+Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0240] The shorter the processing time of the microwave plasma treatment, the higher the productivity. Therefore, for example, the processing time of the microwave plasma treatment is preferably from 1 minute to 60 minutes, more preferably from 1 minute to 30 minutes, and even more preferably from 1 minute to 10 minutes.

[0241] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. Ｏ The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0242] Furthermore, a reaction occurs between part of oxygen present in the oxide semiconductor before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0243] Note that after the microwave plasma treatment, a heat treatment may be performed consecutively without exposure to the open air. The temperature of the heat treatment is, for example, preferably 100° C. to 750° C., more preferably 300° C. to 500° C., and even more preferably 400° C. to 450° C. By setting the temperature within the above range, deformation (distortion or warpage) of the substrate can be significantly reduced even when the heat treatment is performed.

[0244] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0245] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0246] Note that before the insulating layer 50 is formed, treatment for supplying hydrogen to the semiconductor layer 30 (also referred to as hydrogenation treatment) may be performed. By supplying hydrogen to the semiconductor layer 30, dangling bonds present at crystal grain boundaries or the like may be terminated, thereby improving the electrical characteristics and reliability of the transistor in some cases. Note that examples of the treatment for supplying hydrogen include heat treatment and plasma treatment in an atmosphere containing hydrogen.

[0247] Subsequently, an insulating layer 50 is formed to cover the semiconductor layer 30. The insulating layer 50 is preferably formed using an ALD method. A second precursor and a second oxidizing agent can be used to form the insulating layer 50. The second precursor preferably contains one of aluminum and hafnium. In this case, an aluminum oxide film or a hafnium oxide film is formed as the insulating layer 50. In other words, an oxide film containing a single element other than oxygen is formed. Note that when the second precursor contains one of aluminum and hafnium, a thermal ALD method can be used as the ALD method.

[0248] Examples of precursors that can be used include aluminum chloride and trimethylaluminum, and examples of precursors that can be used include hafnium tetrachloride and tetrakis(ethylmethylamido)hafnium (TEMAHf).

[0249] The second oxidizing agent can be any of the materials that can be used for the first oxidizing agent described above. Note that the first oxidizing agent and the second oxidizing agent may be the same oxidizing agent or different oxidizing agents.

[0250] In the ALD process, a precursor is introduced into a chamber and adsorbed onto the substrate surface. The adsorption of the precursor onto the substrate surface activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor onto the precursor layer on the substrate. The appropriate substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the precursor's temperature characteristics, vapor pressure, decomposition temperature, and other factors. In other words, the ALD window varies depending on the precursor. Therefore, when depositing an oxide film containing multiple elements other than oxygen, it is necessary to adjust the film formation conditions taking into account the ALD window of each precursor. On the other hand, when depositing an oxide film containing a single element other than oxygen, such as an indium oxide film or an aluminum oxide film, the film formation conditions can be adjusted by considering only the ALD window of one precursor, which facilitates the adjustment of the film formation conditions and allows for the formation of a high-quality oxide film.

[0251] It is preferable to perform microwave plasma treatment after the formation of the insulating layer 50. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30 can be reduced. For details of the microwave plasma treatment, refer to the above description.

[0252] Subsequently, a conductive layer 60 is formed on the insulating layer 50 so as to fill at least a part of the groove 91. In this manner, the semiconductor device shown in FIGS.

[0253] 1A to 1D, the layer 29 and the semiconductor layer 30 in the vicinity of the layer 29 are left without being removed. This allows the number of manufacturing steps of the semiconductor device to be reduced. However, the present invention is not limited to this. For example, the layer 29 and the semiconductor layer 30 in the vicinity of the layer 29 may be removed. This allows the semiconductor device shown in FIGS. 14A to 14C to be manufactured.

[0254] 9E and 9F, the semiconductor device shown in Fig. 14D and 14E can be manufactured. Specifically, the semiconductor layer 30 is formed on the structure shown in Fig. 9E and 9F, the semiconductor layer 30, the layer 29, and the layer 40 are processed into desired shapes, a first heat treatment and a second heat treatment are performed in this order, and the insulating layer 50 and the conductive layer 60 are formed in this order, thereby manufacturing the semiconductor device shown in Fig. 14D and 14E.

[0255] Furthermore, as shown in FIGS. 10A, 10B, and 10C, by burying the layer 29 in the insulating layer 20, it is not necessary to remove the layer 29, and the number of steps required to manufacture the semiconductor device can be reduced.

[0256] 6B and 6C , a semiconductor device can be fabricated by forming a layer 29, which is a crystalline portion, on the insulating layer 20 having a curved upper end portion in the groove 91, then forming a semiconductor layer 30 containing a metal oxide so as to cover the groove portion, and performing a heat treatment to cause crystal growth of the semiconductor layer 30. In this case, the curved upper end portion of the insulating layer 20 preferably has a portion with a radius of curvature of 1 nm or more and 500 nm or less. Furthermore, the curved upper end portion preferably has a portion with a radius of curvature greater than the thickness of the semiconductor layer 30.

[0257] When the semiconductor layer 30 is formed by the ALD method, the layer 29 may be used as a seed or nucleus to form a highly crystalline semiconductor layer 30 during the process of forming the semiconductor layer 30. For example, by setting the substrate heating temperature during film formation by the ALD method to a range of 150°C to 300°C, a highly crystalline semiconductor layer 30 can be formed during film formation. In this case, it is not necessary to perform a heat treatment for crystal growth of the semiconductor layer 30. Note that if the substrate heating temperature is too high, crystal nuclei may be formed, which may hinder the formation of large crystal grains. On the other hand, if the substrate heating temperature is too low, crystal growth may not occur during the process of forming the semiconductor layer 30.

[0258] In addition, even when a semiconductor layer 30 with high crystallinity can be formed in the process of forming the semiconductor layer 30, at least one of the first heat treatment, the second heat treatment, the microwave plasma treatment, and the hydrogenation treatment described above can be performed. This may further increase the crystallinity of the semiconductor layer 30.

[0259] Furthermore, if a semiconductor layer 30 with high crystallinity can be formed in the process of forming the semiconductor layer 30, the semiconductor layer 30 can be processed into a desired shape after a layer is formed on the semiconductor layer 30.

[0260] By using the method for forming a metal oxide layer according to one embodiment of the present invention, a large-area semiconductor layer 30 can be formed. This enables mass production of transistors using the semiconductor layer 30 and semiconductor chips using the same with high yield. A method for manufacturing a semiconductor chip 81 will be described below with reference to FIGS.

[0261] FIG. 15A shows a schematic perspective view of a substrate 80. As shown in FIG. 15A, a layer 29 is formed near the outer periphery of the substrate 80, and then a semiconductor layer 30 is formed over the entire surface of the substrate 80 to cover the layer 29. As a result, as shown in FIG. 15B, crystal growth proceeds using the layer 29 as a seed crystal, and a single-crystal or polycrystalline semiconductor layer 30 with a uniform crystal orientation can be formed over the entire surface of the substrate 80. More specifically, when the crystal orientation of the layer 29 is <001>, a semiconductor layer 30 can be formed that includes crystals whose crystal orientation <111> is perpendicular to the top surface of the substrate 80. In FIG. 15B, a scribe line 85 is indicated by a dashed line. The layer 29 is preferably provided in a position that overlaps the scribe line 85.

[0262] A silicon wafer can typically be used as the substrate 80. Other examples include insulating substrates such as glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (yttria-stabilized zirconia substrates), and semiconductor substrates such as germanium substrates, silicon carbide substrates, silicon germanium substrates, gallium arsenide substrates, indium phosphide substrates, zinc oxide substrates, and gallium oxide substrates. The substrate 80 may have a diameter of, for example, 3 inches, 5 inches, 8 inches, or 12 inches. Even when a large substrate such as a 12-inch substrate is used, a semiconductor layer 30 with good crystallinity can be obtained, thereby improving productivity.

[0263] Thereafter, transistors having semiconductor layer 30, wiring, electrodes, and the like are formed, thereby forming a plurality of semiconductor chips 81. Subsequently, as shown in Fig. 15D, substrate 80 on which semiconductor chips 81 have been formed is divided along scribe lines 85, thereby separating the plurality of semiconductor chips 81. At this time, by arranging layer 29 in a position overlapping scribe lines 85, it is possible to configure layer 29 so that it does not remain in semiconductor chip 81.

[0264] The layer 29 may be provided outside the scribe line 85. The number of layers 29 is not limited to one, and two or more layers 29 may be provided. For example, a plurality of layers 29 may be provided at equal intervals, and each of the plurality of layers 29 may be arranged to overlap the scribe line 85.

[0265] 15C shows a schematic cross-sectional view of the semiconductor layer 30 shown in FIG. 15B at the stage after formation. Layer 29 is provided at a position overlapping with scribe line 85, and semiconductor layer 30 is formed to cover layer 29. Semiconductor layer 30 is formed along the side and bottom surfaces of groove 91 provided in insulating layer 20. Semiconductor layer 30 is also provided to cover structure 83 formed on insulating layer 20. In this way, even when semiconductor layer 30 is provided to cover the uneven shape on substrate 80, it can be a single-crystal or polycrystalline film with a uniform crystal orientation as described above.

[0266] Examples of the structure 83 include a wiring, an electrode, or a convex portion of the insulating layer 20. The structure 83 may also be a component of a transistor having a different configuration from the transistor provided in the groove portion 91. The following describes the configuration of a transistor applicable to the structure 83.

[0267] 16 is a schematic cross-sectional view of a transistor 400. The transistor 400 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 400 has a pair of gates with a semiconductor in which a channel is formed sandwiched therebetween.

[0268] The transistor 400 is provided over an insulating layer 412. The insulating layer 412 corresponds to the insulating layer 20 described above.

[0269] Insulating films such as an insulating layer 414, an insulating layer 416, an insulating layer 420, an insulating layer 422, an insulating layer 440, an insulating layer 444, an insulating layer 441, an insulating layer 442, an insulating layer 446, and an insulating layer 448 are stacked over the insulating layer 412. The insulating layer 412, the insulating layer 416, the insulating layer 440, the insulating layer 441, the insulating layer 446, and the insulating layer 448 function as interlayer insulating films. Furthermore, for the insulating layer 414, the insulating layer 420, the insulating layer 422, the insulating layer 444, the insulating layer 442, and the like, it is preferable to use an insulating film having a barrier property that prevents diffusion of hydrogen, impurities, and the like.

[0270] The transistor 400 includes a conductive layer 405 arranged to be embedded in the insulating layer 414 and the insulating layer 416, an insulating layer 420 and an insulating layer 422 on the insulating layer 416 and the conductive layer 405, an insulating layer 424 on the insulating layer 422, a semiconductor layer 401 on the insulating layer 424, a pair of conductive layers 404 provided on the semiconductor layer 401, an insulating layer 440 located on the conductive layer 404 and having a groove reaching the semiconductor layer 401, and an insulating layer 403 and a conductive layer 402 provided to be embedded in the insulating layer 440.

[0271] The semiconductor layer 30 can be applied to the semiconductor layer 401 .

[0272] One of the pair of conductive layers 404 functions as a source electrode and the other functions as a drain electrode. The conductive layer 402 functions as a first gate electrode, and the insulating layer 403 functions as a first gate insulating layer. The conductive layer 405 functions as a second gate electrode, and the insulating layers 420, 422, and 424 function as a second gate insulating layer.

[0273] The insulating layer 424 and the insulating layer 403 in contact with the semiconductor layer 401 are preferably made of an oxide or oxynitride, such as silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide. Nitrogen-containing compounds, such as silicon nitride, silicon nitride oxide, and aluminum nitride, can also be used. It is also preferable to use a single layer or a stack of insulators containing a so-called high-dielectric-constant (high-k) material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become more miniaturized and highly integrated, thinning of the gate insulating film can sometimes cause problems such as leakage current. Therefore, using a high-k material as an insulator that functions as a gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0274] A stacked film in which a plurality of insulating films are stacked is preferably used as the insulating layer 403. For example, a stacked film in which two, three, or four or more layers of films made of the above insulating materials are stacked is preferably used.

[0275] The insulating layer 434 is provided to cover the conductive layer 404 and has a function of suppressing oxidation of the conductive layer 404. In this case, the insulating layer 434 is provided to cover the side surfaces of the semiconductor layer 401 and the insulating layer 424 and to be in contact with the insulating layer 422. The insulating layer 434 is preferably an insulating film having a barrier property that prevents diffusion of hydrogen, impurities, and the like.

[0276] A conductive layer 454 functioning as a wiring may be provided over the insulating layer 446. The conductive layer 454 and the conductive layer 404 are connected to each other through the conductive layer 436 and the conductive layer 438. The conductive layer 436 and the conductive layer 438 function as plugs. The conductive layer 436 is preferably formed using a conductive material with low oxygen permeability. In particular, the conductive layer 436 is preferably formed using a conductive material that is resistant to oxidation or a conductive material that maintains its conductivity even when oxidized. The conductive layer 438 is preferably formed using a conductive material with low resistance.

[0277] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0278] Second Embodiment In this embodiment, a semiconductor device to which the configuration described in the first embodiment is applied will be described.

[0279] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 17A to 28D.

[0280] 17A to 17C are schematic perspective views of a semiconductor device including a transistor 200A. FIG. 17B is a perspective view showing a cutaway portion of FIG. 17A. In FIGS. 17A and 17B, only the outlines of some components (such as interlayer insulating layers) are shown by dashed lines. FIG. 17C shows a perspective view cut along the plane indicated by the dashed-dotted line in FIG. 17A.

[0281] Fig. 18A is a plan view of a semiconductor device having a transistor 200A. Fig. 18B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 18A. Fig. 18C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 18A. Fig. 18D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 18B. Note that some elements are omitted in the plan view of Fig. 18A for clarity. Some elements may also be omitted in the subsequent plan views.

[0282] 18A to 18D includes an insulating layer 210 over a substrate (not shown), a transistor 200A over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The semiconductor device also includes an insulating layer 283 over the transistor 200A and an insulating layer 285 over the insulating layer 283. The semiconductor device also includes a conductive layer 243a, a conductive layer 243b, and a conductive layer 246.

[0283] The transistor 200A includes a conductive layer 220, conductive layers 240a and 240b on an insulating layer 280, a layer 229a on the conductive layer 240a, a layer 229b on the conductive layer 240b, a semiconductor layer 230 on the layers 229a and 229b, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the conductive layer 220.

[0284] The semiconductor layer 230, the insulating layer 280, the insulating layer 250, and the conductive layer 260 included in the transistor 200A correspond to the semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1, respectively. Therefore, the structures (material, film thickness, etc.), formation methods, and the like of the semiconductor layer 230, the insulating layer 280, the insulating layer 250, and the conductive layer 260 can be referred to the structures and formation methods, and the like of the semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60 described in Embodiment 1. Furthermore, the layer 229a and the layer 229b correspond to the layer 29 described in Embodiment 1. Therefore, the structures (material, film thickness, etc.), formation methods, and the like of the layer 229a and the layer 229b can be referred to the structure and formation method, and the like of the layer 29 described in Embodiment 1.

[0285] 18A to 18D , the insulating layer 280 has a groove 291 that reaches the conductive layer 220. The groove 291 extends in the X direction. The semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each arranged so that at least a portion thereof is located within the groove 291. The groove 291 corresponds to the groove 91 described in the first embodiment. Therefore, the configuration, formation method, etc. of the groove 291 can be determined by referring to the configuration, formation method, etc. of the groove 91 described in the first embodiment.

[0286] The semiconductor device shown in FIGS. 18A to 18D is a detailed configuration example of the semiconductor device shown in FIGS. 14D and 14E.

[0287] The semiconductor layer 230 is provided in an island shape. The semiconductor layer 230 is provided so as to follow part of the bottom and part of the sidewall of the groove 291. The semiconductor layer 230 has a portion in contact with the side surface of the conductive layer 240a on the groove 291 side, a portion in contact with the side surface of the conductive layer 240b on the groove 291 side, and a portion in contact with the bottom surface and side surface of the recess of the conductive layer 220 in the groove 291.

[0288] The insulating layer 250 is provided to cover the semiconductor layer 230. The insulating layer 250 is also provided on the insulating layer 280 to cover the top and side surfaces of the semiconductor layer 230 and the side surfaces of the conductive layer 240.

[0289] The conductive layer 260 is provided so as to fill at least a part of the groove 291. Therefore, the conductive layer 260 is provided so as to extend in the direction in which the groove 291 extends.

[0290] The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200A, and the conductive layer 240a and the conductive layer 240b function as the other electrode. The conductive layer 260 has a region that functions as a gate wiring.

[0291] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 200A. One of the region of the semiconductor layer 230 near the conductive layer 220, the region of the semiconductor layer 230 near the conductive layer 240b, and the region of the semiconductor layer 230 near the conductive layer 240b functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0292] The semiconductor layer 230 is provided inside the groove 291. The transistor 200A has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240a and the conductive layer 240b here) is located above, allowing current to flow vertically. That is, a channel is formed along the side surface of the groove 291. This allows the transistor 200A to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased. The transistor 200A can be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like because the channel length direction has a component in the height direction (vertical direction).

[0293] As shown in FIG. 18B , the conductive layer 220 has a recess that overlaps with the groove 291. Specifically, the recess is provided in the conductive layer 220 at a position that overlaps with the groove 291. By having the recess in the conductive layer 220, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 in the groove 291 can be lower than the height of the upper surface of the conductive layer 220 that contacts the insulating layer 280, compared to when the conductive layer 220 does not have the recess. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the upper surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the upper surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0294] The semiconductor layer 230 contacts the bottom and side surfaces of the recessed portion of the conductive layer 220. The conductive layer 220 has a recessed portion, which increases the area where the semiconductor layer 230 and the conductive layer 220 contact each other. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220 can be reduced.

[0295] The recess in the conductive layer 220 may have a curved portion, as shown in FIG. 18B . When the recess has a curved portion, the portions of the semiconductor layer 230, insulating layer 250, and the like provided on the recess near the recess may also have a curved portion. In other words, the portions may have a curved or concave surface in cross-sectional view. Furthermore, the portions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 250 near the recess, improves the dielectric strength of the transistor 200A, and suppresses electrostatic breakdown of the transistor 200A. Therefore, the reliability of the semiconductor device can be improved.

[0296] 18B shows a configuration in which the end of the conductive layer 240 and the end of the semiconductor layer 230 coincide or nearly coincide outside the groove 291. The conductive layer 240 and the semiconductor layer 230 can be fabricated by processing using the same mask. This is preferable because it reduces the number of masks required to fabricate a semiconductor device. However, the present invention is not limited to this. For example, a structure in which either the end of the semiconductor layer 230 or the end of the conductive layer 240 is located inside or outside the other in the X or Y direction may be used.

[0297] The width D1 of the groove 291 may vary in the depth direction. Here, the shortest distance between the conductive layer 240a and the conductive layer 240b in a cross-sectional view is used as the width D1. Alternatively, the shortest distance between the upper surface of the conductive layer 240a and the upper surface of the conductive layer 240b, the shortest distance between the lower surface of the conductive layer 240a and the lower surface of the conductive layer 240b, or the average of these two shortest distances may be used as the width D1. Here, an example is shown in which the width D1 of the groove 291 is determined using the shortest distance between the conductive layer 240a and the conductive layer 240b, but the method for determining the width D1 is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 facing the groove 291 may be used as the width D1. Alternatively, the width D1 may be the width of the groove 291 at the highest position in the insulating layer 280, the width of the groove 291 at the lowest position, the width of the groove 291 at the midpoint between these positions, or the average of these three widths.

[0298] The width D1 of the groove 291 is set by the film thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the groove 291. The width D1 of the groove 291 is, for example, preferably 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, still more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm.

[0299] In a plan view, the side surface of the conductive layer 260 provided in the groove 291 has a portion facing the side surface of the semiconductor layer 230 with the insulating layer 250 interposed therebetween. Therefore, the channel width of the transistor 200A is determined by the width D2 of the semiconductor layer 230 (see FIG. 18D ). The channel width of the transistor 200A can be calculated as "2×D2."

[0300] Increasing the width D2 of the semiconductor layer 230 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a plan view, is roughly determined by the width D1 of the groove 291 and the width D2 of the semiconductor layer 230. Reducing the width D1 of the groove 291 and the width D2 of the semiconductor layer 230 reduces the area occupied by the transistor 200A, thereby enabling a higher integration of the semiconductor device.

[0301] The channel length of the transistor 200A is the distance between the source region and the drain region. In other words, the channel length of the transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220. Therefore, the channel length of the transistor 200A does not affect the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a planar view. Note that the channel length can be considered as the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 240a or 240b contact each other in a cross-sectional view. In this case, the channel length corresponds to the length of the side surface of the insulating layer 280 on the groove portion 291 side in a cross-sectional view.

[0302] The channel length of the transistor 200A can be, for example, 500 nm or less, 300 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and can be 0.1 nm or more, 1 nm or more, or 5 nm or more. Typically, the channel length can be 1 nm or more and 300 nm or less, preferably 5 nm or more and 100 nm or less. This can improve productivity and yield in forming the insulating layer 280, forming the groove 291 in the insulating layer 280, and the like. Furthermore, the on-state current of the transistor 200A can be increased, thereby improving frequency characteristics.

[0303] FIG. 18B shows an example in which layers 229a and 229b remain. Note that the present invention is not limited to this. For example, as shown in FIGS. 19A to 19C , a layer functioning as a nucleus (corresponding to layer 29 in Embodiment 1) may be removed. FIG. 19A is a plan view of a semiconductor device including a transistor 200A. FIG. 19B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 19A . FIG. 19C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 19A . Note that FIG. 18D can be referred to for a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 19B .

[0304] For example, a layer functioning as a nucleus (corresponding to layer 29 in Embodiment 1) is formed on a conductive film that will become the conductive layers 240a and 240b, a groove 291 is formed in the layer, the conductive film, and the insulating layer 280, a semiconductor layer 230 is formed to cover the layer, and the first heat treatment and the second heat treatment described in Embodiment 1 are performed to enhance the crystallinity of the semiconductor layer 230. After that, the conductive film and the semiconductor layer 230 in the region overlapping with the layer and in the vicinity thereof are removed, thereby manufacturing the semiconductor device shown in FIGS. 19A to 19C . With this structure, the area where the semiconductor layer 230 contacts the conductive layer 240a or the conductive layer 240b can be increased. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 240a or the conductive layer 240b can be reduced.

[0305] 19A to 19C show a structure in which the conductive layer 240a and the conductive layer 240b are provided between the semiconductor layer 230 and the insulating layer 280. Note that the present invention is not limited to this. For example, as shown in FIGS. 20A to 20C , a structure in which the semiconductor layer 230 is in contact with the top surface of the insulating layer 280 outside the groove 291 may be used. FIG. 20A is a plan view of a semiconductor device including a transistor 200A. FIG. 20B is a cross-sectional view taken along dashed lines A1-A2 in FIG. 20A . FIG. 20C is a cross-sectional view taken along dashed lines A3-A4 in FIG. 20A . Note that FIG. 18D can be referred to for a cross-sectional view taken along dashed lines A5-A6 in FIG. 20B .

[0306] As shown in FIGS. 20A to 20C, by forming the semiconductor layer 230 on an insulating layer 280 that has a flat upper surface and is made of a material with a small thermal expansion coefficient, the crystallinity of the semiconductor layer 230 can be further improved.

[0307] Openings reaching the conductive layer 240a are provided in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, and a conductive layer 243a is provided in the openings. Openings reaching the conductive layer 240b are provided in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, and a conductive layer 243b is provided in the openings. The conductive layer 243a is in contact with the conductive layer 240a, and the conductive layer 243b is in contact with the conductive layer 240b.

[0308] The conductive layers 243a and 243b can be formed using the conductive materials described in the section "Conductive Layer" below. The conductive layers 243a and 243b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example. The conductive layers 243a and 243b may have a stacked structure.

[0309] For example, each of the conductive layers 243a and 243b can have a two-layer structure including a first conductive layer formed along the opening and a second conductive layer formed inside the first conductive layer. The first conductive layer can be formed using a conductive material that has a function of reducing hydrogen diffusion. This can prevent impurities such as water and hydrogen from being mixed into the semiconductor layer 230 through the second conductive layer. The second conductive layer can be formed using a conductive material that can be used for the conductive layers 243a and 243b.

[0310] The conductive layer 246 is provided on the insulating layer 285. The conductive layer 246 is connected to the conductive layer 240a via the conductive layer 243a and to the conductive layer 240b via the conductive layer 243b. The conductive layer 246 functions as the other of the source wiring and the drain wiring. The conductive layer 246 extends in the Y direction. That is, the direction in which the conductive layer 246 extends intersects with the direction in which the groove 291 extends. As shown in FIG. 18A , the transistor 200A is provided at the intersection of the conductive layer 260 extending in the X direction and the conductive layer 246 extending in the Y direction.

[0311] In the transistor 200A, the conductive layers 240a and 240b, which function as the other of the source electrode and the drain electrode, are connected to each other through the conductive layer 246. Therefore, the widths of the conductive layers 240a and 240b in the X direction can be reduced, thereby enabling miniaturization of the semiconductor device. For example, the widths of the conductive layers 240a and 240b in the X direction can be made smaller than the width D1 of the groove 291 (see FIG. 18D ).

[0312] 18A to 18C , the height of the top surface of the conductive layer 260 is lower than the height of the top surface of the insulating layer 250. With this structure, the area where the conductive layer 260 faces the conductive layer 240a or the conductive layer 240b can be reduced, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or the conductive layer 240b can be reduced. Furthermore, with the above structure, the physical distance between the conductive layer 260 and the conductive layer 246 can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 246 can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0313] 18B and other figures show an example in which the semiconductor layer 230 has a single-layer structure. The semiconductor layer 230 can have a stacked structure of two or more layers. For example, the semiconductor layer 230 can have a two-layer structure of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer correspond to the first semiconductor layer and the second semiconductor layer, respectively, described in Embodiment 1. Therefore, the structures (materials, film thicknesses, etc.), formation methods, etc. of the first semiconductor layer and the second semiconductor layer can be determined by referring to the structures, formation methods, etc. of the first semiconductor layer and the second semiconductor layer described in Embodiment 1.

[0314] Since the insulating layer 210 functions as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0315] The insulating layer 210 preferably has a barrier property against hydrogen. When the insulating layer 210 provided below the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200A to the semiconductor layer 230 can be suppressed.

[0316] The insulating layer 210 preferably has a function of capturing or fixing hydrogen. When the insulating layer 210 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 210 through the conductive layer 220 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0317] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0318] 18B shows an example in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0319] 18B shows an example in which the insulating layer 250 has a single layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0320] 21A to 21D are enlarged views of the insulating layer 250 and its vicinity, which are also enlarged views of the region P surrounded by the dashed line in FIG. 18B.

[0321] 21A shows an example in which the insulating layer 250 has a three-layer structure including an insulating layer 250_1, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2. In this case, the insulating layer 250_1 is in contact with the semiconductor layer 230.

[0322] The insulating layer 250_1 can be formed using any of the materials applicable to the insulating layer 50. For example, when the insulating layer 250_1 includes an insulating layer having a function of capturing or fixing oxygen, an excess amount of oxygen in the semiconductor layer 230 can be reduced. In addition, an insulating layer having a function of capturing or fixing oxygen may also have a function of capturing or fixing hydrogen, which may reduce the hydrogen concentration in the semiconductor layer 230. Therefore, a highly reliable transistor can be realized.

[0323] Furthermore, a high-k material can be used for the insulating layer 250_1. Note that an example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulating layer 250_1, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0324] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium for the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is preferably used because an amorphous film can be formed relatively easily using an ALD method. Aluminum oxide is suitable for the insulating layer 250_1 because it has the function of capturing or fixing oxygen and hydrogen. Alternatively, hafnium oxide is suitable for the insulating layer 250_1 because it has a high function of capturing or fixing oxygen and hydrogen.

[0325] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0326] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, as shown in FIG. 21B , the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. This structure allows hydrogen in the semiconductor layer 230 to diffuse into the insulating layer 250_1 through the insulating layer 250_2, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0327] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0328] 21C , a structure in which an insulating layer 250_4 is provided over the insulating layer 250_2 may be used. The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, by providing the insulating layer 250_4 having a function of capturing or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 or the like can be captured or fixed.

[0329] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With such a structure, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0330] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0331] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-described thickness in at least a portion thereof.

[0332] Note that the insulating layer 250 having a four-layer structure may not include the insulating layer 250_3 (see FIG. 21D ). For example, an insulating layer having a function of capturing or fixing oxygen may be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant may be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 250_4. Specifically, the insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0333] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are set to 2 nm, 2 nm, and 1 nm, respectively. This structure allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200A can be improved.

[0334] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 290 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0335] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0336] Although the insulating layer 250 has been described above as having a three-layer structure or a four-layer structure, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. By forming the insulating layer 250 using one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0337] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0338] As described above, by using silicon oxide, which has a small thermal expansion coefficient, for the insulating layer 280 provided before the formation of the semiconductor layer 230, it is possible to promote crystal growth of the semiconductor layer 30 formed inside the groove portion 291 of the insulating layer 280.

[0339] FIG. 18B shows an example in which the insulating layer 280 has a single-layer structure. Note that the insulating layer 280 can have a stacked structure of two or more layers. Another structural example of a semiconductor device including the transistor 200A is shown in FIGS. 22A to 22D. FIG. 22A is a plan view of a semiconductor device including the transistor 200A. FIG. 22B is a cross-sectional view taken along dash-dotted line A1-A2 in FIG. 22A. FIG. 22C is a cross-sectional view taken along dash-dotted line A3-A4 in FIG. 22A. FIG. 22D is a cross-sectional view taken along dash-dotted line A5-A6 in FIG. 22B.

[0340] As shown in FIG. 22B , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use the aforementioned material with a low dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3. This can prevent the conductive layer 220, the conductive layer 240a, and the conductive layer 240b from being oxidized and thus prevent high resistance. Furthermore, the formation of the groove 291 can expose at least a portion of the top surface of the conductive layer 220, while preventing a portion of the insulating layer 210 from being exposed and removed. Therefore, a highly reliable semiconductor device can be provided. Furthermore, the manufacturing yield of the semiconductor device can be increased, thereby providing a semiconductor device that can be manufactured at low cost.

[0341] For example, it is preferable to use silicon nitride or aluminum oxide for the insulating layer 280_1 and the insulating layer 280_3, and to use silicon oxide for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0342] The conductive layer 220, the conductive layer 240a, and the conductive layer 240b are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, because they are in contact with the semiconductor layer 230. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b.

[0343] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, the conductive layer 220, the conductive layer 240a, and the conductive layer 240b can maintain their conductivity even if they absorb oxygen. Furthermore, even when an insulator containing oxygen such as hafnium oxide is used for the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b.

[0344] 18B shows an example in which the conductive layer 220, the conductive layer 240a, and the conductive layer 240b each have a single-layer structure. Note that the conductive layer 220, the conductive layer 240a, and the conductive layer 240b can each have a stacked structure of two or more layers. Note that when the conductive layer 220, the conductive layer 240a, and the conductive layer 240b each have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230, the contact resistance between the conductive layer 220 and the semiconductor layer 230 and between the conductive layer 240a or the conductive layer 240b and the semiconductor layer 230 can be reduced.

[0345] 22B shows an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220_1, a conductive layer 220_2 on the conductive layer 220_1, and a conductive layer 220_3 on the conductive layer 220_2. In this case, for example, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220_1, a material with high conductivity as the conductive layer 220_2, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220_3. Specifically, it is preferable to use titanium nitride as the conductive layer 220_1, tungsten as the conductive layer 220_2, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) as the conductive layer 220_3. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the semiconductor layer 230. Furthermore, an oxide conductor is used for the layer closest to the channel formation region of the semiconductor layer 230. Compared to tungsten, an oxide conductor has lower contact resistance with the semiconductor layer 230; therefore, the current path between the source and drain can be shortened, and the on-state current of the transistor 200A can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 210. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as the conductive layer 220_2, the conductivity of the conductive layer 220 can be increased.

[0346] 22B shows an example in which the conductive layers 240a and 240b each have a two-layer structure including a first conductive layer and a second conductive layer on the first conductive layer. In this case, for example, it is preferable to use a conductive material containing oxygen for the second conductive layer and a material having higher conductivity than the second conductive layer for the first conductive layer. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the second conductive layer and tungsten for the first conductive layer. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the first conductive layer. Using an oxide conductor for the second conductive layer that is mainly in contact with the semiconductor layer 230 can reduce contact resistance with the semiconductor layer 230. Furthermore, using a material having higher conductivity than an oxide conductor for the layers that constitute the conductive layers 240a and 240b can increase the conductivity of the conductive layers 240a and 240b.

[0347] Note that a conductive material containing oxygen can be used for the first conductive layer, and a material having higher conductivity than the first conductive layer can be used for the second conductive layer. In this case, an oxide conductor is used for each of the conductive layers 240a and 240b, in a layer closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and drain can be shortened, and the on-state current of the transistor 200A can be increased.

[0348] FIG. 18B shows an example in which the conductive layer 260 has a single-layer structure. Note that the conductive layer 260 can have a stacked structure of two or more layers. The conductive layer 260 shown in FIG. 22B has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use titanium nitride as the conductive layer 260_1 and tungsten as the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride as the conductive layer 260_1 and copper as the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0349] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0350] 18B, an insulating layer 283 may be provided over the transistor 200A. Specifically, the insulating layer 283 may be provided over the conductive layer 260 and the insulating layer 250.

[0351] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200A to the semiconductor layer 230 can be suppressed.

[0352] In the groove 291, it is preferable that the side surface of the conductive layer 240a or the conductive layer 240b and the side surface of the insulating layer 280 coincide or substantially coincide. With this configuration, the groove 291 can be formed in the conductive layer 240a or the conductive layer 240b and the insulating layer 280 at the same time. Furthermore, the film thickness distribution of the semiconductor layer 230 and the like provided inside the groove 291 can be made uniform. Furthermore, it is possible to prevent the semiconductor layer 230 and the like from being divided by a step or the like between the conductive layer 240a or the conductive layer 240b and the insulating layer 280.

[0353] It should be noted that the present invention is not limited to the above configuration. For example, within the groove 291, the side surface of the conductive layer 240a or the conductive layer 240b and the side surface of the insulating layer 280 may be discontinuous. Furthermore, within the groove 291, the inclination of the side surface of the conductive layer 240a or the conductive layer 240b and the inclination of the side surface of the insulating layer 280 may differ from each other. In this case, part of the side wall of the groove 291 has a tapered shape.

[0354] 18A to 18D illustrate a configuration in which the extension direction of the groove 291 coincides with the extension direction of the conductive layer 260 functioning as the gate wiring, but the present invention is not limited to this. For example, the extension direction of the groove 291 may intersect with the extension direction of the gate wiring.

[0355] 23A to 25C , examples of transistor configurations that are partially different from the transistor 200A will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0356] [Transistor 200B] Fig. 23A is a plan view of a semiconductor device having transistor 200B. Fig. 23B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 23A. Fig. 23C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 23A. Fig. 23D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 23B.

[0357] 23A to 23D differ from the semiconductor device shown in Figures 18A to 18D mainly in that it has a conductive layer 265 and does not have an insulating layer 283, a conductive layer 243a, a conductive layer 243b, or a conductive layer 246. It also differs from the semiconductor device shown in Figures 18A to 18D mainly in that the conductive layer 260 is provided in an island shape and that the conductive layers 240a and 240b are provided in an extended manner.

[0358] The conductive layer 265 is provided on the insulating layer 285 and is in contact with the conductive layer 260. The conductive layer 265 is provided to extend in the Y direction. The conductive layers 240a and 240b are provided to extend in the X direction.

[0359] The conductive layer 260 is provided in an island shape. In a plan view, the outer periphery of the conductive layer 260 is located inside the outer periphery of the semiconductor layer 230. Note that in a plan view, the outer periphery of the conductive layer 260 may overlap with a part of the outer periphery of the semiconductor layer 230, or may be located outside the part of the outer periphery of the semiconductor layer 230.

[0360] In the YZ plane including the semiconductor layer 230, the end of the semiconductor layer 230 outside the groove portion 291 is located more inward than the end of the conductive layer 240 outside the groove portion 291 (see FIG. 23B ). Note that in the YZ plane including the semiconductor layer 230, the end of the semiconductor layer 230 outside the groove portion 291 may coincide or approximately coincide with the end of the conductive layer 240 outside the groove portion 291, or may be located more outward than the end of the conductive layer 240 outside the groove portion 291.

[0361] The insulating layer 285 is provided on the insulating layer 250. The insulating layer 285 is also provided so as to fill in the portion of the groove 291 where the conductive layer 260 is not located.

[0362] 23A to 23D , the physical distance between the conductive layer 260 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or 240b can be reduced. Furthermore, the physical distance between the conductive layer 265 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240a or 240b can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0363] 23A to 23D illustrate a configuration in which the conductive layer 260 has a region facing the side surface of the conductive layer 240a across the semiconductor layer 230 and a region facing the side surface of the conductive layer 240b across the semiconductor layer 230, but the present invention is not limited to this. For example, a first conductive layer facing the side surface of the conductive layer 240a across the semiconductor layer 230 and a second conductive layer facing the side surface of the conductive layer 240b across the semiconductor layer 230 may be provided.

[0364] [Transistor 200Ca and Transistor 200Cb] Fig. 24A is a plan view of a semiconductor device including transistor 200Ca and transistor 200Cb. Fig. 24B is a cross-sectional view taken along dashed dotted lines A1-A2 in Fig. 24A. Fig. 24C is a cross-sectional view taken along dashed dotted lines A5-A6 in Fig. 24B.

[0365] The semiconductor device shown in Figures 24A to 24C differs from the semiconductor device shown in Figures 23A to 23C in that the conductive layer 220, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each separated in and near the groove portion 291.

[0366] The transistor 200Ca includes a conductive layer 220a, a conductive layer 240a on the insulating layer 280, a semiconductor layer 230a, an insulating layer 250a on the semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. The transistor 200Cb includes a conductive layer 220b, a conductive layer 240b on the insulating layer 280, a semiconductor layer 230b, an insulating layer 250b on the semiconductor layer 230b, and a conductive layer 260b on the insulating layer 250b.

[0367] In the transistor 200Ca, the semiconductor layer 230a functions as a semiconductor layer, the conductive layer 260a functions as a gate electrode, the insulating layer 250a functions as a gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and drain electrode. In the transistor 200Cb, the semiconductor layer 230b functions as a semiconductor layer, the conductive layer 260b functions as a gate electrode, the insulating layer 250b functions as a gate insulating layer, the conductive layer 220b functions as one of a source electrode and a drain electrode, and the conductive layer 240b functions as the other of the source electrode and drain electrode.

[0368] By providing the transistor 200Ca in contact with one sidewall of the groove 291 and the transistor 200Cb in contact with the other sidewall, miniaturization and high integration of semiconductor devices can be promoted.

[0369] Although FIGS. 24A to 24C illustrate a configuration in which the insulating layer 250 is separated into insulating layers 250a and 250b, the present invention is not limited to this.

[0370] 25A to 25C will be used to describe modifications of the two transistors described using FIGS. 24A to 24C. Fig. 25A is a plan view of a semiconductor device having two transistors. Fig. 25B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 25A. Fig. 25C is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 25A.

[0371] 25A to 25C differ from the semiconductor device shown in FIGS. 24A to 24C in that an insulating layer 250 covers the semiconductor layer 230a and the semiconductor layer 230b. By covering the semiconductor layer 230a and the semiconductor layer 230b with the insulating layer 250, the side surface of the semiconductor layer 230a on the groove 291 side and the side surface of the semiconductor layer 230b on the groove 291 side can be covered. This makes it possible to suppress the diffusion of hydrogen into the semiconductor layer 230a and the semiconductor layer 230b. This makes it possible to realize a highly reliable transistor.

[0372] Although the transistors 200A to 200Cb each have a configuration in which at least some of the components of the transistor are provided in the extending groove 291, the present invention is not limited to this. At least some of the components of the transistor can be provided in an opening that is circular in plan view.

[0373] [Transistor 200D] Fig. 26A is a plan view of a semiconductor device having transistor 200D. Fig. 26B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 26A. Fig. 26C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 26A. Fig. 26D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 26B.

[0374] 26A to 26D differ from the semiconductor device shown in Figures 18A to 18D in that the semiconductor device does not include the conductive layer 243a, the conductive layer 243b, and the conductive layer 246. The transistor 200D shown in Figures 26A to 26D differs from the transistor 200A shown in Figures 18A to 18D in that some of the components are provided in the opening 290 instead of the groove 291. The transistor 200D also differs from the transistor 200A shown in Figures 18A to 18D in that the transistor 200D includes a conductive layer 240 having a region extending in the Y direction instead of the conductive layer 240a and the conductive layer 240b.

[0375] The conductive layer 220 serves as one of a source electrode and a drain electrode of the transistor 200D, and the conductive layer 240 serves as the other of the source electrode and the drain electrode of the transistor 200D.

[0376] As shown in FIGS. 26B and 26C, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0377] The openings 290 include an opening in the insulating layer 280 and an opening in the conductive layer 240. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the top surface shape of the openings 290 is circular, the openings in each layer may or may not be concentric.

[0378] Each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is arranged so that at least a portion thereof is located within the opening 290. Furthermore, the portions of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are arranged within the opening 290 are provided so as to reflect the shape of the opening 290.

[0379] The semiconductor layer 230 is provided so as to cover the bottom and sidewalls of the opening 290. The semiconductor layer 230 also has a recess that reflects the shape of the opening 290. The semiconductor layer 230 has a portion that contacts the upper surface of the conductive layer 240 and a portion that contacts the upper surface of the conductive layer 220 within the opening 290.

[0380] The insulating layer 250 is provided so as to cover the semiconductor layer 230. Moreover, the insulating layer 250 is provided on the insulating layer 280 so as to cover the top surface and side surfaces of the semiconductor layer 230 and the side surfaces of the conductive layer 240. Moreover, the insulating layer 250 has a recess that reflects the shape of the recess that the semiconductor layer 230 has.

[0381] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region in the opening 290 that overlaps with the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0382] 26D , by forming the opening 290 so as to have a circular shape in a plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 provided at the center of the opening 290 faces the side surface of the semiconductor layer 230 via the insulating layer 250. In other words, in a plan view, the entire periphery of the semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200D is determined by the outer periphery length of the semiconductor layer 230. In other words, it can be said that the channel width of the transistor 200D is determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view).

[0383] Furthermore, by arranging the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 concentrically, the distance between the conductive layer 260 and the semiconductor layer 230 becomes approximately uniform, so that a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0384] In this embodiment, an example in which the opening 290 is circular in plan view is shown. By making the opening circular, the processing accuracy when forming the opening can be improved, and openings of a fine size can be formed. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circle such as an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners.

[0385] [Transistor 200E] Fig. 27A is a plan view of a semiconductor device having transistor 200E. Fig. 27B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 27A. Fig. 27C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 27A. Note that Fig. 26D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 27B.

[0386] The semiconductor device shown in FIGS. 27A to 27C differs from the semiconductor device shown in FIGS. 26A to 26D in that it includes a conductive layer 265, an insulating layer 284, and an insulating layer 285.

[0387] In the transistor 200E, the stacked structure from the conductive layer 220 to the insulating layer 250 is similar to that of the transistor 200D described above, and therefore detailed description thereof will be omitted.

[0388] 27B and 27C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with opening 270 that reaches insulating layer 250 at a position overlapping opening 290.

[0389] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 is provided on the insulating layer 250 and contacts the insulating layer 250 within the opening 270. The conductive layer 260 has a portion that faces the semiconductor layer 230 with the insulating layer 250 interposed therebetween within the opening 290, and a portion that is located within the opening 270.

[0390] 27B and 27C show an example in which both the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 290. Note that when the width of the opening 290 and the width of the opening 270 are small, only the conductive layer 260_1 may be provided in the opening 290, and the conductive layer 260_1 and the conductive layer 260_2 may be provided in the opening 270. Alternatively, only the conductive layer 260_1 may be provided in the opening 270.

[0391] The conductive layer 265 is provided over the conductive layer 260 and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other. The conductive layer 265 may be considered a component of the transistor 200E. The height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same.

[0392] The conductive layer 265 functions as a gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0393] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layers 284 and 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0394] The transistor 200E has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0395] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0396] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0397] The insulating layer 284 preferably has a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230 can be suppressed, and further, hydrogen contained in the semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. The insulating layer 284 can be made of aluminum oxide, hafnium oxide, hafnium zirconium oxide, hafnium silicate, or the like.

[0398] The insulating layer 284 can also be a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the insulating layer 284 into the semiconductor layer 230. Silicon nitride and silicon nitride oxide are suitable for the insulating layer 284 because they are less permeable to oxygen and hydrogen, respectively.

[0399] When the insulating layer 284 includes a silicon nitride film, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0400] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may have a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0401] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0402] [Transistor 200F] Fig. 28A is a plan view of a semiconductor device having a transistor 200F. Fig. 28B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 28A. Fig. 28C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 28A. Fig. 28D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 28B.

[0403] The semiconductor device shown in FIGS. 28A to 28D differs from the semiconductor device shown in FIGS. 26A to 26D mainly in that it has an insulating layer 225, a conductive layer 255, and an insulating layer 281.

[0404] 28B , the conductive layer 255 is located on the insulating layer 280, and the insulating layer 281 is located on the conductive layer 255 and the insulating layer 280. In addition, the conductive layer 240 is located on the insulating layer 281. An opening 290 reaching the conductive layer 220 is provided in the insulating layer 280, the conductive layer 255, the insulating layer 281, and the conductive layer 240. The insulating layer 225 is located between the insulating layer 280 and the semiconductor layer 230.

[0405] As shown in FIG. 28B and other figures, the conductive layer 220 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. Furthermore, the side surface of the second recess coincides or nearly coincides with the side surface of the insulating layer 280 in the opening 290, and the side surface of the first recess coincides or nearly coincides with the surface of the insulating layer 225 facing the semiconductor layer 230. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0406] 28B etc., insulating layer 225 contacts the bottom surface and side surfaces of the second recessed portion of conductive layer 220, and also contacts the side surfaces of insulating layer 280 and conductive layer 240 within opening 290. Semiconductor layer 230 contacts the bottom surface and side surfaces of the first recessed portion of conductive layer 220, insulating layer 225, and the top surface of conductive layer 240. Insulating layer 250 is located inside semiconductor layer 230 within opening 290, and conductive layer 260 is located inside insulating layer 250 within opening 290.

[0407] The transistor 200F may have a structure in which the insulating layer 225 does not cover at least a part of the side surface of the conductive layer 240. In this case, the side surface of the conductive layer 240 that is not covered with the insulating layer 225 is in contact with the semiconductor layer 230. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced.

[0408] 28A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers. For example, the insulating layer 225 can have a two-layer structure of a first insulating layer and a second insulating layer. The first insulating layer contacts the side surface of the insulating layer 280 in the opening 290, and the second insulating layer is located between the first insulating layer and the semiconductor layer 230.

[0409] The first insulating layer can be made of an insulating material described in the "Insulating Layer" section below, and the second insulating layer can be made of a material applicable to the insulating layer 20 described above. For example, the first insulating layer can be made of a barrier insulating layer against hydrogen, and the second insulating layer can be made of an insulating layer having a region containing excess oxygen. With such a structure, oxygen vacancies and / or hydrogen in the semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced. For example, it is preferable to use silicon nitride as the first insulating layer and silicon oxide or silicon oxynitride as the second insulating layer.

[0410] The semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 225 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200F.

[0411] In the transistor 200F, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 255 functions as a second gate electrode, and the insulating layer 225 functions as a second gate insulating layer.

[0412] In the transistor 200F, one of the conductive layer 255 and the conductive layer 260 can be used as a gate electrode, and the other can be used as a back gate electrode. The transistor 200F may have a particularly preferable structure in which the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. By using the conductive layer 260, which has a wider region facing the semiconductor layer 230 than the conductive layer 255, as the gate electrode, a gate electric field can be applied to the semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. Note that when the conductive layer 260 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer, and the insulating layer 225 functions as a back gate insulating layer.

[0413] Since the transistor 200F includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200F can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0414] The conductive layer 255 can be made of a conductive material that can be used for the conductive layer 260 .

[0415] The insulating layer 281 functions as an interlayer film. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0416] FIG. 28B shows an example in which the insulating layer 281 has a single-layer structure. The insulating layer 281 can have a stacked structure of two or more layers. For example, the insulating layer 281 can have a three-layer structure including a first insulating layer, a second insulating layer on the first insulating layer, and a third insulating layer on the second insulating layer. In this case, it is preferable to use a material with a low dielectric constant as described above for the second insulating layer, and to use barrier insulating layers against oxygen as the first insulating layer and the third insulating layer. This can prevent the conductive layer 255 and the conductive layer 240 from being oxidized and thus prevent high resistance.

[0417] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0418] [Oxide Semiconductor Layer] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, the description in <Structure of Semiconductor Device> can be referred to.

[0419] The carrier concentration in the channel formation region is 1×10 １９ cm −３ Less than 1 x 10 １８ cm −３ Less than 5 x 10 １７ cm −３ Less than 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm−３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −７ cm −３ It can be said that:

[0420] As described above, in an OS transistor, oxygen vacancies (V Ｏ The presence of impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0421] When nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of a transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5 × 10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0422] Furthermore, when an alkali metal or alkaline earth metal is contained in an oxide semiconductor, defect levels are formed, which may cause unstable electrical characteristics of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0423] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0424] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 225, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 284, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0425] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0426] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0427] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0428] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0429] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0430] Furthermore, examples of materials that can have ferroelectricity include metal nitrides containing at least one of element M1 and element M2 and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Note that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0431] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0432] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0433] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0434] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0435] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0436] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0437] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0438] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0439] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. For an insulating layer in which a region containing excess oxygen is easily formed, the description in <Structure of Semiconductor Device> can be referred to.

[0440] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0441] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0442] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0443] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0444] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0445] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0446] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0447] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0448] [Conductive Layer] For the conductive layers (conductive layer 220, conductive layer 240, conductive layer 240a, conductive layer 240b, conductive layer 243a, conductive layer 243b, conductive layer 246, conductive layer 255, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0449] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0450] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0451] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0452] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0453] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0454] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0455] 29A to 35 . The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes at least a transistor. For example, the memory cell includes a transistor and a capacitor.

[0456] <Configuration Example 1 of Memory Device> The configuration of a memory device having memory cells will be described using Figures 29A to 29C. Figure 29A is a plan view of a memory device having memory cells 150. Figure 29B is a cross-sectional view taken along dashed line A1-A2 in Figure 29A. Figure 29C is a cross-sectional view taken along dashed line A3-A4 in Figure 29A.

[0457] 29A to 29C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, and an insulating layer 280. The insulating layer 140 and the insulating layer 180 function as interlayer films. The conductive layer 110 functions as wiring.

[0458] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0459] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 220_1 over the insulating layer 130. The conductive layer 220_1 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. That is, the capacitor 100 forms a metal-insulator-metal (MIM) capacitor. Note that the conductive layer 220_2 provided over the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitor 100.

[0460] As shown in FIGS. 29B and 29C , an opening 190 reaching the conductive layer 110 is provided in the insulating layer 180. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulating layer 180. At least a portion of the insulating layer 130 is disposed so as to be located in the opening 190. At least a portion of the conductive layer 220_1 is disposed so as to be located in the opening 190. Note that, as shown in FIGS. 29B and 29C , the conductive layer 220_1 is preferably provided so as to fill the opening 190. Note that the films provided inside the opening 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are preferably formed by an ALD method.

[0461] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0462] 29B and 29C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110 and the opening 190 is circular in plan view. With such a configuration, miniaturization or high integration of the memory device can be achieved.

[0463] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. In addition, a conductive layer 220_1 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor 100 having such a configuration may be called a trench capacitor.

[0464] The conductive layer 110 functions as wiring CAL, which will be described later, and can be provided, for example, in a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, the Y direction, or the Z direction).

[0465] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in [Conductive Layer] in Embodiment 2. For example, a conductive material with high conductivity, such as tungsten, can be used for the conductive layer 110. By using a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, allowing the conductive layer 110 to function sufficiently as a wiring CAL.

[0466] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, and is used in a single layer or a stacked layer. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress oxidation of the conductive layer 115. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress oxidation of the conductive layer 115.

[0467] The insulating layer 130 is provided so as to be in contact with the top surface and side surfaces of the conductive layer 115. That is, the insulating layer 130 preferably has a structure that covers the side end portions of the conductive layer 110. This can prevent a short circuit between the conductive layer 115 and the conductive layer 220_1.

[0468] Furthermore, a structure may be adopted in which the side edges of the insulating layer 130 and the conductive layer 115 coincide or substantially coincide with each other. With such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, which can simplify the manufacturing process of the memory device.

[0469] It is preferable to use a high-k material for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 100 can be sufficiently ensured.

[0470] The insulating layer 130 is preferably formed by stacking insulating layers made of a high-k material, and preferably by stacking a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0471] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, see the description in the second embodiment.

[0472] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nanometers, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0473] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0474] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0475] The conductive layer 220_1 is provided in contact with a part of the upper surface of the insulating layer 130. The side end of the conductive layer 220_1 is preferably located inside the side end of the conductive layer 115 in both the X direction and the Y direction. Note that in a structure in which the insulating layer 130 covers the side end of the conductive layer 115, the side end of the conductive layer 220_1 may be located outside the side end of the conductive layer 115.

[0476] Since the insulating layer 180 functions as an interlayer film, it is preferable that the dielectric constant is low. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0477] 29B and 29C, the insulating layer 180 is shown as a single layer, but the present invention is not limited to this. The insulating layer 180 may have a laminated structure of two or more layers.

[0478] 30A is a diagram showing an example in which the conductive layer 115 has a region 101 with rounded corners within the recess of the conductive layer 110. This makes it possible to suppress electric field concentration in the insulating layer 130 near the region 101, compared to when the region 101 has a corner (right angle or acute angle) in a cross-sectional view. Furthermore, the end 103 of the conductive layer 115 is located at a position lower in height from the reference plane than the top surface of the insulating layer 180. This makes it possible to suppress electric field concentration in the insulating layer 130 near the end 103, compared to when the end 103 is located on the insulating layer 180. As described above, suppressing electric field concentration in the insulating layer 130 suppresses dielectric breakdown of the insulating layer 130, and a highly reliable memory device can be provided.

[0479] 30B is a diagram showing an example in which end 103 shown in FIG. 30A is located on insulating layer 180. In the example shown in FIG. 30B, insulating layer 180 has a region 102 on the top surface and the side surface of opening 190 that has a curved portion. Also, in the example shown in FIG. 30B, end 103 has a tapered shape. By having region 102 have a curved portion and end 103 have a tapered shape, even when end 103 is located on insulating layer 180, electric field concentration in insulating layer 130 near region 102 and near end 103 can be suppressed. This suppresses dielectric breakdown of insulating layer 130, making it possible to provide a highly reliable memory device.

[0480] 30C is a diagram showing an example in which an insulating layer 187 is provided on the insulating layer 130 shown in FIG. 30B, for example, in a region of the insulating layer 130 that overlaps with the insulating layer 180. By providing the insulating layer 187, electric field concentration on the insulating layer 130 can be preferably suppressed in some cases.

[0481] Furthermore, an insulating layer 280 is disposed on the capacitor element 100. The insulating layer 280 has a portion located on the insulating layer 130 and a portion located on the conductive layer 220.

[0482] The transistor 200 can be described in detail in Embodiment 2 (transistor 200A shown in FIG. 18B ), and therefore detailed description thereof will be omitted. The transistor included in the memory cell 150 is not limited to the transistor 200A, and any of the transistors exemplified in Embodiment 2 can be applied. A transistor having a planar structure, a gate all around (GAA) structure, or a lateral gate all around (LGAA) structure can also be applied.

[0483] As shown in FIGS. 29A to 29C , the transistor 200 is provided so as to overlap with the capacitor 100. The groove 291, where part of the structure of the transistor 200 is provided, overlaps with the opening 190, where part of the structure of the capacitor 100 is provided. In particular, the conductive layer 220 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. This structure allows the transistor 200 and the capacitor 100 to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be densely arranged and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. FIGS. 29B and 29C show an example in which the width of the opening 190 is smaller than the width of the groove 291. The relationship between the width of the opening 190 and the width of the groove 291 is not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 is equal to or smaller than the width of the groove 291 .

[0484] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0485] 31A to 31C show a memory device in which the transistor 200E described in Embodiment 2 is used as the transistor 200 included in the memory cell 150. FIG. 31A is a plan view of the memory device including the memory cell 150. FIG. 31B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 31A. FIG. 31C is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 31A.

[0486] 31B and 31C , a structure may be used in which the side edges of the insulating layer 130 and the conductive layer 220 coincide or substantially coincide with each other. By using such a structure, the insulating layer 130 and the conductive layer 220 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.

[0487] 37A shows an example of a circuit diagram of the memory device described in this embodiment. As shown in FIG. 37A, the configurations shown in FIGS. 29A to 29C function as memory cells. The memory cell 951 includes a transistor M1 and a capacitor CA. Here, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 100.

[0488] One of the source and drain of the transistor M1 is connected to one of a pair of electrodes of the capacitor CA. The other of the source and drain of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor CA is connected to a wiring CAL.

[0489] Here, the wiring BIL corresponds to the conductive layer 246, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. As shown in FIGS. 29A to 29C , it is preferable that the conductive layer 260 is provided extending in the X direction, and the conductive layer 246 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided intersecting each other. Also, in FIG. 29C , the wiring CAL (conductive layer 110) is provided parallel to the wiring WOL (conductive layer 260). However, the present invention is not limited to this. The wiring CAL may be provided parallel to the wiring BIL (conductive layer 246), for example.

[0490] The memory cells will be described in detail in a later embodiment.

[0491] <Structure Example 2 of Memory Device> FIGS. 32A and 32B are cross-sectional views of a memory device including a transistor 200a and a transistor 200b.

[0492] 32A and 32B includes an insulating layer 140 over a substrate (not shown), a memory cell 150 over the insulating layer 140, an insulating layer 280a over the insulating layer 140, and an insulating layer 280b above the insulating layer 280a. The insulating layer 140, the insulating layer 280a, and the insulating layer 280b function as interlayer films.

[0493] The memory cell 150 includes a transistor 200a on the insulating layer 140 and a transistor 200b on the transistor 200a.

[0494] For the transistors 200a and 200b, the descriptions of the transistor 200D (see FIG. 26C ) and the transistor 200A (see FIG. 18B ) in Embodiment 2 can be referred to, and detailed descriptions thereof will be omitted. For example, for the configuration of the conductive layer 220a, the semiconductor layer 230a, and the like, the description of FIG. 26C can be referred to by replacing the conductive layer 220 with the conductive layer 220a and the semiconductor layer 230 with the semiconductor layer 230a. For example, for the configuration of the conductive layer 220b, the semiconductor layer 230b, and the like, the description of FIG. 18B can be referred to by replacing the conductive layer 220 with the conductive layer 220b and the semiconductor layer 230 with the semiconductor layer 230b.

[0495] The insulating layer 280a and the insulating layer 280b can have the same structure as that used for the insulating layer 280.

[0496] The transistors included in the memory cell 150 are not limited to the combination of the transistor 200a and the transistor 200b, and one or more of the transistors exemplified in Embodiment 2 can be used.

[0497] In the memory cell 150 shown in FIGS. 32A and 32B, capacitance generated between the conductive layer 220b and the conductive layer 240a can be used; therefore, data can be held without forming a separate capacitor.

[0498] The shortest distance from the top surface of the conductive layer 240a to the conductive layer 220b is preferably shorter than the shortest distance from the top surface of the conductive layer 246 to the gate wiring (conductive layer 260 in FIG. 32A ). This can increase the capacitance generated between the conductive layer 220b and the conductive layer 240a. Furthermore, the parasitic capacitance generated between the conductive layer 246 and the gate wiring can be reduced. For example, the structure of the transistor 200A described in Embodiment 2 can be applied to the transistor 200b.

[0499] As shown in FIGS. 32A and 32B , the transistor 200b is provided so as to overlap with the transistor 200a. The groove 291, in which part of the structure of the transistor 200b is provided, has a region overlapping with the opening 290, in which part of the structure of the transistor 200a is provided. In particular, the conductive layer 220b functions as one of the source electrode and drain electrode of the transistor 200b and as the gate electrode of the transistor 200a. Therefore, the transistors 200b and 200a share part of their structures. With this structure, the transistors 200b and 200a can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0500] 37E shows another example of a circuit diagram of the memory device described in this embodiment. As shown in FIG. 37E, the configuration shown in FIGS. 32A and 32B functions as a memory cell. The memory cell 955 includes a transistor M2 and a transistor M3. Here, the transistor M2 corresponds to the transistor 200b, and the transistor M3 corresponds to the transistor 200a.

[0501] One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M2 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring RBL. The other of the source and drain of transistor M3 is connected to wiring SL.

[0502] Here, the wiring WBL corresponds to the conductive layer 246, and the wiring WOL corresponds to the conductive layer 260. As shown in Figures 32A and 32B, it is preferable that the conductive layer 260 is provided extending in the X direction, and the conductive layer 246 is provided extending in the Y direction. With this configuration, the wiring WBL and the wiring WOL are provided so as to intersect with each other.

[0503] The transistor M2 may have a back gate, and similarly, the transistor M3 may have a back gate.

[0504] <Configuration Example 3 of Memory Device> The memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device. The transistor 200 is an OS transistor. Because the off-state current of the transistor 200 is low, the use of the transistor 200 in a memory device allows stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200 enable high-speed reading and writing of data from and to the memory device.

[0505] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix.

[0506] 33A is a plan view of a memory device, showing an example in which 2×2 memory cells (memory cells 150a to 150d) are arranged in the X and Y directions.

[0507] Fig. 33B is a cross-sectional view taken along dashed line A1-A2 in Fig. 33A. In Fig. 33A and Fig. 33B, two memory cells (memory cell 150a and memory cell 150b in Fig. 33B) are connected to a common wiring (conductive layer 246).

[0508] A circuit diagram corresponding to two memory cells is shown in Figure 37B. As shown in Figure 37B, the memory device 952 has two memory cells, one of which has a transistor M1 and a capacitor CA1, and the other of which has a transistor M2 and a capacitor CA2. For example, when comparing Figure 37B with Figure 33B, the transistor M1 corresponds to the transistor 200a, the capacitor CA1 corresponds to the capacitor 100a, the transistor M2 corresponds to the transistor 200b, and the capacitor CA2 corresponds to the capacitor 100b.

[0509] One of the source and drain of transistor M1 is connected to one of a pair of electrodes of capacitor CA1. The other of the source and drain of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL1. The other of the pair of electrodes of capacitor CA1 is connected to wiring CAL. One of the source and drain of transistor M2 is connected to one of a pair of electrodes of capacitor CA2. The other of the source and drain of transistor M2 is connected to wiring BIL. The gate of transistor M2 is connected to wiring WOL2. The other of the pair of electrodes of capacitor CA2 is connected to wiring CAL.

[0510] Here, the wiring BIL corresponds to the conductive layer 246 , the wiring WOL 1 corresponds to the conductive layer 260 , the wiring WOL 2 corresponds to another conductive layer 260 , and the wiring CAL corresponds to the conductive layer 110 .

[0511] Each of the memory cells 150a and 150b shown in Figures 33A and 33B has a configuration similar to that of the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. The memory cells 150c and 150d shown in Figure 33A also have a configuration similar to that of the memory cell 150. Therefore, in the memory device shown in Figures 33A and 33B, structures having the same functions as those of the structures constituting the memory device shown in Figures 29A to 29C are denoted by the same reference numerals. For details of the memory cells 150a to 150d, the description of the memory cell 150 in <Configuration Example 1 of Memory Device> can be referred to.

[0512] As shown in Figures 33A and 33B, a conductive layer 260 functioning as a wiring WOL is provided in each of the memory cells 150a and 150b. Also, as shown in Figure 33A, one conductive layer 260 is provided in common to the memory cells 150a and 150c, and another conductive layer 260 is provided in common to the memory cells 150b and 150d. Also, one conductive layer 246 functioning as a part of the wiring BIL is provided in common to the memory cells 150a and 150b. That is, the conductive layer 246 is connected to the semiconductor layer 230 of the memory cell 150a and the semiconductor layer 230 of the memory cell 150b. Also, the other conductive layer 246 is provided in common to the memory cells 150c and 150d.

[0513] The memory cell 150a and the memory cell 150b are configured in line symmetry with respect to the perpendicular bisector of the dashed-dotted line A1-A2. That is, the transistor 200a and the transistor 200b are also configured in line symmetry with respect to the perpendicular bisector of the dashed-dotted line A1-A2. The conductive layer 240b functions as the other of the source and drain electrodes of the transistor 200a and the transistor 200b. The transistors 200a and 200b share the conductive layer 240b. This configuration makes it possible to provide a memory device that can be miniaturized or highly integrated.

[0514] Note that the conductive layer 110 may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b.

[0515] 34 shows an example in which the four memory cells shown in FIG. 33A are stacked in n layers (n is an integer of 3 or more) in the Z direction. FIG. 34 is a cross-sectional view taken along dashed dotted line A1-A2 shown in FIG. 33A.

[0516] 34 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided on the topmost level. The number of memory cells in one memory layer 160 is not particularly limited, and one memory layer 160 may have two or more memory cells.

[0517] The conductive layers 245, 247, 248, etc. connect the memory cells included in the n-layer memory layer 160 to a sense amplifier (not shown) provided below the n-layer memory layer 160. The conductive layers 245 and 248 are each disposed in an opening formed in the insulating layer 140, the insulating layer 180, the insulating layer 130, the insulating layer 280, etc., and are in contact with the lower surface of the conductive layer 246. The conductive layer 247 is disposed in an opening formed in the insulating layer 140, the insulating layer 180, the insulating layer 130, the insulating layer 280, etc., and is in contact with the upper surface of the conductive layer 246. The conductive layers 245, 247, and 248 can be formed using a conductive material that can be used for the conductive layer 240, etc.

[0518] The conductive layers 245, 246, and 248 function as plugs or wirings for connecting a circuit element, wiring, electrode, or terminal such as a switch, a transistor, a capacitor, an inductor, a resistor, or a diode to the memory cell 150, plugs or wirings for connecting two or more memory cells 150, or plugs or wirings for connecting the memory device shown in FIG. 34 to a memory device located above or below it. For example, the conductive layer 245 can be connected to a sense amplifier (not shown) provided below the memory device shown in FIG. 34. In this case, the conductive layer 245 functions as part of the wiring BIL. By stacking the sense amplifier (not shown), the memory device, and the like in this manner, the memory capacity per unit area can be increased.

[0519] 31B and 31C may be applied as the memory cell shown in Fig. 34. By configuring the side edge of the insulating layer 130 to coincide with the side edge of the conductive layer 220, the insulating layer 130 does not overlap with the conductive layer 245. This makes it relatively easy to process the opening in which the conductive layer 245 is to be provided. Note that the same effect can be achieved when forming the opening in which the conductive layer 247 or the conductive layer 248 is to be provided.

[0520] 34, by stacking a plurality of memory cells, the cells can be integrated and arranged without increasing the area occupied by the memory cell array, that is, a 3D memory cell array can be configured.

[0521] FIG. 35 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0522] In FIG. 35, a memory cell 150 (a transistor 200 and a capacitor 100 ) is provided above a transistor 300 .

[0523] The transistor 300 is one of the transistors included in the sense amplifier.

[0524] For the memory cell 150 shown in FIG. 35, the description of the memory cell 150 in <Configuration example 1 of memory device> can be referred to.

[0525] 35, the bit lines can be shortened by providing a sense amplifier so as to overlap the memory cells 150. This reduces the bit line capacitance, enabling the memory device to be driven at high speed.

[0526] 35 can correspond to the semiconductor device 900 described in Embodiment 4. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0527] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0528] Alternatively, the substrate 311 may be a structure in which a single-crystal oxide semiconductor film (typically, an indium oxide film) is provided on a stabilized zirconia substrate. As described in Embodiment 1 and the like, an indium oxide film formed on a stabilized zirconia substrate has single crystallinity. By using a part of the indium oxide film as the semiconductor region 313, the field-effect mobility of the transistor 300 can be increased. Furthermore, the reliability of the transistor 300 can be improved.

[0529] Here, in the transistor 300 shown in FIG. 35 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0530] Note that the transistor 300 illustrated in FIG. 35 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0531] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0532] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0533] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0534] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 35, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0535] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a semiconductor device or a memory device.

[0536] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 240 can be used. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0537] The conductive layer 240 of the transistor 200 is connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0538] The conductive layer 643 is embedded in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the insulating layer 280. The conductive layer 642 is provided over the insulating layer 130 and embedded in the insulating layer 280. The conductive layer 642 can be formed using the same material and in the same process as the conductive layer 220. The conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130. The conductive layer 645 is embedded in the insulating layer 180. The conductive layer 645 can be formed using the same material and in the same process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 648. The transistor 300 and the conductive layer 110 are insulated by the insulating layer 648.

[0539] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0540] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0541] Fig. 36 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 36 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 36 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0542] The memory cell 950 can be any of the memory devices described in Embodiment 3 (such as the memory cell 150 ).

[0543] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0544] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0545] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0546] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0547] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0548] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0549] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0550] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0551] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 36, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0552] 37A to 37G, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0553] 37A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0554] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0555] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0556] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0557] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0558] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 951 does not need to include the capacitor CA and the wiring CAL, and the first terminal of the transistor M1 may be in an electrically floating state.

[0559] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951.

[0560] Also, as shown in FIG. 37B, one wiring BIL can be provided in common for two or more DRAM memory cells.

[0561] 37C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0562] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0563] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0564] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0565] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0566] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 37D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0567] 37E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 37F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0568] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0569] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0570] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0571] 37G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitative element CC.

[0572] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0573] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0574] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0575] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0576] Note that at least the transistor M4 is preferably an OS transistor.

[0577] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0578] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 38A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 38B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0579] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0580] 39 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 39 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0581] The arithmetic device 960 shown in FIG. 39 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0582] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0583] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0584] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0585] The arithmetic device 960 shown in FIG. 39 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 39 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0586] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0587] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0588] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0589] In the arithmetic unit 960 shown in FIG. 39 , a register controller 967 selects a holding operation in a register 966 in accordance with an instruction from an ALU 962. That is, it selects whether data is to be held by a flip-flop or by a capacitor in the memory cell of the register 966. If holding data by a flip-flop is selected, a power supply potential is supplied to the memory cell in the register 966. If holding data in a capacitor is selected, data is rewritten to the capacitor,...

Claims

a first step of forming a crystalline portion; a second step of forming a metal oxide layer having an amorphous structure on the crystalline portion; a third step of performing a heat treatment to cause crystal growth of the metal oxide layer using the crystal portions as nuclei, The method for producing a metal oxide layer, wherein the metal oxide layer contains indium. 　 In claim 1, In the first step, the crystal portion is formed on a layer having a groove portion; In the second step, the metal oxide layer is formed so as to cover the groove portion; In the third step, the metal oxide layer is grown as a crystal along the groove portion. 　 a first step of forming a crystalline portion; a second step of forming a single-crystal metal oxide layer on the crystal portion using the crystal portion as a seed crystal, the metal oxide layer contains indium; In the first step, a groove is provided, and the crystal portion is formed on a layer having a curved surface at an upper end of the groove; In the second step, the metal oxide layer is formed so as to cover the groove portion. 　 a first step of forming a crystalline portion; a second step of forming a metal oxide layer having an amorphous structure on the crystalline portion; a third step of performing a heat treatment to cause crystal growth of the metal oxide layer using the crystal portions as nuclei, the metal oxide layer contains indium; In the first step, a groove is provided, and the crystal portion is formed on a layer having a curved surface at an upper end of the groove; In the second step, the metal oxide layer is formed so as to cover the groove portion; In the third step, the metal oxide layer is grown as a crystal along the groove portion. 　 In claim 3, In the second step, the metal oxide layer is formed under conditions where the substrate temperature is 100° C. or higher and 300° C. or lower. 　 In claim 3, In the second step, the metal oxide layer is formed under conditions where the substrate temperature is 150° C. or higher and 250° C. or lower. 　 In claim 3 or claim 4, The method for producing a metal oxide layer, wherein the curved surface has a portion with a radius of curvature of 1 nm or more and 500 nm or less. 　 In claim 3 or claim 4, The method for producing a metal oxide layer, wherein the curved surface has a portion where the radius of curvature is larger than the thickness of the metal oxide layer.

5. The method for producing a metal oxide layer according to claim 3 or claim 4, wherein the layer contains an insulating material.

5. The method for producing a metal oxide layer according to claim 3 or claim 4, wherein the layer contains a conductive material.

5. The method for producing a metal oxide layer according to claim 3, wherein the layer has a curved surface at the bottom of the groove. 　 In any one of claims 1, 3, and 4, The metal oxide layer is formed by a sputtering method, A method for producing a metal oxide layer, using a gas containing hydrogen as a sputtering gas. 　 In claim 1 or claim 4, The heat treatment includes a first heat treatment and a second heat treatment, in this order; The method for forming a metal oxide layer, wherein the second heat treatment is performed at a temperature higher than the temperature of the first heat treatment. 　 In claim 13, The method for forming a metal oxide layer, wherein the first heat treatment is performed in an atmosphere containing hydrogen and nitrogen. 　 In claim 13, The method for forming a metal oxide layer further comprises: performing the second heat treatment to reduce a hydrogen concentration in the metal oxide layer. 　 In claim 1 or claim 4, The metal oxide layer after the heat treatment has crystal grains in portions overlapping with the crystal portions. 　 In claim 16, The method for producing a metal oxide layer, wherein the crystal grains have a crystal orientation of <111>. 　 In claim 17, The method for producing a metal oxide layer, wherein the crystal orientation of the crystal portion is <001>. 　 In claim 18, the crystal portion contains indium, gallium, and zinc; the crystalline portion has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound. 　 In claim 16, The method for producing a metal oxide layer, wherein the crystalline portion contains indium oxide.

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