Display device

Abstract

The present invention addresses the problem of providing a high-definition display device.　A display device according to the present invention has a transistor (100), a first insulating layer (110), and a liquid crystal element. The transistor (100) has a semiconductor layer (108), a first conductive layer (112a), and a second conductive layer (112b). The liquid crystal element has a second conductive layer (112b), a liquid crystal, and a third conductive layer. The first insulating layer (110) is located on the first conductive layer (112a). The second conductive layer (112b) is located on the first insulating layer (110). The first insulating layer (110) and the second conductive layer (112b) have an opening (141) that reaches the first conductive layer (112a). The semiconductor layer (108) has a region in contact with the upper surface of the first conductive layer (112a), lateral surfaces of the first insulating layer (110), and the upper surface and lateral surfaces of the second conductive layer (112b). The semiconductor layer (108) has crystalline indium oxide. The concentrations of aluminum, gallium, and zinc in the semiconductor layer (108) are each 1×1020 atoms / cm3 or less. The second conductive layer (112b) has a region overlapping the third conductive layer with the liquid crystal therebetween.

Description

display device

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a display device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, there has been a demand for high-definition display devices. Devices requiring high-definition display devices, such as devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), have been actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also referred to as light-emitting devices). Examples of light-emitting elements include organic electroluminescence (EL) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using organic EL elements.

[0006] Technologies related to transistors using semiconductor thin films have been attracting attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention.

[0007] Examples of oxide semiconductors that can be used in transistors include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin film transistor using hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization.

[0008] International Publication No. 2016 / 038508

[0009] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Research and Development Agency, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO” FUNDAMENTALS (USA), Wiley-SID Series in Display Technology, 2017, p. 194-198W. R. Thurber et al. , “The relationship between resistivity and dopant density for phosphorus-and boron-doped silicon”, NBS Special Publication 400-64, 1981, p. 7-17

[0010] An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a manufacturing method of the above-described transistor, semiconductor device, or display device. Another object is to provide a highly productive manufacturing method of a transistor, semiconductor device, or display device. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a display device including a transistor, a first insulating layer, and a liquid crystal element. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The liquid crystal element includes a second conductive layer, liquid crystal, and a third conductive layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have openings that reach the first conductive layer. The semiconductor layer has a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The semiconductor layer includes crystalline indium oxide. The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ The second conductive layer has a region overlapping with the third conductive layer with the liquid crystal interposed therebetween.

[0013] One embodiment of the present invention is a display device including a transistor, a first insulating layer, and a light-emitting element. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have openings that reach the first conductive layer. The semiconductor layer includes a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The semiconductor layer includes crystalline indium oxide. The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ The second conductive layer is connected to the light emitting element.

[0014] One embodiment of the present invention is a display device including a driver circuit unit. The driver circuit unit includes a transistor and a first insulating layer. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have openings that reach the first conductive layer. The semiconductor layer has a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The semiconductor layer includes crystalline indium oxide. The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ The following is the result.

[0015] In the display device, the semiconductor layer preferably has crystal grains, and the crystal grains preferably have a grain size of 0.3 μm or more.

[0016] The display device described above preferably includes a second insulating layer. The second insulating layer preferably has a region in contact with the lower surface of the first conductive layer. The first insulating layer preferably includes a third insulating layer and a fourth insulating layer on the third insulating layer. The second insulating layer preferably includes silicon, nitrogen, and hydrogen. The third insulating layer preferably includes silicon and nitrogen. The fourth insulating layer preferably includes silicon and oxygen. The second insulating layer preferably includes a region having a higher hydrogen content than the third insulating layer.

[0017] In the display device described above, the first insulating layer preferably includes a fifth insulating layer on the fourth insulating layer, and the fifth insulating layer preferably includes silicon and nitrogen.

[0018] In the display device described above, the first insulating layer preferably includes a fifth insulating layer on the fourth insulating layer, and the fifth insulating layer preferably includes aluminum and oxygen.

[0019] In the display device described above, the first conductive layer and the second conductive layer preferably contain indium and oxygen, respectively.

[0020] One embodiment of the present invention is a display device including a transistor and a light-emitting element. The transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a first insulating layer. The first insulating layer is located over the first conductive layer. The semiconductor layer has a region overlapping with the first conductive layer with the first insulating layer interposed therebetween. The second conductive layer and the third conductive layer are each connected to the semiconductor layer. The semiconductor layer includes crystalline indium oxide. The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ The second conductive layer is connected to the light emitting element.

[0021] In the display device, the semiconductor layer preferably has crystal grains, and the crystal grains preferably have a grain size of 0.3 μm or more.

[0022] In the display device described above, the first insulating layer preferably includes a second insulating layer and a third insulating layer on the second insulating layer. The second insulating layer preferably includes silicon and nitrogen. The third insulating layer preferably includes silicon and oxygen.

[0023] The display device preferably includes a fourth insulating layer. The fourth insulating layer preferably has a region between the second conductive layer and the third conductive layer that overlaps with the first conductive layer via the semiconductor layer and the first insulating layer. The fourth insulating layer preferably contains silicon and oxygen.

[0024] One embodiment of the present invention is a display device including a transistor and a light-emitting element. The transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a first insulating layer. The first insulating layer is located over the semiconductor layer. The first conductive layer has a region overlapping with the semiconductor layer with the first insulating layer interposed therebetween. The second conductive layer and the third conductive layer are each connected to the semiconductor layer. The semiconductor layer includes crystalline indium oxide. The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ The second conductive layer is connected to the light emitting element.

[0025] In the display device, the semiconductor layer preferably has crystal grains, and the crystal grains preferably have a grain size of 0.3 μm or more.

[0026] In the display device described above, the semiconductor layer preferably includes a first region overlapping with the first conductive layer and a pair of second regions sandwiching the first region. The second region preferably includes a second element. The concentration of the second element in the second region is preferably higher than the concentration of the second element in the first region. The second element is preferably one or more of hydrogen, boron, and phosphorus.

[0027] In the above-described display device, it is preferable that the second conductive layer and the third conductive layer each have a portion in contact with the second region.

[0028] According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a manufacturing method for the above-described transistor, semiconductor device, or display device can be provided. Alternatively, a highly productive manufacturing method for a transistor, semiconductor device, or display device can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0030] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating carrier concentration dependence of hole mobility. FIG. 3C is a cross-sectional view illustrating an indium oxide film. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIG. 5A is a top view showing an example of a semiconductor device. FIG. 5B is a cross-sectional view showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are equivalent circuit diagrams of semiconductor devices. FIG. 7C is a top view showing an example of a semiconductor device. FIG. 8 is a cross-sectional view showing an example of a semiconductor device. FIG. 9 is a perspective view showing an example of a semiconductor device. FIGS. 10A to 10D are perspective views showing an example of a semiconductor device. FIG. 11A is a top view showing an example of a semiconductor device. FIGS. 11B and 11C are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a top view showing an example of a semiconductor device. 13B and 13C are cross-sectional views showing an example of a semiconductor device. FIG. 14A is a top view showing an example of a semiconductor device. FIGS. 14B and 14C are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a top view showing an example of a semiconductor device. FIGS. 15B and 15C are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a top view showing an example of a semiconductor device. FIGS. 16B and 16C are cross-sectional views showing an example of a semiconductor device. FIG. 17A is a top view showing an example of a semiconductor device. FIGS. 17B and 17C are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a top view showing an example of a semiconductor device. FIGS. 18B to 18D are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a top view showing an example of a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing an example of a semiconductor device. FIGS. 20A and 20B are cross-sectional views showing an example of a semiconductor device. FIG. 21A is a top view showing an example of a semiconductor device. FIGS. 21B and 21C are cross-sectional views showing an example of a semiconductor device. 22A and 22B are cross-sectional views showing an example of a semiconductor device, and Fig. 23A is a top view showing an example of a semiconductor device.FIG. 23B is a cross-sectional view showing an example of a semiconductor device. FIG. 24A is a top view showing an example of a semiconductor device. FIG. 24B is a cross-sectional view showing an example of a semiconductor device. FIGS. 25A to 25E are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 26A to 26D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 27A to 27C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 28A is a perspective view showing an example of a display device. FIG. 28B is a block diagram showing an example of a display device. FIGS. 29A to 29E are circuit diagrams of pixel circuits. FIGS. 30A and 30B are circuit diagrams of pixel circuits. FIGS. 31A and 31B are circuit diagrams of pixel circuits. FIG. 32 is a block diagram showing a structural example of a semiconductor device. FIG. 33 is a block diagram showing a structural example of a semiconductor device. FIG. 34A is a block diagram showing a structural example of a semiconductor device. FIG. 34B is a circuit diagram showing a structural example of a semiconductor device. FIG. 35 is a circuit diagram showing a structural example of a semiconductor device. FIG. 36 is a circuit diagram showing a structural example of a semiconductor device. 37A and 37B are circuit diagrams showing an example of the configuration of a semiconductor device. FIGS. 38A and 38B are circuit diagrams showing an example of the configuration of a semiconductor device. FIG. 39 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 40 is a circuit diagram showing an example of the configuration of a semiconductor device. FIGS. 41A and 41B are cross-sectional views showing an example of a display device. FIG. 42 is a cross-sectional view showing an example of a display device. FIG. 43 is a cross-sectional view showing an example of a display device. FIG. 44 is a cross-sectional view showing an example of a display device. FIG. 45 is a cross-sectional view showing an example of a display device. FIGS. 46A to 46C are cross-sectional views showing an example of a display device. FIGS. 47A and 47B are cross-sectional views showing an example of a display device. FIG. 48 is a cross-sectional view showing an example of a display device. FIG. 49 is a cross-sectional view showing an example of a display device. FIG. 50 is a cross-sectional view showing an example of a display device. FIG. 51 is a cross-sectional view showing an example of a display device. FIGS. 52A to 52D are diagrams showing an example of an electronic device. FIGS. 53A to 53F are diagrams showing an example of an electronic device. FIGS. 54A to 54G are diagrams showing an example of an electronic device. 55A to 55D are inverse pole figure orientation maps obtained by EBSD measurement of an indium oxide film.56A to 56C are crystal grain maps obtained by EBSD measurement of an indium oxide film. 56D to 56F are histograms of crystal grain size obtained by EBSD measurement of an indium oxide film. 57 is an SEM image and an inverse pole figure orientation map obtained by EBSD measurement of an indium oxide film. 58 is a diagram showing the results of XRD measurement of an indium oxide film. 59A to 59D are cross-sectional TEM images of an indium oxide film. 60A to 60D are cross-sectional TEM images of an indium oxide film. 61A to 61D are cross-sectional TEM images of an indium oxide film. 62A to 62C are depth profiles obtained by SIMS analysis of an indium oxide film. 63A to 63C are depth profiles obtained by SIMS analysis of an indium oxide film. 64A to 64C are depth profiles obtained by SIMS analysis of an indium oxide film. 65A to 65C are depth profiles obtained by SIMS analysis of an indium oxide film. FIGS. 66A to 66D are graphs showing the relationship between the heating temperature of an indium oxide film and the element concentration in the indium oxide film. FIG. 67A is a graph showing the relationship between the heating temperature and the carrier concentration of an indium oxide film. FIG. 67B is a graph showing the relationship between the heating temperature and the Hall effect mobility of an indium oxide film. FIG. 68A is a graph showing the relationship between the carrier concentration and the Hall effect mobility of an indium oxide film. FIG. 68B is a graph showing the relationship between the carrier concentration and the Hall effect mobility of an indium gallium zinc oxide film. FIG. 68C is a graph showing the relationship between the carrier concentration and the Hall effect mobility of a phosphorus-doped silicon film. FIGS. 69A and 69B are STEM images and EDX mapping images of an indium oxide film. FIG. 70 is a graph showing the Id-Vg characteristics of a transistor according to an example. FIGS. 71A to 71D are graphs showing the reliability of a transistor according to an example. FIG. 72 is a graph showing the Id-Vg characteristics of a transistor according to an example. Fig. 73 is a diagram showing Id-Vd characteristics of a transistor according to an example. Fig. 74 is a diagram showing Id-Vg characteristics of a transistor according to an example. Fig. 75 is a diagram showing sheet resistance of an indium oxide film according to an example. Fig. 76 is an SEM image and an STEM image of an indium oxide film according to an example.FIG. 77 is a diagram showing Id-Vg characteristics of a transistor according to an example. FIG. 78 is a diagram showing Id-Vg characteristics of a transistor according to an example. FIG. 79 is a diagram showing electrical characteristics of a transistor according to an example. FIG. 80A is an optical microscope image of a pixel circuit according to an example. FIG. 80B is a photograph of the display state of an OLED panel according to an example. FIGS. 81A and 81B are diagrams showing XRD measurement results according to an example. FIG. 82 is a cross-sectional view of a sample according to an example. FIG. 83 is a diagram showing Id-Vg characteristics of a transistor according to an example. FIG. 84 is a diagram showing Id-Vg characteristics of a transistor according to an example. FIGS. 85A and 85B are diagrams showing Id-Vg characteristics of a transistor according to an example. FIG. 86 is a diagram showing the reliability of a transistor according to an example. FIGS. 87A and 87B are diagrams showing Id-Vg characteristics of a transistor according to an example. FIG. 88 is a circuit diagram of a pixel circuit according to an example. FIGS. 89A and 89B are photographs of the display state of an OLED panel according to an example.

[0031] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0032] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0033] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0034] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between the components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0035] In this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m, n]" may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which an identification numeral is added, or when it is not necessary to distinguish between them, the elements may be described without the identification numeral.

[0036] The words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0037] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0038] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0039] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0040] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0041] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0042] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0043] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0044] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and the source (also referred to as gate voltage, Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0045] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0046] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0047] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0048] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0049] In this specification, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as a taper angle.

[0050] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0051] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer is physically separated from the adjacent metal oxide layer.

[0052] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0053] In this specification and the like, a structure in which light-emitting layers are separately formed for light-emitting elements (light-emitting devices) with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, thereby expanding the range of material and configuration options and facilitating improvements in brightness and reliability.

[0054] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0055] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element has a first electrode, an EL layer over the first electrode, and a second electrode over the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole blocking layer and an electron blocking layer). In this specification and the like, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0056] In this specification and the like, a light-receiving device (also referred to as a light-receiving element) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0057] In this specification and the like, flexibility refers to the property of an object being soft and bendable, i.e., the property of an object being able to deform in response to an external force applied to the object, regardless of whether or not the object has elasticity or the ability to return to its original shape before deformation.

[0058] For example, a flexible electronic device can deform in response to an external force. A flexible electronic device can be used while fixed in a deformed state, or can be used after repeatedly deforming. A flexible display device (also referred to as a flexible display device, flexible display device, flexible display, etc.) can deform in response to an external force. A flexible display device can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible battery (also referred to as a flexible battery, flexible battery, flexible battery, etc.) can deform in response to an external force. A flexible battery can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible substrate (also referred to as a flexible substrate, flexible substrate, etc.) can deform in response to an external force. A flexible substrate can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. Note that the above phrase "deform in response to an external force" refers to deformation by an average adult's hand without requiring excessive force. Flexibility can be evaluated using a testing machine capable of performing stress-strain measurements (such as a tensile testing machine or a compression testing machine). In stress-strain measurements, an external force is applied to an object, and the strain of the object caused by the resulting stress is measured, thereby making it possible to quantify the flexibility of the object.

[0059] In this specification, when an object is described as having flexibility, it means that at least a part of the object has flexibility. In other words, a flexible object may have an inflexible region (also called a hard region).

[0060] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first portion and a second portion of an object are deformed by the same external force, the region that deforms more can be said to be the region with higher flexibility.

[0061] 1 to 15. The semiconductor device of one embodiment of the present invention can be suitably used for, for example, one or both of a pixel circuit and a driver circuit of a display device.

[0062] <Configuration Example 1> [Configuration Example 1-1] FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view of the cut surface taken along dashed dotted line B1-B2. Note that FIG. 1A omits some of the components of the semiconductor device 10 (such as a gate insulating layer). As with FIG. 1A , some of the components are also omitted from the top views of the semiconductor device in subsequent drawings. FIGS. 2A to 2D show perspective views of the semiconductor device 10. FIG. 2B shows a cross-sectional view taken along dashed dotted line C1-C2 in FIG. 2A. In FIG. 2C, the insulating layer shown in FIG. 2A is transparent, and its outline is indicated by a dashed line. Similarly, in FIG. 2D, the insulating layer shown in FIG. 2B is transparent, and its outline is indicated by a dashed line.

[0063] The semiconductor device 10 includes a transistor 100 and an insulating layer 110. The semiconductor device 10 is provided on an insulating surface. FIG. 1B and other figures show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film.

[0064] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. In the semiconductor layer 108, a region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region. In the semiconductor layer 108, the channel formation region is located between the source region and the drain region.

[0065] The semiconductor layer 108 is preferably formed using a metal oxide (also referred to as an oxide semiconductor (OS)) that exhibits semiconductor characteristics. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0066] The semiconductor layer 108 preferably contains indium and oxygen. The semiconductor layer 108 preferably contains indium oxide. By using an oxide semiconductor with a high indium content for the semiconductor layer of a transistor, the transistor can have high field-effect mobility. Therefore, the transistor can have high on-state current.

[0067] Indium oxide is a semiconductor material having physical properties different from those of metal oxides such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0068] The carrier concentration dependence of the Hall mobility in indium oxide, silicon, and IGZO will be explained. Ｘ The carrier concentration dependence of the hole mobility in IGZO is shown in FIG. 3A. The carrier concentration dependence of the hole mobility in IGZO is shown in FIG. 3B.

[0069] As shown by the arrows in Figure 3B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 3A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that Figure 3A shows the characteristics assuming single-crystal indium oxide. Therefore, when indium oxide is non-single-crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 3A.

[0070] 3A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0071] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the electrical resistivity can be increased to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0072] In the indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. Examples of such elements include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties. The region where the carrier concentration of the indium oxide is in the range R2 preferably contains, for example, an element that is common to the source electrode and drain electrode of the transistor.

[0073] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 3A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived. By using this technical concept, it is possible to realize a transistor that has high field-effect mobility and on-current, low off-current, is normally off, and is highly reliable.

[0074] The semiconductor layer 108 preferably has crystallinity. Using a crystalline oxide semiconductor for the semiconductor layer 108 is preferable because it can suppress deterioration of transistor characteristics. The semiconductor layer 108 preferably has high crystallinity and is preferably polycrystalline or single crystalline.

[0075] When an indium oxide film is used as the semiconductor layer 108, the indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include a single crystal film, a polycrystalline film, and an amorphous film containing crystal grains (also referred to as a microcrystalline film). The indium oxide film used for the semiconductor layer 108 is preferably a polycrystalline film, and more preferably a single crystal film. Note that indium oxide having crystal grains therein may be referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO).

[0076] A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries, resulting in uneven distribution of impurities. The use of a single-crystal film is particularly preferable because it can suppress carrier scattering at grain boundaries and provide a transistor with high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics due to grain boundaries.

[0077] Compared with microcrystalline films and amorphous films, polycrystalline films can reduce carrier scattering, enabling a transistor with high field-effect mobility. When a polycrystalline film is used for the semiconductor layer 108, the grain size of the crystal grains (hereinafter also referred to as the crystal grain size) contained in the semiconductor layer 108 is preferably large. By using a polycrystalline film with large grain sizes, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, resulting in a transistor with high field-effect mobility. Furthermore, it is preferable that the number of crystal grain boundaries intersecting the direction of drain current flow (also referred to as the channel length direction) in the channel formation region be small. Note that in a transistor using a polycrystalline film of indium oxide, if the channel formation region does not have crystal grain boundaries or if no crystal grain boundaries are observed, the channel formation region is located within a single-crystal region included in the polycrystalline film, and therefore, the same effect as a transistor using a single-crystal film of indium oxide can be achieved.

[0078] The grain size of the crystal grains contained in the semiconductor layer 108 is preferably 0.3 μm or more, more preferably 0.4 μm or more, even more preferably 0.5 μm or more, even more preferably 0.6 μm or more, and even more preferably 0.7 μm or more. Since a large grain size of the crystal grains is preferred, no upper limit is particularly set for the grain size. Note that the grain size of the crystal grains contained in the semiconductor layer 108 is not limited to the above-mentioned range.

[0079] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0080] The grain size of the crystal grains contained in the semiconductor layer 108 can be analyzed by, for example, a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), or an electron backscatter diffraction pattern (EBSD or EBSP). Alternatively, the analysis can be performed by combining a plurality of these techniques. For example, the average value of the grain sizes of a plurality of crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be, for example, the diameter of a circle having the same area as the area of ​​the crystal grain. Note that this diameter is sometimes referred to as the circle equivalent diameter.

[0081] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a TEM image, if the crystal orientations of the two crystal grains are identical or nearly identical, the boundary may not be called a grain boundary. Furthermore, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same crystal grain.

[0082] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film.Furthermore, a semiconductor layer in which the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation within one crystal grain in the channel formation region can be called a single crystal film.

[0083] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). In addition, space group numbers in the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be assigned. Crystal planes and crystal directions are also expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal directions are expressed with a bar above the number. However, due to formatting restrictions, in this specification, instead of a bar above the number, a minus sign (-) may be placed before the number. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent directions with < >, individual planes indicating crystal planes with ( ), and collective planes with equivalent symmetry with {}. Even if the space group number is the same, the space group notation may differ depending on how the crystal axes are arranged.

[0084] The crystal structure of cubic indium oxide belongs to space group Ia-3 (space group number 206).

[0085] The grain size of the crystal grains can also be confirmed by, for example, an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating unevenness on the surface of the semiconductor layer 108 using an etchant whose etching rate varies depending on the crystal plane or crystallinity, the crystal grains can be easily observed even with an optical microscope or a scanning electron microscope (SEM). When an indium oxide film is used as the semiconductor layer 108, the crystal grains of the indium oxide can be easily observed by using an etchant containing an acid. As the acid, for example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used. Note that if the etching rate is too fast, part of the semiconductor layer 108 may be lost, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by adjusting the concentration, temperature, and treatment time of the etchant so that the semiconductor layer 108 is thinned without being lost (also referred to as half etching). By performing half etching, the crystal grains can be easily observed.

[0086] The impurity concentration in the channel formation region is preferably low. The channel formation region is preferably highly pure. In the channel formation region, impurities can be a scattering source of carriers, which can cause a decrease in field-effect mobility. Furthermore, impurities can also cause an inhibition of crystal growth of a metal oxide film (e.g., an indium oxide film).

[0087] When an indium oxide film is used as the semiconductor layer 108, elements contained in the impurities in the channel formation region (hereinafter also referred to as the first element) include gallium, zinc, boron, aluminum, and silicon. In the channel formation region, the concentration of each of the first elements is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Note that elements that can be contained in the indium oxide film include, for example, carbon and hydrogen. Carbon and hydrogen are elements that can be contained in a film-forming gas (e.g., a precursor) for the indium oxide film, and may be present in the indium oxide film in greater amounts than the first element. Note that ppm is an abbreviation for "parts per million," and 1 ppm is 1×10 −６ is.

[0088] The concentration of impurities in the semiconductor layer 108 can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectrometry (XPS), or electron spectrometry for chemical analysis (ESCA). When XPS analysis is used, the concentration distribution in the depth direction can be analyzed by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in regions with low impurity concentrations, it may be difficult to quantify the impurity concentration, or the impurities may be below the detection limit.

[0089] Note that the reliability of measured values ​​at the interface and its vicinity may be low due to the matrix effect. Measurement values ​​in regions with low reliability are not treated as the concentration of the first element in the semiconductor layer 108. Furthermore, in concentration analysis, the position of the interface between the semiconductor layer 108 and a layer in contact with the semiconductor layer 108 may be estimated from the intensity of the constituent elements of the semiconductor layer 108. When SIMS is used for analysis, JIS K0146 (ISO 14606) can be referenced for the position of the interface, and the position where the signal intensity of the constituent elements of a layer reaches 50% of the value in the layer can be defined as the interface. For example, the position where the signal intensity of the constituent elements of a metal oxide contained in the semiconductor layer 108 reaches 50% of the maximum value in the semiconductor layer 108 can be defined as the interface. In other words, the range where the intensity of the constituent elements of a metal oxide contained in the semiconductor layer 108 is 50% or more of the maximum value in the semiconductor layer 108 can be defined as the semiconductor layer 108. When indium oxide is used for the semiconductor layer 108 and SIMS is used to analyze the concentration of the first element, a range in which the secondary ion intensity of indium is 50% or more of the maximum value in the semiconductor layer 108 can be referred to as the semiconductor layer 108, and a range in which it is less than 50% of the maximum value can be referred to as a layer other than the semiconductor layer 108 (for example, the insulating layer 106). Alternatively, a range in which the secondary ion intensity of a cluster containing indium (for example, a cluster of indium and oxygen) is 50% or more of the maximum value in the semiconductor layer 108 can be referred to as the semiconductor layer 108, and a range in which it is less than 50% of the maximum value can be referred to as a layer other than the semiconductor layer 108 (for example, the insulating layer 106).

[0090] The concentration of each of the first elements in the channel formation region is 1×10 ２０ atoms / cm ３ Preferably, it is less than 5×10 １９ atoms / cm ３ Preferably, it is less than 3×10 １９ atoms / cm ３ Preferably, it is equal to or less than 1×10 １９ atoms / cm ３ Preferably, it is less than 3×10 １８ atoms / cm ３ Preferably, it is equal to or less than 1×10 １８ atoms / cm ３The following is preferred:

[0091] When the transistor is in the on state, the carrier concentration in the channel formation region is 1×10 １９ cm −３ In this case, to make a normally-off transistor, the carrier concentration in the off state must be 1×10 １９ cm −３ In addition, in the channel formation region, the carrier concentration generated by the first element is preferably 1×10 １９ cm −３ Here, assuming that carriers are generated from 10% of the atoms of the first element in the channel formation region, the concentration of the first element is set to 1×10 ２０ atoms / cm ３ By setting the carrier concentration generated by the first element to 1×10 or less, １９ cm −３ The calculated film density of indium oxide is 7.12 g / cm or less, which is preferable. ３ (See ICSD (Inorganic Crystal Structure Database) coll.code.14387.) The sum of the numbers of indium and oxygen atoms in indium oxide calculated from the film density, molecular weight, and Avogadro's constant is approximately 7.7 × 10 ２２ atoms / cm ３ For example, if the concentration of the first element is 1×10 ２０ atoms / cm ３ In this case, the concentration of the first element is approximately 0.13 atomic %, which can be set to 1 atomic % or less.

[0092] By using an indium oxide film with large crystal grains and a low impurity concentration for a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, even 100 cm ２ / (V·s) or more, and even 150 cm ２ / (V·s) or more, even 200 cm ２ / (V s) or more, and even 250 cm ２ / (V·s) or more.

[0093] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 3C, an indium oxide film (InO Ｘ Oxygen (O) diffusing through the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ When oxygen vacancies (V) exist, the diffusing oxygen atoms form oxygen vacancies (V Ｏ ) is compensated for. Since oxygen easily diffuses in the indium oxide film, there is less oxygen deficiency (V Ｏ ) can be easily compensated for.

[0094] Thus, the indium oxide film has fewer oxygen vacancies (V Ｏ ) can be easily reduced, so that by using an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0095] Here, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms. Therefore, by lowering the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability of the indium oxide film from decreasing. This increases the oxygen permeability of the indium oxide film, and oxygen vacancies (V) in the indium oxide film are reduced. Ｏ ) can be reduced. In particular, it is preferable that the concentrations of aluminum, gallium, and zinc in the channel formation region are low. For the concentrations of aluminum, gallium, and zinc in the channel formation region, see the description of the concentration of the first element above.

[0096] As shown in FIG. 3C, hydrogen diffuses through the indium oxide film. Hydrogen that diffuses from the outside into the indium oxide film permeates the indium oxide film and becomes hydrogen molecules (H ２) or, as mentioned above, reacts with the oxygen contained in the film and is released as water molecules.

[0097] A transistor using an indium oxide film is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in the transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current and field-effect mobility of the transistor can be increased.

[0098] Single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si) are shown in Table 1. As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide for a transistor, a transistor with a large on-current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with an extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher f characteristics and smaller off-state current than a transistor using silicon in a channel formation region (hereinafter also referred to as a Si transistor).

[0099]

[0100] For a layer in contact with at least a portion of a crystalline indium oxide film, a material containing crystals with a small difference in lattice constant with indium oxide (also called lattice mismatch) is preferably used. This allows the crystals contained in the layer to serve as seed crystals to enhance the crystallinity of the indium oxide film, and the layer can be called a seed crystal layer or a seed layer. Note that a substrate (e.g., a single-crystal substrate) can also be used as the seed layer.

[0101] One method for evaluating the degree of lattice mismatch is the lattice mismatch ratio. The lattice mismatch ratio Δa [%] of the crystals of the formed film (here, the indium oxide film) to the crystals of the seed layer is expressed as Δa=((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0102] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0103] Here, the crystal of indium oxide has a cubic crystal structure (bixbyite type) and a lattice constant of 1.0117 nm (see ICSD coll.code.14387). On the other hand, YSZ (Zr ０．９ Y ０．１ O １．９５) has a lattice constant of 0.51481 nm (see ICSD coll.code.248790). Therefore, the lattice mismatch of the indium oxide film crystal with the YSZ crystal is -1.74%. The lattice mismatch of the indium oxide crystal with the cubic crystal structure of YSZ (yttria-stabilized zirconia) is in the range of -2% to 2%, and an indium oxide single crystal film can be epitaxially grown on the YSZ substrate. Here, the yttrium content in the YSZ can be 2 atomic % to 15 atomic %, preferably 5 atomic % to 10 atomic %.

[0104] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0105] As described above, by using indium oxide for the semiconductor layer, a transistor with high on-state current can be obtained. Therefore, a semiconductor device that operates at high speed can be provided. When the semiconductor device of one embodiment of the present invention is applied to a display device, the display device can operate at high speed and have high display quality. Furthermore, a transistor using indium oxide for the semiconductor layer has high field-effect mobility, and thus can obtain a large on-state current even when the channel width is small. Therefore, the area occupied by the transistor can be reduced, and the area occupied by the semiconductor device can be reduced. When the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit (e.g., one or both of a gate line driver circuit and a source line driver circuit) of a display device, the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame.

[0106] A conductive layer 112a is provided on a substrate 102, an insulating layer 110 is provided on the conductive layer 112a, and a conductive layer 112b is provided on the insulating layer 110. The insulating layer 110 is in contact with the conductive layer 112a and the conductive layer 112b and has a region sandwiched between them. The conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141. The conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141. Note that in FIG. 1A and other drawings, the opening 141 in the insulating layer 110 and the opening 143 in the conductive layer 112b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 112b have openings that reach the conductive layer 112a.

[0107] The semiconductor layer 108 is provided to cover the openings 141 and 143. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a and the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 is in contact with not only the side surface but also the top surface of the conductive layer 112b, which increases the contact area between the semiconductor layer 108 and the conductive layer 112b and reduces the contact resistance between the semiconductor layer 108 and the conductive layer 112b. This increases the on-state current of the transistor 100. The semiconductor layer 108 has a shape that follows the shapes of the top and side surfaces of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.

[0108] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0109] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0110] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.

[0111] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ ), and defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ H) can be reduced.

[0112] The insulating layer 106, which functions as a gate insulating layer of the transistor 100, is provided to cover the openings 141 and 143. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the top surface of the insulating layer 110, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 108, and the top surface of the conductive layer 112a.

[0113] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106.

[0114] In the transistor 100, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor 100 is formed, and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like. The conductive layer 112a can be called a lower electrode of the transistor, and the conductive layer 112b can be called an upper electrode. Since the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner in the VFET, the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0115] Note that there is no particular limitation on the structure of a transistor that can be used in a semiconductor device that is one embodiment of the present invention.

[0116] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high precision. Furthermore, the variation in characteristics among the plurality of transistors 100 is also reduced. This stabilizes the operation of the semiconductor device 10, thereby improving its reliability. Furthermore, the reduced variation in transistor characteristics increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device to be lowered. Therefore, the power consumption of the semiconductor device can be reduced.

[0117] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the area occupied by the transistor 100 and the wirings can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided. Furthermore, when the semiconductor device is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be provided. Furthermore, for example, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be provided.

[0118] 1B and the like show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143; however, one embodiment of the present invention is not limited to this. A step may be formed between the insulating layer 110, the conductive layer 112b, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.

[0119] [Insulating Layer 110] The insulating layer 110 preferably has a stacked structure. In Fig. 1A and other figures, the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can each be made of the materials listed for the insulating layer 110.

[0120] A region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region. The insulating layer 110b preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. Specifically, the insulating layer 110b can be made of silicon oxide, silicon oxynitride, or both.

[0121] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0122] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. Then, the film can be removed.

[0123] The insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a PECVD method. In particular, when the insulating layer 110b is formed by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, the film can have an extremely low hydrogen content. The sputtering method is particularly suitable for forming the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0124] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., water and hydrogen) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0125] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting favorable electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layer 112a from increasing. Similarly, the conductive layer 112b can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layer 112b from increasing. Therefore, a transistor with a large on-state current can be obtained.

[0126] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0127] The insulating layer 110a and the insulating layer 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 110a and the insulating layer 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Note that the insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0128] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) when the insulating layer 110c (or the insulating film that will become the insulating layer 110c) is formed.

[0129] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0130] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0131] When the insulating layer 110c has a stacked structure, the layers constituting the insulating layer 110c can be made of the materials listed for the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have, for example, a stacked structure of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0132] 4A and 4B are cross-sectional views of a semiconductor device 10A according to one embodiment of the present invention. For a top view of the semiconductor device 10A, see FIG. 1A. FIG. 4A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 4B is a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG.

[0133] The semiconductor device 10A includes a transistor 100 and an insulating layer 110. The semiconductor device 10A differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 110e.

[0134] The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c.

[0135] The insulating layer 110d is provided between the conductive layer 112a and the insulating layer 110a. The insulating layer 110d is provided so as to cover the conductive layer 112a. The insulating layer 110d has regions in contact with the top surface and side surfaces of the conductive layer 112a, the top surface of the substrate 102, and the side surfaces of the semiconductor layer 108.

[0136] The insulating layer 110e is provided between the conductive layer 112b and the insulating layer 110c. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, and the side surface of the semiconductor layer .

[0137] It is more preferable that the insulating layer 110d and the insulating layer 110e each be made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. Impurities are released from the insulating layer 110d and diffuse into a region of the semiconductor layer 108 that is in contact with the insulating layer 110d. This allows the region of the semiconductor layer 108 that is in contact with the insulating layer 110d to contain impurities and become a low-resistance region. The semiconductor layer 108 can have a low-resistance region between a region that is in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110e, impurities are released from the insulating layer 110e and diffuse into a region of the semiconductor layer 108 that is in contact with the insulating layer 110e. The region of the semiconductor layer 108 that is in contact with the insulating layer 110e contains impurities and becomes a low-resistance region. The semiconductor layer 108 may have a low-resistance region between a region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance region can function as a buffer region for reducing the drain electric field. Note that these low-resistance regions may function as the source or drain region.

[0138] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. For example, when the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. When the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor.

[0139] When the region of the semiconductor layer 108 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be made more uniform, thereby making the electric field of the gate electrode applied to the channel formation region more uniform.

[0140] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released from the insulating layers 110d and 110e include hydrogen. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen (V Ｏ H) functions as a donor, generating electrons as carriers. This increases the carrier concentration in the region of the semiconductor layer 108 that is in contact with the insulating layer 110d and the region that is in contact with the insulating layer 110e, thereby reducing the electrical resistance.

[0141] The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0142] The amount of released hydrogen can be adjusted by differentiating the film formation conditions between the insulating layer 110d and the insulating layer 110a. Specifically, it is preferable to make one or more of the film formation power (film formation power density), film formation pressure, film formation gas type, film formation gas flow rate ratio, film formation temperature, and distance between the substrate and the electrode different between the insulating layer 110d and the insulating layer 110a. For example, by making the film formation power density of the insulating layer 110d lower than the film formation power density of the insulating layer 110a, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0143] The hydrogen content in the deposition gas used to deposit the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to deposit the insulating layer 110a. Specifically, when silicon nitride films or silicon nitride oxide films are deposited as the insulating layer 110d and the insulating layer 110a by a PECVD method, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to deposit the insulating layer 110d (hereinafter also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow rate of the deposition gas used to deposit the insulating layer 110a. By depositing the insulating layer 110d under conditions with a high ammonia flow ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased.

[0144] It is more preferable that the film density of the insulating layer 110a be higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker transmission electron (TE) image, whereas a low film density results in a lighter transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear darker than the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0145] The insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layers 110c and 110e, the descriptions of the insulating layers 110a and 110d can be referred to.

[0146] Here, the insulating layer 110 is shown to have a stacked structure of three or five layers, but one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b. A structure without one or more of the insulating layer 110d, the insulating layer 110a, the insulating layer 110c, and the insulating layer 110e is also possible. The insulating layer 110 can have a stacked structure of two, four, or six or more layers. Alternatively, the insulating layer 110 can have a single-layer structure.

[0147] The configuration of the insulating layer 110 can be applied to other configuration examples.

[0148] [Opening 141, Opening 143] The top surface shapes of openings 141 and 143 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shapes of openings 141 and 143 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other documents, "circular" does not necessarily mean a perfect circle.

[0149] In this specification and the like, the top surface shape of the opening 141 refers to the shape of the top surface end portion of the insulating layer 110 on the opening 141 side. Also, the top surface shape of the opening 143 refers to the shape of the bottom surface end portion of the conductive layer 112b on the opening 143 side.

[0150] As shown in FIG. 1A and other figures, the top shapes of the openings 141 and 143 can be identical or substantially identical to each other. In this case, as shown in FIGS. 1B and 1C and other figures, it is preferable that the bottom edge of the conductive layer 112b on the opening 143 side be identical or substantially identical to the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side. The top shapes of the openings 141 and 143 can also be configured to not be identical to each other. When the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 can also be concentric. Alternatively, the openings 141 and 143 can be configured not to be concentric.

[0151] 5A and 5B, the channel length and the channel width of the transistor 100 will be described. Here, a region of the semiconductor layer 108 in contact with the insulating layer 110b will be described as a channel formation region.

[0152] In FIG. 5B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110 of the insulating layer 110b and the angle θ110 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the top surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0153] The channel length L100 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0154] As described above, it is preferable that the grain size of the crystal grains contained in the semiconductor layer 108 is large. The above description can be referred to for the grain size of the crystal grains contained in the semiconductor layer 108. For example, when the channel length L100 is 500 nm and the grain size of the crystal grains is 0.3 μm, the number of crystal grains in the channel length direction is two or three, and the number of crystal grain boundaries intersecting with the channel length direction is one or two. When the channel length L100 is 500 nm and the grain size of the crystal grains is 0.7 μm, the number of crystal grains in the channel length direction is one or two, and the number of crystal grain boundaries intersecting with the channel length direction is zero or one. In this way, by increasing the grain size of the crystal grains contained in the semiconductor layer 108, the number of crystal grain boundaries intersecting with the channel length direction can be reduced, resulting in a transistor with high field-effect mobility.

[0155] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0156] The channel length L100 can be controlled by adjusting the thickness T110 and angle θ110 of the insulating layer 110b.

[0157] The thickness T110 of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0158] When the angle θ110 is 90 degrees or less, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0159] 5B and the like, the angle θ110 is shown as being less than 90 degrees; however, one embodiment of the present invention is not limited to this. The angle θ110 can be set to 90 degrees or approximately 90 degrees. This can shorten the channel length L100 of the transistor 100.

[0160] 1B and the like show a structure in which the shape of the side surface of the insulating layer 110 on the opening 141 side is straight in a cross-sectional view, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side can be curved. Alternatively, a structure having both a straight region and a curved region in the shape of the side surface is also possible.

[0161] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a top view.

[0162] 5A and 5B, the width D141 of the opening 141 is indicated by a two-dot chain line with a double arrow. FIG. 5A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the length of the circumference of the circle. In other words, the channel width W100 is π×D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0163] The width D141 of the opening 141 may vary in the depth direction. For example, the width D141 of the opening 141 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view. Alternatively, the diameter of the opening 141 may be any of the diameter at the highest point, the diameter at the lowest point, or the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view.

[0164] When the opening 141 is formed using lithography, the width D141 of the opening 141 is equal to or greater than the minimum exposure dimension of the exposure device. The width D141 can be, for example, 20 nm or greater, 50 nm or greater, 100 nm or greater, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and can be less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0165] Note that although the example in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region has been described here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region in contact with the insulating layer 110c may also function as a channel formation region.

[0166] [Insulating Layer 106] The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be formed using the materials listed for the insulating layer 110.

[0167] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0168] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0169] 1B and the like, the insulating layer 106 has a single-layer structure; however, one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers. When the insulating layer 106 has a stacked structure, the insulating layer on the semiconductor layer 108 side preferably contains oxide or oxynitride. The insulating layer on the semiconductor layer 108 side can preferably be made of, for example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0170] It is preferable to use a material that is difficult for substances to permeate for at least one of the layers constituting the insulating layer 106. The layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100 from diffusing into the semiconductor layer 108 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the semiconductor layer 108 from diffusing into the conductive layer 104 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ) can be suppressed. In addition, the conductive layer 104 can be prevented from being oxidized by oxygen contained in the semiconductor layer 108, which can prevent the electrical resistance of the conductive layer 104 from increasing. As a result, a transistor with good electrical characteristics and high reliability can be obtained. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of oxides and oxynitrides can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0171] The insulating layer 106 can have, for example, a stacked structure of a silicon oxynitride film and a silicon nitride film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of a silicon oxynitride film and an aluminum oxide film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon oxynitride film over the aluminum oxide film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0172] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0173] The configuration of the insulating layer 106 shown here can also be applied to other configuration examples.

[0174] [Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 104] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0175] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be formed using a conductive metal oxide (also referred to as an oxide conductor (OC)).

[0176] Examples of oxide conductors include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also called ITO containing silicon, or ITSO), zinc oxide doped with gallium, and In—Ga—Zn oxide. Oxide conductors containing indium are particularly preferred because of their high conductivity.

[0177] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0178] The conductive layers 112a, 112b, and 104 can each have a stacked-layer structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0179] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied to each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0180] Note that the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can be formed using the same material, or at least one of them can be formed using a different material.

[0181] The conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, for the conductive layer 112a and the conductive layer 112b, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material.

[0182] For the conductive layer 112a and the conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108.

[0183] The conductive layer 112 a and the conductive layer 112 b can each be formed using any of the above-described oxide conductors, such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium.

[0184] The conductive layer 112a and the conductive layer 112b may each be formed using a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104 may also be formed using any of the nitride conductors described above.

[0185] [Substrate 102] The material of the substrate 102 is not particularly limited, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited, and can be, for example, circular or rectangular.

[0186] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0187] [Insulating Layer 218] An insulating layer 218 is provided over the transistor 100. The insulating layer 218 functions as a protective layer for the transistor. The insulating layer 218 can be formed using the same material as that used for the insulating layer 110. The insulating layer 218 preferably includes one or more inorganic insulating layers. Note that the insulating layer 218 is omitted from the perspective views shown in FIGS. 2A to 2D.

[0188] The insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen do not easily diffuse. This allows the insulating layer 218 to function as a barrier film. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the semiconductor device. The above description can be referred to for the barrier film.

[0189] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0190] [Configuration Example 1-2] Cross-sectional views of a semiconductor device 10B according to one embodiment of the present invention are shown in Fig. 6A and Fig. 6B. For a top view of the semiconductor device 10B, refer to Fig. 1A. Fig. 6A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in Fig. 1A, and Fig. 6B is a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in Fig. 1A.

[0191] The semiconductor device 10B includes a transistor 100, an insulating layer 110, and an insulating layer 109. The semiconductor device 10B differs from the semiconductor device 10 shown in FIG.

[0192] The insulating layer 109 is located between the substrate 102 and the conductive layer 112a. The insulating layer 109 is provided on the substrate 102, the conductive layer 112a is provided on the insulating layer 109, and the insulating layer 110 is provided on the conductive layer 112a. The insulating layer 109 has regions in contact with the bottom surface of the conductive layer 112a and the bottom surface of the insulating layer 110. The conductive layer 112a has regions in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. The insulating layer 110 has regions in contact with the top and side surfaces of the conductive layer 112a, the top surface of the insulating layer 109, the side surface of the semiconductor layer 108, the bottom surface of the conductive layer 112b, and the bottom surface of the insulating layer 106.

[0193] The insulating layer 109 preferably has a barrier property. The insulating layer 109 is preferably made of a material through which impurities (for example, water and hydrogen) contained in the substrate 102 do not easily diffuse. This can prevent impurities from diffusing from the substrate 102 to the transistor 100.

[0194] The description of the barrier film can be referred to for the insulating layer 109. For example, the insulating layer 109 can be formed using one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, for example, the insulating layer 109 can be formed using one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0195] The insulating layer 109 is preferably formed using a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. The insulating layer 109 can be formed using the same material as that used for the insulating layer 110d and the insulating layer 110e. For example, the insulating layer 109 can preferably be formed using silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

[0196] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a also diffuse into a region of the semiconductor layer 108 that is in contact with the conductive layer 112a. This reduces the electrical resistance of the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, that is, one of the source region and the drain region. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be obtained.

[0197] When a metal oxide is used for the semiconductor layer 108, the impurities released from the insulating layer 109 preferably contain hydrogen. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 108 through the conductive layer 112a increases the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a, thereby reducing the electrical resistance of one of the source and drain regions.

[0198] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112a. This can reduce the electrical resistance of the conductive layer 112a. For example, when a metal oxide is used for the conductive layer 112a, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layer 112a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a can function as a wiring, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 108.

[0199] The materials that can be used for the conductive layer 112a are as described above. Note that the conductive layer 112a preferably easily transmits impurities and more preferably does not easily adsorb impurities.

[0200] The insulating layer 110a has a region in contact with the top surface of the insulating layer 109 and the top surface and side surfaces of the conductive layer 112a, which can suppress diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel formation region of the semiconductor layer 108 through the insulating layer 110b.

[0201] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For the insulating layer 109, the descriptions of the insulating layers 110d and 110e can be referred to.

[0202] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor that has both a small cutoff current (a drain current that flows when the gate voltage (Vg) is 0 V) ​​and a large on-state current. Therefore, a semiconductor device that has both low power consumption and high performance can be provided.

[0203] 6A and other drawings show the insulating layer 110 having a four-layer structure including insulating layers 110a, 110b, 110c, and 110e, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 can have a five-layer structure including insulating layers 110d, 110a, 110b, 110c, and 110e. Alternatively, the insulating layer 110 can have a three-layer structure including insulating layers 110a, 110b, and 110c.

[0204] The structure of the insulating layer 109 shown here can also be applied to other structure examples.

[0205] 7A shows an equivalent circuit diagram of a semiconductor device 10C according to one embodiment of the present invention. The semiconductor device 10C includes transistors 100_1 to 100_q (q is an integer of 2 or greater). The transistors 100_1 to 100_q are connected in series. The transistors 100_1 to 100_q share a gate, and the semiconductor device 10C can be regarded as a single transistor.

[0206] 7A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_q may be p-channel transistors.

[0207] A specific description will be given taking the case where q is 4 as an example. FIG. 7B shows an equivalent circuit diagram of a semiconductor device 10C according to one embodiment of the present invention. FIG. 7C shows a top view of the semiconductor device 10C. FIG. 8 shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6 in FIG. 7C. FIG. 9 shows a perspective view of the semiconductor device 10C.

[0208] The semiconductor device 10C includes transistors 100_1 to 100_4. The transistors 100_1 to 100_4 can each have the same structure as the transistor 100. Note that although the example in which the insulating layer 110 has a three-layer structure is described, one embodiment of the present invention is not limited to this.

[0209] 7C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, but the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0210] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100_1, and the conductive layer 112b functions as the other electrode.

[0211] The transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c. The conductive layer 112a serves as one of a source electrode and a drain electrode of the transistor 100_2, and the conductive layer 112c serves as the other electrode. The conductive layer 112a is shared by the transistor 100_1 and the transistor 100_2.

[0212] The transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. The conductive layer 112c serves as one of a source electrode and a drain electrode of the transistor 100_3, and the conductive layer 112d serves as the other electrode. The conductive layer 112c is shared by the transistors 100_2 and 100_3.

[0213] The transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. The conductive layer 112d functions as one of a source electrode and a drain electrode of the transistor 100_4, and the conductive layer 112e functions as the other. The conductive layer 112d is shared by the transistors 100_3 and 100_4. The conductive layer 104 is shared by the transistors 100_1 to 100_4.

[0214] 10A is a perspective view showing the conductive layer 112a and the conductive layer 112d. The conductive layer 112a and the conductive layer 112d can be formed in the same process.

[0215] 10B is a perspective view illustrating the conductive layers 112a, 112b, 112c, 112d, and 112e, the openings 141_1 to 141_4, and the openings 143_1 to 143_4. The conductive layers 112a to 112e can be formed in the same process. The conductive layer 112b has an opening 143_1, the conductive layer 112c has openings 143_2 and 143_3, and the conductive layer 112e has an opening 143_4.

[0216] 10C is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the semiconductor layers 108_1 to 108_4. The semiconductor layers 108_1 to 108_4 can be formed in the same process.

[0217] 10D is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the conductive layer 104. The conductive layer 104 is shared by the transistors 100_1 to 100_4 and functions as a gate electrode thereof.

[0218] One of a source electrode and a drain electrode of the transistor 100_1 is connected to one of a source electrode and a drain electrode of the transistor 100_2. The other of the source electrode and the drain electrode of the transistor 100_2 is connected to one of a source electrode and a drain electrode of the transistor 100_3. The other of the source electrode and the drain electrode of the transistor 100_3 is connected to one of a source electrode and a drain electrode of the transistor 100_4.

[0219] To avoid complicating the drawings, the insulating layer 109 is not shown with hatching patterns in FIGS. 9 to 10D.

[0220] When the semiconductor device 10C is regarded as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is L100, the semiconductor device 10C can be regarded as a transistor having a channel length of "L100×4" (see FIG. 5B). The semiconductor device 10C, which is composed of q transistors, can be regarded as a transistor having a channel length of "L100×q". Note that the semiconductor device 10C can be regarded as a transistor having a channel width W100 (see FIGS. 5A and 5B). By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel lengths can be varied by adjusting the number (q) of transistors connected in series. The number (q) of transistors connected in series can be determined so as to achieve a desired saturation.

[0221] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0222] The configuration of the semiconductor device 10C shown here can be applied to other configuration examples. Also, a configuration can be adopted in which a group of series-connected transistors are further connected in parallel (hereinafter also referred to as series-parallel connection).

[0223] 11A shows a top view of a semiconductor device 20 according to one embodiment of the present invention. FIG. 11B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 11A, and FIG. 11C shows a cross-sectional view of a cut surface taken along dashed dotted line A3-A4 in FIG.

[0224] The semiconductor device 20 includes a transistor 200. The transistor 200 includes an insulating layer 202 over a substrate 102, a semiconductor layer 203 over the insulating layer 202, an insulating layer 204 over the semiconductor layer 203, and a conductive layer 205 over the insulating layer 204. The conductive layer 205 has a region overlapping with the semiconductor layer 203 with the insulating layer 204 interposed therebetween. The conductive layer 205 functions as a gate electrode of the transistor 200, and the insulating layer 204 functions as a gate insulating layer.

[0225] The semiconductor layer 203 preferably contains indium oxide. For the semiconductor layer 203, the description of the semiconductor layer 108 can be referred to.

[0226] The semiconductor layer 203 has regions 203P, 203Q, and 203R. The region 203Q overlaps with the conductive layer 205 with the insulating layer 204 interposed therebetween and functions as a channel formation region. The region 203P functions as one of a source region and a drain region. The region 203R functions as the other of the source region and the drain region. In the semiconductor layer 203, the region 203Q is located between the regions 203P and 203R.

[0227] The transistor 200 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 203. By supplying impurities to the semiconductor layer 203 using the conductive layer 205 functioning as the gate electrode as a mask, regions 203P and 203R functioning as source and drain regions can be formed in a self-aligned manner. The transistor 200 can be called a TGSA (Top Gate Self-Aligned) transistor.

[0228] The regions 203P and 203R contain impurities. Supplying the impurities to the semiconductor layer 203 can reduce the electrical resistance of the regions 203P and 203R. The impurity concentrations in the regions 203P and 203R are higher than the impurity concentration in the region 203Q. The elements contained in the impurities (hereinafter also referred to as "second elements") can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the second element. The impurities can be supplied by plasma ion doping or ion implantation. These methods allow for highly accurate control of the depth concentration profile by adjusting the ion acceleration voltage, dose, and other parameters. Using plasma ion doping can improve productivity. Furthermore, by using an ion implantation method using mass separation, the purity of the supplied impurities can be increased.

[0229] When an element that easily bonds with oxygen is used as the second element, the second element takes away oxygen from the semiconductor layer 203 and exists in a state of being bonded to oxygen. Ｏ ) occurs. When an element that becomes stable when bonded with oxygen is used as the second element, the second element in the semiconductor layer 203 exists stably in an oxidized state and is therefore unlikely to be desorbed by heat or the like applied during the manufacturing process of the semiconductor device, and the electrical resistance of the regions 203P and 203R can be kept low. For this reason, it is preferable to use an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process as the second element. One or both of boron and phosphorus can be suitably used as the second element.

[0230] The supply of hydrogen causes oxygen vacancies (V Ｏ ) occurs, and oxygen deficiency (V Ｏ ) by entering V ＯThe generation of H can efficiently reduce the electrical resistance of the region 203P and the region 203R. Therefore, hydrogen can be suitably used as the second element.

[0231] In supplying the impurity, it is preferable to adjust the supply conditions so that the impurity concentration is highest on the surface of the semiconductor layer 203 or in a region close to the surface.

[0232] The source material used to supply the impurity may be, for example, a gas containing the second element. ２ H ６ Gas, or BF ３ In addition, when phosphorus is supplied, one or more of the following gases can be used: PH ３ Furthermore, gases obtained by diluting these source gases with noble gases can also be used.

[0233] As a raw material used for supplying impurities, for example, CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg and noble gases can be used. Note that the raw material is not limited to gas, and a solid or liquid can also be heated and vaporized for use.

[0234] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 204 and the semiconductor layer 203. Note that when the impurities are supplied to the semiconductor layer 203 through the insulating layer 204 using the conductive layer 205 as a mask, the region of the insulating layer 204 that does not overlap with the conductive layer 205 may also contain the impurities when the impurities are supplied to the region. Furthermore, the region of the insulating layer 202 that does not overlap with the conductive layer 205 may also contain the impurities when the impurities are supplied to the region.

[0235] For example, when boron is supplied by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, and more preferably 10 kV or more and 50 kV or less. The dose can be, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ Less than 1×10, more preferably 1×10 １５ ions / cm ２ That's it, 3 x 10 １６ ions / cm ２ The range can be as follows:

[0236] When phosphorus is supplied by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less. The dose can be set to, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ Less than 1×10, more preferably 1×10 １５ ions / cm ２ 3x10 or more １６ ions / cm ２ The range can be as follows:

[0237] The method of supplying the impurities is not limited to this, and for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, the impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc. can be used.

[0238] The length of region 203Q in the X direction is the channel length L of transistor 200 (see FIG. 11B), and the length of region 203Q in the Y direction is the channel width W of transistor 200 (see FIG. 11C).

[0239] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203P of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203R of the semiconductor layer 203.

[0240] A conductive layer 208a is provided to cover the opening 207a, and a conductive layer 208b is provided to cover the opening 207b. The conductive layer 208a is connected to the region 203P of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is connected to the region 203R of the semiconductor layer 203 at the bottom of the opening 207b. The conductive layer 208a functions as one of the source electrode and drain electrode of the transistor 200, and the conductive layer 208b functions as the other of the source electrode and drain electrode of the transistor 200.

[0241] An insulating layer 218 is provided over the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0242] In the TGSA transistor, the physical distance between the conductive layer 208 functioning as a source electrode and a drain electrode and the conductive layer 205 functioning as a gate electrode can be increased, and therefore, the parasitic capacitance between them can be reduced.

[0243] The insulating layer 204 has a region in contact with the semiconductor layer 203. When a metal oxide is used for the semiconductor layer 203, at least a part of the region of the insulating layer 204 in contact with the semiconductor layer 203 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 203 and the insulating layer 204. Specifically, the region of the insulating layer 204 in contact with the channel formation region of the semiconductor layer 203 preferably contains oxygen. One or more of an oxide and an oxynitride can be preferably used for the region of the insulating layer 204 in contact with the channel formation region of the semiconductor layer 203. The same applies to the insulating layer 202. For example, the insulating layer 204 and the insulating layer 202 each preferably contain silicon and oxygen. The insulating layer 204 and the insulating layer 202 can each preferably contain silicon oxide or silicon oxynitride.

[0244] 12A and 12B show examples of a structure different from those shown in FIGS. 11A to 11C . FIGS. 12A and 12B are cross-sectional views of a semiconductor device 20A according to one embodiment of the present invention. For a top view of the semiconductor device 20A, refer to FIG. 11A . FIG. 12A is a cross-sectional view of a section taken along dashed dotted line A1-A2 in FIG. 11A , and FIG. 12B is a cross-sectional view of a section taken along dashed dotted line A3-A4 in FIG.

[0245] The semiconductor device 20A includes a transistor 200A. The transistor 200A differs from the transistor 300 mainly in that the insulating layer 202 has a stacked structure.

[0246] 12A and 12B show an example in which the insulating layer 202 includes an insulating layer 202a and an insulating layer 202b on the insulating layer 202a.

[0247] The insulating layer 202b has a region in contact with the semiconductor layer 203. As described above, the insulating layer 202b in contact with the semiconductor layer 203 preferably contains oxygen.

[0248] The insulating layer 202a located on the substrate 102 side preferably functions as a barrier film. By providing the barrier film, it is possible to suppress the diffusion of components (e.g., metals) contained in the substrate 102 into the transistor, thereby making it possible to provide a highly reliable semiconductor device. The above description of the barrier film can be referred to. The insulating layer 202a preferably contains nitrogen.

[0249] The insulating layer 202a preferably contains silicon and nitrogen. The insulating layer 202b preferably contains silicon and nitrogen. For example, silicon nitride can be preferably used for the insulating layer 202a, and silicon oxynitride can be preferably used for the insulating layer 202b.

[0250] The configuration of the insulating layer 202 shown here can also be applied to other configuration examples.

[0251] 13A to 13C show examples of structures different from those shown in FIGS. 11A to 11C . Fig. 13A is a top view of a semiconductor device 20B according to one embodiment of the present invention. Fig. 13B is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in Fig. 13A , and Fig. 13C is a cross-sectional view of a cut surface taken along dashed dotted line A3-A4 in Fig. 13A .

[0252] The semiconductor device 20B includes a transistor 200B. The transistor 200B differs from the transistor 200 shown in FIG.

[0253] The conductive layer 219 is provided between the substrate 102 and the insulating layer 202. The conductive layer 219 functions as a back gate electrode of the transistor 200C. The conductive layer 219 is provided in a position overlapping with the region 203Q. The conductive layer 219 preferably extends beyond the end of the region 203Q. That is, the conductive layer 219 preferably covers the region 203Q. Covering the region 203Q with the conductive layer 219 can enhance the effect of making an electric field generated outside the transistor less likely to act on the channel formation region (also referred to as an electric field shielding effect). The conductive layer 205 can also be referred to as a top gate electrode, and the conductive layer 219 can also be referred to as a back gate electrode. The insulating layer 202 functions as a back gate insulating layer of the transistor 200B. The insulating layer 202 can have a stacked structure (see FIGS. 12A and 12B ). By providing a barrier film for the insulating layer 202, components (for example, metals) contained in the conductive layer 219 and the substrate 102 can be prevented from diffusing into the transistor, thereby providing a highly reliable semiconductor device.

[0254] 14A shows a top view of a semiconductor device 20C according to one embodiment of the present invention, FIG. 14B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 14A , and FIG. 14C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG.

[0255] The semiconductor device 20C includes a transistor 200C. The transistor 200C differs from the transistor 200B shown in FIG. 13B and other figures mainly in that an edge of an insulating layer 204 coincides with or substantially coincides with an edge of a conductive layer 205.

[0256] An end portion of the insulating layer 204 is located on the semiconductor layer 203. The insulating layer 204 overlaps with the region 203Q but does not overlap with the region 203P or the region 203R. It can also be said that the top surface shape of the insulating layer 204 matches or substantially matches that of the conductive layer 205. The insulating layer 204 can be formed, for example, by processing using a resist mask for processing the conductive layer 205.

[0257] The insulating layer 206 has regions in contact with the top surface and side surfaces of the semiconductor layer 203, the side surfaces of the insulating layer 204, and the top surface and side surfaces of the conductive layer 205. The insulating layer 206 has an opening 207a that reaches the region 203P and an opening 207b that reaches the region 203R. Conductive layers 208a and 208b are formed to cover the openings 207a and 207b. The conductive layer 208a contacts the region 203P at the opening 207a and is connected to the region 203P. The conductive layer 208b contacts the region 203R at the opening 207b and is connected to the region 203R.

[0258] The above description can be referred to for a method of supplying impurities to the semiconductor layer 203. For example, hydrogen is supplied as an impurity to a region of the semiconductor layer 203 that does not overlap with the conductive layer 205 by performing plasma treatment in an atmosphere containing a gas containing a hydrogen element using a plasma CVD apparatus. This makes it possible to form the regions 203P and 203R. Furthermore, by using a plasma CVD apparatus for supplying the impurity and forming the insulating layer 206, the supply of the impurity and the formation of the insulating layer 206 can be performed continuously within the apparatus, thereby improving productivity.

[0259] 15A to 15C show examples of structures different from those shown in FIGS. 14A to 14C . Fig. 15A is a top view of a semiconductor device 20C according to one embodiment of the present invention. Fig. 15B is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in Fig. 15A , and Fig. 15C is a cross-sectional view of a cut surface taken along dashed dotted line A3-A4 in Fig. 15A .

[0260] The semiconductor device 20D includes a transistor 200D. The transistor 200D differs from the transistor 200C shown in FIG. 14B and the like mainly in that the insulating layer 204 has a region that protrudes beyond the conductive layer 205.

[0261] An end of the insulating layer 204 is located on the semiconductor layer 203, and an end of the conductive layer 205 is located on the insulating layer 204. It can also be said that the end of the insulating layer 204 is located outside the end of the conductive layer 205. The insulating layer 204 has a region that overlaps with the conductive layer 205 and a region that does not overlap with the conductive layer 205 on the semiconductor layer 203.

[0262] The semiconductor layer 203 has a region 203Q, regions 203S and 203T sandwiching the region 203Q, and regions 203P and 203R located outside of the regions 203S and 203T. The regions 203S and 203T are regions of the semiconductor layer 203 that overlap with the insulating layer 204 but do not overlap with the conductive layer 205. The region 203S is located between the regions 203Q and 203P, and the region 203T is located between the regions 203Q and 203R.

[0263] The regions 203S and 203T function as buffer regions for alleviating the drain electric field. The regions 203S and 203T do not overlap with the conductive layer 205, and therefore, are regions in which a channel is hardly formed even when a gate voltage is applied to the conductive layer 205. The regions 203S and 203T preferably have a higher carrier concentration than the region 203Q. This allows the regions 203S and 203T to function as LDD (lightly doped drain) regions.

[0264] Compared to region 203Q, regions 203S and 203T can also be described as regions with the same or lower electrical resistance, regions with the same or higher carrier concentration, regions with the same or higher oxygen defect density, and regions with the same or higher impurity concentration.

[0265] Compared to regions 203P and 203R, regions 203S and 203T can also be described as regions with the same or higher electrical resistance, regions with the same or lower carrier concentration, regions with the same or lower oxygen defect density, and regions with the same or lower impurity concentration.

[0266] The insulating layer 206 has regions in contact with the upper surface and side surfaces of the semiconductor layer 203 , the upper surface and side surfaces of the insulating layer 204 , and the upper surface and side surfaces of the conductive layer 205 .

[0267] 16A shows a top view of a semiconductor device 20E according to one embodiment of the present invention, FIG. 16B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 16A , and FIG. 16C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG.

[0268] The semiconductor device 20E includes a transistor 200E. The transistor 200E differs mainly from the transistor 200D shown in FIG. 15B and the like in that the conductive layers 208a and 208b are formed in the same process as the conductive layer 205.

[0269] The insulating layer 204 has openings 207a and 207b that reach the semiconductor layer 203. Conductive layers 208a and 208b are provided so as to cover part of the openings 207a and 207b. The conductive layer 208a has a region in contact with the semiconductor layer 203 in the openings 207a, and the conductive layer 208b has a region in contact with the semiconductor layer 203 in the openings 207b.

[0270] The conductive layer 205, the conductive layer 208a, and the conductive layer 208b can be formed using the same material and in the same process. For example, an insulating film that becomes the insulating layer 204 is formed over the semiconductor layer 203, and the insulating film is processed to form the insulating layer 204 having the openings 207a and 207b. Then, a conductive film that becomes the conductive layer 205, the conductive layer 208a, and the conductive layer 208b is formed so as to cover the insulating layer 204 and the openings 207a and 207b, and the conductive film is processed to form the conductive layer 205, the conductive layer 208a, and the conductive layer 208b. Forming the conductive layer 208a and the conductive layer 208b in the same process as the conductive layer 205 can simplify the process.

[0271] By supplying the second element to the semiconductor layer 203 using the conductive layer 205, the conductive layer 208a, and the conductive layer 208b as masks, the regions 203P and 203R can be formed in a self-aligned manner. The regions 203P and 203R are formed in regions of the semiconductor layer 203 that do not overlap with any of the conductive layer 205, the conductive layer 208a, the conductive layer 208b, and the insulating layer 204. Furthermore, the regions 203S and 203T are formed in regions of the semiconductor layer 203 that do not overlap with any of the conductive layer 205, the conductive layer 208a, and the conductive layer 208b, and that overlap with the insulating layer 204.

[0272] A region of the semiconductor layer 203 in contact with the conductive layer 208a and a region 203P in contact with the conductive layer 208a function as one of a source region and a drain region. A region of the semiconductor layer 203 in contact with the conductive layer 208b and a region 203R in contact with the conductive layer 208b function as the other of the source region and the drain region.

[0273] 16B and 16C show a structure example in which the insulating layer 206 is not provided, one embodiment of the present invention is not limited to this. The insulating layer 206 can also be provided over the transistor 200E.

[0274] 17A shows a top view of a semiconductor device 20F according to one embodiment of the present invention, FIG. 17B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 17A, and FIG. 17C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG.

[0275] The semiconductor device 20F includes a transistor 200F. The transistor 200F includes a semiconductor layer 520 disposed on the substrate 102, conductive layers 542a and 542b disposed on the semiconductor layer 520 and spaced apart from each other, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, and an insulating layer 550 disposed between the semiconductor layer 520, the conductive layers 542a and 542b, and the insulating layer 580. As shown in FIGS. 17B and 17C , the top surface of the conductive layer 560 is substantially flush with the top surfaces of the insulating layers 550 and 580. The conductive layers 542a and 542b may be collectively referred to as the conductive layer 542.

[0276] 17A to 17C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520, the conductive layers 542a and 542b, and the insulating layer 580. The insulating layer 554 is in contact with the side surface of the insulating layer 550, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surface of the semiconductor layer 520, and the side surface of the insulating layer 524.

[0277] For the semiconductor layer 520, the description of the semiconductor layer 108 can be referred to.

[0278] Here, the conductive layer 560 functions as the gate electrode of the transistor, and the conductive layers 542a and 542b function as source and drain electrodes, respectively. As described above, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and in the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200F, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200F. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0279] 17A to 17C , the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 in the transistor 200F has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0280] The semiconductor device 20F has an insulating layer 202 disposed on the substrate 102, an insulating layer 514 disposed on the insulating layer 202, and an insulating layer 516 disposed on the insulating layer 514. The transistor 200F has a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520 is disposed on the insulating layer 524.

[0281] An insulating layer 574 and an insulating layer 581 functioning as interlayer films are provided over the transistor 200F. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the insulating layer 554, and the insulating layer 580.

[0282] The insulating layers 522, 554, and 574 may be insulating layers having a function of suppressing diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, and the like). For example, the insulating layers 522, 554, and 574 may be insulating layers having lower hydrogen permeability than the insulating layers 524, 550, and 580. The insulating layers 522 and 554 may be insulating layers having a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulating layers 522 and 554 may be insulating layers having lower oxygen permeability than the insulating layers 524, 550, and 580.

[0283] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from being mixed into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0284] 17B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) connected to the transistor 200F and functioning as a plug is provided. Note that an example is shown in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 functioning as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 17B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0285] Here, the height of the top surface of the conductive layer 545 and the height of the top surface of the insulating layer 581 can be approximately the same. Note that although the transistor 200F shows a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0286] The thickness of the semiconductor layer 520 in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520 when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520, a region with low electrical resistance may be formed near the interface with the conductive film. In this way, removing the region with low electrical resistance located between the conductive layer 542a and the conductive layer 542b on the top surface of the semiconductor layer 520 can prevent a channel from being formed in the region.

[0287] Next, the detailed structure of the transistor 200F that can be used in the semiconductor device of one embodiment of the present invention will be described.

[0288] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0289] The conductive layer 505 includes a conductive layer 505a and a conductive layer 505b. The conductive layer 505a is provided in contact with the bottom surface and sidewalls of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to be embedded in a recessed portion of the conductive layer 505a. The height of the top surface of the conductive layer 505b is approximately the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516.

[0290] The conductive layer 505a is made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO２ A conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is used.

[0291] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 505a, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 via the insulating layer 524 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layer 505a, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0292] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode.

[0293] The conductive layer 505 is preferably provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 17C, the conductive layer 505 preferably extends to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0294] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0295] The conductive layer 505 may be used as a wiring by extending it beyond the end of the semiconductor layer 520. However, the present invention is not limited to this, and a conductive layer that functions as a wiring may be provided under the conductive layer 505.

[0296] The insulating layer 514 may be formed using an insulating material that functions as a barrier insulating layer that prevents impurities such as water or hydrogen from entering the transistor 200F from the substrate side. ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., impurities are difficult to permeate), or an insulating material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is difficult to permeate).

[0297] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200F side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing toward the substrate side of the insulating layer 514.

[0298] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0299] When the conductive layer 560 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0300] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200F is improved.

[0301] As the insulating layer 522, like the insulating layer 514, a material that functions as a barrier insulating layer that prevents impurities such as water or hydrogen from entering the transistor 200F from the substrate side is used. For example, the insulating layer 522 is made of a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be prevented from entering the transistor 200F from the outside.

[0302] Furthermore, the insulating layer 522 is preferably made of a material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., a material through which the oxygen is less likely to permeate). For example, the insulating layer 522 is made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, which can reduce oxygen diffusing from the semiconductor layer 520 toward the substrate. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0303] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used as the insulating layer 522. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200F.

[0304] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layers. For example, the insulating layer 522 may have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0305] The insulating layer 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as BST may be used as a single layer or a laminate. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0306] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0307] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520. In the case where an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or a conductive material that maintains low electrical resistance even when it absorbs oxygen.

[0308] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200F. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0309] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0310] As the insulating layer 550, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similarly to the insulating layer 524. The thickness of the insulating layer 550 is 1 nm to 20 nm.

[0311] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0312] Although the conductive layer 560 is shown as a two-layer structure in FIGS. 17A to 17C, a single-layer structure or a stacked structure of three or more layers can also be used.

[0313] The conductive layer 560a is formed of the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive layer having a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0314] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0315] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0316] 17B and 17C , in a region of the semiconductor layer 520 that does not overlap with the conductive layer 542, in other words, in a channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200F, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200F and improves its frequency characteristics.

[0317] Like the insulating layer 514, the insulating layer 554 is made of an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200F from the insulating layer 580 side. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 17B and 17C , the insulating layer 554 is provided in contact with the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surface of the semiconductor layer 520, and the side surface of the insulating layer 524. With this structure, hydrogen contained in the insulating layer 580 can be prevented from entering the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520, and the insulating layer 524.

[0318] Furthermore, an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., is less permeable to oxygen) is used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0319] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, thereby preventing the transistor from becoming normally on.

[0320] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0321] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0322] As for the insulating layer 574, similar to the insulating layer 514, an insulating material that functions as a barrier insulating layer that suppresses impurities such as water or hydrogen from entering the insulating layer 580 from above is used. For the insulating layer 574, for example, an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like is used.

[0323] 17A to 17C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524 and the like.

[0324] The conductive layers 545a and 545b are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layers 545a and 545b are provided opposite each other with the conductive layer 560 interposed therebetween. Note that the height of the top surfaces of the conductive layers 545a and 545b can be the same as the height of the top surface of the insulating layer 581.

[0325] Note that an insulating layer 541a is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the openings, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the openings, and the conductive layer 545b is in contact with the conductive layer 542b.

[0326] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b may have a stacked structure of two or more layers.

[0327] When the conductive layer 545 has a stacked-layer structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used for the conductive layer 542 and the conductive layer in contact with the insulating layer 541. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be prevented from entering the semiconductor layer 520 through the conductive layers 545a and 545b.

[0328] The insulating layers 541a and 541b may be, for example, insulating layers that can be used for the insulating layer 554. The insulating layers 541a and 541b are provided in contact with the insulating layer 554, and therefore can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0329] [Configuration Example 2-5] Fig. 18A shows a top view of a semiconductor device 20G according to one embodiment of the present invention. Fig. 18B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 18A, Fig. 18C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4, and Fig. 18D shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6.

[0330] The semiconductor device 20G includes a transistor 200G. Fig. 18B is a cross-sectional view of the transistor 200G in the channel length direction. Fig. 18C and Fig. 18D are cross-sectional views of the transistor 200G in the channel width direction.

[0331] The transistor 200G includes a conductive layer 505 (conductive layer 505a and conductive layer 505b) embedded in the insulating layer 816, an insulating layer 521 over the insulating layer 816 and the conductive layer 505, an insulating layer 522 over the insulating layer 521, an insulating layer 524 over the insulating layer 522, a semiconductor layer 520 over the insulating layer 524, a conductive layer 542a (conductive layer 542a1 and conductive layer 542a2) and a conductive layer 542b (conductive layer 542b1 and conductive layer 542b2) over the semiconductor layer 520, an insulating layer 871a over the conductive layer 542a, an insulating layer 871b over the conductive layer 542b, an insulating layer 850 over the semiconductor layer 520, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) over the insulating layer 850. For the semiconductor layer 520, the description of the semiconductor layer 108 can be referred to.

[0332] An insulating layer 875 is provided over the insulating layers 871a and 871b, and an insulating layer 885 is provided over the insulating layer 875. The insulating layer 855, the insulating layer 850, and the conductive layer 560 are disposed inside openings provided in the insulating layer 885 and the insulating layer 875. An insulating layer 882 is provided over the insulating layer 885 and the conductive layer 560. An insulating layer 883 is provided over the insulating layer 882. An insulating layer 815 is provided under the insulating layer 816 and the conductive layer 505. An insulating layer 855 is provided between the insulating layer 850 and the conductive layer 542a2, the conductive layer 542b2, the insulating layer 871a, the insulating layer 871b, the insulating layer 875, and the insulating layer 885.

[0333] Note that insulating layer 815, insulating layer 816, conductive layer 505, insulating layer 521, insulating layer 522, insulating layer 524, semiconductor layer 520, conductive layer 542a, conductive layer 542b, insulating layer 871a, insulating layer 871b, insulating layer 875, insulating layer 885, insulating layer 855, insulating layer 850, conductive layer 560, insulating layer 882, and insulating layer 883 can each have a single-layer structure or a stacked-layer structure.

[0334] The semiconductor layer 520 has a region that functions as a channel formation region. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode). The insulating layer 850 has a region that functions as a first gate insulator. The conductive layer 505 has a region that functions as a second gate electrode (lower gate electrode). The insulating layer 524, the insulating layer 522, and the insulating layer 521 each have a region that functions as a second gate insulator.

[0335] The conductive layer 542a has a region which functions as one of a source electrode and a drain electrode, and the conductive layer 542b has a region which functions as the other of the source electrode and the drain electrode.

[0336] The conductive layer 542a has a stacked structure of a conductive layer 542a1 and a conductive layer 542a2, and the conductive layer 542b has a stacked structure of a conductive layer 542b1 and a conductive layer 542b2. The conductive layers 542a1 and 542b1 in contact with the semiconductor layer 520 are preferably made of a conductor that is resistant to oxidation, such as a metal nitride. This prevents the conductive layers 542a and 542b from being excessively oxidized by oxygen contained in the semiconductor layer 520. The conductive layers 542a2 and 542b2 are preferably made of a conductor such as a metal layer that has higher conductivity than the conductive layers 542a1 and 542b1. This allows the conductive layers 542a and 542b to function as highly conductive wirings or electrodes.

[0337] For example, tantalum nitride or titanium nitride can be used for the conductive layers 542a1 and 542b1, and tungsten can be used for the conductive layers 542a2 and 542b2.

[0338] The openings in the insulating layer 885 and the insulating layer 875 overlap with the region between the conductive layer 542a2 and the conductive layer 542b2. In a plan view, the side surfaces of the openings in the insulating layer 885 coincide or substantially coincide with the side surfaces of the conductive layer 542a2 and the conductive layer 542b2. Furthermore, portions of the conductive layers 542a1 and 542b1 are formed to protrude into the openings. Here, a portion of the top surface of the conductive layer 542a1 contacts the conductive layer 542a2, and a portion of the top surface of the conductive layer 542b1 contacts the conductive layer 542b2. Therefore, the insulating layer 855 contacts another portion of the top surface of the conductive layer 542a1, another portion of the top surface of the conductive layer 542b1, the side surfaces of the conductive layer 542a2, and the side surfaces of the conductive layer 542b2 within the openings. The insulating layer 850 is in contact with the top surface of the semiconductor layer 520 , the side surface of the conductive layer 542 a 1 , the side surface of the conductive layer 542 b 1 , and the side surface of the insulating layer 855 .

[0339] The insulating layer 855 is preferably an insulator that is resistant to oxidation, such as nitride. The insulating layer 855 is formed by anisotropic etching in contact with the sidewalls of the openings (here, the sidewalls of the openings correspond to, for example, the side surfaces of the insulating layer 885) provided in the insulating layer 885 or the like. The insulating layer 855 is formed in contact with the side surfaces of the conductive layer 542a2 and the conductive layer 542b2 and functions to protect the conductive layers 542a2 and 542b2. In order to supply oxygen to the semiconductor layer 520, heat treatment is preferably performed in an oxygen-containing atmosphere after the conductive layer 542a1 and the conductive layer 542b1 are separated and before the insulating layer 850 is formed. At this time, since the insulating layer 855 is formed in contact with the side surfaces of the conductive layer 542a2 and the conductive layer 542b2, excessive oxidation of the conductive layers 542a2 and 542b2 can be prevented. For example, silicon nitride can be used as the insulating layer 855.

[0340] The insulating layer 850 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 520. Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0341] The insulating layer 850 functions as a gate insulator. The insulating layer 850, together with the insulating layer 855 and the conductive layer 560, is provided in an opening formed in the insulating layer 885. To miniaturize the transistor 200G, the insulating layer 850 preferably has a small thickness. The thickness of each of the layers constituting the insulating layer 850 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each layer constituting the insulating layer 850 may have a region with the above thickness in at least a portion thereof.

[0342] The insulating layer 850 is preferably formed by an ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma-enhanced ALD method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0343] The thickness of the insulating layer 855 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and still more preferably 0.5 nm to 3 nm. By setting the insulating layer 855 to the above thickness, excessive oxidation of the conductive layer 542a2 and the conductive layer 542b2 can be suppressed. Note that the insulating layer 855 only needs to have a region with the above thickness in at least a portion. If the insulating layer 855 is made too thick, the time required for forming the insulating layer 855 by ALD increases, resulting in reduced productivity. Therefore, the thickness of the insulating layer 855 is preferably set to about the above range.

[0344] The insulating layer 815, the insulating layer 521, the insulating layer 522, the insulating layer 882, and the insulating layer 883 each preferably include an insulator that suppresses the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulating layer 883 and the insulating layer 521 are preferably made of silicon nitride, which has a high hydrogen barrier property. Furthermore, for example, the insulating layer 882 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulating layer 522 is preferably made of hafnium oxide, which is a high-dielectric-constant (high-k) material and has a high ability to capture or fix hydrogen.

[0345] The conductive layer 505 is disposed so as to overlap with the semiconductor layer 520 and the conductive layer 560. Here, the conductive layer 505 is preferably provided so as to be embedded in an opening formed in the insulating layer 816. Furthermore, the conductive layer 505 is preferably provided so as to extend in the channel width direction as shown in FIGS. 18A and 18C. With such a structure, when a plurality of transistors are provided, the conductive layer 505 functions as a wiring.

[0346] 18B and 18C , the conductive layer 505 preferably includes a conductive layer 505a and a conductive layer 505b. The conductive layer 505a is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 505b is provided so as to fill a recess in the conductive layer 505a formed along the opening. Here, the height of the upper surface of the conductive layer 505 coincides with or approximately coincides with the height of the upper surface of the insulating layer 816.

[0347] By using a conductive material that has a function of reducing hydrogen diffusion for the conductive layer 505a, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 through the insulating layer 816 or the like. Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 505a, oxidation of the conductive layer 505b and a decrease in conductivity can be suppressed. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 505a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 505a preferably contains titanium nitride.

[0348] The conductive layer 505b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0349] The conductive layer 505 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200G can be controlled by changing the potential applied to the conductive layer 505 independently of the potential applied to the conductive layer 560. In particular, applying a negative potential to the conductive layer 505 can increase the threshold voltage (Vth) of the transistor 200G and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 505 can reduce the drain current when the potential applied to the conductive layer 560 is 0 V compared to not applying a negative potential to the conductive layer 505.

[0350] The insulating layer 524 in contact with the semiconductor layer 520 preferably contains, for example, silicon oxide or silicon oxynitride, so that oxygen can be supplied from the insulating layer 524 to the semiconductor layer 520 and oxygen vacancies can be reduced.

[0351] The insulating layer 524 is preferably processed into an island shape, similar to the semiconductor layer 520. As a result, when a plurality of transistors 200G are provided, each transistor 200G has an insulating layer 524 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 524 to the semiconductor layer 520 in each transistor 200G becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200G within the substrate surface can be suppressed. However, this is not a limitation, and similar to the insulating layer 522, the insulating layer 524 may also be configured without being patterned.

[0352] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for each of the conductive layers 542a, 542b, and 560. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 542a, 542b, and 560.

[0353] The insulating layers 871a and 871b are inorganic insulators that function as etching stoppers and protect the conductive layers 542a2 and 542b2 when the conductive layers 542a2 and 542b2 are processed. Furthermore, since the insulating layers 871a and 871b are in contact with the conductive layers 542a2 and 542b2, they are preferably inorganic insulators that do not easily oxidize the conductive layers 542a and 542b. The insulating layers 871a and 871b preferably have a stacked structure of, for example, a nitride insulator and an oxide insulator.

[0354] The conductive layer 560 preferably includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, the conductive layer 560a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 560b. In this case, the conductive layer 560a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion. The conductive layer 560a has the function of suppressing oxygen diffusion, which can suppress oxidation of the conductive layer 560b due to oxygen contained in the insulating layer 885 or the like, which can reduce the conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0355] The conductive layer 560b is preferably formed using a conductor with high conductivity. For example, the conductive layer 560b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 560b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0356] The insulating layers 816 and 885 preferably have a dielectric constant lower than that of the insulating layer 522. When a material with a low dielectric constant is used as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0357] 19A shows a top view of a semiconductor device 30 according to one embodiment of the present invention. FIG. 19B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 19A , and FIG. 19C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG.

[0358] The semiconductor device 30 includes a transistor 300. The transistor 300 includes a conductive layer 180 over a substrate 102, an insulating layer 182 over the conductive layer 180, a semiconductor layer 184 over the insulating layer 182, and conductive layers 186a and 186b over the semiconductor layer 184. The conductive layer 180 has a region overlapping with the semiconductor layer 184 with the insulating layer 182 interposed therebetween. The conductive layer 180 functions as a gate electrode of the transistor 300, and the insulating layer 182 functions as a gate insulating layer. The conductive layer 186a functions as one of a source electrode and a drain electrode of the transistor 300, and the conductive layer 186b functions as the other of the source electrode and drain electrode.

[0359] The semiconductor layer 184 preferably contains indium oxide. For the semiconductor layer 184, the description of the semiconductor layer 108 can be referred to.

[0360] The conductive layer 186a and the conductive layer 186b have regions in contact with the semiconductor layer 184. A region of the semiconductor layer 184 in contact with the conductive layer 186a functions as one of the source region and the drain region. A region of the semiconductor layer 184 in contact with the conductive layer 186b functions as the other of the source region and the drain region. A region of the semiconductor layer 184 that overlaps with the conductive layer 180 with the insulating layer 182 interposed therebetween functions as a channel formation region.

[0361] In the region where the semiconductor layer 184 and the conductive layer 180 overlap, the shortest distance between the source region and the drain region is the channel length L of the transistor 300 (see FIG. 19B). Also, the width of the region where the semiconductor layer 184 and the conductive layer 180 overlap in a direction perpendicular to the channel length direction is the channel width W of the transistor 300 (see FIG. 19C).

[0362] The transistor 300 is a so-called bottom-gate transistor having a gate electrode below the semiconductor layer 184. In addition, conductive layers 186a and 186b functioning as a source electrode and a drain electrode are provided over the semiconductor layer 184. The transistor 300 can be referred to as a bottom-gate top-contact (BGTC) transistor.

[0363] The BGTC transistor can reduce the number of masks used in manufacturing the transistor, thereby reducing the manufacturing cost of the semiconductor device.

[0364] Note that there may be a recess in a region of the semiconductor layer 184 that does not overlap with either the conductive layer 186a or the conductive layer 186b. For example, the conductive layers 186a and 186b can be formed by depositing a conductive film that will become the conductive layer 186a and the conductive layer 186b over the semiconductor layer 184 and processing the conductive film. When processing the conductive film, part of the semiconductor layer 184 is removed, and thus a recess may be formed in the semiconductor layer 184.

[0365] An insulating layer 188 is provided over the transistor 300, and an insulating layer 189 is provided over the insulating layer 188. The insulating layer 188 and the insulating layer 189 function as protective layers for the transistor 300. The insulating layer 188 has a region between the conductive layer 186a and the conductive layer 186b that overlaps with the conductive layer 180 with the semiconductor layer 184 and the insulating layer 182 interposed therebetween. The insulating layer 188 preferably contains oxygen because it has a region in contact with the channel formation region. The insulating layer 188 can preferably use one or more of an oxide and an oxynitride. The insulating layer 188 can preferably use the materials listed for the insulating layer 110b. The insulating layer 189 preferably functions as a barrier film. By providing a barrier film, diffusion of impurities from the outside into the transistor can be effectively suppressed, resulting in a highly reliable semiconductor device. The above description can be referred to for the barrier film. Note that the insulating layer 188 can also function as a barrier film.

[0366] The insulating layer 182 has a region in contact with the semiconductor layer 184. When a metal oxide is used for the semiconductor layer 184, at least a part of the region of the insulating layer 182 in contact with the semiconductor layer 184 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 184 and the insulating layer 182. Specifically, the region of the insulating layer 182 in contact with the channel formation region of the semiconductor layer 184 preferably contains oxygen. One or more of an oxide and an oxynitride can be preferably used for the region of the insulating layer 182 in contact with the channel formation region of the semiconductor layer 184. The same applies to the insulating layer 188. For example, the insulating layer 182 and the insulating layer 188 each preferably contain silicon and oxygen. Silicon oxide or silicon oxynitride can be preferably used for the insulating layer 182 and the insulating layer 188.

[0367] 20A and 20B show examples of a structure different from those shown in FIGS. 19A to 19C . FIGS. 20A and 20B are cross-sectional views of a semiconductor device 30A according to one embodiment of the present invention. For a top view of the semiconductor device 30A, refer to FIG. 19A . FIG. 20A is a cross-sectional view of a section taken along dashed dotted line A1-A2 in FIG. 19A , and FIG. 20B is a cross-sectional view of a section taken along dashed dotted line A3-A4 in FIG.

[0368] The semiconductor device 30A includes a transistor 300A. The transistor 300A differs from the transistor 300 mainly in that the insulating layer 182 has a stacked structure.

[0369] 20A and 20B show an example in which the insulating layer 182 includes an insulating layer 182a and an insulating layer 182b on the insulating layer 182a.

[0370] The insulating layer 182b has a region in contact with the semiconductor layer 184. As described above, the insulating layer 182b in contact with the semiconductor layer 184 preferably contains oxygen.

[0371] The insulating layer 182a located on the conductive layer 180 side preferably functions as a barrier film. By providing the barrier film, it is possible to suppress diffusion of components (e.g., metals) contained in the conductive layer 180 or the substrate 102 into the transistor, thereby providing a highly reliable semiconductor device. The above description of the barrier film can be referred to. The insulating layer 182a preferably contains nitrogen.

[0372] The insulating layer 182a preferably contains silicon and nitrogen, and the insulating layer 182b preferably contains silicon and oxygen. For example, silicon nitride can be preferably used for the insulating layer 182a, and silicon oxynitride can be preferably used for the insulating layer 182b.

[0373] The configuration of the insulating layer 182 shown here can also be applied to other configuration examples.

[0374] 21A to 21C show examples of structures different from those shown in FIGS. 21A to 21C. Fig. 21A is a top view of a semiconductor device 30B according to one embodiment of the present invention. Fig. 21B is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in Fig. 21A, and Fig. 21C is a cross-sectional view of a cut surface taken along dashed dotted line A3-A4 in Fig. 21A.

[0375] The semiconductor device 30B includes a transistor 300B. The transistor 300B differs from the transistor 300 mainly in that the transistor 300B includes a conductive layer 185.

[0376] The conductive layer 185 is provided over the insulating layer 188. The conductive layer 185 functions as a back gate electrode of the transistor 300B. The conductive layer 185 is provided so as to overlap with the conductive layer 180 with the semiconductor layer 184 interposed therebetween. The conductive layer 185 is preferably provided so as to cover the entire channel formation region. This can enhance the effect of making an electric field generated outside the transistor less likely to act on the channel formation region (also referred to as an electric field shielding effect). The insulating layer 188 functions as a back gate insulating layer of the transistor 300B.

[0377] The structure of the conductive layer 185 shown here can also be applied to other structure examples.

[0378] 22A and 22B are cross-sectional views of a semiconductor device 30C according to one embodiment of the present invention. For a top view of the semiconductor device 30C, see FIG. 19A. FIG. 22A is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 19A , and FIG. 22B is a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG.

[0379] The semiconductor device 30C includes a transistor 300C. The transistor 300C differs from the transistor 300 shown in FIG.

[0380] The insulating layer 187 is provided over the semiconductor layer 184. The insulating layer 187 has a region overlapping with the conductive layer 180 with the semiconductor layer 184 and the insulating layer 182 interposed therebetween. Part of the conductive layer 186a and part of the conductive layer 186b are provided over the insulating layer 187.

[0381] The insulating layer 187 functions as a channel protective film that protects the channel formation region when the conductive layers 186a and 186b are formed. The insulating layer 187 is provided over the semiconductor layer 184, and a conductive film that will become the conductive layers 186a and 186b is formed on the insulating layer 187. The conductive film is then processed to form the conductive layers 186a and 186b. Since the channel formation region is not exposed during the formation and processing of the conductive film, damage to the channel formation region can be suppressed. Therefore, a transistor with favorable electrical characteristics can be obtained. Note that a transistor having a channel protective film (e.g., the transistor 300C) can be referred to as a channel protective transistor. On the other hand, a transistor without a channel protective film (e.g., the transistor 300 and the transistor 300B) can be referred to as a channel-etched transistor.

[0382] 23A and 23B show examples of a structure different from those shown in FIGS. 22A and 22B . FIG. 23A is a top view of a semiconductor device 30D according to one embodiment of the present invention. FIG. 23B is a cross-sectional view of the cross section taken along dashed dotted line A1-A2 in FIG. 23A . For a cross-sectional view of the cross section taken along dashed dotted line A3-A4, refer to FIG. 22B .

[0383] The semiconductor device 30D includes a transistor 300D. The transistor 300D differs from the transistor 300C shown in FIG. 22A and other drawings mainly in that the insulating layer 187 has an opening 181a and an opening 181b.

[0384] The insulating layer 187 has openings 181a and 181b that reach the semiconductor layer 184. Conductive layers 186a and 186b are provided so as to cover the openings 181a and 181b. The conductive layer 186a has a region in contact with the semiconductor layer 184 in the opening 181a, and the conductive layer 186b has a region in contact with the semiconductor layer 184 in the opening 181b.

[0385] The insulating layer 187 has a region in contact with the semiconductor layer 184. At least a part of the region of the insulating layer 187 in contact with the semiconductor layer 184 preferably contains oxygen. For example, the insulating layer 187 preferably contains silicon and oxygen. Silicon oxide or silicon oxynitride can be suitably used for the insulating layer 187.

[0386] The configuration of the insulating layer 187 shown here can also be applied to other configuration examples.

[0387] 24A shows a top view of a semiconductor device 30E according to one embodiment of the present invention. FIG. 24B shows a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 24A. FIG. 19C shows a cross-sectional view taken along dashed dotted line A3-A4.

[0388] The semiconductor device 30E includes a transistor 300E. The transistor 300E differs from the transistor 300 shown in FIG. 19B and the like mainly in that the conductive layer 186a and the conductive layer 186b are located between the semiconductor layer 184 and the insulating layer 182.

[0389] The transistor 300E is a so-called bottom-gate transistor. The semiconductor layer 184 is provided over the conductive layers 186a and 186b, which function as a source electrode and a drain electrode. The transistor 300E can be referred to as a bottom-gate bottom-contact (BGBC) transistor.

[0390] Since the semiconductor layer 184 is formed after the conductive layers 186a and 186b are formed, damage to the semiconductor layer 184 can be prevented when the conductive layers 186a and 186b are formed.

[0391] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0392] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described.

[0393] 25A to 27C show a cross-sectional view taken along dashed line A1-A2 in FIG. 1A and a cross-sectional view taken along dashed line B1-B2 in FIG. 1A.

[0394] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0395] Next, a conductive film to be the conductive layer 112a is formed over the insulating layer 109 and processed to form the conductive layer 112a (FIG. 25A). The conductive film can be formed by a sputtering method.

[0396] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a (FIG. 25B).

[0397] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, it is preferable to form the insulating film 110bf continuously using the same device after forming the insulating film 110af.

[0398] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating films 110af and 110bf within the above-described range, the amount of impurities (e.g., water and hydrogen) released from the insulating films 110af and 110bf can be reduced, and the diffusion of the impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0399] Since the insulating films 110af and 110bf are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to heat applied when the insulating films 110af and 110bf are formed.

[0400] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0401] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. Examples of methods for supplying oxygen include ion implantation, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ The plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, carbon monoxide, and carbon dioxide. The amount of oxygen supplied can be adjusted by, for example, the power and treatment time in the plasma treatment.

[0402] After the insulating film 110bf is formed, nitrogen can be supplied to the insulating film 110bf. The nitrogen supply method can be referred to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO ２ The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0403] In the insulating layer (here, the insulating film 110bf or the later insulating layer 110b), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ , X is a real number greater than 0). ２ O, NO and NO ２ In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level at which the charge of the indium oxide changes between a 0 state and a -1 state is located within the band gap of indium oxide. Therefore, when nitrogen oxide diffuses to the interface between the insulating layer and the semiconductor layer having the metal oxide or near the interface, the level traps electrons. As a result, the trapped electrons remain at the interface between the insulating layer and the semiconductor layer or near the interface, and the threshold voltage of the transistor can be increased in the positive direction. This allows a normally-off transistor to be obtained, resulting in a semiconductor device with low power consumption.

[0404] Increasing the amount of nitrogen oxide can increase the threshold voltage to the positive side. However, if the amount of nitrogen oxide is too large, the threshold voltage may fluctuate greatly when a positive potential (positive bias) is applied to the gate of the transistor, which may result in reduced reliability. Therefore, it is preferable to use a nitrogen oxide amount within a range that does not affect reliability.

[0405] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of desorption in thermal desorption spectrometry (TDS) or the amount of electron spin in electron spin resonance (ESR). In TDS, NO (mass-to-charge ratio (m / z) = 30), N ２ O (m / z=44), and NO ２ The amount of NO (m / z = 46) desorbed can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２ Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２ Since the molecule has a lone electron, it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４ The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0406] The order of the treatment for supplying oxygen and the treatment for supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same treatment. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N ２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0407] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0408] Next, a film 139 is preferably formed on the insulating film 110bf ( FIG. 25D ). The film 139 can be formed by a sputtering method. By forming the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf. FIG. 25C shows a schematic diagram of oxygen being supplied to the insulating film 110bf using solid arrows.

[0409] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 139.

[0410] The film 139 is preferably formed using an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108.

[0411] When forming the film 139, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the ratio of the flow rate of oxygen gas to the total film formation gas introduced into the processing chamber of the film formation apparatus (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber. The oxygen flow rate ratio or the oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0412] In this way, by forming the film 139 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 139, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be confined in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0413] Heat treatment may be performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf.

[0414] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. If the temperature of the heat treatment is too low, the amount of oxygen supplied from the film 139 to the insulating film 110bf decreases, and oxygen vacancies and V in the semiconductor layer 108 are formed. Ｏ On the other hand, if the temperature of the heat treatment is too high, the productivity may decrease and deformation (distortion or warpage) of the substrate may occur. By setting the temperature of the heat treatment in the above range, oxygen vacancies and V in the semiconductor layer 108 may be reduced. ＯH can be effectively reduced. Furthermore, productivity can be improved and deformation (distortion or warpage) of the substrate can be suppressed. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or less, preferably −100° C. or less. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being incorporated into the insulating film 110af and the insulating film 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, or the like. Using an RTA apparatus can shorten the heat treatment time.

[0415] After the film 139 is formed or after the heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 139. Oxygen can be supplied by, for example, ion implantation, plasma immersion ion implantation, or plasma treatment. The above description of the plasma treatment can be referred to, and therefore, detailed description thereof will be omitted.

[0416] Next, the film 139 is removed ( FIG. 25E ). There is no particular limitation on the method for removing the film 139, but wet etching is preferably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 139. This prevents the thickness of the insulating film 110bf from becoming thin, and allows the thickness of the insulating layer 110b to be made uniform.

[0417] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0418] Next, an insulating film 110cf that will become the insulating layer 110c and an insulating film 110ef that will become the insulating layer 110e are formed on the insulating film 110bf ( FIG. 26A ). The insulating film 110cf can be preferably formed by sputtering. The description of the formation of the insulating film 110af and the insulating layer 109 can be referred to for the formation of the insulating film 110cf and the insulating film 110ef, and therefore detailed description thereof will be omitted.

[0419] Next, a conductive film 112bf to be the conductive layer 112b is formed over the insulating film 110ef (FIG. 26B). The conductive film 112bf can be preferably formed by sputtering.

[0420] Next, the conductive film 112bf is processed to form the conductive layer 112B (FIG. 26C). The conductive layer 112B will later become the conductive layer 112b. The conductive layer 112B can be preferably formed by, for example, wet etching.

[0421] Subsequently, a part of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143. The conductive layer 112b can be preferably formed by wet etching.

[0422] Subsequently, parts of the insulating films 110af, 110bf, and 110cf are removed to form the insulating layer 110 having an opening 141 ( FIG. 26D ). The opening 141 is provided in a region overlapping with the opening 143. The formation of the opening 141 exposes the conductive layer 112a. The insulating layer 110 can be preferably formed by dry etching.

[0423] The opening 141 can be formed using, for example, the resist mask used to form the opening 143. Specifically, a resist mask is formed over the conductive layer 112B, part of the conductive layer 112B is removed using the resist mask to form the opening 143, and part of the insulating films 110af, 110bf, and 110cf is removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the resist mask used to form the opening 143.

[0424] Next, a metal oxide film 108f to be the semiconductor layer 108 is formed so as to cover the openings 141 and 143 ( FIG. 27A ). The metal oxide film 108f is provided in contact with the upper and side surfaces of the conductive layer 112b, the upper and side surfaces of the insulating layer 110, and the upper surface of the conductive layer 112a.

[0425] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method. By using the ALD method, a metal oxide film can be formed with high coverage on the side surfaces of the insulating layer 110 and the conductive layer 112b. Furthermore, the ALD method allows easy control of the film formation rate, and thus allows thin films to be formed with high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Alternatively, the CVD method can be used to form the metal oxide film 108f.

[0426] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0427] Oxygen gas is preferably used when the metal oxide film 108f is formed. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0428] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 in a later step, and oxygen vacancies and V Ｏ H can be reduced.

[0429] When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film, the more the crystallinity of the metal oxide film can be improved, and a highly reliable transistor can be realized. In addition, when forming the metal oxide film, a gas containing a hydrogen element (e.g., H ２ or H ２ As a deposition gas for the metal oxide film, for example, a mixture of oxygen gas, hydrogen gas, and argon gas can be used.

[0430] The higher the substrate temperature during deposition of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor.

[0431] The substrate temperature during deposition of the metal oxide film 108f is preferably from room temperature (e.g., 25°C) to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, setting the substrate temperature from room temperature to 140°C is preferable because it increases productivity. Alternatively, the metal oxide film can be deposited at room temperature or without heating the substrate.

[0432] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0433] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0434] For example, when forming an indium oxide film, a precursor containing indium can be used, such as triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]indium.

[0435] Oxidizing agents include, for example, ozone, oxygen, hydrogen peroxide, and water.

[0436] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is possible to form a metal oxide film 108f whose composition changes continuously.

[0437] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0438] Subsequently, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 (FIG. 27B).

[0439] The semiconductor layer 108 can be preferably formed by wet etching. At this time, a part of the conductive layer 112b in a region that does not overlap with the semiconductor layer 108 may be etched and thinned. Similarly, a part of the insulating layer 110 in a region that does not overlap with either the semiconductor layer 108 or the conductive layer 112b may be etched and thinned. For example, the insulating layer 110c of the insulating layer 110 may be removed by etching, and the surface of the insulating layer 110b may be exposed. Note that, in etching the metal oxide film 108f, using a material with a high etching selectivity for the insulating layer 110c can prevent the insulating layer 110c from becoming thin.

[0440] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108. Heat treatment can remove hydrogen and water contained in or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108. Furthermore, heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (e.g., reduce defects or improve crystallinity). The above-described description can be referred to for the heat treatment. If the heat treatment temperature is too low, the effects of removing hydrogen and water and improving film quality may be reduced. On the other hand, if the heat treatment temperature is too high, productivity may be reduced and deformation (distortion or warpage) of the substrate may occur. Setting the heat treatment temperature within the above-described range can effectively reduce hydrogen and water contained in or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108. Furthermore, productivity may be increased and deformation (distortion or warpage) of the substrate may be suppressed.

[0441] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108.

[0442] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a process in which heat is applied in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0443] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110 (FIG. 27C). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0444] When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing from above the insulating layer 106 to the conductive layer 104, thereby suppressing oxidation of the conductive layer 104. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0445] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108, causing oxygen vacancies and V in the semiconductor layer 108. Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0446] Before forming the insulating layer 106, plasma treatment can be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0447] Subsequently, the conductive layer 104 is formed over the insulating layer 106 (FIGS. 6A and 6B). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0448] Subsequently, an insulating layer 218 is formed. The insulating layer 218 can be preferably formed by a PECVD method.

[0449] Through the above steps, the semiconductor device 10B of one embodiment of the present invention can be manufactured.

[0450] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0451] Embodiment 2 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0452] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0453] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0454] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0455] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0456] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0457] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0458] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0459] <Configuration Example 1 of Display Device> FIG. 28A shows a perspective view of a display device 50A.

[0460] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 28A, the substrate 152 is indicated by a dashed line.

[0461] The display device 50A includes a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 28A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 28A can also be said to be a display module including the display device 50A, an IC, and an FPC.

[0462] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 28A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0463] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0464] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0465] 28A shows an example in which an IC 173 is provided on a substrate 151 by a COG method. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0466] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0467] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0468] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 28A shows an enlarged view of one pixel 201.

[0469] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0470] 28A includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the number of sub-pixels included in one pixel is not particularly limited.

[0471] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0472] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0473] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0474] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0475] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0476] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0477] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0478] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0479] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0480] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0481] 28B is a block diagram illustrating a display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or greater). The circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232. The circuit unit 164 can be referred to as a drive circuit unit.

[0482] The circuit included in the first driver circuit unit 231 functions as, for example, a scanning line driver circuit (also referred to as a gate line driver circuit, gate driver, scan driver, or row driver). The circuit included in the second driver circuit unit 232 functions as, for example, a signal line driver circuit (also referred to as a source line driver circuit, source driver, data driver, or column driver). Note that some kind of circuit may be provided at a position facing the first driver circuit unit 231 across the display unit 162. Some kind of circuit may be provided at a position facing the second driver circuit unit 232 across the display unit 162.

[0483] The circuit portion 164 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. A transistor, a capacitor, or the like can be used for the circuit portion 164. The transistors included in the circuit portion 164 can be formed in the same process as the transistors included in the pixel 230.

[0484] The display device 50A has wirings 236 that are arranged parallel or approximately parallel to each other and whose potential is controlled by a circuit included in a first drive circuit unit 231, and wirings 238 that are arranged parallel or approximately parallel to each other and whose potential is controlled by a circuit included in a second drive circuit unit 232. Note that Fig. 28B shows an example in which wirings 236 and 238 are connected to pixel 230. However, wirings 236 and 238 are just an example, and wirings connected to pixel 230 are not limited to wirings 236 and 238.

[0485] 28B , the direction in which the wiring 236 extends may be referred to as the row direction, and the direction in which the wiring 238 extends may be referred to as the column direction. Note that although the horizontal direction in the drawing is the row direction and the vertical direction is the column direction, this is not limiting, and the row direction and the column direction may be interchanged.

[0486] 29A shows an example of the configuration of a pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

[0487] The pixel circuit 51 includes a transistor 52A, a transistor 52B, and a capacitor 53. The pixel circuit 51 is a 2Tr1C pixel circuit including two transistors and one capacitor. Note that there is no particular limitation on the pixel circuit that can be applied to the display device of one embodiment of the present invention.

[0488] The anode of the light-emitting device 61 is connected to one of the source and drain of the transistor 52B and one electrode of the capacitor 53. The other of the source and drain of the transistor 52B is connected to a wiring ANO. The gate of the transistor 52B is connected to one of the source and drain of the transistor 52A and the other electrode of the capacitor 53. The other of the source and drain of the transistor 52A is connected to a wiring SL. The gate of the transistor 52A is connected to a wiring GL. The cathode of the light-emitting device 61 is connected to a wiring VCOM.

[0489] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting device 61. The transistor 52A has a function of controlling the conduction or non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0490] In this specification and the like, a high power supply potential VDD (also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. Also, a low power supply potential VSS (also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. Also, a ground potential GND (also simply referred to as "GND") can be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0491] The transistor 52A functions as a selection transistor for controlling the selection state of the pixel 230. The transistor 52B functions as a drive transistor for controlling the amount of current flowing through the light-emitting device 61. The capacitance element 53 has a function of maintaining the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting device 61 is controlled in accordance with an image signal supplied to the gate of the transistor 52B.

[0492] The above-described semiconductor device can be used for the pixel circuit 51. This allows the area occupied by the pixel circuit 51 to be reduced, resulting in a high-definition display device. In addition, the display device can operate at high speed.

[0493] By using a plurality of transistors and capacitors in a pixel circuit, a high-performance display device can be provided. By applying the semiconductor device of one embodiment of the present invention, the occupied area can be reduced even when the number of transistors and capacitors is increased, and a high-performance and high-resolution display device can be provided. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be provided.

[0494] Since the semiconductor device according to one embodiment of the present invention can occupy a small area, the aperture ratio of a pixel in a bottom-emission display device can be increased. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0495] In this specification and the like, the aperture ratio refers to the ratio of the area of ​​the region through which light is emitted to the area of ​​the pixel.

[0496] 29B shows an example of a configuration different from that of the pixel 230 shown in FIG. 29A. The pixel 230 has a pixel circuit 51A and a light-emitting device 61.

[0497] The pixel circuit 51A differs from the pixel circuit 51 shown in FIG. 29A mainly in that the anode of the light-emitting device 61 is connected to the line ANO.

[0498] One of the source and drain of the transistor 52B and one electrode of the capacitor 53 are connected to the wiring VCOM. The cathode of the light-emitting device 61 is connected to the other of the source and drain of the transistor 52B.

[0499] In the pixel circuit 51A, the source potential of the transistor 52B functioning as a driving transistor is the potential of the wiring VCOM, so that fluctuations in the voltage (Vgs) between the gate and source of the transistor 52B can be suppressed, thereby reducing variations in luminance.

[0500] 29C shows an example of a configuration different from that of the pixel 230 shown in FIG. 29A. The pixel 230 has a pixel circuit 51B and a light-emitting device 61.

[0501] 29A in that the pixel circuit 51B includes a transistor 52C. The pixel circuit 51B includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51B is a 3Tr1C type pixel circuit including three transistors and one capacitor.

[0502] One of the source and drain of the transistor 52C is connected to one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52C is connected to a wiring V0. For example, a reference potential is supplied to the wiring V0. The gate of the transistor 52C is connected to a wiring GL.

[0503] The transistor 52C has a function of controlling conduction or non-conduction between the wiring V0 and one of the source electrode and the drain electrode of the transistor 52B based on the potential of the wiring GL. The reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source potential of the transistor 52B.

[0504] The wiring V0 can be used to obtain a current value that can be used to set pixel parameters. Specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.

[0505] A backgate can be provided in some or all of the transistors included in the pixel circuit 51. A pixel circuit 51C shown in FIG. 29D illustrates a configuration in which the transistor 52B in the pixel circuit 51 shown in FIG. 29A has a backgate connected to one of the source and drain of the transistor 52B. A pixel circuit 51D shown in FIG. 29E illustrates a configuration in which the transistor 52B in the pixel circuit 51B shown in FIG. 29C has a backgate connected to one of the source and drain of the transistor 52B. This can improve reliability. Note that the backgate of the transistor 52B can also be connected to the gate of the transistor 52B. This can increase the on-state current of the transistor 52B.

[0506] 30A shows an example of a configuration different from the above-described pixel 230. The pixel 230 has a pixel circuit 51E and a light-emitting device 61.

[0507] The pixel circuit 51E includes transistors M21, M22, and M23, and a capacitor C21. The pixel circuit 51E is a 3Tr1C pixel circuit having three transistors and one capacitor. One of the source and drain of the transistor M21 is connected to a wiring SL. One of the source and drain of the transistor M22 is connected to a wiring ANO. One of the source and drain of the transistor M23 is connected to a wiring V0. The other of the source and drain of the transistor M21 is connected to the gate of the transistor M22 and one electrode of the capacitor C21. The other of the source and drain of the transistor M22 is connected to the other of the source and drain of the transistor M23, the other electrode of the capacitor C21, and the anode of the light-emitting device 61. The cathode of the light-emitting device 61 is connected to a wiring VCOM.

[0508] The gate of the transistor M21 is connected to the wiring GL11. The gate of the transistor M23 is connected to the wiring GL12. By connecting the gate of the transistor M21 to a wiring different from the wiring to which the gate of the transistor M23 is connected, potentials of different magnitudes can be applied to the gate of the transistor M21 and the gate of the transistor M23, respectively, and these transistors can operate independently.

[0509] The transistor M21 functions as a selection transistor, the transistor M22 functions as a drive transistor, and the capacitive element C21 has a function of holding the gate potential of the transistor M22. The intensity of light emitted by the light-emitting device 61 is controlled in accordance with an image signal supplied to the gate of the transistor M22. For the transistor M23, the description of the transistor 52C can be referred to.

[0510] 30B shows an example of a configuration different from the above-described pixel 230. The pixel 230 has a pixel circuit 51F and a light-emitting device 61.

[0511] The pixel circuit 51F includes a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a capacitor C11, and a capacitor C12. The pixel circuit 51F is a 6Tr2C type pixel circuit including six transistors and two capacitors.

[0512] The anode of the light-emitting device 61 is connected to one of the source and drain of the transistor M15. The cathode of the light-emitting device 61 is connected to the wiring VCOM. The other of the source and drain of the transistor M15 is connected to one of the source and drain of the transistor M12, one of the source and drain of the transistor M13, one of the source and drain of the transistor M16, one electrode of the capacitance element C11, and one electrode of the capacitance element C12. The gate of the transistor M12 is connected to one of the source and drain of the transistor M11, the other of the source and drain of the transistor M13, and the other electrode of the capacitance element C11. The back gate of the transistor M12 is connected to one of the source and drain of the transistor M14 and the other electrode of the capacitance element C12.

[0513] The other of the source and drain of transistor M11 is connected to wiring SL. The other of the source and drain of transistor M12 is connected to wiring ANO. The other of the source and drain of transistor M14 is connected to wiring V0. The other of the source and drain of transistor M16 is connected to wiring V1. For example, a constant potential is supplied to wiring V1. The gates of transistors M11 and M16 are connected to wiring GL1. The gates of transistors M13 and M14 are connected to wiring GL2. The gate of transistor M15 is connected to wiring GL3.

[0514] The transistor M11 functions as a selection transistor that controls the conductive state or non-conductive state between the gate of the transistor M12 and the wiring SL. The transistor M12 functions as a drive transistor that controls the current flowing through the light-emitting device 61. The transistor M14 changes the potential supplied from the wiring V0 to a potential corresponding to the threshold voltage of the transistor M12 and supplies the changed potential to the back gate of the transistor M12. The threshold voltage can be controlled by supplying a constant potential to the back gate of the transistor M12. The capacitor C11 maintains the gate potential (potential difference between the gate and source) of the transistor M12. The capacitor C12 maintains the back gate potential (potential difference between the back gate and source) of the transistor M12. The pixel circuit 51F has a so-called internal threshold voltage correction function that corrects the threshold voltage of the transistor M12 using the back gate. Specifically, the capacitor C12 maintains a back gate potential such that the threshold voltage of the transistor M12 becomes 0 V. This makes it possible to correct the threshold voltage of the transistor M12 to a constant value of 0 V or near 0 V, regardless of variations in the threshold voltage of the transistor and deterioration over time.

[0515] 31A shows an example of a configuration different from the above-described pixel 230. The pixel 230 includes a pixel circuit 51G and a liquid crystal device 62.

[0516] The pixel circuit 51G includes a transistor 52A and a capacitor 53. One of the source and drain of the transistor 52A is connected to a wiring SL, and the gate of the transistor 52A is connected to a wiring GL. The other of the source and drain of the transistor 52A is connected to one electrode of the capacitor 53 and the liquid crystal device 62. The other electrode of the capacitor 53 is connected to a wiring VCOM.

[0517] A pixel circuit 51H shown in Fig. 31B may have a back gate in the transistor 52A, in which the back gate of the transistor 52A is connected to the gate.

[0518] <Configuration Example of Circuit Unit> A configuration example of the circuit unit 164 will be described.

[0519] FIG. 32 shows a block diagram of a semiconductor device 90 applicable to the circuit portion 164. The semiconductor device 90 includes a shift register portion 91, a latch portion 93, and an amplifier portion 95. The semiconductor device 90 can be applied to, for example, a source driver having a light-emitting element as a display element. The source driver can be provided in, for example, the second driver circuit portion 232. One or more of the semiconductor devices 10 to 10C, 20 to 20G, and 30 to 30E described in Embodiment 1 can be suitably used for the semiconductor device 90. This allows the semiconductor device to operate at high speed. When the semiconductor device 90 is applied to a driver portion of a display device, the display device can operate at high speed. In particular, the transistor 100, which is a VFET, is suitable because it has a short channel length and a large on-state current.

[0520] The shift register unit 91 is connected to a wiring SP, a plurality of wirings CLK, and a plurality of wirings PWC. The shift register unit 91 is also connected to a latch unit 93 via a plurality of wirings SOUT. The latch unit 93 is connected to a wiring SELA, a wiring PRE, and a plurality of wirings DATA. The latch unit 93 is also connected to an amplifier unit 95 via a plurality of wirings LATOUT. The amplifier unit 95 is also connected to a wiring SELB and a wiring LRES. The amplifier unit 95 is also connected to a plurality of wirings SL.

[0521] The shift register unit 91 has a function of sequentially outputting signals to the wiring SOUT in response to signals input via the wirings SP, CLK, and PWC. The wiring SP is a wiring to which a start pulse signal is applied, which serves as a trigger for starting the operation of sequentially outputting signals. The multiple wirings CLK are each a wiring to which a clock signal whose potential changes periodically with different phases from each other is applied. The multiple wirings PWC are each a wiring to which a clock signal whose potential changes periodically with different phases from each other is applied.

[0522] The latch unit 93 has a function of storing and holding potentials input via a plurality of wirings DATA, triggered by signals sequentially input from the wiring SOUT, and outputting the potentials to the wiring LATOUT. That is, the latch unit 93 has a function of a sample-and-hold circuit. The wiring DATA is a wiring to which a data potential corresponding to image data to be displayed on the display device is applied. A digital signal or an analog signal can be used as the image data. The wiring SELA is a wiring to which a selection signal is supplied. The wiring PRE is a wiring to which a precharge signal is supplied.

[0523] Note that as the resolution of a display device increases, the pixel pitch decreases and the spacing between the wirings SL also decreases. Furthermore, as the number of terminals connecting the wirings SL to an IC (e.g., IC 173) increases, the spacing between the terminals decreases, which may make it difficult to mount the IC. Therefore, by using analog signals as image data, the number of terminals can be reduced, making it easier to mount the IC. The wiring SELA is a wiring to which a selection signal is supplied. The wiring LRES is a wiring to which a reset signal is supplied.

[0524] The amplifier portion 95 has a function of outputting a potential corresponding to the potential of the wiring LATOUT to the wiring SL.

[0525] By applying the semiconductor device 90 to a source driver, a display device can be realized that uses line-sequential driving, which drives pixels row by row. Note that the configuration of the source driver is not particularly limited, and for example, a display device that uses point-sequential driving can be realized without providing the latch unit 93.

[0526] An example configuration of a semiconductor device 90 is shown in FIG. 33. The shift register section 91 has multiple register sections 92. The latch section 93 has multiple latch unit sections 94. The amplifier section 95 has multiple amplifier unit sections 96. Note that in FIG. 33, to avoid cluttering the diagram, the same reference numerals are used for the register sections 92 of the shift register section 91. The same applies to the latch unit sections 94, amplifier unit sections 96, wiring SOUT, wiring LATOUT, and wiring SL.

[0527] FIG. 34A shows an example of a circuit diagram of the shift register unit 91. The shift register unit 91 is connected to a wiring CLK, a wiring PWC, and a wiring SP. The register units 92 are connected to each other via wiring SR. FIG. 34A shows the register units 92_1, 92_w-1 (where w is an integer greater than or equal to 3), 92_w, 92_w+1, and 92_w+2 as the multiple register units 92 included in the shift register unit 91. Furthermore, wiring SR_1, wiring SR_w-2, wiring SR_w-1, wiring SR_w, wiring SR_w+1, and wiring SR_w+2 are shown as the wiring SR. The register unit 92_w is connected to register units 92_w-1 and 92_w-3 (not shown) via wiring SR_w-1. The register unit 92_w is connected to the register unit 92_w+1 and the register unit 92_w-2 (not shown) via the wiring SR_w. The register unit 92_w is also connected to the register unit 92_w+2 and the register unit 92_w+3 (not shown) via the wiring SR_w+2. That is, the register unit 92_w is connected to the register unit 92_w-3, the register unit 92_w-2, the register unit 92_w-1, the register unit 92_w+1, the register unit 92_w+2, and the register unit 92_w+3. Note that the connections between the register units 92 are not limited to the configuration shown in FIG. 34A .

[0528] 34B is a circuit diagram illustrating an example configuration of the register unit 92. The register unit 92 includes a transistor M51, a transistor M52, a transistor M53, a transistor M54, a transistor M55, a transistor M56, a transistor M57, a transistor M58, a transistor M59, a transistor M60, a transistor M61, a transistor M62, a transistor M63, a capacitance element C51, a capacitance element C52, and a capacitance element C53.

[0529] One of the source and drain of transistor M51 is connected to one of the source and drain of transistor M63, one of the source and drain of transistor M56, and one of the source and drain of transistor M58. FIG. 34B shows a wiring NL51 connecting these. The gate of transistor M63 is connected to one of the source and drain of transistor M52, one of the source and drain of transistor M54, one of the source and drain of transistor M55, the gate of transistor M60, the gate of transistor M61, one of the source and drain of transistor M62, and one electrode of capacitor C51. FIG. 34B shows a wiring NL53 connecting these. The other of the source and drain of transistor M52 is connected to one of the source and drain of transistor M53. The other of the source and drain of transistor M56 is connected to the gate of transistor M57 and one electrode of capacitor C52. One of the source and drain of transistor M57 is connected to one of the source and drain of transistor M61 and the other electrode of capacitor C52. The other of the source and drain of transistor M58 is connected to the gate of transistor M59 and one electrode of capacitor C53. One of the source and drain of transistor M59 is connected to one of the source and drain of transistor M60 and the other electrode of capacitor C53.

[0530] The gate of the transistor M51 is connected to the wiring LIN, and the other of the source and drain is connected to the wiring SVDD. The transistor M51 has a function of bringing the wiring NL51 and the wiring SVDD into a conductive state or a non-conductive state depending on the potential of the wiring LIN. The gate of the transistor M62 is connected to the wiring LIN, and the other of the source and drain is connected to the wiring SVSS. The transistor M62 has a function of bringing the wiring NL53 and the wiring SVSS into a conductive state or a non-conductive state depending on the potential of the wiring LIN. The wiring LIN is connected to the wiring SROUT of the register unit 92 in the previous stage.

[0531] The gate of the transistor M54 is connected to the wiring RIN, and the other of the source and drain is connected to the wiring SVDD. The transistor M54 has a function of bringing the wiring NL53 and the wiring SVDD into a conductive state or a non-conductive state depending on the potential of the wiring RIN. The transistor M54 has a function of bringing the wiring NL53 and the wiring SVDD into a conductive state or a non-conductive state depending on the potential of the wiring RIN. The wiring RIN is connected to the wiring SROUT of the register unit 92 one stage later or two stages later.

[0532] The gate of the transistor M56 is connected to the wiring SVDD. The other of the source and drain of the transistor M57 is connected to the wiring CLK1. One of the source and drain of the transistor M57 and the other electrode of the capacitor C52 are connected to the wiring SROUT. The capacitor C52 can be referred to as a bootstrap capacitance.

[0533] The gate of the transistor M58 is connected to the wiring SVDD. The other of the source and drain of the transistor M59 is connected to the wiring PWC1. One of the source and drain of the transistor M59 and the other electrode of the capacitor C53 are connected to the wiring SOUT. The capacitor C53 can be referred to as a bootstrap capacitance.

[0534] Here, when the potential H is transmitted from the wiring CLK1 to the wiring SROUT, a potential decrease due to the threshold voltage of the transistor M57 may occur. However, the capacitive coupling by the bootstrap capacitance allows the transistor M57 to be maintained in an on state. Therefore, the potential decrease due to the threshold voltage can be suppressed, and the potential H can be transmitted to the wiring SROUT. Similarly, when the potential H is transmitted from the wiring PWC1 to the wiring SOUT, a potential decrease due to the threshold voltage may occur in the transistor M59. However, the capacitive coupling by the bootstrap capacitance allows the transistor M59 to be maintained in an on state. Therefore, the potential decrease due to the threshold voltage can be suppressed, and the potential H can be transmitted to the wiring SOUT.

[0535] The other of the source and the drain of the transistor M60 is connected to the wiring SVSS. The transistor M60 has a function of bringing the wiring SVSS and the wiring SOUT into a conductive state or a non-conductive state depending on the potential of the wiring NL53.

[0536] The other of the source and the drain of the transistor M61 is connected to the wiring SVSS. The transistor M61 has a function of bringing the wiring SVSS and the wiring SROUT into a conductive state or a non-conductive state depending on the potential of the wiring NL53.

[0537] The gate of the transistor M55 is connected to the wiring SRES, and the other of the source and drain is connected to the wiring SVDD. The transistor M55 has a function of bringing the wiring SVDD and the wiring NL53 into a conductive state or a non-conductive state depending on the potential of the wiring SRES.

[0538] A gate of the transistor M52 is connected to the wiring CLK2. A gate of the transistor M53 is connected to the wiring CLK3, and the other of the source and the drain is connected to the wiring SVDD.

[0539] The other electrode of the capacitor C51 is connected to the wiring SVSS. The capacitor C51 has a function of holding the potential of the wiring NL53.

[0540] For example, the wiring SVDD can function as a high-potential power supply line, and the wiring SVSS can function as a low-potential power supply line. For example, a reset signal is supplied to the wiring SRES. The wirings CLK1, CLK2, and CLK3 each correspond to one of the above-described multiple wirings CLK. The wiring PWC1 corresponds to one of the above-described multiple wirings PWC.

[0541] It is preferable to use transistors with long channel lengths for the transistors M62 and M63. FIG. 35 shows a configuration example different from that of the shift register unit 91 shown in FIG. 34B . The shift register unit 91 shown in FIG. 35 includes transistors M62a and M62b instead of the transistor M62, and transistors M63a and M63b instead of the transistor M63. The transistors M62a and M62b are connected in series and correspond to the transistor M62 shown in FIG. 34B . The transistors M63a and M63b are connected in series and correspond to the transistor M63 shown in FIG. 34B . Using transistors connected in series can increase the channel length of the transistors, thereby reducing the leakage current of the transistors. This allows signals to be held more stably in the shift register unit 91. For example, a semiconductor device 10C in which VFETs are connected in series can be used as a transistor with a long channel length (see FIGS. 7A to 10 ). Note that although the structure in which two transistors are connected in series is shown here, one embodiment of the present invention is not limited to this; a structure in which three or more transistors are connected in series can also be used.

[0542] The semiconductor device 90 can suitably use one or more of the semiconductor devices 10 to 10C, 20 to 20G, and 30 to 30E described in Embodiment 1. This allows a semiconductor device that operates at high speed. Furthermore, a semiconductor device that occupies a small area can be obtained. By applying the semiconductor device to a circuit portion of a display device, a display device that operates at high speed and has a narrow frame can be obtained.

[0543] In a VFET, the parasitic capacitance between the upper electrode and the gate electrode may be larger than the parasitic capacitance between the lower electrode and the gate electrode. For example, in the transistor 100 shown in FIG. 1A, the parasitic capacitance between the conductive layer 112b and the conductive layer 104 may be larger than the parasitic capacitance between the conductive layer 112b and the conductive layer 104. In this case, it is preferable to configure the upper electrode to be connected to the wiring NL53, which serves as a floating node. This can make the holding operation in the shift register unit 91 more stable. In FIG. 36, the upper electrodes of each transistor are indicated by thick lines. As shown in FIG. 36, the upper electrodes of the transistors M54 and M55 are connected to the wiring NL53, which can make the holding operation more stable. Furthermore, the upper electrodes of the transistors M57 and M59 are connected to the wiring SROUT and the wiring SOUT, respectively, which can increase the capacitances of the capacitors C52 and C53, which function as bootstrap capacitances. The capacitance of the capacitor C51 can be increased by connecting the top electrodes of the transistors M61 and M60 to the wirings SVSS.

[0544] 37A is a circuit diagram illustrating an example configuration of the latch unit section 94. The latch unit section 94 has a transistor M71, a transistor M72, a transistor M73, a transistor M74, a transistor M75, a capacitance element C71, and a capacitance element C72.

[0545] One of the source and drain of transistor M71 is connected to one of the source and drain of transistor M72 and one of the source and drain of transistor M73. The other of the source and drain of transistor M72 is connected to one of the source and drain of transistor M74 and one electrode of capacitor C71. The other of the source and drain of transistor M73 is connected to one of the source and drain of transistor M75 and one electrode of capacitor C72.

[0546] The gate of transistor M71 is connected to wiring SOUT, and the other of the source and drain is connected to wiring DATA. The gate of transistor M72 is connected to wiring SELA[2]. The gate of transistor M73 is connected to wiring SELA[1]. The gate of transistor M74 is connected to wiring PRE[2], and the other of the source and drain is connected to wiring VPRE. The gate of transistor M75 is connected to wiring PRE[1], and the other of the source and drain is connected to wiring VPRE. The other electrode of capacitor C71 is connected to wiring SVSS. The other electrode of capacitor C72 is connected to wiring SVSS. The other of the source and drain of transistor M72, one of the source and drain of transistor M74, and one electrode of capacitor C71 are connected to wiring OUTE. The other of the source and the drain of the transistor M73, one of the source and the drain of the transistor M75, and one electrode of the capacitor C72 are connected to the wiring OUTO. Note that an inverted signal of the wiring SELA[1] is supplied to the wiring SELA[2].

[0547] The transistors M71 to M75 can be, for example, the transistor 100, which is a VFET. In FIG. 37B , the upper electrodes of the transistors included in the latch unit portion 94 are indicated by bold lines. As shown in FIG. 37B , connecting the lower electrodes of the transistors M72 and M74 to one electrode of the capacitor C71 can reduce electrical noise from the wiring SELA[2] and the wiring PRE[2] to the wiring OUTO. Similarly, connecting the lower electrodes of the transistors M73 and M75 to one electrode of the capacitor C72 can reduce electrical noise from the wiring SELA[1] and the wiring PRE[1] to the wiring OUTO.

[0548] 38A is a circuit diagram illustrating an example of the configuration of the amplifier unit section 96. The amplifier unit section 96 has a transistor M81, a transistor M82, a transistor M83, a transistor M84, and a transistor M85.

[0549] One of the source and drain of transistor M81 is connected to one of the source and drain of transistor M83. Fig. 38A shows a wiring NL81 connecting them. One of the source and drain of transistor M82 is connected to one of the source and drain of transistor M84. Fig. 38A shows a wiring NL83 connecting them. The other of the source and drain of transistor M83 is connected to the other of the source and drain of transistor M84 and one of the source and drain of transistor M85.

[0550] The gate of the transistor M81 is connected to the wiring INO, and the other of the source and drain is connected to the wiring SFVDD. The wiring INO is connected to the wiring OUTO. The transistor M81 functions as a source follower.

[0551] The gate of the transistor M82 is connected to the wiring INE, and the other of the source and drain is connected to the wiring SFVDD. The wiring INE is connected to the wiring OUTE. The transistor M82 functions as a source follower.

[0552] The gate of the transistor M83 is connected to the wiring SELB[2]. The gate of the transistor M84 is connected to the wiring SELB[1]. The wiring SELB[2] receives an inverted signal of the wiring SELB[1].

[0553] The gate of the transistor M85 is connected to the wiring LRES, and the other of the source and the drain is connected to the wiring SFVSS.

[0554] The other of the source and the drain of the transistor M83, the other of the source and the drain of the transistor M84, and one of the source and the drain of the transistor M85 are connected to a wiring OUT. The wiring OUT is connected to a wiring SL.

[0555] For example, the wiring SFVDD can function as a high-potential power supply line, and the wiring SFVSS can function as a low-potential power supply line.

[0556] It is preferable to use transistors with long channel lengths for the transistors M81 and M82. An example configuration different from that of the amplifier unit section 96 shown in FIG. 38A is shown in FIG. 38B. The amplifier unit section 96 shown in FIG. 38B includes transistors M81a, M81b, M81c, and M81d instead of the transistor M81, and transistors M82a, M82b, M82c, and M82d instead of the transistor M82. The transistors M81a, M81b, M81c, and M81d are connected in series and correspond to the transistor M81 shown in FIG. 38A. The transistors M82a, M82b, M82c, and M82d are connected in series and correspond to the transistor M82 shown in FIG. 38A. Using transistors connected in series allows the channel lengths of the transistors to be longer, thereby increasing the amplification factor of the amplifier unit section 96. As a transistor having a long channel length, for example, a semiconductor device 10C in which VFETs are connected in series can be preferably used (see FIGS. 7A to 10). Note that although the structure in which four transistors are connected in series is shown here, one embodiment of the present invention is not limited thereto, and the number of transistors connected in series is not particularly limited.

[0557] 38B, the upper electrodes of the transistors in the amplifier unit section 96 are indicated by thick lines. As shown in FIG. 38B, connecting the lower electrode of transistor M81d to transistor M83 reduces the electrical influence of wiring INO from wiring NL81. Similarly, connecting the lower electrode of transistor M82d to transistor M84 reduces the electrical influence of wiring INE from wiring NL83.

[0558] FIG. 39 is a schematic diagram showing the operation of the latch unit section 94 and the amplifier unit section 96. For ease of understanding, FIG. 39 is a simplified representation of the circuit diagrams shown in FIGS. 37A and 38A, with transistors M71 and M85 omitted. The circuit sections LATE and LATO shown in FIG. 39 correspond to the circuit sections LATE and LATO shown by the dashed line in FIG. 37A. The circuit sections AMPE and AMPO shown in FIG. 39 correspond to the circuit sections AMPE and AMPO shown by the dashed line in FIG. 38A. Note that in FIG. 39, transistors M73, M75, M83, and M84 are represented as switches.

[0559] As shown on the left side of Figure 38, by turning transistor M73 off, transistor M75 on, transistor M84 on, and transistor M83 off, a signal is output from circuit unit AMPE to wiring OUT, and a signal is input to circuit unit LATO from wiring DATA. At this time, the signal output from circuit unit AMPE is the signal supplied to the pixel in row i (i is an integer greater than or equal to 1), and the signal input to circuit unit LATO is the signal supplied to the pixel in row i+1. Then, in the next period, as shown on the right side of Figure 38, by turning transistor M73 on, transistor M75 off, transistor M84 off, and transistor M83 on, a signal is output from circuit unit AMPO to wiring OUT, and a signal is input to circuit unit LATE from wiring DATA. At this time, the signal output from the circuit unit AMPE is the signal supplied to the pixels in the (i+1)th row, and the signal input to the circuit unit LATO is the signal supplied to the pixels in the (i+2)th row. Thereafter, the above-described operation is repeated.

[0560] The circuit units LATE and LATO operate alternately, and the circuit units AMPE and AMPO operate alternately. Furthermore, when the circuit unit LATO operates, the circuit unit AMPE operates, and when the circuit unit LATE operates, the circuit unit AMPO operates. This allows a signal to be output from the amplifier unit 96 while a signal is being input to the latch unit 94. It can be said that the signal output to the wiring OUT via the circuit units LATE and AMPE is supplied to one of the pixels in the even and odd rows, and the signal output to the wiring OUT via the circuit units LATO and AMPO is supplied to the other of the pixels in the even and odd rows. By using this operation method, the entire horizontal period can be used as the output time to the wiring SL. Therefore, the semiconductor device 90 can be suitably used as a driver for a high-resolution display device with a short horizontal period.

[0561] FIG. 40 is a schematic diagram illustrating the operation of the amplifier unit section 96. FIG. 40 selectively illustrates the transistors M81, M83, and M85 of the amplifier unit section 96 illustrated in FIG. 38A . It also illustrates a plurality of wirings SL connected to the amplifier unit section 96. Note that the resistances illustrated in FIG. 40 represent the wiring resistances of the respective wirings SL, and the transistors M83 and M85 are depicted as switches. The upper side of FIG. 40 illustrates a reset (initialization) operation for initializing the potential of the wiring SL. At this time, the transistor M83 is turned off and the transistor M85 is turned on. As a result, the potential of the wiring SL becomes the potential of the wiring SFVSS. When the wiring SFVSS functions as a low-potential power supply line, the potential of the wiring SL becomes low. In other words, the reset (initialization) operation of the wiring SL can also be considered an operation for discharging the charge of the wiring SL. The lower side of FIG. 40 illustrates an operation for outputting a signal to the wiring SL. At this time, the transistor M83 is turned on and the transistor M85 is turned off, so that a potential according to the voltage applied to the gate of the transistor M51 and the threshold voltage of the transistor M51 is output to the wiring SL.

[0562] As described above, by switching the conduction states of the transistors M83 and M85, the wiring SL can be reset (initialized) and a signal can be output to the wiring SL. As a result, after the voltage of the wiring SL is lowered, the wiring SL can be charged to a desired voltage and a signal can be output.

[0563] The configuration of the amplifier unit section 96 is not limited to the configuration shown in FIG. 38 etc. For example, a transistor connected to one of the source and drain of the transistor M81 can be provided instead of the transistor M85. Then, a bias voltage can be applied to the gate of the transistor to allow a bias current to flow through the amplifier unit section 96. In this case, whether or not a bias current flows through the transistor can be switched depending on whether or not a bias voltage is applied.

[0564] 38 and other figures show a configuration of an amplifier unit 96 that does not include a transistor to which a bias voltage is applied. By not including a transistor to which a bias voltage is applied, a bias current does not flow steadily, and power consumption can be reduced.

[0565] Figure 41A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0566] 41A includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0567] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0568] The display device 50A is a top emission type, which allows transistors and the like to be arranged so as to overlap the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0569] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured in the same process. Note that the transistors 205D, the transistor 205R, the transistor 205G, and the transistor 205B may have different structures.

[0570] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0571] Specifically, the transistors 205D, 205R, 205G, and 205B...

Claims

a transistor, a first insulating layer, and a liquid crystal element; the transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer; the liquid crystal element includes the second conductive layer, a liquid crystal, and a third conductive layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; the semiconductor layer comprises crystalline indium oxide; The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ is as follows: The second conductive layer has an area overlapping with the third conductive layer with the liquid crystal interposed therebetween. 　 a transistor, a first insulating layer, and a light-emitting element; the transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; the semiconductor layer comprises crystalline indium oxide; The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ is as follows: The second conductive layer is connected to the light-emitting element. 　 Has a drive circuit section the drive circuit unit includes a transistor and a first insulating layer; the transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; the semiconductor layer comprises crystalline indium oxide; The concentrations of aluminum, gallium, and zinc in the semiconductor layer are each 1×10 ２０ atoms / cm ３ A display device as follows: 　 In any one of claims 1 to 3, the semiconductor layer has crystal grains, A display device, wherein the grain size of the crystal grains is 0.3 μm or more. 　 In any one of claims 1 to 3, a second insulating layer; the second insulating layer has a region in contact with a lower surface of the first conductive layer; the first insulating layer has a third insulating layer and a fourth insulating layer on the third insulating layer; the second insulating layer comprises silicon, nitrogen, and hydrogen; the third insulating layer comprises silicon and nitrogen; the fourth insulating layer includes silicon and oxygen; The display device, wherein the second insulating layer has a region having a higher hydrogen content than the third insulating layer. 　 In claim 5, the first insulating layer has a fifth insulating layer on the fourth insulating layer; The display device, wherein the fifth insulating layer includes silicon and nitrogen. 　 In claim 5, the first insulating layer has a fifth insulating layer on the fourth insulating layer; The display device, wherein the fifth insulating layer contains aluminum and oxygen. 　 In any one of claims 1 to 3, The display device, wherein the first conductive layer and the second conductive layer each contain indium and oxygen.

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