Apparatus for manufacturing display device and method for manufacturing display device

Abstract

Provided are an apparatus for manufacturing a display device and a method for manufacturing a display device. The apparatus for manufacturing a display device comprises: an alignment unit; a carrier disposed on the alignment unit and including an accommodation part configured to accommodate a wafer; a pressing unit disposed on the carrier; a first vision device disposed on the carrier and positioned on one side of the pressing unit; and a controller configured to adjust the alignment of the wafer and the carrier.

Description

Manufacturing device for display device and manufacturing method for display device

[0001] The present invention relates to a manufacturing device for a display device and a manufacturing method for a display device.

[0002] Recently, interest in extended reality (XR) has been growing, driven by the development of electronic devices and displays capable of implementing it. XR encompasses virtual reality (VR), augmented reality (AR), and mixed reality (MR).

[0003] Various display devices are emerging to implement this augmented reality. For example, head-mounted displays (HMDs) and AR glasses are examples of display devices for implementing augmented reality.

[0004] Recently, research on small displays has been actively underway due to the trend toward lightweight and miniaturized devices. Examples of small displays or electronic devices containing them include smart watches, watch phones, automotive head-up displays (HUDs), and the Internet of Things (IoT).

[0005] Display devices for implementing this augmented reality are small and placed close to the user's eyes, magnifying images or video using multiple lenses. Furthermore, even for small displays, it is necessary to present a large amount of information on a small screen while still providing clear images or video. Therefore, display devices and small displays for implementing augmented reality must provide high-resolution images, such as images with a resolution of 3,000 PPI (Pixels Per Inch) or higher.

[0006] For this purpose, OLEDoS (Organic Light Emitting Diode on Silicon), a high-resolution, compact organic light-emitting display device, is being used. OLEDoS is a device that displays images by arranging organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate containing CMOS (Complementary Metal Oxide Semiconductor).

[0007] The problem to be solved by the present invention is to provide a manufacturing device for a display device including a carrier for accommodating a wafer and a manufacturing method for a display device so that display process equipment using an existing substrate can be utilized in a display process using a wafer.

[0008] Another problem to be solved by the present invention is to provide a manufacturing device for a display device and a manufacturing method for a display device having improved alignment accuracy between a carrier and a wafer.

[0009] Another problem that the present invention seeks to solve is to provide a manufacturing device for a display device and a manufacturing method for a display device that minimizes damage to a wafer when the wafer is removed from a carrier.

[0010] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0011] According to one embodiment of the present invention, a manufacturing device for a display device for solving the above problem comprises: an alignment unit; a carrier including a receiving portion arranged on the alignment unit and configured to receive a wafer; a pressing unit arranged on the carrier; a first vision device arranged on one side of the pressing unit on the carrier; and a control unit configured to adjust alignment of the wafer and the carrier.

[0012] The carrier further includes a first alignment mark arranged on one side of the receiving portion, and the first vision device can capture the first alignment mark of the carrier and the second alignment mark of the wafer.

[0013] The first vision device may include a camera, and the number of cameras included in the first vision device may be equal to the number of first alignment marks in the carrier.

[0014] The carrier further includes a coupling portion arranged on the bottom surface of the receiving portion, the coupling portion being arranged between the wafer and the carrier, and the wafer and the carrier can be coupled to each other by the coupling portion.

[0015] The above-mentioned joint may include an adhesive chuck or an electrostatic chuck.

[0016] The carrier further includes a buffer portion arranged on a portion of the bottom surface of the receiving portion other than a portion where the coupling portion is arranged, and a step compensation portion arranged below the coupling portion, and the thickness of the buffer portion may be equal to the sum of the thickness of the coupling portion and the thickness of the step compensation portion.

[0017] The alignment unit may include a pin extending in the direction of the carrier, and the carrier may further include a pin hole disposed at a lower portion of the receiving portion, and the pin may be configured to move through the pin hole.

[0018] The wafer can be mounted on the pin.

[0019] The above alignment unit further includes a pin driving unit disposed below the pin, and the pin driving unit may include a vertical driving unit and a rotational driving unit.

[0020] The alignment unit further includes a first pressure sensor disposed below the pin, and the first pressure sensor may be configured to measure a pressure applied when the wafer coupled to the carrier is detached.

[0021] The above pins are configured in multiple numbers, and the first pressure sensor can be arranged in one-to-one correspondence with each of the multiple pins.

[0022] The pressurizing unit includes a pressurizing portion arranged on a first surface facing the carrier, and a second pressure sensor arranged between the first surface and the pressurizing portion, and the second pressure sensor can be configured to measure a pressing force applied when the carrier and the wafer are combined.

[0023] The first vision device captures a first image before the first pressurization of the wafer after the first alignment of the wafer, and captures a second image after the first pressurization of the wafer, and the control unit includes an alignment correction value calculation unit, and the alignment correction value calculation unit compares the first image with the second image to calculate a correction value, and the alignment unit can align the wafer to shift by the correction value during the second pressurization of the wafer.

[0024] The present invention further includes a second vision device disposed on the carrier, wherein the second vision device can capture images of the carrier and the alignment unit.

[0025] The carrier may further include a carrier transfer unit configured to position the carrier on the alignment unit.

[0026] It may further include a wafer transfer unit configured to position the wafer on the carrier.

[0027] The control unit includes an alignment processing unit, and the alignment processing unit provides a driving signal to the wafer transfer unit, and the wafer transfer unit, which has received the driving signal, positions the wafer on the carrier, and the first vision device provides an image capturing the carrier and the wafer to the alignment processing unit, and the alignment processing unit, which has received the image, provides the driving signal again to the wafer transfer unit to align the wafer to the carrier in real time.

[0028] On a plane, the carrier may have a square shape and the wafer may have a circular shape.

[0029] According to one embodiment of the present invention for solving the above problem, a method for manufacturing a display device includes a step of first aligning a wafer to a reference point of a carrier, a step of first pressurizing the wafer, a first misalignment inspection step of measuring a first misalignment degree of the wafer and the carrier, a step of detaching the wafer from the carrier, a step of second aligning the wafer to the carrier, a step of second pressurizing the wafer, and a second misalignment inspection step of measuring a second misalignment degree of the wafer and the carrier, wherein the second alignment step includes a step of aligning the wafer so that it is shifted from the reference point by the correction value using the first misalignment degree measured in the first misalignment inspection step as a correction value.

[0030] If the second degree of warping is below the threshold in the second warping inspection step, the method for manufacturing the display device may be terminated.

[0031] If the second degree of distortion exceeds the threshold in the second distortion inspection step, a step of recalculating the correction value and realigning the wafer may be further performed.

[0032] The step of recalculating the correction value and realigning the wafer may include a step of recalculating the correction value, a step of realigning the wafer, a step of repressurizing the wafer, and a step of re-inspecting the misalignment of the wafer and the carrier to measure a third degree of misalignment.

[0033] The step of recalculating the above correction value may include a step of calculating the correction value of the current wafer using the correction values ​​of previous wafers.

[0034] If the third degree of warping is below the threshold in the above warping re-examination step, the method for manufacturing the display device may be terminated.

[0035] If the third degree of misalignment exceeds the threshold in the above misalignment re-inspection step, the step of recalculating the correction value and realigning the wafer may be performed again.

[0036] The correction values ​​of the previous wafers may each include at least one sub-correction value, and the number of sub-correction values ​​included in the correction values ​​of the previous wafers may be equal to the number of repetitions of the step of recalculating the correction values.

[0037] Among the sub-correction values ​​included in each of the correction values ​​of the previous wafers, the final sub-correction value may be the correction value of the previous wafers.

[0038] In each of the first step of pressurizing the wafer and the second step of pressurizing the wafer, the combined pressing force can be corrected in real time according to the pressing force measured by the pressing sensor.

[0039] In the step of detaching the wafer from the carrier, the detachment pressure can be corrected in real time according to the pressure measured by the pressure sensor.

[0040] According to an embodiment of the present invention, a display device manufacturing device and a display device manufacturing method may include a carrier for accommodating a wafer so that display process equipment using an existing substrate can be utilized in a display process using a wafer.

[0041] According to the manufacturing apparatus and manufacturing method of the display device according to one embodiment of the present invention, the alignment accuracy of the carrier and the wafer can be improved.

[0042] According to an embodiment of the present invention, a manufacturing device for a display device and a manufacturing method for a display device can minimize damage to a wafer when the wafer is removed from a carrier.

[0043] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0044] Figure 1 is an exploded perspective view showing a display device according to one embodiment.

[0045] FIG. 2 is a block diagram showing a display device according to one embodiment.

[0046] FIG. 3 is an equivalent circuit diagram of a first sub-pixel according to one embodiment.

[0047] FIG. 4 is a plan view showing an example of a display panel according to one embodiment.

[0048] Figures 5 and 6 are plan views showing examples of the display area of ​​Figure 4.

[0049] Fig. 7 is a cross-sectional view showing an example of a display panel cut along line X1-X1' of Fig. 5.

[0050] FIG. 8 is an exploded perspective view showing a head-mounted display device according to one embodiment.

[0051] FIG. 9 is a perspective view showing an augmented reality content providing device according to one embodiment.

[0052] FIG. 10a is an exploded perspective view of the rear surface of the augmented reality content providing device of FIG. 9.

[0053] FIG. 10b is a front exploded perspective view of the augmented reality content providing device of FIG. 9.

[0054] Fig. 11 is a perspective view showing a manufacturing device of a display device according to one embodiment.

[0055] Fig. 12 is a cross-sectional view showing a manufacturing device of a display device according to one embodiment.

[0056] Fig. 13 is a perspective view showing a carrier according to one embodiment.

[0057] Fig. 14 is a cross-sectional view showing the carrier cut along X2-X2' of Fig. 13.

[0058] Fig. 15 is a block diagram showing a control unit according to one embodiment.

[0059] Fig. 16 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0060] Fig. 17 is a cross-sectional view showing step S100 of Fig. 16.

[0061] Figures 18 and 19 are cross-sectional views showing step S200 of Figure 16.

[0062] Figures 20 and 21 are cross-sectional views showing step S300 of Figure 16.

[0063] Figure 22 is a cross-sectional view showing step S400 of Figure 16.

[0064] Figure 23 is a plan view illustrating a method for measuring the degree of warpage of a wafer.

[0065] Figure 24 is a cross-sectional view showing step S500 of Figure 16.

[0066] Figures 25 and 26 are cross-sectional views showing step S600 of Figure 16.

[0067] Figure 27 is a schematic diagram for explaining alignment correction data processed by the control unit.

[0068] Figure 28 is a cross-sectional view showing step S700 of Figure 16.

[0069] Figure 29 is a cross-sectional view showing step S800 of Figure 16.

[0070] Figure 30 is a cross-sectional view showing step S900 of Figure 16.

[0071] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0072] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly above the other element or layer or where there is another layer or material intervening therebetween. Similarly, references to "below," "left," and "right" include both cases where the other element or layer is directly adjacent to the other element or where there is another layer or material intervening therebetween. Like reference numerals throughout the specification refer to like elements.

[0073] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0074] The features of each of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0075] Specific embodiments are described below with reference to the attached drawings.

[0076] Fig. 1 is an exploded perspective view showing a display device according to one embodiment. Fig. 2 is a block diagram showing a display device according to one embodiment.

[0077] Referring to FIGS. 1 and 2, a display device (10) according to one embodiment may be a device that displays a moving image or a still image. The display device (10) according to one embodiment may be applied to portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an ultra mobile PC (UMPC), etc. For example, the display device (10) according to one embodiment may be applied as a display unit of a television, a laptop, a monitor, a billboard, or the Internet of Things (IOT). Alternatively, the display device (10) according to one embodiment may be applied to a smart watch, a watch phone, a head mounted display (HMD) for implementing virtual reality and augmented reality.

[0078] A display device (10) according to one embodiment may include a display panel (100), a heat dissipation layer (200), a circuit board (300), a timing control circuit (400), and a power supply circuit (500).

[0079] The display panel (100) may have a planar shape similar to a rectangle. For example, the display panel (100) may have a planar shape similar to a rectangle having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). In the display panel (100), an edge where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may have a rounded shape or a right-angled shape to have a predetermined curvature. The planar shape of the display panel (100) is not limited to a rectangle, and may have a shape similar to another polygon, circle, or oval. The planar shape of the display device (10) may follow the planar shape of the display panel (100), but the embodiments of the present specification are not limited thereto.

[0080] In the illustrated drawing, the first direction (DR1) and the second direction (DR2) are each a horizontal direction and intersect with each other. For example, the first direction (DR1) and the second direction (DR2) are orthogonal to each other. In addition, the third direction (DR3) intersects with the first direction (DR1) and the second direction (DR2), and is, for example, a vertical direction that is orthogonal to the first direction (DR1) and the second direction (DR2). Unless otherwise defined, in this specification, the direction indicated by the arrows of the first to third directions (DR1, DR2, DR3) is referred to as one side, and the opposite direction is referred to as the other side. Here, the third direction (DR3) may be a thickness direction of the display panel (100). In addition, in this specification, “upper”, “upper side”, “top”, “top”, and “top surface” refer to the direction in which the arrow in the drawing is pointing among the third direction (DR3) based on the drawing, and “lower”, “lower side”, “lower”, “bottom”, and “lower side” refer to the opposite direction to the direction in which the arrow in the third direction (DR3) based on the drawing is pointing.

[0081] The display panel (100) may include a display area (DAA) that displays an image and a non-display area (NDA) that does not display an image, as shown in FIG. 2.

[0082] A display area (DAA) may include a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of emission control lines (EL), and a plurality of data lines (DL).

[0083] A plurality of pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). A plurality of scan lines (SL) and a plurality of emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). A plurality of data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1).

[0084] The plurality of scan lines (SL) may include a plurality of write scan lines (GWL), a plurality of control scan lines (GCL), and a plurality of bias scan lines (GBL). The plurality of emission control lines (EL) may include a plurality of first emission control lines (EL1) and a plurality of second emission control lines (EL2).

[0085] The plurality of pixels (PX) may include a plurality of sub-pixels (SP1, SP2, SP3). The plurality of sub-pixels (SP1, SP2, SP3) may include a plurality of pixel transistors as illustrated in FIG. 3 described below, and the plurality of pixel transistors may be formed by a semiconductor process and may be arranged on a semiconductor substrate (SSUB) (see FIG. 7). For example, the plurality of pixel transistors of the data driver (700) may be formed of a CMOS (Complementary Metal Oxide Semiconductor).

[0086] Each of the plurality of sub-pixels (SP1, SP2, SP3) may be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines (GCL), one of the plurality of bias scan lines (GBL), one of the plurality of first light emission control lines (EL1), one of the plurality of second light emission control lines (EL2), and one of the plurality of data lines (DL). Each of the plurality of sub-pixels (SP1, SP2, SP3) may be supplied with a data voltage of the data line (DL) according to a write scan signal of the write scan line (GWL), and may emit light through a light-emitting element according to the data voltage.

[0087] The non-display area (NDA) may include a scan driver (610), a light emitting driver (620), and a data driver (700).

[0088] The scan driver (610) includes a plurality of scan transistors, and the light emitting driver (620) includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed by a semiconductor process and may be arranged on a semiconductor substrate (SSUB) (see FIG. 7). For example, the plurality of scan transistors and the plurality of light emitting transistors may be formed of CMOS. In FIG. 2, the scan driver (610) is arranged on the left side of the display area (DAA), and the light emitting driver (620) is arranged on the right side of the display area (DAA), but the present invention is not limited thereto. For example, the scan driver (610) and the light emitting driver (620) may be arranged on both the left and right sides of the display area (DAA).

[0089] The scan driving unit (610) includes a write scan signal output unit (611), a control scan signal output unit (612), and a bias scan signal output unit (613). Each of the write scan signal output unit (611), the control scan signal output unit (612), and the bias scan signal output unit (613) can receive a scan timing control signal (SCS) from the timing control circuit (400). The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (400) and sequentially output the write scan signals to the write scan lines (GWL). The control scan signal output unit (612) can generate control scan signals according to the scan timing control signal (SCS) and sequentially output the control scan signals to the control scan lines (GCL). The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (GBL).

[0090] The light emitting driver (620) includes a first light emitting control driver (621) and a second light emitting control driver (622). Each of the first light emitting control driver (621) and the second light emitting control driver (622) can receive a light emitting timing control signal (ECS) from the timing control circuit (400). The first light emitting control driver (621) can generate first light emitting control signals according to the light emitting timing control signal (ECS) and sequentially output the same to the first light emitting control lines (EL1). The second light emitting control driver (622) can generate second light emitting control signals according to the light emitting timing control signal (ECS) and sequentially output the same to the second light emitting control lines (EL2).

[0091] The data driving unit (700) includes a plurality of data transistors, and the plurality of data transistors are formed through a semiconductor process and can be placed on a semiconductor substrate (SSUB) (see FIG. 7). For example, the plurality of data transistors can be formed of CMOS.

[0092] The data driving unit (700) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (400). The data driving unit (700) can convert the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and output the converted data voltages to the data lines (DL). In this case, the sub-pixels (SP1, SP2, SP3) are selected by the write scan signal of the scan driving unit (610), and the data voltages can be supplied to the selected sub-pixels (SP1, SP2, SP3).

[0093] The heat dissipation layer (200) may overlap the display panel (100) in the third direction (DR3), which is the thickness direction of the display panel (100). The heat dissipation layer (200) may be disposed on one surface of the display panel (100), for example, the back surface. The heat dissipation layer (200) serves to dissipate heat generated in the display panel (100). The heat dissipation layer (200) may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

[0094] The circuit board (300) may be electrically connected to the first plurality of pads (PD1) (see FIG. 4) of the first pad portion (PDA1) (see FIG. 4) of the display panel (100) using a conductive adhesive material such as an anisotropic conductive film. The circuit board (300) may be a flexible printed circuit board made of a flexible material or a flexible film. In FIG. 1, the circuit board (300) is illustrated as being unfolded, but the circuit board (300) may be bent. In this case, one end of the circuit board (300) may be disposed on the back surface of the display panel (100) and / or the back surface of the heat dissipation layer (200). One end of the circuit board (300) may be connected to a plurality of first pads (PD1) (see FIG. 4) of a first pad portion (PDA1) (see FIG. 4) of a display panel (100) using a conductive adhesive material, which is opposite to the other end of the circuit board (300).

[0095] The timing control circuit (400) can receive digital video data and timing signals from the outside. The timing control circuit (400) can generate a scan timing control signal (SCS), an emission timing control signal (ECS), and a data timing control signal (DCS) for controlling the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the scan driver (610) and output the emission timing control signal (ECS) to the emission driver (620). The timing control circuit (400) can output digital video data and a data timing control signal (DCS) to the data driver (700).

[0096] The power supply circuit (500) can generate a plurality of panel driving voltages according to an external power voltage. For example, the power supply circuit (500) can generate a first driving voltage (VSS), a second driving voltage (VDD), and a third driving voltage (VINT) and supply them to the display panel (100). The first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) will be described later with reference to FIG. 3.

[0097] The timing control circuit (400) and the power supply circuit (500) may each be configured as an integrated circuit (IC) and attached to one surface of the circuit board (300). In this case, the scan timing control signal (SCS), the emission timing control signal (ECS), the digital video data (DATA), and the data timing control signal (DCS) of the timing control circuit (400) may be supplied to the display panel (100) through the circuit board (300). In addition, the first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) of the power supply circuit (500) may be supplied to the display panel (100) through the circuit board (300).

[0098] Alternatively, each of the timing control circuit (400) and the power supply circuit (500) may be disposed in a non-display area (NDA) of the display panel (100), similarly to the scan driver (610), the light emitting driver (620), and the data driver (700). In this case, the timing control circuit (400) may include a plurality of timing transistors, and each of the power supply circuits (500) may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed by a semiconductor process and disposed on a semiconductor substrate (SSUB) (see FIG. 7). For example, the plurality of timing transistors and the plurality of power transistors may be formed of a CMOS. Each of the timing control circuit (400) and the power supply circuit (500) may be disposed between the data driver (700) and the first pad unit (PDA1) (see FIG. 4).

[0099] FIG. 3 is an equivalent circuit diagram of a first sub-pixel according to one embodiment.

[0100] In addition to FIGS. 1 and 2, referring to FIG. 3, the first sub-pixel (SP1) may be connected to a write scan line (GWL), a control scan line (GCL), a bias scan line (GBL), a first emission control line (EL1), a second emission control line (EL2), and a data line (DL). In addition, the first sub-pixel (SP1) may be connected to a first driving voltage line (VSL) to which a first driving voltage (VSS) corresponding to a low potential voltage is applied, a second driving voltage line (VDL) to which a second driving voltage (VDD) corresponding to a high potential voltage is applied, and a third driving voltage line (VIL) to which a third driving voltage (VINT) corresponding to an initialization voltage is applied. That is, the first driving voltage line (VSL) may be a low potential voltage line, the second driving voltage line (VDL) may be a high potential voltage line, and the third driving voltage line (VIL) may be an initialization voltage line. At this time, the first driving voltage (VSS) may be a voltage lower than the third driving voltage (VINT). The second driving voltage (VDD) may be a voltage higher than the third driving voltage (VINT).

[0101] The first sub-pixel (SP1) may include a plurality of transistors (T1 to T6), a light emitting element (LE), a first capacitor (CP1), and a second capacitor (CP2).

[0102] The light emitting element (LE) is driven by a driving current (source-drain current: I) flowing in the channel of the first transistor (T1). ds) can emit light. The amount of light emitted by the light emitting element (LE) can be proportional to the driving current. The light emitting element (LE) can be disposed between the fourth transistor (T4) and the first driving voltage line (VSL). The first electrode of the light emitting element (LE) can be connected to the drain electrode of the fourth transistor (T4), and the second electrode can be connected to the first driving voltage line (VSL). The first electrode of the light emitting element (LE) can be an anode electrode, and the second electrode of the light emitting element (LE) can be a cathode electrode. The light emitting element (LE) can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but the embodiments of the present specification are not limited thereto. For example, the light emitting element (LE) can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, for example, the light emitting element (LE) can be a micro light emitting diode.

[0103] The first transistor (T1) may be a driving transistor that controls a driving current flowing between the source electrode and the drain electrode according to a voltage applied to the gate electrode. The first transistor (T1) may include a gate electrode connected to a first node (N1), a source electrode connected to a drain electrode of a sixth transistor (T6), and a drain electrode connected to a second node (N2).

[0104] The second transistor (T2) may be disposed between one electrode of the first capacitor (CP1) and the data line (DL). The second transistor (T2) may be turned on by a write scan signal of the write scan line (GWL) to connect one electrode of the first capacitor (CP1) to the data line (DL). Accordingly, when the second transistor (T2) is turned on, the data voltage of the data line (DL) may be applied to one electrode of the first capacitor (CP1). The second transistor (ST2) may include a gate electrode connected to the write scan line (GWL), a source electrode connected to the data line (DL), and a drain electrode connected to one electrode of the first capacitor (CP1).

[0105] A third transistor (T3) may be placed between a first node (N1) and a second node (N2). The third transistor (T3) may be turned on by a write control signal of a control scan line (GCL) to connect the first node (N1) to the second node (N2). Accordingly, when the third transistor (T3) is turned on, the gate electrode and the source electrode of the first transistor (T1) are connected, so that the first transistor (T1) may operate like a diode. The third transistor (T3) may include a gate electrode connected to the control scan line (GCL), a source electrode connected to the second node (N2), and a drain electrode connected to the first node (N1).

[0106] The fourth transistor (T4) may be connected between the second node (N2) and the third node (N3). The fourth transistor (ST4) may be turned on by the first light emission control signal of the first light emission control line (EL1) to connect the second node (N2) to the third node (N3). Accordingly, when the fourth transistor (T4) is turned on, the driving current of the first transistor (T1) may be supplied to the light emitting element (LE). The fourth transistor (T4) may include a gate electrode connected to the first light emission control line (EL1), a source electrode connected to the second node (N2), and a drain electrode connected to the third node (N3).

[0107] The fifth transistor (T5) may be disposed between the third node (N3) and the third driving voltage line (VIL). The fifth transistor (T5) may be turned on by a bias scan signal of the bias scan line (GBL) to connect the third node (N3) to the third driving voltage line (VIL). Accordingly, when the fifth transistor (T5) is turned on, the third driving voltage (VINT) of the third driving voltage line (VIL) may be applied to the first electrode of the light emitting element (LE). The fifth transistor (T5) may include a gate electrode connected to the bias scan line (GBL), a source electrode connected to the third node (N3), and a drain electrode connected to the third driving voltage line (VIL).

[0108] The sixth transistor (T6) may be disposed between the source electrode of the first transistor (T1) and the second driving voltage line (VDL). The sixth transistor (T6) may be turned on by the second emission control signal of the second emission control line (EL2) to connect the source electrode of the first transistor (T1) to the second driving voltage line (VDL). Accordingly, when the sixth transistor (T6) is turned on, the second driving voltage (VDD) of the second driving voltage line (VDL) may be applied to the source electrode of the first transistor (T1). The sixth transistor (T6) may include a gate electrode connected to the second emission control line (EL2), a source electrode connected to the second driving voltage line (VDL), and a drain electrode connected to the source electrode of the first transistor (T1).

[0109] A first capacitor (CP1) may be placed between a first node (N1) and a drain electrode of a second transistor (T2). The first capacitor (CP1) may include one electrode connected to the drain electrode of the second transistor (T2) and the other electrode connected to the first node (N1).

[0110] A second capacitor (CP2) may be placed between the gate electrode of the first transistor (T1) and the second driving voltage line (VDL). The second capacitor (CP2) may include one electrode connected to the gate electrode of the first transistor (T1) and the other electrode connected to the second driving voltage line (VDL).

[0111] The first node (N1) may be a contact point of the gate electrode of the first transistor (T1), the drain electrode of the third transistor (T3), the other electrode of the first capacitor (CP1), and one electrode of the second capacitor (CP2). The second node (N2) may be a contact point of the drain electrode of the first transistor (T1), the source electrode of the third transistor (T3), and the source electrode of the fourth transistor (T4). The third node (N3) may be a contact point of the drain electrode of the fourth transistor (T4), the source electrode of the fifth transistor (T5), and the first electrode of the light emitting element (LE).

[0112] Each of the first to sixth transistors (T1 to T6) may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors (T1 to T6) may be a P-type MOSFET, but the embodiments of the present specification are not limited thereto. Each of the first to sixth transistors (T1 to T6) may be an N-type MOSFET. Alternatively, among the first to sixth transistors (T1 to T6), some of the transistors may be P-type MOSFETs, and the remaining transistors may be N-type MOSFETs.

[0113] Although FIG. 3 illustrates that the first sub-pixel (SP1) includes six transistors (T1 to T6) and two capacitors (CP1, CP2), the equivalent circuit diagram of the first sub-pixel (SP1) is not limited to that illustrated in FIG. 3. For example, the number of transistors and the number of capacitors of the first sub-pixel (SP1) may be varied.

[0114] In addition, the equivalent circuit diagram of the second sub-pixel (SP2) and the equivalent circuit diagram of the third sub-pixel (SP3) may be substantially the same as the equivalent circuit diagram of the first sub-pixel (SP1) described in conjunction with Fig. 3. Therefore, in this specification, descriptions of the equivalent circuit diagram of the second sub-pixel (SP2) and the equivalent circuit diagram of the third sub-pixel (SP3) are omitted.

[0115] FIG. 4 is a plan view showing an example of a display panel according to one embodiment.

[0116] Referring to FIG. 4, a display area (DAA) of a display panel (100) according to one embodiment may include a plurality of pixels (PX) arranged in a matrix form. A non-display area (NDA) of a display panel (100) according to one embodiment may include a scan driver (610), a light emitting driver (620), a data driver (700), a first distribution circuit (710), a second distribution circuit (720), a first pad unit (PDA1), and a second pad unit (PDA2). In one embodiment, the pixels (PX) may be arranged or not included in the non-display area.

[0117] The scan driver (610) may be disposed on a first side of the non-display area (NDA), and the light emitting driver (620) may be disposed on a second side of the non-display area (NDA). For example, the scan driver (610) may be disposed on the other side of the non-display area (NDA) in the first direction (DR1), and the light emitting driver (620) may be disposed on one side of the non-display area (NDA) in the first direction (DR1). That is, the scan driver (610) may be disposed on the left side of the non-display area (NDA), and the light emitting driver (620) may be disposed on the right side of the non-display area (NDA). However, the embodiment of the present specification is not limited thereto, and the scan driver (610) and the light emitting driver (620) may be disposed on both the first side and the second side of the non-display area (NDA).

[0118] The first pad portion (PDA1) may include a plurality of first pads (PD1) connected to pads or bumps of the circuit board (300) via a conductive adhesive material. The first pad portion (PDA1) may be arranged on a third side of the non-display area (NDA). For example, the first pad portion (PDA1) may be arranged on the other side of the second direction (DR2) of the non-display area (NDA). That is, the first pad portion (PDA1) may be arranged on the lower side of the non-display area (NDA).

[0119] The first pad portion (PDA1) may be positioned on the outside of the data driving portion (700) in the second direction (DR2). That is, the first pad portion (PDA1) may be positioned closer to the edge of the display panel (100) than the data driving portion (700).

[0120] The second pad unit (PDA2) may include a plurality of second pads (PD2) corresponding to test pads for testing whether the display panel (100) is operating normally. The plurality of second pads (PD2) may be connected to a jig or probe pin or to a test circuit board during the test process. The test circuit board may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0121] The first distribution circuit (710) can distribute data voltages applied through the first pad portion (PDA1) to a plurality of data lines (DL). For example, the first distribution circuit (710) can distribute data voltages applied through one first pad (PD1) of the first pad portion (PDA1) to P (where P is a positive integer greater than or equal to 2) data lines (DL), thereby reducing the number of the plurality of first pads (PD1). The first distribution circuit (710) can be arranged on the third side of the non-display area (NDA) of the display panel (100). For example, the first distribution circuit (710) can be arranged on the other side of the second direction (DR2) of the non-display area (NDA). That is, the first distribution circuit (710) can be arranged on the lower side of the non-display area (NDA).

[0122] The second distribution circuit (720) can distribute signals applied through the second pad unit (PDA2) to the scan driver (610), the light emitting driver (620), and the data lines (DL). The second pad unit (PDA2) and the second distribution circuit (720) may be configured to inspect the operation of each pixel (PX) of the display area (DAA). The second distribution circuit (720) may be arranged on the fourth side of the non-display area (NDA) of the display panel (100). For example, the second distribution circuit (720) may be arranged on one side of the second direction (DR2) of the non-display area (NDA). That is, the second distribution circuit (720) may be arranged on the upper side of the non-display area (NDA).

[0123] Figures 5 and 6 are plan views showing examples of the display area of ​​Figure 4.

[0124] Referring to FIGS. 5 and 6, each of the plurality of pixels (PX) may include a first light-emitting area (EA1) which is a light-emitting area of ​​a first sub-pixel (SP1), a second light-emitting area (EA2) which is a light-emitting area of ​​a second sub-pixel (SP2), and a third light-emitting area (EA3) which is a light-emitting area of ​​a third sub-pixel (SP3).

[0125] In some embodiments, as illustrated in FIGS. 5 and 6 , the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may have a hexagonal shape composed of six straight lines in a plane (or when viewed in the third direction (DR3)), but the embodiments of the present disclosure are not limited thereto. The first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may have a polygonal, circular, elliptical, or irregular planar shape other than a hexagon.

[0126] In some embodiments, as illustrated in FIG. 5, the maximum length in the first direction (DR1) of the third light-emitting area (EA3) may be less than the maximum length in the first direction (DR1) of the first light-emitting area (EA1) and the maximum length in the first direction (DR1) of the second light-emitting area (EA2). The maximum length in the first direction (DR1) of the first light-emitting area (EA1) and the maximum length in the first direction (DR1) of the second light-emitting area (EA2) may be substantially the same.

[0127] In some embodiments, as illustrated in FIG. 5, the maximum length in the second direction (DR2) of the third light-emitting area (EA3) may be longer than the maximum length in the second direction (DR2) of the first light-emitting area (EA1) and the maximum length in the second direction (DR2) of the second light-emitting area (EA2). The maximum length in the second direction (DR2) of the first light-emitting area (EA1) may be longer than the maximum length in the second direction (DR2) of the second light-emitting area (EA2).

[0128] In one embodiment, as illustrated in FIG. 5, in each of the plurality of pixels (PX), a first light-emitting area (EA1) and a second light-emitting area (EA2) may be adjacent in the second direction (DR2). A first light-emitting area (EA1) and a third light-emitting area (EA3) may be adjacent in the first direction (DR1). A second light-emitting area (EA2) and a third light-emitting area (EA3) may be adjacent in the first direction (DR1). An area of ​​the first light-emitting area (EA1), an area of ​​the second light-emitting area (EA2), and an area of ​​the third light-emitting area (EA3) may be different.

[0129] In another embodiment, as illustrated in FIG. 6, in each of the plurality of pixels (PX), the first light-emitting area (EA1) and the second light-emitting area (EA2) may be adjacent in the first direction (DR1), the second light-emitting area (EA2) and the third light-emitting area (EA3) may be adjacent in the first diagonal direction (DD1), and the first light-emitting area (EA1) and the third light-emitting area (EA3) may be adjacent in the second diagonal direction (DD2).

[0130] In the illustrated drawing, the first diagonal direction (DD1) intersects with the first direction (DR1) and the second direction (DR2) as horizontal directions, respectively. For example, the first diagonal direction (DD1) may be a direction inclined at 45 degrees with respect to the first direction (DR1) and the second direction (DR2), respectively, but is not limited thereto. The second diagonal direction (DD2) intersects with the first direction (DR1) and the second direction (DR2), respectively, as horizontal directions. For example, the second diagonal direction (DD2) may be a direction opposite to the first direction (DR1) and inclined at 45 degrees with respect to the second direction (DR2), respectively, but is not limited thereto. The second diagonal direction (DD2) is a direction orthogonal to the first diagonal direction (DD1).

[0131] The first light-emitting area (EA1) can emit light of a first color, the second light-emitting area (EA2) can emit light of a second color, and the third light-emitting area (EA3) can emit light of a third color. Here, the light of the first color can be light in a red wavelength band, the second light can be light in a green wavelength band, and the third light can be light in a blue wavelength band. For example, the blue wavelength band refers to a light whose main peak wavelength is included in a wavelength band of about 370 nm to 460 nm, the green wavelength band refers to a light whose main peak wavelength is included in a wavelength band of about 480 nm to 560 nm, and the red wavelength band refers to a light whose main peak wavelength is included in a wavelength band of about 600 nm to 750 nm.

[0132] Although FIGS. 5 and 6 illustrate that each of the plurality of pixels (PX) includes three light-emitting areas (EA1, EA2, EA3), the embodiments of the present specification are not limited thereto. That is, each of the plurality of pixels (PX) may include four or more light-emitting areas.

[0133] In addition, the shape and arrangement of the light-emitting areas of the plurality of pixels (PX) are not limited to those illustrated in FIGS. 5 and 6. For example, the light-emitting areas of the plurality of pixels (PX) may be arranged in a stripe structure in which the light-emitting areas are arranged in the first direction (DR1), a PenTile® structure in which the light-emitting areas have a diamond arrangement, or a hexagonal structure in which the light-emitting areas are arranged in a hexagonal planar shape as illustrated in FIG. 6.

[0134] Fig. 7 is a cross-sectional view showing an example of a display panel cut along line X1-X1' of Fig. 5.

[0135] Referring to FIG. 7, the display panel (100) may include a semiconductor backplane (SBP), a light emitting element backplane (EBP), an display element layer (EML), an encapsulation layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0136] A semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) including a plurality of pixel transistors (PTRs), a plurality of semiconductor insulating films covering the plurality of pixel transistors (PTRs), and a plurality of contact terminals (CTEs) electrically connected to each of the plurality of pixel transistors (PTRs). The plurality of pixel transistors (PTRs) may be the first to sixth transistors (T1 to T6) (see FIG. 4) described in conjunction with FIG. 4.

[0137] The semiconductor substrate (SSUB) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate (SSUB) may be a substrate doped with a first type impurity. A plurality of well regions (WA) may be arranged on an upper surface of the semiconductor substrate (SSUB). The plurality of well regions (WA) may be regions doped with a second type impurity. The second type impurity may be different from the first type impurity described above. For example, when the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Alternatively, when the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0138] Each of the plurality of well regions (WA) may include a source region (SA) corresponding to a source electrode of a pixel transistor (PTR), a drain region (DA) corresponding to a drain electrode, and a channel region (CH) disposed between the source region (SA) and the drain region (DA).

[0139] A bottom insulating film (BINS) may be disposed between the gate electrode (GE) and the well region (WA). A side insulating film (SINS) may be disposed on a side of the gate electrode (GE). The side insulating film (SINS) may be disposed on the bottom insulating film (BINS).

[0140] Each of the source region (SA) and the drain region (DA) may be a region doped with a first type impurity. The gate electrode (GE) of the pixel transistor (PTR) may overlap the well region (WA) in the third direction (DR3). The channel region (CH) may overlap the gate electrode (GE) in the third direction (DR3). The source region (SA) may be arranged on one side of the gate electrode (GE), and the drain region (DA) may be arranged on the other side of the gate electrode (GE).

[0141] Each of the plurality of well regions (WA) may further include a first low-concentration impurity region (LDD1) disposed between the channel region (CH) and the source region (SA), and a second low-concentration impurity region (LDD2) disposed between the channel region (CH) and the drain region (DA). The first low-concentration impurity region (LDD1) may be a region having a lower impurity concentration than the source region (SA) due to the lower insulating film (BINS). The second low-concentration impurity region (LDD2) may be a region having a lower impurity concentration than the drain region (DA) due to the lower insulating film (BINS). The distance between the source region (SA) and the drain region (DA) may increase due to the first low-concentration impurity region (LDD1) and the second low-concentration impurity region (LDD2). Therefore, since the length of the channel region (CH) of each pixel transistor (PTR) increases, punch-through and hot carrier phenomena due to short channels are prevented.

[0142] The first semiconductor insulating film (SINS1) may be disposed on a semiconductor substrate (SSUB). The first semiconductor insulating film (SINS1) may be formed of an inorganic film of the silicon nitride carbon (SiCN) or silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto.

[0143] The second semiconductor insulating film (SINS2) may be disposed on the first semiconductor insulating film (SINS1). The second semiconductor insulating film (SINS2) may be formed of an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto.

[0144] A plurality of contact terminals (CTEs) may be arranged on a second semiconductor insulating film (SINS2). Each of the plurality of contact terminals (CTEs) may be connected to one of a gate electrode (GE), a source region (SA), and a drain region (DA) of each of the pixel transistors (PTRs) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The plurality of contact terminals (CTEs) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these.

[0145] A third semiconductor insulating film (SINS3) may be disposed on each side of the plurality of contact terminals (CTE). The upper surface of each of the plurality of contact terminals (CTE) may be exposed without being covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) may be formed of an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto.

[0146] The semiconductor substrate (SSUB) can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, thin film transistors (TFTs) can be arranged on the glass substrate or polymer resin substrate. The glass substrate is a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can bend or flex.

[0147] The light emitting element backplane (EBP) may include a plurality of conductive layers (ML1 to ML8), a plurality of vias (VA1 to VA9), and a plurality of insulating films (INS1 to INS9).

[0148] The first to eighth conductive layers (ML1 to ML8) connect a plurality of contact terminals (CTE) exposed on the semiconductor backplane (SBP) to implement the pixel circuit of the first sub-pixel (SP1) illustrated in FIG. 4. For example, only the first to sixth transistors (T1 to T6) are disposed on the semiconductor backplane (SBP), and the connection wiring of the first to sixth transistors (T1 to T6), and the first capacitor (CP1) and the second capacitor (CP2) may be disposed on the first to eighth conductive layers (ML1 to ML8). In addition, a drain region corresponding to the drain electrode of the fourth transistor (T4), a source region corresponding to the source electrode of the fifth transistor (T5), and a connection portion between the first electrode of the light-emitting element (LE) may also be disposed on the first to eighth conductive layers (ML1 to ML8).

[0149] A first insulating film (INS1) may be disposed on a semiconductor backplane (SBP). Each of the first vias (VA1) may penetrate the first insulating film (INS1) and be connected to a contact terminal (CTE) exposed on the semiconductor backplane (SBP). Each of the first conductive layers (ML1) may be disposed on the first insulating film (INS1) and connected to the first via (VA1).

[0150] A second insulating film (INS2) may be disposed on the first insulating film (INS1) and the first conductive layers (ML1). Each of the second vias (VA2) may be connected to the first conductive layer (ML1) exposed through the second insulating film (INS2). Each of the second conductive layers (ML2) may be disposed on the second insulating film (INS2) and connected to the second via (VA2).

[0151] A third insulating film (INS3) may be disposed on the second insulating film (INS2) and the second conductive layers (ML2). Each of the third vias (VA3) may be connected to the second conductive layer (ML2) exposed through the third insulating film (INS3). Each of the third conductive layers (ML3) may be disposed on the third insulating film (INS3) and connected to the third via (VA3).

[0152] A fourth insulating film (INS4) may be disposed on the third insulating film (INS3) and the third conductive layers (ML3). Each of the fourth vias (VA4) may be connected to the third conductive layer (ML3) exposed through the fourth insulating film (INS4). Each of the fourth conductive layers (ML4) may be disposed on the fourth insulating film (INS4) and connected to the fourth via (VA4).

[0153] A fifth insulating film (INS5) may be disposed on the fourth insulating film (INS4) and the fourth conductive layers (ML4). Each of the fifth vias (VA5) may be connected to the fourth conductive layer (ML4) exposed through the fifth insulating film (INS5). Each of the fifth conductive layers (ML5) may be disposed on the fifth insulating film (INS5) and connected to the fifth via (VA5).

[0154] The sixth insulating film (INS6) may be disposed on the fifth insulating film (INS5) and the fifth conductive layers (ML5). Each of the sixth vias (VA6) may be connected to the fifth conductive layer (ML5) exposed through the sixth insulating film (INS6). Each of the sixth conductive layers (ML6) may be disposed on the sixth insulating film (INS6) and connected to the sixth via (VA6).

[0155] The seventh insulating film (INS7) may be disposed on the sixth insulating film (INS6) and the sixth conductive layers (ML6). Each of the seventh vias (VA7) may be connected to the sixth conductive layer (ML6) exposed through the seventh insulating film (INS7). Each of the seventh conductive layers (ML7) may be disposed on the seventh insulating film (INS7) and connected to the seventh via (VA7).

[0156] The eighth insulating film (INS8) may be disposed on the seventh insulating film (INS7) and the seventh conductive layers (ML7). Each of the eighth vias (VA8) may be connected to the seventh conductive layer (ML7) exposed through the eighth insulating film (INS8). Each of the eighth conductive layers (ML8) may be disposed on the eighth insulating film (INS8) and connected to the eighth via (VA8).

[0157] The first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8) may be formed of substantially the same material. The first to eighth conductive layers (ML1 to ML8) and the first to eighth vias (VA1 to VA8) may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these. The first to eighth insulating films (INS1 to ILD8) may be formed of an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto.

[0158] Each of the thickness of the first conductive layer (ML1), the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) may be greater than each of the thickness of the first via (VA1), the thickness of the second via (VA2), the thickness of the third via (VA3), the thickness of the fourth via (VA4), the thickness of the fifth via (VA5), and the thickness of the sixth via (VA6). Each of the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) may be greater than the thickness of the first conductive layer (ML1). The thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) may be substantially the same. For example, the thickness of the first conductive layer (ML1) is approximately 1360 Å, the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6) are each approximately 1440 Å, and the thickness of the first via (VA1), the thickness of the second via (VA2), the thickness of the third via (VA3), the thickness of the fourth via (VA4), the thickness of the fifth via (VA5), and the thickness of the sixth via (VA6) are each approximately 1150 Å. However, the thicknesses of the first to sixth conductive layers (ML1, ML2, ML3, ML4, ML5, ML6) and the first to sixth vias (VA1, VA2, VA3, VA4, VA5, VA6) are not limited thereto.

[0159] The thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) may each be greater than the thickness of the first conductive layer (ML1), the thickness of the second conductive layer (ML2), the thickness of the third conductive layer (ML3), the thickness of the fourth conductive layer (ML4), the thickness of the fifth conductive layer (ML5), and the thickness of the sixth conductive layer (ML6). The thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) may each be greater than the thickness of the seventh via (VA7) and the thickness of the eighth via (VA8). The thickness of the seventh via (VA7) and the thickness of the eighth via (VA8) may each be greater than the thickness of the first via (VA1), the thickness of the second via (VA2), the thickness of the third via (VA3), the thickness of the fourth via (VA4), the thickness of the fifth via (VA5), and the thickness of the sixth via (VA6). The thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) may be substantially the same. For example, the thickness of the seventh conductive layer (ML7) and the thickness of the eighth conductive layer (ML8) are each approximately 9000 Å, and the thickness of the seventh via (VA7) and the thickness of the eighth via (VA8) are each approximately 6000 Å. However, the thicknesses of the seventh conductive layer (ML7), the eighth conductive layer (ML8), the seventh via (VA7), and the eighth via (VA8) are not limited thereto.

[0160] The ninth insulating film (INS9) may be disposed on the eighth insulating film (INS8) and the eighth conductive layer (ML8). The ninth insulating film (INS9) may be formed of an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto.

[0161] Each of the ninth vias (VA9) can be connected to the exposed eighth conductive layer (ML8) through the ninth insulating film (INS9). The ninth vias (VA9) can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy including any one of these. The thickness of the ninth via (VA9) is approximately 16500 Å. However, the thickness of the ninth via (VA9) is not limited thereto.

[0162] An EML may be disposed on an EBP. The EML may include light emitting elements (LEs), each of which includes a reflective electrode layer (RL), tenth and eleventh insulating films (INS10, INS11), a tenth via (VA10), a first electrode (AND), a light emitting stack (IL), and a second electrode (CAT), a pixel defining layer (PDL), and a plurality of trenches (TRC).

[0163] A reflective electrode layer (RL) may be disposed on the ninth insulating film (INS9). The reflective electrode layer (RL) may include at least one reflective electrode (RL1, RL2, RL3, RL4). For example, the reflective electrode layer (RL) may include first to fourth reflective electrodes (RL1, RL2, RL3, RL4) as illustrated in FIG. 7, but is not limited thereto.

[0164] Each of the first reflective electrodes (RL1) is disposed on the ninth insulating film (INS9) and can be connected to the ninth via (VA9). The first reflective electrodes (RL1) can be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these. For example, the first reflective electrodes (RL1) can include titanium nitride (TiN).

[0165] Each of the second reflective electrodes (RL2) may be disposed on the first reflective electrode (RL1). The second reflective electrodes (RL2) may be formed of one or an alloy including one or more of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the second reflective electrodes (RL2) may include aluminum (Al).

[0166] Each of the third reflective electrodes (RL3) may be disposed on the second reflective electrode (RL2). The third reflective electrodes (RL3) may be formed of one or an alloy including one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the third reflective electrodes (RL3) may include titanium nitride (TiN).

[0167] Each of the fourth reflective electrodes (RL4) may be disposed on the third reflective electrode (RL3). The fourth reflective electrodes (RL4) may be formed of one or an alloy including one or more of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the fourth reflective electrodes (RL4) may include titanium (Ti).

[0168] Since the second reflective electrode (RL2) is an electrode that substantially reflects light from the light emitting elements (LE), the thickness of the second reflective electrode (RL2) may be greater than the thickness of the first reflective electrode (RL1), the thickness of the third reflective electrode (RL3), and the thickness of the fourth reflective electrode (RL4). For example, the thickness of the first reflective electrode (RL1), the thickness of the third reflective electrode (RL3), and the thickness of the fourth reflective electrode (RL4) are approximately 100 Å, and the thickness of the second reflective electrode (RL2) is approximately 850 Å. However, the thicknesses of the first to fourth reflective electrodes (RL1, RL2, RL3, RL4) are not limited thereto.

[0169] The tenth insulating film (INS10) may be disposed on the ninth insulating film (INS9). The tenth insulating film (INS10) may be disposed between reflective electrode layers (RL) that are adjacent to each other in the horizontal direction. The tenth insulating film (INS10) may be formed of an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto. In some embodiments, although not shown in the drawings, the tenth insulating film (INS10) may be disposed not only between the reflective electrode layers (RL) but also on the reflective electrode layers (RL).

[0170] The eleventh insulating film (INS11) may be disposed on the tenth insulating film (INS10) and the reflective electrode layer (RL). The eleventh insulating film (INS11) may be formed of an inorganic film of the silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto. The tenth insulating film (INS10) and the eleventh insulating film (INS11) may be optical auxiliary layers through which light reflected by the reflective electrode layer (RL) among the light emitted from the light emitting elements (LE) passes.

[0171] In some embodiments, in order to match the resonance distance of light emitted from light emitting elements (LE) in at least one of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3), the total thicknesses of the insulating films disposed between the first electrode (AND) and the reflective electrode layer (RL) of each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3) may be different from each other.

[0172] In one embodiment, as illustrated in the drawing, when the tenth insulating film (INS10) is not disposed between the first electrode (AND) and the reflective electrode layer (RL) and the eleventh insulating film (INS11) is disposed, the thicknesses of the eleventh insulating films (INS11) disposed in each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3) may be different. For example, the thickness of the eleventh insulating film (INS11) disposed in the first sub-pixel (SP1) may be smaller than the thickness of the eleventh insulating film (INS11) disposed in the second sub-pixel (SP2), and the thickness of the eleventh insulating film (INS11) disposed in the second sub-pixel (SP2) may be smaller than the thickness of the eleventh insulating film (INS11) disposed in the third sub-pixel (SP3).

[0173] In another embodiment, in the first sub-pixel (SP1), neither the tenth insulating film (INS10) nor the eleventh insulating film (INS11) may be disposed between the first electrode (AND) and the reflective electrode layer (RL), in the second sub-pixel (SP2), either the tenth insulating film (INS10) or the eleventh insulating film (INS11) may be disposed between the first electrode (AND) and the reflective electrode layer (RL), and in the third sub-pixel (SP3), both the tenth insulating film (INS10) and the eleventh insulating film (INS11) may be disposed between the first electrode (AND) and the reflective electrode layer (RL).

[0174] In another embodiment, a twelfth insulating film may be further disposed between the first electrode (AND) and the reflective electrode layer (RL). In this case, in the first sub-pixel (SP1), any one layer of the tenth insulating film (INS10), the eleventh insulating film (INS11), and the twelfth insulating film may be disposed between the first electrode (AND) and the reflective electrode layer (RL), in the second sub-pixel (SP2), any two layers of the tenth insulating film (INS10), the eleventh insulating film (INS11), and the twelfth insulating film may be disposed between the first electrode (AND) and the reflective electrode layer (RL), and in the third sub-pixel (SP3), all of the tenth insulating film (INS10), the eleventh insulating film (INS11), and the twelfth insulating film may be disposed between the first electrode (AND) and the reflective electrode layer (RL).

[0175] In summary, the distance between the first electrode (AND) and the reflective electrode layer (RL) in each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3) may be different. That is, in order to adjust the distance from the reflective electrode layer (RL) to the second electrode (CAT) according to the main wavelength of light emitted from each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3), the presence or absence or thickness of the tenth insulating film (INS10) and the eleventh insulating film (INS11) in each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3) may be set.

[0176] In Fig. 7, the total thickness of the insulating film disposed between the first electrode (AND) and the reflective electrode layer (RL) is illustrated as being larger in the order of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3), but is not limited thereto. That is, the distance between the first electrode (AND) and the reflective electrode layer (RL) in the third sub-pixel (SP3) is illustrated as being larger than the distance between the first electrode (AND) and the reflective electrode layer (RL) in the second sub-pixel (SP2) and the distance between the first electrode (AND) and the reflective electrode layer (RL) in the first sub-pixel (SP1), and the distance between the first electrode (AND) and the reflective electrode layer (RL) in the second sub-pixel (SP2) is illustrated as being larger than the distance between the first electrode (AND) and the reflective electrode layer (RL) in the first sub-pixel (SP1), but the embodiments of the present specification are not limited thereto. The relationship between the total thickness of the insulating film disposed between the first electrode (AND) and the reflective electrode layer (RL) in each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3) can be varied depending on the resonance distance.

[0177] Each of the tenth vias (VA10) may be connected to the exposed reflective electrode layer (RL) through the tenth insulating film (INS10) and / or the eleventh insulating film (INS11). The tenth vias (VA10) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy including any one of these. The thickness of the tenth via (VA10) in the second sub-pixel (SP2) may be smaller than the thickness of the tenth via (VA10) in the third sub-pixel (SP3), and the thickness of the tenth via (VA10) in the first sub-pixel (SP1) may be smaller than the thickness of the tenth via (VA10) in the second sub-pixel (SP2), but is not limited thereto.

[0178] A first electrode (AND) of each of the light emitting elements (LE) is disposed on an eleventh insulating film (INS11) and may be connected to a tenth via (VA10). The first electrode (AND) of each of the light emitting elements (LE) may be connected to a drain region (DA) or a source region (SA) of a pixel transistor (PTR) through the tenth via (VA10), the first to fourth reflective electrodes (RL1 to RL4), the first to ninth vias (VA1 to VA9), the first to eighth conductive layers (ML1 to ML8), and the contact terminal (CTE). The first electrode (AND) of each of the light emitting elements (LE) may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these. For example, the first electrode (AND) of each of the light emitting elements (LE) may be titanium nitride (TiN).

[0179] A pixel defining layer (PDL) may be disposed on a portion of the first electrode (AND) of each of the light emitting elements (LE). The pixel defining layer (PDL) may cover an edge of the first electrode (AND) of each of the light emitting elements (LE). The pixel defining layer (PDL) serves to define first light emitting areas (EA1), second light emitting areas (EA2), and third light emitting areas (EA3).

[0180] The first light-emitting area (EA1) may be defined as an area in which a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT) are sequentially stacked in the first sub-pixel (SP1) to emit light. The second light-emitting area (EA2) may be defined as an area in which a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT) are sequentially stacked in the second sub-pixel (SP2) to emit light. The third light-emitting area (EA3) may be defined as an area in which a first electrode (AND), a light-emitting stack (IL), and a second electrode (CAT) are sequentially stacked in the third sub-pixel (SP3) to emit light.

[0181] The pixel defining layer (PDL) may include first to third pixel defining layers (PDL1, PDL2, and PDL3). The first pixel defining layer (PDL1) may be disposed on the edge of the first electrode (AND) of each of the light emitting elements (LE), the second pixel defining layer (PDL2) may be disposed on the first pixel defining layer (PDL1), and the third pixel defining layer (PDL3) may be disposed on the second pixel defining layer (PDL2). The first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) may be formed of an inorganic layer of a silicon oxide (SiOx) series, but the embodiments of the present specification are not limited thereto. The thickness of the first pixel defining layer (PDL1), the thickness of the second pixel defining layer (PDL2), and the thickness of the third pixel defining layer (PDL3) may each be approximately 500 Å.

[0182] When the first pixel defining film (PDL1), the second pixel defining film (PDL2), and the third pixel defining film (PDL3) are formed as a single pixel defining film, the height of the single pixel defining film increases, and the first encapsulating inorganic film (TFE1) may be broken due to step coverage. Step coverage refers to the ratio of the degree to which the thin film is coated on an inclined portion to the degree to which the thin film is coated on a flat portion. The lower the step coverage, the higher the possibility that the thin film will be broken on an inclined portion.

[0183] Therefore, in order to prevent the first encapsulating inorganic film (TFE1) from being broken due to step coverage, the first pixel defining film (PDL1), the second pixel defining film (PDL2), and the third pixel defining film (PDL3) may have a cross-sectional structure having a step-shaped step. For example, the width of the first pixel defining film (PDL1) may be greater than the width of the second pixel defining film (PDL2) and the width of the third pixel defining film (PDL3), and the width of the second pixel defining film (PDL2) may be greater than the width of the third pixel defining film (PDL3). The width of the first pixel defining film (PDL1), the width of the second pixel defining film (PDL2), and the width of the third pixel defining film (PDL3) each indicate a length in a horizontal direction perpendicular to the third direction (DR3).

[0184] Each of the plurality of trenches (TRC) may penetrate the first pixel defining film (PDL1), the second pixel defining film (PDL2), and the third pixel defining film (PDL3). In addition, each of the plurality of trenches (TRC) may penetrate the eleventh insulating film (INS11). In each of the plurality of trenches (TRC), a portion of the eleventh insulating film (INS11) may have a fine shape.

[0185] At least one trench (TRC) may be arranged between adjacent sub-pixels (SP1, SP2, SP3). In FIG. 7, two trenches (TRC) are arranged between adjacent sub-pixels (SP1, SP2, SP3), but the embodiment of the present specification is not limited thereto.

[0186] The light-emitting stack (IL) may include a plurality of intermediate layers. In FIG. 7, the light-emitting stack (IL) is illustrated as having a three-tandem structure including a first stack layer (IL1), a second stack layer (IL2), and a third stack layer (IL3), but the embodiments of the present specification are not limited thereto. For example, the light-emitting stack (IL) may have a two-tandem structure including two intermediate layers.

[0187] In a 3-tandem structure, the light-emitting stack (IL) may have a tandem structure including a plurality of stack layers (IL1, IL2, IL3) that emit different light. For example, the light-emitting stack (IL) may include a first stack layer (IL1) that emits light of a first color, a second stack layer (IL2) that emits light of a third color, and a third stack layer (IL3) that emits light of the second color. The first stack layer (IL1), the second stack layer (IL2), and the third stack layer (IL3) may be sequentially stacked.

[0188] The first stack layer (IL1) may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stack layer (IL2) may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stack layer (IL3) may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0189] A first charge generation layer may be disposed between the first stack layer (IL1) and the second stack layer (IL2) to supply charges to the second stack layer (IL2) and electrons to the first stack layer (IL1). The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first stack layer (IL1) and a P-type charge generation layer that supplies holes to the second stack layer (IL2). The N-type charge generation layer may include a dopant of a metallic material.

[0190] A second charge generation layer may be disposed between the second stack layer (IL2) and the third stack layer (IL3) to supply charges to the third stack layer (IL3) and electrons to the second stack layer (IL2). The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stack layer (IL2) and a P-type charge generation layer that supplies holes to the third stack layer (IL3).

[0191] A first stack layer (IL1) is disposed on the first electrodes (AND) and the pixel defining layer (PDL), and may be disposed on the bottom surface of each trench (TRC). Due to the trench (TRC), the first stack layer (IL1) may be disconnected between adjacent sub-pixels (SP1, SP2, SP3). A second stack layer (IL2) may be disposed on the first stack layer (IL1). Due to the trench (TRC), the second stack layer (IL2) may be disconnected between adjacent sub-pixels (SP1, SP2, SP3). A cavity (ESS) or empty space may be disposed between the first stack layer (IL1) and the second stack layer (IL2). A third stack layer (IL3) may be disposed on the second stack layer (IL2). The third stack layer (IL3) is not interrupted by the trench (TRC) and may be arranged to cover the second stack layer (IL2) in each of the trenches (TRC). That is, in the 3-tandem structure, each of the plurality of trenches (TRC) may be a structure for interrupting the first and second stack layers (IL1, IL2), the first charge generation layer, and the second charge generation layer of the display element layer (EML) between the neighboring sub-pixels (SP1, SP2, SP3). In addition, in the 2-tandem structure, each of the plurality of trenches (TRC) may be a structure for interrupting the charge generation layer and the lower intermediate layer, which are arranged between the lower intermediate layer and the upper intermediate layer.

[0192] In order to stably separate the first and second stack layers (IL1, IL2) of the display element layer (EML) between adjacent sub-pixels (SP1, SP2, SP3), the height of each of the plurality of trenches (TRC) may be greater than the height of the pixel defining layer (PDL). The height of each of the plurality of trenches (TRC) refers to the length of each of the plurality of trenches (TRC) in the third direction (DR3). The height of the pixel defining layer (PDL) refers to the length of the pixel defining layer (PDL) in the third direction (DR3). In order to separate the first to third stack layers (IL1, IL2, IL3) of the display element layer (EML) between adjacent sub-pixels (SP1, SP2, SP3), another structure may exist instead of the trenches (TRC). For example, instead of the trenches (TRC), a reverse-tapered partition wall may be disposed on the pixel defining layer (PDL).

[0193] The number of stack layers (IL1, IL2, IL3) that emit different light is not limited to that illustrated in FIG. 7. For example, the light-emitting stack (IL) may include two intermediate layers. In this case, one of the two intermediate layers may be substantially identical to the first stack layer (IL1), and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be disposed between the two intermediate layers to supply electrons to one of the intermediate layers and charges to the other intermediate layer.

[0194] In addition, although FIG. 7 illustrates that the first to third stack layers (IL1, IL2, IL3) are disposed in the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3), the embodiments of the present specification are not limited thereto. For example, the first stack layer (IL1) may be disposed in the first light-emitting area (EA1) and may not be disposed in the second light-emitting area (EA2) and the third light-emitting area (EA3). In addition, the second stack layer (IL2) may be disposed in the second light-emitting area (EA2) and may not be disposed in the first light-emitting area (EA1) and the third light-emitting area (EA3). In addition, the third stack layer (IL3) may be disposed in the third light-emitting area (EA3) and may not be disposed in the first light-emitting area (EA1) and the second light-emitting area (EA2). In this case, the first to third color filters (CF1, CF2, CF3) of the optical layer (OPL) may be omitted.

[0195] The second electrode (CAT) may be disposed on the third stack layer (IL3). The second electrode (CAT) may be disposed on the third stack layer (IL3) in each of the plurality of trenches (TRC). The second electrode (CAT) may be formed of a transparent conductive material (TCO) that can transmit light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode (CAT) is formed of a semi-transmissive metallic material, the light output efficiency of each of the first to third sub-pixels (SP1, SP2, SP3) may be increased by a micro cavity.

[0196] An encapsulating layer (TFE) may be disposed on an indicator element layer (EML). The encapsulating layer (TFE) may include at least one inorganic film (TFE1, TFE2) to prevent oxygen or moisture from penetrating into the indicator element layer (EML). For example, the encapsulating layer (TFE) may include a first encapsulating inorganic film (TFE1) and a second encapsulating inorganic film (TFE2).

[0197] The first encapsulating inorganic film (TFE1) may be disposed on the second electrode (CAT). The first encapsulating inorganic film (TFE1) may be formed as a multi-film in which one or more inorganic films of silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx) are alternately laminated. The first encapsulating inorganic film (TFE1) may be formed by a chemical vapor deposition (CVD) process.

[0198] The second encapsulating inorganic film (TFE2) may be disposed on the first encapsulating inorganic film (TFE1). The second encapsulating inorganic film (TFE2) may be formed of a titanium oxide (TiOx) or aluminum oxide layer (AlOx), but the embodiments of the present specification are not limited thereto. The second encapsulating inorganic film (TFE2) may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulating inorganic film (TFE2) may be smaller than the thickness of the first encapsulating inorganic film (TFE1).

[0199] The display panel (100) may further include an organic film (APL). The organic film (APL) may be a layer for increasing interfacial adhesion between the encapsulation layer (TFE) and the optical layer (OPL). The organic film (APL) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0200] The optical layer (OPL) may include a plurality of color filters (CF1, CF2, CF3), a plurality of lenses (LNS), and a filling layer (FIL). The plurality of color filters (CF1, CF2, CF3) may include first to third color filters (CF1, CF2, CF3). The first to third color filters (CF1, CF2, CF3) may be disposed on an organic film (APL).

[0201] The first color filter (CF1) may overlap with the first emission area (EA1) of the first sub-pixel (SP1). The first color filter (CF1) may transmit light of a first color, i.e., light in a red wavelength band. The red wavelength band refers to a wavelength band of approximately 600 nm to 750 nm. Therefore, the first color filter (CF1) may transmit light of the first color among the light emitted from the first emission area (EA1).

[0202] The second color filter (CF2) may overlap with the second emission area (EA2) of the second sub-pixel (SP2). The second color filter (CF2) may transmit light of a second color, i.e., light in a green wavelength band. The green wavelength band refers to a wavelength band of approximately 480 nm to 560 nm. Therefore, the second color filter (CF2) may transmit light of a second color among the light emitted from the second emission area (EA2).

[0203] The third color filter (CF3) may overlap with the third emission area (EA3) of the third sub-pixel (SP3). The third color filter (CF3) may transmit light of a third color, i.e., light in a blue wavelength band. The blue wavelength band refers to a wavelength band of approximately 370 nm to 460 nm. Therefore, the third color filter (CF3) may transmit light of a third color among the light emitted from the third emission area (EA3).

[0204] Each of the plurality of lenses (LNS) may be positioned on each of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3). Each of the plurality of lenses (LNS) may be a structure for increasing the proportion of light directed toward the front of the display device (10). Each of the plurality of lenses (LNS) may have a cross-sectional shape that is convex in the upward direction.

[0205] A filling layer (FIL) may be disposed on a plurality of lenses (LNS). The filling layer (FIL) may have a predetermined refractive index so that light may propagate in a third direction (DR3) at an interface between the plurality of lenses (LNS) and the filling layer (FIL). In addition, the filling layer (FIL) may be a planarizing layer. The filling layer (FIL) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0206] The cover layer (CVL) may be disposed on the filler layer (FIL). The cover layer (CVL) may be a glass substrate or a polymer resin such as resin. If the cover layer (CVL) is a glass substrate, it may be attached to the filler layer (FIL). In this case, the filler layer (FIL) serves to adhere the cover layer (CVL). If the cover layer (CVL) is a glass substrate, it serves as an encapsulation substrate. If the cover layer (CVL) is a polymer resin such as resin, it may be applied directly on the filler layer (FIL).

[0207] A polarizing plate (POL) may be disposed on one surface of the cover layer (CVL). The polarizing plate (POL) may be a structure for preventing visibility degradation due to external light reflection. The polarizing plate (POL) may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but the embodiments of the present specification are not limited thereto. However, if visibility due to external light reflection is sufficiently improved by the first to third color filters (CF1, CF2, CF3), the polarizing plate (POL) may be omitted.

[0208] FIG. 8 is an exploded perspective view showing a head-mounted display device according to one embodiment.

[0209] Referring to FIG. 8, the head-mounted display device (1000) is formed in the form of glasses or a head-mounted form, and provides an image to the user using the display device (10_1).

[0210] The head-mounted display device (1000) may include a see-through type that provides augmented reality based on actual external objects, and a see-closed type that provides virtual reality to the user with a screen independent of external objects.

[0211] A head-mounted display device (1000) may include a main frame (MF) mounted on a user's body, a display device (10_1) mounted on the main frame (MF) to display an image, and a cover frame (CF) covering the display device (10_1).

[0212] The display device (10_1) may be formed integrally with a head-mounted display device (1000) that can be carried by a user and easily mounted or removed on the face or head, and may also be formed in a form assembled to the head-mounted display device (1000). The display device (10_1) may be substantially the same as the display device (10) described in conjunction with FIGS. 1 and 2.

[0213] The display device (10_1) may include a display panel (DP) for displaying an image, first and second lens frames (OS1, OS2) for refracting image display light, and first and second multi-channel lenses (LS1, LS2) for forming an optical path so that the image display light of the display panel (DP) is visible to the user.

[0214] The main frame (MF) can be worn on the user's face and head. The main frame (MF) can be formed into a shape corresponding to the structure of the user's head and face.

[0215] The display device (10_1), that is, the display panel (DP), the first and second lens frames (OS1, OS2), and the first and second multi-channel lenses (LS1, LS2), together with the main frame (MF), may be formed integrally. Alternatively, the display panel (DP), the first and second lens frames (OS1, OS2), and the first and second multi-channel lenses (LS1, LS2) may be assembled and mounted on the main frame (MF). To this end, the main frame (MF) may include a space or structure in which the display panel (DP), the first and second lens frames (OS1, OS2), and the first and second multi-channel lenses (LS1, LS2) can be stored. The main frame (MF) may further include a structure such as a strap or a belt to facilitate mounting, and the main frame (MF) may further include a control unit, an image processing unit, a lens storage unit, and the like.

[0216] The display panel (DP) may be divided into a front surface (DP_FS) on which an image is displayed, and a rear surface (DP_RS) located on the opposite side of the front surface (DP_FS). Image display light may be emitted through the front surface (DP_FS) of the display panel (DP). As described below, first and second lens frames (OS1, OS2) may be arranged on the front surface (DP_FS) of the display panel (DP), and first and second multi-channel lenses (LS1, LS2) may be arranged on the front surfaces of the first and second lens frames (OS1, OS2). Meanwhile, although not illustrated, at least one infrared camera may be further arranged on at least one surface of the front surface (DP_FS) or the rear surface (DP_RS) of the display panel (DP). The display panel (DP) may be substantially the same as the display panel (100) described in connection with FIG. 1, etc.

[0217] The display panel (DP) may be built into the main frame (MF) with the first and second lens frames (OS1, OS2) and the first and second multi-channel lenses (LS1, LS2) mounted and fixed thereto, or may be detachably assembled to the main frame (MF). The display panel (DP) may be configured to be opaque, transparent, or translucent depending on the design of the display device (10_1), for example, the usage form of the display device (10_1).

[0218] Each of the first and second lens frames (OS1, OS2) may have an area corresponding to the image display surface of the display panel (DP) and may be formed in a shape corresponding to the image display surface. In addition, each of the first and second lens frames (OS1, OS2) may be formed in an area and a shape corresponding to the rear surface shapes of each of the first and second multi-channel lenses (LS1, LS2). The rear surfaces of each of the first and second lens frames (OS1, OS2) may be attached to the image display surface of the display panel (DP), and the first and second multi-channel lenses (LS1, LS2) may be attached to the front surfaces of each of the first and second lens frames (OS1, OS2). The first and second lens frames (OS1, OS2) refract image display light emitted from the image display surface of the display panel (DP) at a preset angle and provide the light to the first and second multi-channel lenses (LS1, LS2) on the front surfaces, respectively.

[0219] Specifically, the first and second lens frames (OS1, OS2) can refract image display light emitted in the front direction from the image display surface of the display panel (DP) in the outward direction (or in the outer peripheral direction) compared to the front direction and provide the light to the first and second multi-channel lenses (LS1, LS2) arranged at the front, respectively. In particular, the first and second lens frames (OS1, OS2) can refract image display light incident on the rear surface in the outward direction (or in the outer peripheral direction) and provide the light to the rear surfaces of the first and second multi-channel lenses (LS1, LS2), respectively.

[0220] The first and second multi-channel lenses (LS1, LS2) form a path for light emitted through the first and second lens frames (OS1, OS2), so that the image display light can be viewed in the front direction to the user's eyes.

[0221] Each of the first and second multi-channel lenses (LS1, LS2) can provide multiple channels (or paths) for passing image display light emitted from the display panel (DP). The multiple channels can pass the image display light emitted from the display panel (DP) through different paths and provide it to the user. The image display light emitted through the first and second lens frames (OS1, OS2) is incident on each channel, and the enlarged image through each channel can be focused on the user's eyes.

[0222] The first and second multi-channel lenses (LS1, LS2) can be arranged on the front of the first and second lens frames (OS1, OS2) corresponding to the positions of the user's left and right eyes. The first and second multi-channel lenses (LS1, LS2) can be stored inside the main frame (MF).

[0223] The first and second multi-channel lenses (LS1, LS2) can refract and / or reflect the image display light emitted through the first and second lens frames (OS1, OS2) at least once to form a path to the user's eyes. At least one infrared light source may be further arranged on one side of each of the first and second multi-channel lenses (LS1, LS2) facing the main frame (MF) or the user's eyes.

[0224] A cover frame (CF) can be arranged to cover the display panel (DP) in the direction of the back surface (DP_RS) of the display panel (DP) to protect the display panel (DP). The cover frame (CF) can be mounted on the main frame (MF) by covering the display panel (DP).

[0225] Although not shown, the display device (10_1) may further include a control unit that controls the overall operation of the display device (10_1) including the display panel (DP). The control unit may control the image display operation of the display panel (DP) and the audio device, etc. Specifically, the control unit performs image processing (e.g., image mapping) according to the image display path and magnification according to the first and second lens frames (OS1, OS2) and the first and second multi-channel lenses (LS1, LS2), and controls the mapped image to be displayed on the display panel (DP). The control unit may be implemented as a dedicated processor including an embedded processor, etc., and / or a general-purpose processor including a central processing unit or an application processor, etc., but is not limited thereto.

[0226] FIG. 9 is a perspective view showing an augmented reality content providing device according to one embodiment. FIG. 10a is an exploded perspective view of the rear surface of the augmented reality content providing device of FIG. 9. FIG. 10b is an exploded perspective view of the front surface of the augmented reality content providing device of FIG. 9.

[0227] Referring to FIGS. 9, 10a, and 10b, an augmented reality content providing device (1000_1) may include a support frame (1002) supporting at least one transparent lens (1001), at least one image display module (1010), an ambient environment detection unit (1040), and a control module (1020).

[0228] The support frame (1002) may be formed in a spectacles shape including a spectacles frame and spectacles frame arms that support the frame of at least one transparent lens (1001). The shape of the support frame (1002) is not limited to a spectacles shape and may be formed in a goggle shape including a transparent lens (1001) or a head mountain shape.

[0229] The transparent lens (1001) may be formed as a left-right integral type, or may be formed as first and second transparent lenses that are separated from each other. The transparent lens (1001) formed as a left-right integral type or as a first and second transparent lens may be formed transparently or translucently using glass or plastic. Accordingly, the user can view an image of reality through the transparent lens (1001) formed as a left-right integral type or as a first and second transparent lens. Here, the transparent lens (1001), i.e., the integral lens or the first and second transparent lenses, may have a refractive power that takes the user's eyesight into consideration.

[0230] The transparent lens (1001) may further include at least one reflective member that reflects an augmented reality content image provided from at least one image display module (1010) toward the transparent lens (1001) or a user's eyes, and optical members that adjust focus and size. The at least one reflective member may be integrally built into the transparent lens (1001) and may be formed by a plurality of refractive lenses or a plurality of prisms having a predetermined curvature.

[0231] At least one image display module (1010) may include a micro LED display device (micro-LED), a nano LED display device (nano-LED), an organic light emitting display device (OLED), an inorganic EL display device (inorganic EL), a quantum dot emitting display (QED), a cathode ray tube display (CRT), a liquid crystal display (LCD), etc. The image display module (1010) may substantially include the display device (10) described with reference to FIGS. 1 and 2, etc.

[0232] The surrounding environment detection unit (1040) is assembled to or formed integrally with the support frame (1002) to detect the distance (or depth) from an object in the front direction of the support frame (1002), illuminance, the moving direction of the support frame (1002), the moving distance, the inclination, etc. To this end, the surrounding environment detection unit (1040) includes a depth sensor (1041) such as an infrared sensor or a lidar sensor, and an image sensor (1050) such as a camera. In addition, the surrounding environment detection unit (1040) may further include at least one motion sensor among an illuminance sensor, a human body detection sensor, a gyro sensor, an inclination sensor, and an acceleration sensor. In addition, the surrounding environment detection unit (1040) may further include first and second biometric sensors (1031, 1032) that detect movement information of a user's eyes or pupils.

[0233] The surrounding environment detection unit (1040) can transmit sensing signals generated through a depth sensor (1041) and at least one motion sensor to the control module (1020) in real time. In addition, the image sensor (1050) can transmit image data of at least one frame generated in real time to the control module (1020). The first and second biometric sensors (1031, 1032) of the surrounding environment detection unit (1040) can each transmit detected pupil detection signals to the control module (1020).

[0234] The control module (1020) may be assembled to at least one side of the support frame (1002) together with at least one image display module (1010) or may be formed integrally with the support frame (1002). The control module (1020) supplies augmented reality content data to at least one image display module (1010) so that the at least one image display module (1010) displays augmented reality content, for example, an augmented reality content image. At the same time, the control module (1020) may receive sensing signals, image data, and pupil detection signals from the surrounding environment detection unit (1040) in real time.

[0235] Below, a manufacturing device for a display device for manufacturing display devices (10, 10_1, 10_2, 10_3) according to the above-described embodiment is described.

[0236] Fig. 11 is a perspective view showing a manufacturing apparatus of a display device according to one embodiment. Fig. 12 is a cross-sectional view showing a manufacturing apparatus of a display device according to one embodiment. Fig. 13 is a perspective view showing a carrier according to one embodiment. Fig. 14 is a cross-sectional view showing the carrier taken along line X2-X2' of Fig. 13.

[0237] In addition to FIG. 7, referring to FIGS. 11 to 14, the manufacturing device (2000) of the display device may be a device that combines a wafer (WF) and a carrier (2200). The wafer (WF) may be a semiconductor substrate (SSUB) of the display devices (10, 10_1, 10_2, 10_3) according to the above-described embodiment. The carrier (2200) is a transport means for settling and transporting the wafer (WF) in the manufacturing process of the display devices (10, 10_1, 10_2, 10_3) according to the embodiment.

[0238] Unlike the existing display process that performs a micro-level patterning process, the manufacturing process of the display devices (10, 10_1, 10_2, 10_3) according to the above-described embodiment may perform a semiconductor process that can perform a finer patterning process and cell integration to achieve high resolution. When performing the semiconductor process, semiconductor process equipment is used instead of the existing display process equipment. However, in order to reduce costs, the logistics / transportation equipment that moves or stores the target wafer (WF) between each semiconductor process may use the existing display process equipment as is. In addition, for processes that can use the existing display process equipment other than the semiconductor process to achieve high resolution, the existing display process equipment may be used as is to reduce costs.

[0239] The shape and size of the wafer (WF) included in the display devices (10, 10_1, 10_2, 10_3) according to the above-described embodiment are different from that of the conventional glass substrate or the polymer resin substrate such as polyimide. Therefore, in order to utilize the existing display process equipment as is, the manufacturing apparatus (2000) of the display device according to the present embodiment can couple the wafer (WF) to a carrier (2200) having the same shape and size as the existing mother substrate. The wafer (WF) coupled to the carrier (2200) can be used as an object in the existing display process equipment.

[0240] A manufacturing device (2000) of a display device according to one embodiment may include a carrier transfer unit (2100), a carrier (2200), an alignment unit (2300), a first vision device (2400), a wafer transfer unit (2500), a second vision device (2600), a pressurizing unit (2700), and a control unit (2800).

[0241] The carrier transport unit (2100) transports and transfers the carrier (2200). The carrier transport unit (2100) can adjust the position of the carrier (2200) on the alignment unit (2300). The carrier transport unit (2100) can place the carrier (2200) on the alignment unit (2300).

[0242] The carrier (2200) is a transport vehicle for mounting and transporting a wafer (WF). As described above, the carrier (2200) may have the same shape and size as the main substrate used in a conventional display process. For example, the carrier (2200) may have a rectangular shape on a flat surface, but is not limited thereto.

[0243] In some embodiments, the carrier (2200) has the same size as a 10.5 generation ledger board, which is 2940 mm wide and 3370 mm high, or the same size as an 8 generation ledger board, which is 2200 mm wide and 2500 mm high, or the same size as a 7 generation ledger board, which is 1870 mm wide and 2200 mm high, or the same size as a 6 generation ledger board, which is 1500 mm wide and 1850 mm high, or the same size as a 5.5 generation ledger board, which is 1300 mm wide and 1500 mm high, or the same size as a 4 generation ledger board, which is 730 mm wide and 920 mm high, or the same size as a 3 generation ledger board, which is 550 mm wide and 650 mm high, or the same size as a 2 generation ledger board, which is 370 mm wide and 470 mm high, or the same size as a 1 generation ledger board, which is 270 mm wide and 270 mm high. It has a size of 360 mm. However, the size of the carrier (2200) is not limited thereto.

[0244] The carrier (2200) may include a carrier body (2210), a wafer receiving portion (2220), a pin hole (2230), a carrier mark (2240), a joining portion (2250), a buffer portion (2260), and a step compensation portion (2270).

[0245] The carrier body (2210) constitutes the overall shape of the carrier (2200). The carrier body (2210) can support a wafer (WF). The carrier body (2210) can be mounted on an alignment unit (2300) in a manufacturing method (S1) of a display device (see FIG. 16). The carrier body (2210) can be mounted on a manufacturing process facility in a manufacturing process of the display devices (10, 10_1, 10_2, 10_3) according to the above-described embodiment.

[0246] The wafer receiving portion (2220) may be positioned on the carrier body (2210). For example, the wafer receiving portion (2220) may be a groove recessed from the upper surface of the carrier body (2210) toward the lower surface. The wafer receiving portion (2220) provides a space in which a wafer (WF) can be received. The shape of the wafer receiving portion (2220) may correspond to the shape of the wafer (WF). The size of the wafer receiving portion (2220) may be equal to or larger than the size of the wafer (WF).

[0247] The pin hole (2230) may be located inside the carrier body (2210). For example, the pin hole (2230) may be a hole that penetrates the lower surface of the carrier body (2210) from the bottom surface of the wafer receiving portion (2220) in the third direction (DR3). At least one pin hole (2230) may be located inside the carrier body (2210), and preferably, a plurality of pin holes may be configured. The pin hole (2230) may be a passage through which the pin (2320) of the alignment unit (2300) can reciprocate in the third direction (DR3).

[0248] The carrier mark (2240) may be positioned on the carrier body (2210). For example, the carrier mark (2240) may be positioned on the upper surface of the carrier body (2210). The carrier mark (2240) may be positioned on the outside of the wafer receiving portion (2220). At least one carrier mark (2240) may be positioned on the carrier body (2210), and preferably, a plurality of carrier marks (2240) may be formed. In the drawing, four carrier marks (2240) are illustrated, but this is not limited thereto, and the shape of the carrier mark (2240) is also not limited to that illustrated in the drawing.

[0249] The carrier mark (2240) is an alignment mark for aligning the wafer (WF) and the carrier (2200). For example, the wafer (WF) may include a wafer mark (WF_M). At least one wafer mark (WF_M) may be arranged on the wafer (WF), and preferably, a plurality of wafer marks may be provided. For example, the number of wafer marks (WF_M) may be the same as the number of carrier marks (2240), but is not limited thereto. Whether the carrier (2200) and the wafer (WF) are aligned can be determined through the relative positions of the carrier mark (2240) and the wafer mark (WF_M).

[0250] The coupling part (2250) may be positioned within the wafer receiving part (2220), as illustrated in FIGS. 13 and 14. The coupling part (2250) may be positioned on the bottom surface of the wafer receiving part (2220). The coupling part (2250) may be positioned between the wafer (WF) and the bottom surface of the wafer receiving part (2220) when the wafer (WF) and the carrier (2200) are coupled. The coupling part (2250) is a coupling means for coupling the wafer (WF) and the carrier (2200).

[0251] In one embodiment, the coupling member (2250) may include an adhesive or sticky material. For example, the coupling member (2250) may include a physical sticky chuck.

[0252] In another embodiment, the coupling unit (2250) may be involved in coupling and detachment between the wafer (WF) and the carrier (2200) using electrostatic force. For example, the coupling unit (2250) may include an electrostatic chuck. In some embodiments, when the coupling unit (2250) includes an electrostatic chuck, the display device manufacturing apparatus (2000) may further include a separate electrostatic force supply unit capable of supplying electrostatic force to the electrostatic chuck and wiring connecting the electrostatic force supply unit and the electrostatic chuck.

[0253] The buffer unit (2260) may be disposed within the wafer receiving unit (2220), as illustrated in FIGS. 13 and 14. The buffer unit (2260) may be disposed on the bottom surface of the wafer receiving unit (2220). The buffer unit (2260) may be disposed on a portion of the bottom surface of the wafer receiving unit (2220) other than a portion where the coupling unit (2250) is disposed. The buffer unit (2260) may be positioned between the wafer (WF) and the bottom surface of the wafer receiving unit (2220) when the wafer (WF) and the carrier (2200) are coupled. In some embodiments, the buffer unit (2260) may be positioned closer to the center of the wafer receiving unit (2220) than the coupling unit (2250) on a plane. That is, the coupling unit (2250) may be positioned closer to the outside of the wafer receiving unit (2220) than the buffer unit (2260) on a plane. The buffer (2260) reduces the amount of impact applied to the wafer (WF) when the wafer (WF) and the carrier (2200) are combined. For example, the buffer (2260) may include an embossing material.

[0254] In some embodiments, the buffer (2260) may have a plurality of island-type structures, as illustrated in FIG. 13. This disperses the impact force when the wafer (WF) and the carrier (2200) are joined, and prevents bubbles from forming in the central portion.

[0255] The step compensation unit (2270) may be positioned within the wafer receiving unit (2220), as illustrated in FIG. 14. The step compensation unit (2270) may be positioned on the bottom surface of the wafer receiving unit (2220). The step compensation unit (2270) may be positioned between the joining unit (2250) and the bottom surface of the wafer receiving unit (2220).

[0256] The step compensation unit (2270) is a means for compensating for the height difference between the coupling unit (2250) and the buffer unit (2260). For example, in some embodiments, the thickness (H2) of the buffer unit (2260) may be greater than the thickness (H1) of the coupling unit (2250). In this case, the step compensation unit (2270) may be arranged below the coupling unit (2250). The thickness (H2) of the buffer unit (2260) may be substantially equal to the sum of the thickness (H1) of the coupling unit (2250) and the thickness (H3) of the step compensation unit (2270).

[0257] The alignment unit (2300) is an alignment device for aligning the carrier (2200) and the wafer (WF). The alignment unit (2300) may be placed below the carrier (2200). The alignment unit (2300) may adjust the first direction (DR1) position (e.g., x in FIG. 23), the second direction (DR2) position (e.g., y in FIG. 23), the third direction (DR3) position, and the rotation angle (e.g., θ in FIG. 23) of the wafer (WF). For example, the alignment unit (2300) may be a UVW stage.

[0258] The alignment unit (2300) may include a base (2310), a pin (2320), a pin driver (2330), a carrier fixing member (2340), and a first pressure sensor (2350).

[0259] The base (2310) provides a space in which other components of the alignment unit (2300), such as a pin (2320), a pin driver (2330), a carrier fixing member (2340), and a first pressure sensor (2350), can be placed. The base (2310) can support the above other components of the alignment unit (2300). In the drawing, the base (2310) is illustrated as having a square shape, but is not limited thereto.

[0260] The pin (2320) may be disposed on the base (2310). The pin (2320) may be disposed between the base (2310) and the carrier (2200). The pin (2320) may have a shape extending in the third direction (DR3). The pin (2320) may be a pillar extending from the upper surface of the base (2310) in the third direction (DR3). At least one pin (2320) may be disposed on the base (2310), and preferably, the pin (2320) may be configured in multiple numbers. The number of pins (2320) may be substantially the same as the number of pin holes (2230). The pin (2320) may support the wafer (WF) by passing through the pin hole (2230). The pin (2320) can be moved in the opposite direction of the third direction (DR3) by the pin driver (2330) to place the wafer (WF) in the wafer receiving portion (2220) of the carrier (2200). Alternatively, the pin (2320) can be moved in the third direction (DR3) by the pin driver (2330) to detach the wafer (WF) coupled to the carrier (2200) from the carrier (2200).

[0261] In some embodiments, as illustrated in FIG. 12, the width (W2) of the pin hole (2230) may be greater than or equal to the width (W1) of the pin (2320). In FIG. 11, the pin (2320) is illustrated as having a cylindrical shape, but is not limited thereto.

[0262] The pin driver (2330) may be disposed on the base (2310). The pin driver (2330) may be disposed between the pin (2320) and the base (2310) in the third direction (DR3). The pin driver (2330) may be a driving device for adjusting the position of the pin (2320). In some embodiments, the pin driver (2330) may include a vertical driver (2331) and a rotational driver (2332).

[0263] The vertical driving unit (2331) can move the pin (2320) in a third direction (DR3). For example, the vertical driving unit (2331) can be extended or contracted in the third direction (DR3) to move the pin (2320) in the third direction (DR3). Accordingly, the wafer (WF) mounted on the pin (2320) can move in the third direction (DR3). The rotational driving unit (2332) can adjust the rotational angle of the pin (2320). Accordingly, the rotational angle of the wafer (WF) mounted on the pin (2320) can be adjusted.

[0264] The carrier fixing member (2340) may be disposed on the base (2310). The carrier fixing member (2340) may be disposed between the base (2310) and the carrier (2200). In some embodiments, as illustrated in the drawing, the carrier fixing member (2340) may have a shape extending in the third direction (DR3). The carrier fixing member (2340) may be a pillar extending in the third direction (DR3) from the upper surface of the base (2310). However, the present invention is not limited thereto, and the carrier fixing member (2340) may have various shapes that can support the carrier (2200) between the base (2310) and the carrier (2200).

[0265] In some embodiments, at least one carrier fixing member (2340) may be disposed on the base (2310), and preferably, a plurality of carrier fixing members (2340) may be disposed. For example, as illustrated in the drawing, four carrier fixing members (2340) may be disposed adjacent to corners of the base (2310). However, the present invention is not limited thereto, and the carrier fixing members (2340) may be a single wall disposed along the perimeter of the base (2310) surrounding the pin (2320). The number and shape of the carrier fixing members (2340) are not limited to those illustrated in the drawing.

[0266] The carrier fixing member (2340) can support the carrier (2200). The carrier (2200) can be mounted on the carrier fixing member (2340). The carrier fixing member (2340) can fix the carrier (2200) when the carrier (2200) and the wafer (WF) are coupled.

[0267] The first pressure sensor (2350) may be disposed between the base (2310) and the pin (2320) in the third direction (DR3). For example, the first pressure sensor (2350) may be disposed between the pin driver (2330) and the pin (2320) in the third direction (DR3). The first pressure sensor (2350) may be disposed below the pin (2320). In some embodiments, the first pressure sensors (2350) may be disposed in a one-to-one correspondence with each pin (2320). The first pressure sensor (2350) may measure the pressing force applied to each pin (2320) when the wafer (WF) is detached in the wafer detachment inspection step (S500) (see FIG. 16).

[0268] Although not shown in the drawing, the alignment unit (2300) may further include a base driving unit. The base driving unit may be a driving device for adjusting the positions of the base (2310) and other components arranged on the base (2310). For example, the base driving unit may move the base (2310) and other components arranged on the base (2310) in a first direction (DR1), a second direction (DR2), and a third direction (DR3), respectively. When the base driving unit moves the base (2310) in the first direction (DR1) and the second direction (DR2), the wafer (WF) may move along the pin (2320) in the first direction (DR1) and the second direction (DR2). When the base driving unit moves the base (2310) in the third direction (DR3), the carrier fixing unit (2340) may move in the third direction (DR3) to secure the carrier (2200).

[0269] Although not shown in the drawing, the alignment unit (2300) may further include a case that can accommodate other components of the alignment unit (2300), such as the base (2310), pin (2320), pin driver (2330), carrier fixing unit (2340), and first pressure sensor (2350), and block them from the external space. The case may be arranged on a side of the alignment unit (2300) to surround the base (2310), pin (2320), pin driver (2330), carrier fixing unit (2340), and first pressure sensor (2350).

[0270] The first vision device (2400) can be placed on the carrier (2200) and the alignment unit (2300). The first vision device (2400) can capture images of the carrier (2200) and the alignment unit (2300). The first vision device (2400) provides the captured images of the carrier (2200) and the alignment unit (2300) to the control unit (2800).

[0271] In some embodiments, the first vision device (2400) may include first to fourth cameras (2410, 2420, 2430, 2440). The first to fourth cameras (2410, 2420, 2430, 2440) may be positioned on a corner of the carrier (2200) and a corner of the alignment unit (2300), respectively. The first to fourth cameras (2410, 2420, 2430, 2440) capture images of the corner of the carrier (2200) and the corner of the alignment unit (2300), respectively, and the control unit (2800) may determine whether the corner of the carrier (2200) and the corner of the alignment unit (2300) are aligned. However, the number of cameras included in the first vision device (2400) is not limited thereto and may vary. For example, the number of cameras included in the first vision device (2400) may be equal to the number of corners of the carrier (2200).

[0272] The wafer transfer unit (2500) transports and transfers a wafer (WF). The wafer transfer unit (2500) can adjust the position of the wafer (WF) on the carrier (2200) and the alignment unit (2300). The wafer transfer unit (2500) can place the wafer (WF) on the pin (2320) of the alignment unit (2300).

[0273] The second vision device (2600) may be placed on the carrier (2200) and the wafer (WF). In some embodiments, the second vision device (2600) may be placed on a side wall of the pressurizing unit (2700), but is not limited thereto. The second vision device (2600) may capture images of the carrier (2200) and the wafer (WF). The second vision device (2600) provides images of the captured carrier (2200) and the wafer (WF) to the control unit (2800).

[0274] In some embodiments, the second vision device (2600) may include fifth through eighth cameras (2610, 2620, 2630, 2640). The fifth through eighth cameras (2610, 2620, 2630, 2640) may be disposed on the outer surface (or side wall) of the wafer receiving portion (2220). The fifth through eighth cameras (2610, 2620, 2630, 2640) capture images of the carrier mark (2240) of the carrier (2200) and the wafer mark (WF_M) of the wafer (WF), respectively, and the control unit (2800) may determine whether the carrier mark (2240) and the wafer mark (WF_M) of the wafer (WF) are aligned. However, the number of cameras included in the second vision device (2600) is not limited thereto and may be variously modified. For example, the number of cameras included in the second vision device (2600) may be equal to the number of carrier marks (2240).

[0275] The pressurizing unit (2700) can be placed on the carrier (2200) and the wafer (WF). The pressurizing unit (2700) provides a pressurizing force to the wafer (WF) placed on the carrier (2200). The wafer (WF) can be coupled to the carrier (2200) by the pressurizing force of the pressurizing unit (2700).

[0276] In some embodiments, the pressurization unit (2700) may include a pressurization body (2710), a pressurization portion (2720), and a second pressure sensor (2730).

[0277] The pressurizing body (2710) constitutes the overall shape of the pressurizing unit (2700). The pressurizing body (2710) provides a space in which the pressurizing body (2720) and the second pressure sensor (2730) are placed. In the drawing, the pressurizing body (2710) is illustrated as having a rectangular parallelepiped shape, but the shape of the pressurizing body (2710) is not limited thereto.

[0278] The pressurizing member (2720) may be disposed on the pressurizing member body (2710). For example, the pressurizing member (2720) may be disposed on the lower surface of the pressurizing member body (2710). The pressurizing member (2720) may be disposed between the pressurizing member body (2710) and the carrier (2200) or between the pressurizing member body (2710) and the wafer (WF). The pressurizing member (2720) may directly contact the wafer (WF) when the wafer (WF) is pressurized. The pressurizing member (2720) may include an elastic material to minimize damage to the wafer (WF). The pressurizing members (2720) may be configured in multiple units to distribute the pressing force applied to the wafer (WF). In this case, the island-type pressure members (2720) can be evenly distributed on the lower surface of the pressure member body (2710). In the drawing, three pressure members (2720) are illustrated, but the number of pressure members (2720) is not limited thereto.

[0279] The second pressure sensor (2730) may be disposed between the pressurizing body (2710) and the pressurizing portion (2720). For example, the second pressure sensor (2730) may be disposed between the pressurizing body (2710) and the pressurizing portion (2720) in the third direction (DR3). The second pressure sensor (2730) may be disposed above the pressurizing portion (2720). In some embodiments, the second pressure sensors (2730) may be disposed in a one-to-one correspondence with each pressurizing portion (2720). The second pressure sensor (2730) can measure the pressure applied to each pressurizing unit (2720) when the wafer (WF) is pressed in the wafer first pressurizing step (S300) (see FIG. 16), the wafer second pressurizing step (S700) (see FIG. 16), and the wafer re-pressurizing step (S930) (see FIG. 16).

[0280] Although not shown in the drawing, the pressurizing unit (2700) may further include a pressurizing driving unit. The pressurizing driving unit may be a driving device for adjusting the position of the pressurizing unit (2700). For example, the pressurizing driving unit may move the pressurizing unit (2700) in a third direction (DR3). When the pressurizing driving unit moves the pressurizing unit (2700) in the third direction (DR3), the pressurizing unit (2720) may pressurize the wafer (WF), thereby combining the wafer (WF) and the carrier (2200).

[0281] The control unit (2800) can perform operations to control other components of the manufacturing device (2000) of the display device, and generate processing signals to provide the signals to the other components. For example, the control unit (2800) can determine whether the carrier (2200) and the alignment unit (2300) are aligned, and control the carrier transport unit (2100), the alignment unit (2300), and the first vision device (2400) to align the carrier (2200) and the alignment unit (2300). As another example, the control unit (2800) can determine whether the carrier (2200) and the wafer (WF) are aligned, and control the alignment unit (2300), the wafer transport unit (2500), and the second vision device (2600) to align the carrier (2200) and the wafer (WF). As another example, the control unit (2700) can be controlled to control the pressing force when the wafer (WF) and the carrier (2200) are combined. As another example, the alignment unit (2300) can be controlled to control the pressure during detachment of the wafer (WF).

[0282] The control unit (2800) is described below with further reference to FIG. 15.

[0283] Fig. 15 is a block diagram showing a control unit according to one embodiment.

[0284] In addition to FIGS. 11 to 14, referring to FIG. 15, the control unit (2800) may include an alignment processing unit (2810), an alignment correction value calculation unit (2820), a pressure processing unit (2830), and a detachment processing unit (2840).

[0285] The alignment processing unit (2810) can control the alignment between the carrier (2200) and the alignment unit (2300) and the alignment between the carrier (2200) and the wafer (WF).

[0286] For example, the alignment processing unit (2810) can provide a driving signal to the carrier transfer unit (2100) to position the carrier (2200) on the alignment unit (2300). The alignment processing unit (2810) can provide a driving signal to the first vision device (2400) to capture an image of the carrier (2200) and the alignment unit (2300). The alignment processing unit (2810), which receives the image from the first vision device (2400), can determine whether the carrier (2200) and the alignment unit (2300) are aligned. If the carrier (2200) and the alignment unit (2300) are correctly aligned, the alignment processing unit (2810) can provide a driving signal to the alignment unit (2300) to seat and fix the carrier (2200) on the carrier fixing unit (2340) of the alignment unit (2300).

[0287] As another example, the alignment processing unit (2810) can provide a driving signal to the wafer transfer unit (2500) to position the wafer (WF) on the carrier (2200). The alignment processing unit (2810) can provide a driving signal to the second vision device (2600) to capture an image of the carrier mark (2240) of the carrier (2200) and the wafer mark (WF_M) of the wafer (WF). The alignment processing unit (2810), which receives the image from the second vision device (2600), can determine whether the carrier (2200) and the wafer (WF) are aligned. If the carrier (2200) and the wafer (WF) are correctly aligned, the alignment processing unit (2810) can provide a driving signal to the pin driving unit (2330) of the alignment unit (2300) to place the wafer (WF) in the wafer receiving portion (2220) of the carrier (2200).

[0288] The alignment correction value calculation unit (2820) can calculate the degree of warpage of the wafer (WF) due to pressurization. The alignment correction value calculation unit (2820) can calculate the degree of warpage of the wafer (WF) due to pressurization as a correction value and reflect this in advance when realigning the wafer (WF).

[0289] For example, the alignment correction value calculation unit (2820) after pressurizing the wafer (WF) can provide a driving signal to the second vision device (2600) to re-capture the image of the carrier mark (2240) of the carrier (2200) and the wafer mark (WF_M) of the wafer (WF). The alignment correction value calculation unit (2820), which receives the image from the second vision device (2600), can compare the image before pressing with the image after pressing to calculate the degree of misalignment of the wafer (WF) after pressing. The alignment correction value calculation unit (2820) can calculate the degree of misalignment of the wafer (WF) after pressing as a correction value and provide the correction value to the alignment unit (2300). The alignment unit (2300) can align the wafer (WF) and the carrier (2200) by shifting from the existing alignment position by the correction value, and in this state, the second pressurization of the wafer (WF) can be performed again.

[0290] Meanwhile, if a misalignment still occurs between the wafer (WF) and the carrier (2200) even after the secondary pressurization, the alignment correction value calculation unit (2820) can calculate a new correction value using the accumulated data of the existing correction values. This will be described later with reference to FIG. 30.

[0291] The manufacturing device (2000) of the display device according to the present embodiment can improve the alignment accuracy of the carrier (2200) and the wafer (WF) through the calculation of the correction value of the alignment correction value calculation unit (2820).

[0292] The pressurizing unit (2830) can control the pressurizing force of the pressurizing unit (2700) when pressurizing the wafer (WF).

[0293] For example, the pressurizing unit (2830) can provide a driving signal to the pressurizing unit (2700) so that the pressurizing unit (2720) presses the wafer (WF) placed on the carrier (2200). At the same time, the pressurizing unit (2830) can receive in real time the pressurizing force applied to the pressurizing unit (2720) from the second pressure sensor (2730) of the pressurizing unit (2700). Accordingly, the pressurizing unit (2830) can prevent damage to the wafer (WF) by causing the pressurizing unit (2700) to provide an appropriate pressurizing force to the wafer (WF) in real time.

[0294] The detachment processing unit (2840) can control the pressure of the alignment unit (2300) when detaching the wafer (WF).

[0295] For example, the detachment processing unit (2840) can provide a driving signal to the alignment unit (2300) to cause the pin (2320) to press the wafer (WF) coupled to the carrier (2200). At the same time, the detachment processing unit (2840) can receive in real time the pressing force applied to the pin (2320) from the first pressure sensor (2350) of the alignment unit (2300). Accordingly, the detachment processing unit (2840) can prevent damage to the wafer (WF) by causing the alignment unit (2300) to provide an appropriate pressing force to the wafer (WF) in real time.

[0296] Below, a method for manufacturing a display device according to one embodiment is described.

[0297] Fig. 16 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0298] Referring to FIG. 16, a method (S1) for manufacturing a display device according to one embodiment may include a carrier and alignment unit alignment step (S100), a wafer primary alignment and settling step (S200), a wafer primary pressurization step (S300), a first misalignment inspection step (S400), a wafer detachment inspection step (S500), a wafer secondary alignment and settling step (S600), a wafer secondary pressurization step (S700), a second misalignment inspection step (S800), and an alignment correction value recalculation and wafer realignment step (S900).

[0299] The alignment correction value recalculation and wafer realignment step (S900) may include an alignment correction value recalculation step (S910), a wafer realignment and settling step (S920), a wafer re-pressurization step (S930), and a misalignment re-inspection step (S940).

[0300] Fig. 17 is a cross-sectional view showing step S100 of Fig. 16.

[0301] In addition to FIGS. 15 and 16, referring to FIG. 17, in the carrier and alignment unit alignment step (S100), the carrier transfer unit (2100) (see FIG. 11) can receive a driving signal from the alignment processing unit (2810) of the control unit (2800) to position the carrier (2200) on the alignment unit (2300).

[0302] The first vision device (2400) can receive a driving signal from the alignment processing unit (2810) of the control unit (2800) and capture an image of the carrier (2200) and the alignment unit (2300). The first vision device (2400) can provide the captured image to the alignment processing unit (2810) of the control unit (2800).

[0303] The alignment processing unit (2810), which receives an image from the first vision device (2400), can determine whether the carrier (2200) and the alignment unit (2300) are aligned. The alignment processing unit (2810) can provide a driving signal to the carrier transport unit (2100) (see FIG. 11) in real time to align the carrier (2200) with the alignment unit (2300).

[0304] When the carrier (2200) and the alignment unit (2300) are properly aligned, the alignment unit (2300) can receive a driving signal from the alignment processing unit (2810) and move in the third direction (DR3). Accordingly, the carrier (2200) can be placed and fixed on the carrier fixing unit (2340) of the alignment unit (2300).

[0305] Figures 18 and 19 are cross-sectional views showing step S200 of Figure 16.

[0306] In addition to FIGS. 15 and 16, referring to FIGS. 18 and 19, in the wafer primary alignment and settling step (S200), the wafer transfer unit (2500) (see FIG. 11) can receive a driving signal from the alignment processing unit (2810) of the control unit (2800) to position the wafer (WF) on the carrier (2200).

[0307] The second vision device (2600) can receive a driving signal from the alignment processing unit (2810) of the control unit (2800) to capture an image of the carrier mark (2240) of the carrier (2200) and the wafer mark (WF_M) of the wafer (WF). The second vision device (2600) can provide the captured image to the alignment processing unit (2810) of the control unit (2800).

[0308] The alignment processing unit (2810) that receives an image from the second vision device (2600) can determine whether the carrier (2200) and the wafer (WF) are aligned. The alignment processing unit (2810) can provide a driving signal to the wafer transfer unit (2500) (see FIG. 11) in real time to align the wafer (WF) to the carrier (2200).

[0309] When the carrier (2200) and the wafer (WF) are properly aligned, the pin driving unit (2330) of the alignment unit (2300) can receive a driving signal from the alignment processing unit (2810) and move in the third direction (DR3). Accordingly, the wafer (WF) can be placed on the pin (2320).

[0310] When the wafer (WF) is seated on the pin (2320), the pin driving unit (2330) of the alignment unit (2300) can receive a driving signal from the alignment processing unit (2810) and move in the opposite direction of the third direction (DR3). Accordingly, the wafer (WF) can be seated in the wafer receiving unit (2220) of the carrier (2200).

[0311] Figures 20 and 21 are cross-sectional views showing step S300 of Figure 16.

[0312] In addition to FIGS. 15 and 16, referring to FIGS. 20 and 21, in the wafer primary pressurization step (S300), the pressurization unit (2700) may receive a driving signal from the pressurization processing unit (2830) and move in the opposite direction of the third direction (DR3). Accordingly, the pressurization portion (2720) of the pressurization unit (2700) may pressurize the upper surface of the wafer (WF) mounted on the carrier (2200).

[0313] Simultaneously with pressurization, the second pressure sensor (2730) of the pressurization unit (2700) can provide the pressurization force applied to the pressurization part (2720) to the pressurization processing unit (2830) in real time. The pressurization processing unit (2830) can store first pressurization data that is preset so that the pressurization unit (2700) can apply an appropriate pressurization force to the wafer (WF) when the wafer (WF) and the carrier (2200) are combined. The first pressurization data can include information about the maximum pressurization force and pressurization time when the wafer (WF) and the carrier (2200) are combined. The pressurization processing unit (2830) can provide the first pressurization data to the pressurization unit (2700) in real time so that the pressurization unit (2700) can pressurize the wafer (WF) with an appropriate pressurization force. Accordingly, damage to the wafer (WF) can be prevented.

[0314] Meanwhile, as illustrated in Fig. 21, a slip phenomenon may occur when the wafer (WF) is pressed depending on the pressing angle of the pressing portion (2720), the thickness difference of the joining portion (2250), the frictional force between the wafer (WF) and the joining portion (2250), etc. Accordingly, a misalignment may occur between the wafer (WF) and the carrier (2200).

[0315] Fig. 22 is a cross-sectional view showing step S400 of Fig. 16. Fig. 23 is a plan view for explaining a method for measuring the degree of warpage of a wafer.

[0316] In addition to FIGS. 15 and 16, referring to FIGS. 22 and 23, in the first distortion inspection step (S400), the pressurizing unit (2700) can receive a driving signal from the pressurizing processing unit (2830) and move in the third direction (DR3).

[0317] After the first pressurization step, the second vision device (2600) can receive a driving signal from the alignment correction value calculation unit (2820) of the control unit (2800) to re-capture images of the carrier mark (2240) of the carrier (2200) and the wafer mark (WF_M) of the wafer (WF). The second vision device (2600) can provide the re-captured image to the alignment correction value calculation unit (2820) of the control unit (2800).

[0318] The alignment correction value calculation unit (2820) that receives the image from the second vision device (2600) can calculate the degree of warpage of the wafer (WF) after pressing by comparing the image before pressing and the image after pressing.

[0319] As illustrated in FIG. 23, the wafer (WF'') after being pressed may be deviated to a certain degree compared to the wafer (WF') before being pressed. For example, the center (C'') of the wafer (WF'') after being pressed may be shifted by x in the first direction (DR1) and by y in the second direction (DR2) compared to the center (C') of the wafer (WF') before being pressed. In addition, the wafer (WF'') after being pressed may be rotated by θ compared to the wafer (WF') before being pressed.

[0320] The alignment correction value calculation unit (2820) can convert the misalignment degree of (x, y, θ) into a correction value of (-x, -y, -θ). The alignment correction value calculation unit (2820) can provide the correction value of (-x, -y, -θ) to the alignment unit (2300). The alignment unit (2300) can use the correction value in the wafer secondary alignment and settling step (S600). This will be described with reference to FIGS. 25 and 26 together with a description of the wafer secondary alignment and settling step (S600).

[0321] Figure 24 is a cross-sectional view showing step S500 of Figure 16.

[0322] In addition to FIGS. 15 and 16, referring to FIG. 24, in the wafer detachment inspection step (S500), the pin driving unit (2330) of the alignment unit (2300) may receive a driving signal from the detachment processing unit (2840) and move in the third direction (DR3). Accordingly, the pin (2320) may pressurize the lower surface of the wafer (WF) coupled to the carrier (2200).

[0323] Simultaneously with the pressurization, the first pressure sensor (2350) of the alignment unit (2300) can provide the pressing force applied to the pin (2320) to the detachment processing unit (2840) in real time. The detachment processing unit (2840) can store second pressing data that is preset so that the alignment unit (2300) can apply an appropriate pressing force to the wafer (WF) when detaching the wafer (WF). The second pressing data can include information about the maximum pressing force and the pressing time when detaching the wafer (WF). The detachment processing unit (2840) can provide the second pressing data to the alignment unit (2300) in real time so that the alignment unit (2300) can press the wafer (WF) with an appropriate pressing force. Accordingly, damage to the wafer (WF) can be prevented.

[0324] The method (S1) for manufacturing a display device according to the present embodiment includes a wafer detachment inspection step (S500), so that after the manufacturing process of the display device is completely completed, the wafer (WF) is inspected in advance to prevent the wafer (WF) from being detached or damaged due to detachment, resulting in process loss, thereby enabling the wafer (WF) with poor detachment to be selected in advance, thereby minimizing process loss.

[0325] Figures 25 and 26 are cross-sectional views illustrating step S600 of Figure 16. Figure 27 is a schematic diagram for explaining alignment correction value data processed by the control unit.

[0326] In addition to FIGS. 15, 16, and 23, referring to FIGS. 25 to 27, in the wafer secondary alignment and settling step (S600), the alignment unit (2300) can receive an alignment correction value from the alignment correction value calculation unit (2820) of the control unit (2800).

[0327] The alignment unit (2300) provided with the alignment correction value can shift the wafer (WF) from the existing alignment position (e.g., the center (C') of the wafer (WF') before pressing) by the correction value of (-x, -y, -θ) described above to align the wafer (WF) on the carrier (2200).

[0328] During the process of aligning the wafer (WF) on the carrier (2200) by shifting the alignment correction value by the alignment unit (2300), the second vision device (2600) can provide in real time an image obtained by capturing the carrier mark (2240) and the wafer mark (WF_M) of the wafer (WF) to the alignment correction value calculation unit (2820). The alignment processing unit (2810) that receives the image from the second vision device (2600) can provide a driving signal to the alignment unit (2300) to adjust the position and rotation angle of the wafer (WF).

[0329] When the carrier (2200) and the wafer (WF) are shifted by a correction value and are correctly aligned, the pin driving unit (2330) of the alignment unit (2300) can receive a driving signal from the alignment correction value calculation unit (2820) and move in the opposite direction of the third direction (DR3). Accordingly, the wafer (WF) can be seated in the wafer receiving unit (2220) of the carrier (2200).

[0330] Meanwhile, as illustrated in FIG. 27, the alignment correction data (ADT) provided by the alignment correction calculation unit (2820) to the alignment unit (2300) may include the alignment correction values ​​(t-10 to t-1) of the previous wafers (WF) and the correction value (t) of the current wafer (WF). The correction value (t) of the current wafer (WF) refers to the correction values ​​of (-x, -y, -θ) calculated by the alignment correction calculation unit (2820) after the first pressurization of the current wafer (WF). The alignment correction values ​​(t-10 to t-1) of the previous wafers (WF) will be described later with reference to FIG. 30.

[0331] In the wafer secondary alignment and settling step (S600), the secondary alignment of the wafer (WF) can be performed using only the correction value (t) of the current wafer (WF), rather than the alignment correction values ​​(t-10 to t-1) of previous wafers (WF).

[0332] Figure 28 is a cross-sectional view showing step S700 of Figure 16.

[0333] In addition to FIGS. 15 and 16, referring to FIG. 28, in the wafer secondary pressurization step (S700), the pressurization unit (2700) can pressurize the wafer (WF). The wafer secondary pressurization step (S700) is substantially the same as the wafer primary pressurization step (S300) described with reference to FIG. 20, and therefore, further description thereof is omitted.

[0334] Figure 29 is a cross-sectional view showing step S800 of Figure 16.

[0335] In addition to FIGS. 15 and 16, referring to FIG. 29, in the second distortion inspection step (S800), the pressurizing unit (2700) can receive a driving signal from the pressurizing processing unit (2830) and move in the third direction (DR3).

[0336] After the second pressurization step, the second vision device (2600) can receive a driving signal from the alignment correction value calculation unit (2820) of the control unit (2800) to re-capture an image of the carrier mark (2240) of the carrier (2200) and the wafer mark (WF_M) of the wafer (WF). The second vision device (2600) can provide the re-captured image to the alignment correction value calculation unit (2820) of the control unit (2800).

[0337] The alignment correction value calculation unit (2820) that receives the image from the second vision device (2600) can calculate the degree of warpage of the wafer (WF) after pressing by comparing the image before pressing and the image after pressing.

[0338] If the degree of warpage of the wafer (WF) before the first pressurization and the wafer (WF) after the second pressurization is below a threshold (OK), the method (S1) for manufacturing a display device according to one embodiment is terminated.

[0339] On the other hand, if the degree of misalignment between the wafer (WF) before the first pressurization and the wafer (WF) after the second pressurization exceeds the threshold (NG), the alignment correction value recalculation and wafer realignment step (S900) is performed.

[0340] In some embodiments, the threshold may be approximately 10 μm to 50 μm. For example, when the threshold is 10 μm, if the degree of misalignment between the wafer (WF) before the first pressurization and the wafer (WF) after the second pressurization is 10 μm or less, the method (S1) for manufacturing a display device according to one embodiment is terminated, and if the degree of misalignment between the wafer (WF) before the first pressurization and the wafer (WF) after the second pressurization exceeds 10 μm, the alignment correction value recalculation and wafer realignment step (S900) is performed. Alternatively, when the threshold is 30㎛, if the degree of misalignment between the wafer (WF) before the first pressurization and the wafer (WF) after the second pressurization is 30㎛ or less, the manufacturing method (S1) of the display device according to one embodiment is terminated, and if the degree of misalignment between the wafer (WF) before the first pressurization and the wafer (WF) after the second pressurization exceeds 30㎛, the alignment correction value re-calculation and wafer realignment step (S900) is performed. The threshold may be variously set in the range of 10㎛ to 50㎛ depending on the process conditions of the manufacturing method (S1) of the display device according to one embodiment.

[0341] Hereinafter, with reference to FIG. 30, when the degree of misalignment of the wafer (WF) before the first pressurization and the wafer (WF) after the second pressurization exceeds the threshold (NG), the alignment correction value recalculation and wafer realignment step (S900) will be described.

[0342] Figure 30 is a cross-sectional view showing step S900 of Figure 16.

[0343] In addition to FIGS. 15 and 16, referring to FIG. 30, in the alignment correction value recalculation step (S910), the alignment correction value calculation unit (2820) can recalculate the alignment correction value. Using the recalculated alignment correction value, the wafer realignment and settling step (S920), the wafer re-pressurization step (S930), and the misalignment re-inspection step (S940) can be performed.

[0344] The wafer realignment and settling step (S920), the wafer re-pressurization step (S930), and the warp re-inspection step (S940) are substantially the same as the wafer secondary alignment and settling step (S600) described with reference to FIGS. 25 and 26, the wafer secondary pressurization step (S700) described with reference to FIG. 28, and the second warp inspection step (S800) described with reference to FIG. 29, respectively, and therefore further description thereof is omitted.

[0345] In the warpage re-inspection step (S940), if the degree of warpage of the wafer (WF) before the first pressurization and the wafer (WF) after the re-pressurization is below a threshold (OK), the method for manufacturing a display device according to one embodiment (S1) is terminated.

[0346] On the other hand, if the degree of misalignment between the wafer (WF) before the first pressurization and the wafer (WF) after the re-pressurization exceeds the threshold (NG), the alignment correction value re-calculation and wafer realignment steps (S900) are repeated.

[0347] More specifically, in the alignment correction value recalculation step (S910), unlike in the wafer secondary alignment and settling step (S600), the alignment correction values ​​(t-10 to t-1) of previous wafers (WF) included in the alignment correction value data (ADT) can be further utilized.

[0348] The alignment correction values ​​(t-10 to t-1) of the previous wafers (WF) may each include sub-correction values. For example, the t-1th alignment correction value is S t-1 1, S t-1 2, S t-1 3, S t-1 It contains 4 sub-correction values, and the t-2th alignment correction value is S t-2 1, S t-2 2 contains sub-correction values, and the t-3th alignment correction value is S t-3 1, S t-3 2, S t-3 Includes 3 sub-corrections.

[0349] The number of sub-compensation values ​​included in each alignment correction value (t-10~t) may be the same as the number of correction value calculations for each wafer (WF), i.e., the number of repetitions of the alignment correction value recalculation step (S910). For example, the correction value calculated in the first misalignment inspection (S400) may be the first sub-compensation value (S) of each alignment correction value (t-10~t). t 1, S t-1 1, S t-2 1, S t-3 1, …) can be used. The second sub-correction value (S t 2, S t-1 2, S t-2 2, S t-3 2, … ) and the subsequent sub-compensation values ​​may be correction values ​​calculated in the second misalignment inspection step (S800) or the misalignment re-inspection step (S940). The final sub-compensation values ​​(S) included in the alignment correction values ​​(t-10 to t-1) of the previous wafers (WF) t-10 , S t-9 , S t-8 , … , S t-3 3, S t-2 2, S t-1 4) may be the final correction values ​​when the degree of warpage of the wafer (WF) is below the threshold in the second warpage inspection step (S800) or the warpage re-inspection step (S940).

[0350] If the degree of warpage of the wafer (WF) exceeds the threshold in the second warpage inspection step (S800) of the current wafer (WF), the alignment correction value calculation unit (2820) calculates the average value of the alignment correction values ​​(t-10 to t-1) of the previous wafers (WF) as a new correction value (e.g., S t 1) can be used. For example, the average value of the t-10th alignment correction value to the t-1th alignment correction value can be used as a new correction value.

[0351] If the degree of warpage of the wafer (WF) exceeds the threshold in the warpage re-inspection step (S940) of the first cycle (R1), the alignment correction value calculation unit (2820) in the second cycle (R2) calculates the alignment correction values ​​(t-9 to t-1) of the previous wafers (WF) and the previous sub-correction value (S) of the current wafer (WF). t 1) The average value of the new correction value (e.g., S t 3) can be used. For example, the t-9th alignment correction value to the t-1th alignment correction value and S t The average of the first sub-sort correction values ​​can be used as a new correction value.

[0352] If the degree of warpage of the wafer (WF) exceeds the threshold in the warpage re-inspection step (S940) of the second cycle (R2), the alignment correction value calculation unit (2820) in the third cycle (R3) calculates the alignment correction values ​​(t-8 to t-1) of the previous wafers (WF) and the previous sub-correction values ​​(S) of the current wafer (WF). t 1, S t 2) The average value can be used as a new correction value. For example, the t-8th alignment correction value or the t-1th alignment correction value, S t 1st sub-alignment correction, and S t The average of the second sub-sort correction values ​​can be used as a new correction value.

[0353] In the drawing, it is illustrated that a new correction value is derived using 10 existing alignment correction values, but this is not limited to this, and the number of existing alignment correction values ​​used to derive a new correction value can be varied.

[0354] The manufacturing method (S1) of the display device according to the present embodiment can minimize warping of the wafer (WF) after the second pressurization by first reflecting the correction value calculated through the first warp inspection in the second pressurization step that follows the detachment inspection of the wafer (WF).

[0355] In addition, when a misalignment of the wafer (WF) occurs even after the secondary pressurization, the alignment process of the wafer (WF) and the carrier (2200) can be quickly performed by calculating a new correction value using the alignment correction values ​​(t-10 to t-1) of the previous wafers (WF), and the alignment accuracy of the wafer (WF) and the carrier (2200) can be improved.

[0356] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Alignment unit; A carrier disposed on the alignment unit and including a receiving portion configured to receive a wafer; A pressurizing unit placed on the carrier; A first vision device disposed on one side of the pressurizing unit on the carrier; and A manufacturing apparatus for a display device including a control unit configured to control alignment of the wafer and the carrier.

2. In paragraph 1, The carrier further includes a first alignment mark disposed on one side of the receiving portion, The above first vision device is a manufacturing device of a display device that captures the first alignment mark of the carrier and the second alignment mark of the wafer.

3. In paragraph 2, The first vision device includes a camera, A manufacturing device for a display device, wherein the number of the cameras included in the first vision device is equal to the number of the first alignment marks in the carrier.

4. In paragraph 1, The carrier further includes a coupling portion arranged on the bottom surface of the receiving portion, The above-mentioned joint is disposed between the wafer and the carrier, A manufacturing device for a display device in which the wafer and the carrier are joined to each other by the joining part.

5. In paragraph 4, The above-mentioned joint is a manufacturing device of a display device including an adhesive chuck or an electrostatic chuck.

6. In paragraph 4, The above carrier, A buffer portion disposed on a portion of the bottom surface of the receiving portion other than the portion where the connecting portion is disposed; and Further comprising a step compensation part arranged at the lower part of the above-mentioned joint, A manufacturing device for a display device, wherein the thickness of the buffer portion is equal to the sum of the thickness of the joining portion and the thickness of the step compensation portion.

7. In paragraph 1, The above alignment unit includes a pin extending in the direction of the carrier, The carrier further includes a pin hole disposed at the lower portion of the receiving portion, A manufacturing device for a display device, wherein the above pin is configured to move by penetrating the above pin hole.

8. In paragraph 7, A manufacturing device for a display device in which the wafer is mounted on the pin.

9. In paragraph 7, The above alignment unit further includes a pin driving unit disposed below the pin, The above pin driving unit is a manufacturing device of a display device including a vertical driving unit and a rotational driving unit.

10. In paragraph 7, The above alignment unit further includes a first pressure sensor disposed below the pin, A manufacturing device of a display device, wherein the first pressure sensor is configured to measure the pressure applied when the wafer is detached from the carrier.

11. In paragraph 10, The above pins are composed of multiple pieces, A manufacturing device for a display device in which the first pressure sensor is arranged in a one-to-one correspondence with each of the plurality of pins.

12. In paragraph 1, The above pressurizing unit, A pressurizing portion disposed on a first surface facing the carrier; and Including a second pressure sensor disposed between the first surface and the pressurizing portion, The second pressure sensor is a manufacturing device of a display device configured to measure the pressure applied when the carrier and the wafer are combined.

13. In paragraph 1, The first vision device captures a first image before the first pressing of the wafer after the first alignment of the wafer, and captures a second image after the first pressing of the wafer. The above control unit includes an alignment correction value calculation unit, The above alignment correction value calculation unit calculates a correction value by comparing the first image and the second image, The above alignment unit is a manufacturing device for a display device that aligns the wafer so that it shifts by the compensation value when the wafer is secondarily pressed.

14. In paragraph 1, Further comprising a second vision device disposed on the carrier, The second vision device is a manufacturing device of a display device that captures images of the carrier and the alignment unit.

15. In paragraph 1, A manufacturing apparatus for a display device further comprising a carrier transfer unit configured to position the carrier on the alignment unit.

16. In paragraph 1, A manufacturing apparatus for a display device further comprising a wafer transfer unit configured to position the wafer on the carrier.

17. In paragraph 16, The above control unit includes an alignment processing unit, The above alignment processing unit provides a driving signal to the wafer transfer unit, The wafer transfer unit, which receives the driving signal, positions the wafer on the carrier, The first vision device provides an image of the carrier and the wafer to the alignment processing unit, A manufacturing device for a display device in which the alignment processing unit, which has received the image, provides the driving signal again to the wafer transfer unit to align the wafer to the carrier in real time.

18. In paragraph 1, A manufacturing apparatus for a display device, wherein on a plane, the carrier has a square shape and the wafer has a circular shape.

19. Step of first aligning the wafer to the reference point of the carrier; A step of first pressurizing the above wafer; A first warpage inspection step for measuring the first warpage degree of the wafer and the carrier; A step of detaching the wafer from the carrier; A step of secondarily aligning the wafer to the carrier; A step of secondarily pressurizing the wafer; and A second warpage inspection step for measuring the second warpage degree of the wafer and the carrier; A method for manufacturing a display device, wherein the second alignment step includes a step of aligning the wafer so that it is shifted from the reference point by the correction value using the first degree of distortion measured in the first distortion inspection step as a correction value.

20. In paragraph 19, A method for manufacturing a display device, wherein the method for manufacturing the display device is terminated when the second degree of distortion is below a threshold value in the second distortion inspection step.

21. In paragraph 19, A method for manufacturing a display device, wherein, if the second distortion degree exceeds a threshold in the second distortion inspection step, a step of recalculating the correction value and realigning the wafer is further performed.

22. In paragraph 21, The step of recalculating the above correction value and realigning the wafer is as follows: A step of recalculating the above correction value; A step of rearranging the above wafer; a step of repressurizing the wafer; and A method for manufacturing a display device, comprising a misalignment re-inspection step of measuring a third misalignment degree of the wafer and the carrier.

23. In paragraph 22, A method for manufacturing a display device, wherein the step of recalculating the above correction value includes a step of calculating the correction value of the current wafer using the correction values ​​of previous wafers.

24. In paragraph 23, A method for manufacturing a display device, wherein the method for manufacturing the display device is terminated when the third degree of distortion is below the threshold in the above distortion re-examination step.

25. In paragraph 23, A method for manufacturing a display device, wherein, if the third degree of distortion exceeds the threshold in the above distortion re-inspection step, the step of recalculating the correction value and realigning the wafer is performed again.

26. In paragraph 25, The correction values ​​of the above previous wafers each include at least one sub-correction value, A method for manufacturing a display device, wherein the number of sub-correction values ​​included in the correction values ​​of the previous wafers is equal to the number of repetitions of the step of recalculating the correction values.

27. In paragraph 26, A method for manufacturing a display device, wherein the final sub-correction value among the sub-correction values ​​included in each of the correction values ​​of the previous wafers is the correction value of the previous wafers.

28. In paragraph 19, A method for manufacturing a display device in which, in the step of first pressurizing the wafer and the step of second pressurizing the wafer, the combined pressing force is corrected in real time according to the pressing force measured by the pressing sensor.

29. In paragraph 19, A method for manufacturing a display device in which, in the step of detaching the wafer from the carrier, the detachment pressure is corrected in real time according to the pressure measured by the pressure sensor.

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