Method of manufacturing semiconductor RRAM memory structure based on silicon oxide and structure produced by this method

Abstract

Disclosed is a method of manufacturing a semiconductor RRAM memory structure of metal-insulator-semiconductor configuration, where the top electrode (1) is a metal, the dielectric layer (2) is silicon oxide, and the bottom electrode (3) is a silicon layer of n-type or p- type. The dielectric layer (2) is formed on a silicon substrate during a rapid thermal oxidation process under an atmosphere of oxygen or a mixture of oxygen and an inert gas, at a temperature in the range of 600-1200°C during 10-2500 s. A memory structure produced by this method is also disclosed.

Description

[0001] Method of manufacturing semiconductor RRAM memory structure based on silicon oxide and structure produced by this method

[0002] The subject of the invention is a method of manufacturing a semiconductor RRAM memory structure based on silicon oxide and a structure manufactured by the method.

[0003] Resistive RAM memory - RRAM or ReRAM - (Resistive Random Access Memory) is a type of non-volatile semiconductor random access memory (RAM) based on the Metal-Insulator- Semiconductor (MIS) structure.

[0004] Several manufacturing methods of MIS structures are known in the art, employing technological processes for example wet etching and cleaning, photolithography, thermal oxidation, deposition of layers, for example, using the magnetron sputtering technique.

[0005] The deposition of a layer of dielectric material such as silicon oxide on an electrode is known, for example, from the application specification No. US20140291602A1 entitled “Oxide memory resistor including semiconductor nanoparticles” which discloses memory resistors, arrays of memory resistors and a method of manufacturing memory resistors. This specification presents memory resistors having an ‘on’ state and an ‘off’ state, and comprising: (a) a first electrode; (b) a second electrode; (c) a dielectric layer disposed between the first and second electrodes; wherein the dielectric layer comprises nanoparticles of a semiconductor material, and in the ‘on’ state the nanoparticles form at least one conductive fiber surrounded by the dielectric layer, thereby providing a conductive path between the first electrode and the second electrode.

[0006] Another document describing a MIS structure is the application specification No. US20200043550A1 entitled “A Switching Resistor And Method Of Making Such A Device”, which introduces a switching resistor having a low-resistance state and a high-resistance state. The switching resistor comprises a dielectric layer placed between a first electrode and a second electrode. The switching resistor further comprises a structured interface between the first electrode and the dielectric layer. The structured interface promotes the formation of a conductive path in the dielectric layer between the first electrode and the second electrode.

[0007] Furthermore, from the application specification No. GB2589320A entitled “Method for manufacturing a memory resistor device” a memory resistor device and a method of manufacturing comprising depositing a first layer of a dielectric material on a first electrode, removing (for example, by etching) a subsection of the first dielectric layer (for example, by lithography) to expose an edge (greater number of edges) of the dielectric material (for example, to form dielectric posts), and further depositing a second layer of a dielectric material to form one or more boundaries or interfaces between the edges of the first and second layers of dielectric material, are known. A second electrode is also provided, wherein the boundaries between the edges of the first layer and the second dielectric material extend at least partially from the first electrode to the second electrode. The boundaries act as nucleation centers and allow conductive filaments to form between the electrodes upon application of voltage between the electrodes, creating alternate resistance states. The dielectric material may be silicon oxide (SiOx), which can be deposited using the ALD (Atomic Layer Deposition) method. Additional buffer layers may be used, together with the planarization process. The second dielectric layer may comprise nanoscale columns of dielectric material. Additional layers of material (for example, aluminum oxide) may be deposited between the first and second dielectric layers.

[0008] Another method known in the art of manufacturing MIS structures is the production of dielectric material using the method of thermal oxidation in a high-temperature furnace. From the article by Piotr Wisniewski, Jakub Jasinski, Andrzej Mazurak, Bartlomiej Stonio and Bogdan Majkusiak entitled “Investigation of Electrical Properties of the Al / SiO2 / n++-Si Resistive Switching Structures by Means of Static, Admittance, and Impedance Spectroscopy Measurements” (Materials 2021, 14(20), 6042; https: / / doi.org / 10.3390 / mal4206042), a phenomenon of resistive switching in Al / SiO2 / n++-Si structures is known, characterized by DC measurements, small-signal admittance and complex impedance spectroscopy. In this work, possible transport mechanisms in the high- and low-resistance states were identified. Based on the results from the applied measurement techniques, an electrical equivalent circuit of the structure was proposed. The influence of parasitic elements on the measurement results was discussed and it was shown that an appropriate model can provide useful information about the electrical properties of the device. Good agreement between the characteristics of the proposed equivalent circuit and the experimental data obtained using different measurement procedures confirmed validity of the applied methodology and its suitability for electrical characterization of RRAM memory. However, in the case of these studies, the key dielectric layer is produced by thermal oxidation in a high-temperature furnace. This technique involves introducing silicon substrates into a furnace heated to a temperature of over 800°C. The duration of such a process can range from several minutes to several hours. The disadvantage of this process is the longterm exposure of the structures produced on the substrate to high temperature, which can negatively affect the forms from technological processes already carried out. An answer to this problem is to perform the thermal oxidation process in an RTP-type reactor. A technical problem of known state-of-the-art technical solutions is the formation of the RRAM MIS structure by oxidizing silicon while maintaining a low thermal budget. By utilizing RTP processes, one shortens the duration of the oxidation process, which enables maintaining an acceptable thermal budget. This enables easier integration of structures with components already formed on the semiconductor substrate.

[0009] Rapid Thermal Processing (RTP) is a technological process used in the semiconductor industry, during which the semiconductor substrate can be heated to a temperature exceeding 1000°C within a few seconds, and the key factor is the heating rate of the substrate, which can be up to 200°C / second. The challenge is to carry out the process in a predictable and controllable manner by measuring and controlling the temperature across the substrate in order to obtain uniform heating of the substrate under a given gas atmosphere.

[0010] The subject of the invention in an embodiment is shown in the drawing in which:

[0011] Fig. 1. shows the arrangement of layers of the RRAM structure,

[0012] Fig. 2 shows a schematic drawing of a cross-section of the RRAM structure after electroforming,

[0013] Fig. 3 shows example current- voltage characteristics of the structure according to the invention.

[0014] The invention provides a method of manufacturing a semiconductor RRAM memory structure based on a metal-insulator-semiconductor structure, in which the top electrode is metal, the dielectric layer is silicon oxide, and the bottom electrode is a silicon layer of n-type or p-type, characterized in that the dielectric layer is formed on a silicon substrate during a rapid thermal oxidation process under an atmosphere of oxygen or a mixture of oxygen and an inert gas at a ratio of oxygen flow to the overall gas flow in the RTP reactor in the range of 10% -100%, at a temperature in the range of 600-1200°C, taking 10-2500 s.

[0015] Preferably, the rapid thermal oxidation temperature is no more than 900 degrees Celsius.

[0016] Preferably, the dielectric layer is formed for a time necessary to obtain a thickness of 1 to 100 nm.

[0017] Preferably, the dielectric layer consisting of silicon oxide is formed for a time necessary to obtain a thickness of 5 nm.

[0018] Preferably, the inert gas is argon or nitrogen. The invention also provides a semiconductor RRAM memory structure produced by the method as defined above.

[0019] Preferably, the metallic top electrode has a thickness in the range of 5-500 nm.

[0020] Preferably, the top electrode is made of the following materials: Al, Ti, TiN, Hf, Si, Ge, W, Mo, Ni, Pt, Pd, Au, Ta, Cr, Zn, or combinations thereof.

[0021] Preferably, the dielectric layer has a thickness of 1 to 100 nm.

[0022] Preferably, the bottom electrode is made of silicon with a resistivity in the range of 0.0001-100 Ohm*cm.

[0023] Preferably, the resistivity of the bottom electrode is not greater than 0.005 Ohm*cm.

[0024] Advantages of the invention are reduction of the thermal budget, compatibility with the CMOS technology (Complementary Metal-Oxide-Semiconductor), and thus the possibility of integrating structures on a semiconductor substrate with other semiconductor structures already produced.

[0025] The invention is illustrated by the following embodiments.

[0026] Method of obtaining a semiconductor RRAM memory structure with variable resistance (Resistive Random Access Memory, RRAM or ReRAM) based on the MIS structure (Metal - Insulator-Semiconductor)

[0027] By applying an appropriate voltage between the electrodes of the memory structure, it is possible to affect the values of resistance and impedance of the dielectric layer. While doing so, the aforementioned parameters can change continuously or stepwise over a wide range of values.

[0028] It is distinctive that changes introduced in resistance and impedance can be altered by appropriate polarization of the structure. This enables permanent but reversible writing of information in the form of resistance or conductance levels of the structure, making the structure a non-volatile memory cell.

[0029] The memory structure according to the invention can be driven by voltage pulses with an amplitude comparable to the powering voltage of contemporary CMOS (Complementary Metal-Oxide-Semiconductor) chips. Appropriate control allows obtaining several levels of resistance and / or conductance, which enables using this type of structure to implement multistate logic systems similar to MLC (Multi Level Cell). The structure can be used in a non- volatile memory cell - easily integrated with the so-called selector, for example, a MOSFET transistor, which is a very important feature of this technology.

[0030] The memory structure according to the invention can be manufactured employing processes used in the semiconductor industry. By using the RTP reactor, one reduces the exposure time of structures already made on the semiconductor substrate (for example, transistors) to high temperature, which has a positive effect on the thermal budget. The structure can be used in a non-volatile memory cell. The materials and techniques used to manufacture the memory structure according to the invention are fully compatible with the silicon CMOS technology.

[0031] First, the surface of the silicon substrate is cleaned using the RCA method to remove organic impurities, native oxide and metal ions. Then, a process of etching the remaining or formed silicon oxide in a solution of buffered hydrofluoric acid (BHF) can be carried out. In the next step, a silicon oxide layer is produced by the thermal oxidation method using the RTP (Rapid Thermal Processing) process. Then, the process of making the top electrode is carried out by depositing a layer of Al metal using the physical vapor deposition method (PVD), for example magnetron sputtering. A lithography process and plasma etching of the electrode are carried out in order to reproduce its target shape and define the area of the structure being formed. The last step is thermal soaking of the structure in a mixture of hydrogen and argon gases at a temperature not exceeding 450°C.

[0032] The structure (Fig. 1) obtained by the above method has two electrodes - top (1) and bottom (3), as well as a dielectric layer (or several layers) (2) disposed between these electrodes. The bottom electrode (3) is made of silicon of n-type with a resistivity lower than 0.005 Ohm*cm. The top electrode is made of Al.

[0033] The dielectric layer (2) is silicon oxide, formed on the silicon substrate in the process of rapid thermal oxidation of silicon under the atmosphere of oxygen or the mixture of oxygen and an inert gas, using the RTP (Rapid Thermal Processing) method. The process temperature is 850 degrees Celsius. The thickness of the obtained dielectric layer is 4-5 nm, and the process is performed under the atmosphere of 100% oxygen. The process duration is 150 seconds. The dielectric layer (2) is formed by rapid thermal oxidation of silicon in the RTP-type reactor.

[0034] Oxidation of a highly doped silicon substrate in a suitable manner results in a silicon oxide layer exhibiting the resistive switching effect, being a feature required for the construction of RRAM- type memory (Resistive Random Access Memory). Fig. 2 shows the current-voltage characteristics of the structure obtained. As a result of voltage applied between the top and bottom electrodes, the properties of the silicon oxide layer change. The primary structure must be formed by applying a sufficiently high voltage (in the range of 2.5 - 4.5 V) between the electrodes. This process is called the electroforming process (5), in which a partial breakdown of the layer occurs. During this process, it is necessary to provide a current limitation (for example of 10 mA) of a certain finite value to avoid the complete electrical breakdown of the structure. As a result of the applied electric field, conductive paths (4) are formed in the material through which current can flow. They consist of, inter alia, oxygen vacancies, silicon nanocrystals or metal ions originating from the top electrode (1). After this process, the structure is ‘on’, i.e., it is in the low-resistance state (6). Changing the polarity of the applied voltage results in an interruption of the path / paths created, and the structure becomes ‘off’, i.e., it assumes the high-resistance state (7). Alternately applying voltage of different polarity turns the structure on and off. This process is completely reversible and repeatable.

[0035] List of reference numerals

[0036] 1 - top electrode

[0037] 2 - silicon oxide layer

[0038] 3 - bottom electrode

[0039] 4 - conductive path

[0040] 5 - electro forming process

[0041] 6 - low-resistance state

[0042] 7 - high-resistance state

Claims

Claims1. A method of manufacturing a semiconductor RRAM memory structure based on a metalinsulator-semiconductor structure, where the top electrode (1) is metal, the dielectric layer (2) is silicon oxide, and the bottom electrode (3) is silicon layer of an n-type or p-type, characterized in that the dielectric layer (2) is formed on a silicon substrate during a rapid thermal oxidation process under an atmosphere of oxygen or a mixture of oxygen and an inert gas at a ratio of oxygen flow to the overall gas flow in the RTP reactor in the range of 10%- 100%, at a temperature in the range of 600-1200°C, taking 10-2500 s.

2. The method of manufacturing a structure according to claim 1, characterized in that the rapid thermal oxidation temperature is no more than 900 degrees Celsius.

3. The method of manufacturing a structure according to claim 1 or 2, characterized in that the dielectric layer (2) is formed for a time necessary to obtain a thickness of 1 to 100 nm.

4. The method of manufacturing a structure according to claim 3, characterized in that the dielectric layer (2) which is silicon oxide is formed for a time necessary to obtain a thickness of 5 nm.

5. The method of manufacturing a structure according to claim 1, characterized in that the inert gas is argon or nitrogen.

6. A semiconductor RRAM memory structure produced by the method as defined in claims 1- 5.

7. The structure according to claim 6, characterized in that it comprises a metallic top electrode (1) with a thickness in the range of 5-500 nm.

8. The structure according to claim 7, characterized in that the top electrode (1) is made of the following materials: Al, Ti, TiN, Hf, Si, Ge, W, Mo, Ni, Pt, Pd, Au, Ta, Cr, Zn, or combinations thereof.

9. The structure of claim 6, characterized in that it comprises a dielectric layer (2) with a thickness of 1 to 100 nm.

10. The structure of claim 6, characterized in that it comprises a bottom electrode (3) made of silicon with a resistivity in the range of 0.0001-100 Ohm*cm.

11. The structure of claim 10, characterized in that the resistivity of the electrode (3) is not greater than 0.005 Ohm*cm.

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