Trenched semiconductor structure and manufacturing method therefor

Abstract

The present application relates to a trenched semiconductor structure and a manufacturing method therefor. The trenched semiconductor structure comprises: a semiconductor material layer, which has a first surface and a second surface and is of a first conductivity type; a first trench structure, extending from the first surface to the second surface and comprising a first electrode and a first gate, the first electrode comprising a first portion adjacent to the first gate and a second portion located below the first portion and the first gate and connected to the first portion; a first doped region, which is located on the semiconductor material layer, is adjacent to the first surface and the first portion, and is of a second conductivity type; an interlayer dielectric layer, which is located on the first surface and covers the first trench structure; a shielding metal layer, which covers the interlayer dielectric layer and the first doped region, and is in contact with the first electrode; and a metal layer, located on the interlayer dielectric layer and the first doped region. The first portion of the first electrode is located between the first doped region and the first gate, and the first electrode and the first doped region are both in contact with the shielding metal layer and are both electrically connected to the metal layer.

Description

Trench semiconductor structure and its manufacturing method Technical Field

[0001] This invention relates to trench semiconductor structures and their manufacturing methods, and more specifically, to trench metal oxide semiconductor (MOS) structures and their manufacturing methods. Background Technology

[0002] Modern power circuits require rectifiers with high power, low power loss, and fast switching. Integrating a trench MOS barrier Schottky (TMBS) diode with a shielded gate metal-oxide-semiconductor field-effect transistor (SGT MOSFET) involves placing the TMBS and SGT MOSFET in separate trenches and positioning the charge coupling between the primary charge carriers in the plateau region of the epitaxial / drift region and the metal on the insulating sidewalls of the trench. This charge coupling redistributes the electric field beneath the Schottky contact, thereby improving breakdown voltage and reducing reverse leakage current. Integrating the TMBS into the SGT-MOSFET further reduces resistance and gate capacitance, thereby reducing power loss in semiconductor power circuits and increasing switching speed.

[0003] Known methods for integrating TMBS and SGT MOSFETs involve placing the TMBS and SGT-MOSFET in adjacent areas of the same chip, requiring additional chip area. Current manufacturing methods and power circuit structures lack efficiency and flexibility, often resulting in wasted chip area and increased production costs. Therefore, existing semiconductor structures incorporating TMBS and SGT MOSFETs require further improvements in device miniaturization techniques to achieve more ideal high power and low loss, thereby improving device performance.

[0004] Summary of the Invention

[0005] Embodiments of this disclosure relate to a trench semiconductor structure. The trench semiconductor structure includes: a semiconductor material layer having a first surface and a second surface opposite to the first surface, wherein the semiconductor material layer has a first conductivity type; a first trench structure extending from the first surface to the second surface, wherein the first trench structure includes a first electrode, a first gate, and a first oxide layer separating the first electrode from the first gate, the first electrode including a first portion adjacent to the first gate, and a second portion located below and connected to the first portion and the first gate; a first doped region located on the semiconductor material layer adjacent to the first surface and adjacent to the first portion of the first electrode, wherein the first doped region has a second conductivity type; an interlayer dielectric layer located on the first surface of the semiconductor material layer and covering the first trench structure; a shielding metal layer covering the interlayer dielectric layer and the first doped region, and contacting the first electrode; and a metal layer located on the interlayer dielectric layer and the first doped region. A first portion of the first electrode is located between the first doped region and the first gate, and both the first electrode and the first doped region are in contact with the shielding metal layer for electrical connection to the metal layer.

[0006] Embodiments of this disclosure also relate to a trench semiconductor structure. The trench semiconductor structure includes: a semiconductor material layer having a first conductivity type and having a first region and a second region surrounding the first region; a first trench structure recessed into the semiconductor material layer and including a first electrode, a first gate, and a first oxide layer surrounding the first electrode and the first gate, the first electrode including a first portion adjacent to the first gate and a second portion, viewed from top view, overlapping and connected to the first portion and the first gate; a second trench structure recessed into the semiconductor material layer and including a second electrode, a second gate, and a second oxide layer surrounding the second electrode and the second gate; and a first doped region disposed within the semiconductor material layer and located between the first trench structure and the second trench structure, wherein the first doped region has a second conductivity type. The first electrode and the second electrode are disposed between the first gate and the second gate, a portion of the first electrode, a portion of the second electrode, and the first doped region located between the first electrode and the second electrode are located in the first region, and the first gate and the second gate are located in the second region.

[0007] Embodiments of this disclosure relate to a method for manufacturing a trench semiconductor structure. A method for manufacturing a trench semiconductor structure includes: forming a first trench in a semiconductor material layer, the first trench extending from a first surface to a second surface; forming a first electrode in the first trench, the first electrode including a first portion and a second portion located below and in contact with the first portion; forming a first gate in the first trench, the first gate being adjacent to the first portion of the first electrode and located above the second portion of the first electrode, the first electrode and the first gate forming a first trench structure; forming a first doped region in the semiconductor material layer adjacent to the first surface, wherein the first doped region has a second conductivity type, and the first portion of the first electrode is located between the first doped region and the first gate; forming an interlayer dielectric layer on the first surface of the semiconductor material layer, the interlayer dielectric layer covering the first trench structure and the first doped region; forming a groove penetrating the interlayer dielectric layer, exposing the first doped region and the first portion of the first electrode; forming a shielding metal layer in the groove and on the interlayer dielectric layer, the shielding metal layer covering the interlayer dielectric layer and the first doped region, and contacting the first portion of the first electrode; and forming a metal layer in the groove and on the interlayer dielectric layer and the shielding metal layer. The first part of the first electrode and the first doped region are in contact with the shielding metal layer to be electrically connected to the metal layer. Attached Figure Description

[0008] The various embodiments of this disclosure can be best understood when read in conjunction with the accompanying drawings and the following detailed description. It should be noted that the structures are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0009] Figure 1 shows a top view of a trench semiconductor structure according to certain embodiments of the present invention;

[0010] Figure 2 shows a cross-sectional view of a trench semiconductor structure according to certain embodiments of the present invention along the tangent line A-A' shown in Figure 1;

[0011] Figure 3 shows a top view of a trench semiconductor structure according to certain embodiments of the present invention;

[0012] Figure 4 shows a top view of a trench semiconductor structure according to certain embodiments of this case;

[0013] Figure 5 shows a cross-sectional view of a trench semiconductor structure according to certain embodiments of this case;

[0014] Figure 6 shows a cross-sectional view of a trench semiconductor structure according to certain embodiments of the present invention;

[0015] Figure 7 shows a cross-sectional view of a trench semiconductor structure according to certain embodiments of the present invention;

[0016] Figure 8 shows a cross-sectional view of a trench semiconductor structure according to certain embodiments of the present invention;

[0017] Figure 9 shows a cross-sectional view of a trench semiconductor structure according to certain embodiments of the present invention;

[0018] Figures 10 to 34 show one or more stages in a method for manufacturing a trench semiconductor structure according to certain embodiments of this case.

[0019] Identical or similar components are designated using the same reference numerals in the drawings and detailed description. Several embodiments of this disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0022] This disclosure provides a trench semiconductor structure and its manufacturing method. In the trench semiconductor structure of this disclosure, a TMBS diode and an SGT MOSFET are integrated, minimizing the distance between the TMBS and the SGT MOSFET, improving chip area utilization, and saving chip space.

[0023] Figure 1 shows a top view of a trench semiconductor structure 10 according to certain embodiments of the present invention. Figure 2 shows a cross-sectional view of a trench semiconductor structure 10 according to certain embodiments of the present invention along tangent A-A' in Figure 1. Specifically, the trench semiconductor structure 10 is a trench MOSFET structure having a vertical current conduction path. For example, current in the trench semiconductor structure 10 can be conducted vertically through the trench semiconductor structure 10.

[0024] In some embodiments, referring to Figures 1 and 2, the trench semiconductor structure 10 includes a semiconductor material layer 11, a first trench structure 21, a second trench structure 22, a first doped region 131, an interlayer dielectric layer 16, and a conductive material layer 18. In some embodiments, the trench semiconductor structure 10 further includes a third trench structure 23, a second doped region 132, and a third doped region 142.

[0025] In some embodiments, the semiconductor material layer 11 includes a substrate 111 and an epitaxial layer 112 located on the substrate 111. In some embodiments, the substrate 111 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon-germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the epitaxial layer 112 includes, for example, silicon, silicon carbide, germanium, silicon-germanium, gallium nitride, gallium arsenide, gallium arsenide phosphide, or other semiconductor materials. The substrate 111 is an N-type or P-type semiconductor material. The epitaxial layer 112 is an N-type or P-type semiconductor material. In some embodiments, the substrate 111 and the epitaxial layer 112 have the same conductivity type, for example, both the substrate 111 and the epitaxial layer 112 are N-type.

[0026] The substrate 111 has the same conductivity type doping as the epitaxial layer 112. In some embodiments, the substrate 111 is part of a silicon substrate or a silicon wafer. In some embodiments, the doping concentration of the substrate 111 is greater than the doping concentration of the epitaxial layer 112.

[0027] In some embodiments, the semiconductor material layer 11 defines a first region R1 as viewed from a top view and a second region R2 adjacent to the first region R1. The first region R1 contains a TMBS, and the second region R2 contains an SGT MOSFET. In some embodiments, the semiconductor material layer 11 further defines a third region R3 adjacent to the first region R1 as viewed from a top view. In some embodiments, the first region R1 is located between or surrounded by the second region R2 and the third region R3, and the third region R3 also contains an SGT MOSFET.

[0028] The semiconductor material layer 11 may have a first surface 11A and a second surface 11B opposite to the first surface 11A. The second surface 11B and the first surface 11A may be located on opposite sides of the semiconductor material layer 11. The first surface 11A and the second surface 11B may be horizontal planes. For ease of explanation, the direction orthogonal to the first surface 11A and the second surface 11B is defined as the vertical direction Z, and the plane formed by the first direction X and the second direction Y is orthogonal to the vertical direction Z. In some embodiments, the first surface 11A may be the active surface of the epitaxial layer 112. The bottom surface of the substrate 111 is the second surface 11B.

[0029] A first trench structure 21 is recessed into the semiconductor material layer 11 and extends from the first surface 11A to the second surface 11B. The first trench structure 21 includes a first electrode 210, a first gate 213, and a first oxide layer 214 separating the first electrode 210 from the first gate 213. The first electrode 210 includes a first portion 211 adjacent to the first gate 213 and a second portion 212 located below and connected to the first portion 211 and the first gate 213. In some embodiments, the first portion 211 and the second portion 212 of the first electrode 210 are integrally formed. The first portion 211 of the first electrode 210 is located between the first gate 213 and the first doped region 131. In some embodiments, the first gate 213 has a columnar structure.

[0030] In some embodiments, the top surface of the first trench structure 21 is coplanar with the first surface 11A. In some embodiments, the top surfaces of the first electrode 210 and the first gate 213 are coplanar with the first surface 11A. Viewed from a top angle, the first trench structure 21 extends in a first direction X parallel to the first surface 11A, and the first portion 211 of the first electrode 210 and the first gate 213 overlap with the second portion 212 of the lower first electrode 210.

[0031] The first oxide layer 214 is used to electrically isolate the epitaxial layer 112 from the first electrode 210 and the first gate 213. In other words, the first electrode 210 and the first gate 213 are separated from the epitaxial layer 112 via the first oxide layer 214 in the trench. The first electrode 210 and the first gate 213 are each surrounded by the first oxide layer 214. At least a portion of the first oxide layer 214 is located between the first electrode 210 and the first gate 213. At least a portion of the first oxide layer 214 serves as the gate oxide layer of the SGT MOSFET located in the third region R3. In some embodiments, the first oxide layer 214 located between the first portion 211 of the first electrode 210 and the semiconductor material layer 11 has a first thickness T1, and the first oxide layer 214 located between the first gate 213 and the semiconductor material layer 11 has a second thickness T2, which is less than the first thickness T1. In some embodiments, the first thickness T1 and the second thickness T2 are substantially the same. The first thickness T1 and the second thickness T2 can be adjusted according to the size of the first electrode 210 and the first gate 213 or the operating voltage, respectively.

[0032] In some embodiments, a first portion 211 of the first electrode 210 has a first width W211, and a second portion 212 of the first electrode 210 has a second width W212, wherein the first width W211 is greater than the second width W212. A first gate 213 has a third width W213, which is greater than or equal to the first width W211. In some embodiments, the first width W211 and the third width W213 are substantially the same. In some embodiments, the second width W212 is greater than the third width W213, and the third width W213 is greater than the first width W211. In some embodiments, the sum of the first width W211 and the third width W213 is greater than or equal to the second width W212 of the second portion 212 of the first electrode 210.

[0033] The semiconductor material layer 11 includes a first doped region 131. The first doped region 131 extends in a first direction X. In some embodiments, the first doped region 131 is disposed between a first surface 11A and a second surface 11B, adjacent to a first oxide layer 214 and separated from a first electrode 210. The first doped region 131 is located in the semiconductor material layer 11 adjacent to the first surface 11A and adjacent to a first trench structure 21. In some embodiments, the first doped region 131 is located in an epitaxial layer 112 and in contact with the first oxide layer 214. At least a portion of the first oxide layer 214 is located between the first electrode 210 and the first doped region 131.

[0034] In some embodiments, the first doped region 131 serves as the bulk doped region of the trench semiconductor structure 10. At least a portion of the epitaxial layer 112 is disposed between the first doped region 131 and the substrate 111. In some embodiments, the first doped region 131 has a different conductivity type than the epitaxial layer 112, for example, a conductivity type of type II. In some embodiments, the first doped region 131 is P-type, while the epitaxial layer 112 is N-type. The first doped region 131 contains a P-type dopant, which may be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the P-type dopant contained in the first doped region 131 is boron. The doping concentration of the first doped region 131 is greater than the doping concentration of the epitaxial layer 112. The depth of the first doped region 131 is less than the depth of the bottom surface 213b of the first gate 213. The first doped region 131 is electrically connected to the conductive material layer 18.

[0035] The second trench structure 22 is disposed at an interval from the first trench structure 21. A first doped region 131 is located between the first trench structure 21 and the second trench structure 22. The trench depth of the first trench structure 21 and the trench depth of the second trench structure 22 may be the same or different, and the trench width W21 of the first trench structure 21 and the trench width W22 of the second trench structure 22 may be the same or different. In some embodiments, the trench depth D21 of the first trench structure 21 and the trench depth D22 of the second trench structure 22 are the same. The trench width W21 of the first trench structure 21 and the trench width W22 of the second trench structure 22 are the same.

[0036] The second trench structure 22 is recessed into the semiconductor material layer 11 and extends from the first surface 11A to the second surface 11B. The second trench structure 22 includes a second electrode 220, a second gate 223, and a second oxide layer 224 separating the second electrode 220 from the second gate 223. The second electrode 220 includes a third portion 221 adjacent to the second gate 223 and a fourth portion 222 located below the third portion 221 and the second gate 223 and connected to the third portion 221. In some embodiments, the third portion 221 and the fourth portion 222 of the second electrode 220 are integrally formed. The third portion 221 of the second electrode 220 is located between the second gate 223 and the first doped region 131. In some embodiments, the second gate 223 has a columnar structure.

[0037] In some embodiments, the top surface of the second trench structure 22 is coplanar with the first surface 11A. In some embodiments, the top surfaces of the second electrode 220 and the second gate 223 are coplanar with the first surface 11A. Viewed from a top angle, the second trench structure 22 extends in a first direction X parallel to the first surface 11A, and the third portion 221 of the second electrode 220 and the second gate 223 overlap with the fourth portion 222 of the lower second electrode 220.

[0038] The second oxide layer 224 is used to electrically isolate the epitaxial layer 112 from the second electrode 220 and the second gate 223. In other words, the second electrode 220 and the second gate 223 are separated from the epitaxial layer 112 via the second oxide layer 224 in the trench. The second electrode 220 and the second gate 223 are respectively surrounded by the second oxide layer 224. At least a portion of the second oxide layer 224 is located between the second electrode 220 and the second gate 223. At least a portion of the second oxide layer 224 serves as the gate oxide layer of the SGT MOSFET located in the second region R2. In some embodiments, the second oxide layer 224 located between the third portion 221 and the semiconductor material layer 11 has a fourth thickness T4, and the second oxide layer 224 located between the second gate 223 and the semiconductor material layer 11 has a fifth thickness T5, the fifth thickness T5 being less than the fourth thickness T4. In some embodiments, the fourth thickness T4 and the fifth thickness T5 are substantially the same. The fourth thickness T4 and the fifth thickness T5 can be adjusted according to the size of the second electrode 220 and the second gate 223 or the operating voltage, respectively.

[0039] In some embodiments, the third portion 221 of the second electrode 220 has a fourth width W221, and the fourth portion 222 of the second electrode 220 has a fifth width W222, wherein the fourth width W221 is greater than the fifth width W222. The second gate 223 has a sixth width W223, which is greater than or equal to the fourth width W221. In some embodiments, the fourth width W221 and the fifth width W222 are substantially the same. In some embodiments, the fifth width W222 is greater than the sixth width W223, and the sixth width W223 is greater than the fourth width W221. In some embodiments, the sum of the fourth width W221 and the third width W213 is greater than or equal to the fifth width W222 of the fourth portion 222 of an electrode 210.

[0040] The trench semiconductor structure 10 includes a TMBS. In some embodiments, the TMBS is located in a first region R1, including a first electrode 210, a second electrode 220, and a first doped region 131, and extends from the first region R1 below a first gate 213 and a second gate 223 through the configuration of the first electrode 210 and the second electrode 220, wherein the first gate 213 is located in a third region R3 and the second gate 223 is located in a second region R2. The first electrode 210, the second electrode 220, and the first doped region 131 form a TMBS diode. A first portion 211 of the first electrode 210, a third portion 221 of the second electrode 220, and the first doped region 131 located between the first electrode 210 and the second electrode 220 are located in the first region R1. The first portion 211 of the first electrode 210 and the third portion 221 of the second electrode 220 are disposed between the first gate 213 and the second gate 223. Viewed from a top-down angle, the length L211 of the first portion 211 of the first electrode 210 along the first direction X and the length L221 of the third portion 221 of the second electrode 220 along the first direction X can be the same. In some embodiments, the TMBS is surrounded by a second region R2 and a third region R3 containing the SGT MOSFET. The trench semiconductor structure 10 of this invention integrates the TMBS and the SGT MOSFET in a first trench structure 21, wherein the first electrode 210 can serve as the source or shielding electrode of the TMBS, and the first gate 213 serves as the gate of the SGT MOSFET. A portion of the first trench structure 21 belongs to the first region R1, and another portion belongs to the third region R3.

[0041] The semiconductor material layer 11 between the first trench structure 21 and the second trench structure 22 forms a mesa surface. In some embodiments, the mesa surface separates the first trench structure 21 and the second trench structure 22. The width of the mesa surface can be adjusted by the positions of the first trench structure 21 and the second trench structure 22. In some embodiments, the mesa surface is located in a first region R1.

[0042] The third trench structure 23 is spaced apart from the first trench structure 21. The trench depth D21 of the first trench structure 21 and the trench depth D23 of the third trench structure 23 may be the same or different, and the trench width W21 of the first trench structure 21 and the trench width W23 of the third trench structure 23 may be the same or different. In some embodiments, the trench depth D21 of the first trench structure 21 and the trench depth D23 of the third trench structure 23 are the same, and the trench width W21 of the first trench structure 21 and the trench width W23 of the third trench structure 23 are the same.

[0043] The third trench structure 23 is recessed into the semiconductor material layer 11, extends from the first surface 11 to the second surface 11B, and is disposed adjacent to the first trench structure 21. The third trench structure 23 includes a third electrode 231, a third gate 233 located on the third electrode 231, and a third oxide layer 234 separating the third electrode 231 and the third gate 233 from each other. In some embodiments, the third electrode 231 and the third gate 233 are both columnar structures. In some embodiments, the top surface of the third trench structure 23 is coplanar with the first surface 11A. In some embodiments, the top surface of the third gate 233 is coplanar with the first surface 11A. Viewed from a top angle, the third trench structure 23 extends in a first direction X parallel to the first surface 11A, and the third gate 233 overlaps with the third electrode 231 below it.

[0044] The third oxide layer 234 is used to electrically isolate the third electrode 231 and the third gate 233 from the epitaxial layer 112. In other words, the third electrode 231 and the third gate 233 are separated from the epitaxial layer 112 via the third oxide layer 234 in the trench. The third electrode 231 and the third gate 233 are each surrounded by the third oxide layer 234. At least a portion of the third oxide layer 234 is located between the third electrode 231 and the third gate 233. At least a portion of the third oxide layer 234 serves as the gate oxide layer of the SGT MOSFET located in the third region R3.

[0045] In some embodiments, the third electrode 231 has a sixth width W231, and the third gate 233 has a seventh width W233, wherein the sixth width W231 and the seventh width W233 are substantially the same. In some embodiments, the sixth width W231 is smaller than the seventh width W233.

[0046] The second doped region 132 is located between the first trench structure 21 and the third trench structure 23, extending in the first direction X. In some embodiments, the second doped region 132 is disposed between the first surface 11A and the second surface 11B, adjacent to the first oxide layer 214 and separated from the first gate 213. At least a portion of the first oxide layer 214 is located between the first gate 213 and the second doped region 132. In some embodiments, the second doped region 132 is located in the epitaxial layer 112 and is in contact with the first oxide layer 214 and the third oxide layer 234. The second doped region 132 is located in the semiconductor material layer 11 and adjacent to the first surface 11A, wherein the second doped region 132 has a second conductivity type, and the first trench structure 21 is located between the first doped region 131 and the second doped region 132.

[0047] The second doped region 132 is disposed between the first trench structure 21 and the third trench structure 23, serving as the bulk doped region of the trench semiconductor structure 10. At least a portion of the epitaxial layer 112 is disposed between the second doped region 132 and the substrate 111. In some embodiments, the second doped region 132 has a different conductivity type than the epitaxial layer 112, for example, a conductivity type of type II. In some embodiments, the second doped region 132 is P-type, while the epitaxial layer 112 is N-type. The second doped region 132 contains a P-type dopant, which may be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the P-type dopant contained in the second doped region 132 is boron. The doping concentration of the second doped region 132 is greater than the doping concentration of the epitaxial layer 112. In some embodiments, the doping concentration of the second doped region 132 is different from the doping concentration of the first doped region 131. In some embodiments, the doping concentration of the second doped region 132 is greater than the doping concentration of the first doped region 131, for example, but not limited to, the doping concentration of the second doped region 132 being an order of magnitude greater than the doping concentration of the first doped region 131. The depth of the second doped region 132 is less than the depth of the bottom surface 213b of the first gate 213. The depth of the second doped region 132 may be the same as or different from the depth of the first doped region 131. In some embodiments, the depth of the second doped region 132 is greater than the depth of the first doped region 131. The doping concentration and depth of the second doped region 132 and the doping concentration and depth of the first doped region 131 can be adjusted independently. Adjusting the doping concentration of the first doped region 131 can control the forward current and reverse leakage current of the TMBS of the trench semiconductor structure 10.

[0048] The semiconductor material layer 11 further includes a third doped region 142. The third doped region 142 extends in a first direction X. In some embodiments, the third doped region 142 is located between the first surface 11A and the second doped region 132, adjacent to the first oxide layer 214 and separated from the first gate 213. The third doped region 142 is located in the semiconductor material layer 11 adjacent to the first surface 11A and adjacent to the first trench structure 21. In some embodiments, the third doped region 142 is located in the epitaxial layer 112 and in contact with the first oxide layer 214. At least a portion of the first oxide layer 214 is located between the first gate 213 and the third doped region 142.

[0049] The third doped region 142 is disposed between the first trench structure 21 and the third trench structure 23, serving as the source of the trench semiconductor structure 10. In some embodiments, the third doped region 142 has the same conductivity type as the epitaxial layer 112, for example, a first conductivity type. In some embodiments, the third doped region 142 and the epitaxial layer 112 are N-type. The doping concentration of the third doped region 142 is greater than the doping concentration of the epitaxial layer 112. The depth of the third doped region 142 is less than the depth of the bottom surface 213b of the first gate 213. The depth of the third doped region 142 is less than the depth of the second portion 212 of the first electrode 210.

[0050] An interlayer dielectric layer 16 is located on the first surface 11A of the semiconductor material layer 11, and is used to separate the conductive material layer 18 located on the interlayer dielectric layer 16 from the semiconductor material layer 11, the first trench structure 21, the second trench structure 22, and the third trench structure 23. The interlayer dielectric layer 16 covers the first trench structure 21, the second trench structure 22, the third trench structure 23, the first doped region 131, and the third doped region 142.

[0051] In some embodiments, a fourth oxide layer 24 is located on the first surface 11A of the semiconductor material layer 11 between the interlayer dielectric layer 16 and the first trench structure 21, the second trench structure 22, the third trench structure 23, and the third doped region 142. In some embodiments, the fourth oxide layer 24 and the first oxide layer 214, the second oxide layer 224 and the third oxide layer 234 are made of the same or different materials. The thickness T24 of the fourth oxide layer 24 is less than the second thickness T2 of the first oxide layer 214 located between the first gate 213 and the semiconductor material layer 11.

[0052] The first groove 161 and the second groove 162 penetrate the interlayer dielectric layer 16 and the fourth oxide layer 24. The first groove 161 is located in the first region R1 and is situated on the first doped region 131, the first electrode 210, and the second electrode 220. The second groove 162 is located in the third region R3 and is situated on the third doped region 142, extending into the semiconductor material layer 11. In some embodiments, at least a portion of the first electrode 210 and at least a portion of the second electrode 220 are exposed from the first groove 161. The width of the first groove 161 is greater than the width of the second groove 162. The depth of the first groove 161 is less than the depth of the second groove 162.

[0053] Figure 3 shows a top view of a trench semiconductor structure 10 according to certain embodiments of the present invention. In some embodiments, referring to Figures 1, 2, and 3, the trench semiconductor structure 10 includes a conductive material layer 18 located on an interlayer dielectric layer 16 and a first doped region 131, and at least a portion of the conductive material layer 18 is located in a first trench 161. A first electrode 210, a second electrode 220, and the first doped region 131 are all electrically connected to the conductive material layer 18.

[0054] In some embodiments, the conductive material layer 18 may be the source of the trench semiconductor structure 10. In some embodiments, the conductive material layer 18 may be a patterned metal wire layer for adjusting the electrical path according to actual operational needs, including multiple metal wires electrically connected to different electrodes or doped regions. In some embodiments, the conductive material layer 18 may be the first metal layer (M1) in an interconnect structure. The conductive material layer 18 contains a conductive material, such as a metal, and may include, but is not limited to, molybdenum (Co), copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum-silicon (AlSi) alloy, aluminum-silicon-copper (AlSiCu) alloy, or other metals or alloys. In some embodiments, the conductive material layer 18 includes a shielding metal layer 181 and a metal layer 182 located on the shielding metal layer 181.

[0055] In some embodiments, a shielding metal layer 181 covers the interlayer dielectric layer 16 and is conformally located in the first recess 161 and the second recess 162. The shielding metal layer 181 is located between the interlayer dielectric layer 16 and the metal layer 182. The first electrode 210, the second electrode 220, and the first doped region 131 are all in contact with the shielding metal layer 181 to be electrically connected to the metal layer 182. The shielding metal layer 181 covers the interlayer dielectric layer 16, the first doped region 131, and the inner surfaces (including opposing sidewalls and a bottom extending between the sidewalls) of the first recess 161 and the second recess 162. The shielding metal layer 181 located in the first recess 161 contacts and covers the interlayer dielectric layer 16, the fourth oxide layer 24, the first portion 211 of the first electrode 210, and the third portion 221 of the second electrode. The shielding metal layer 181 located in the second groove 162 contacts the interlayer dielectric layer 16, the fourth oxide layer 24, the second doped region 132, and the third doped region 142. The second electrode 220 contacts the shielding metal layer 181 to be electrically connected to the metal layer 182. The shielding metal layer 181 includes molybdenum, copper, or titanium.

[0056] Metal layer 182 covers shielding metal layer 181. First electrode 210 and first doped region 131 are both in contact with shielding metal layer 181 and electrically connected to metal layer 182. In some embodiments, metal layer 182 includes a recess 183 located on first groove 161. The position and size of recess 183 correspond to the position and size of first groove 161.

[0057] In some embodiments, the shielding metal layer 181 has a notch (not shown) on the first doped region 131, and the metal layer 182 is located in the notch and contacts the first doped region 131 through the notch.

[0058] The first electrode 210, the second electrode 220, and the first doped region 131 are electrically connected to the metal layer 182. In some embodiments, the first conductive plug 171 and the second conductive plug 172 are located in the first groove 161. The first conductive plug 171 is located on the first portion 211 of the first electrode 210 and electrically connects the first electrode 210 to the conductive material layer 18. The second conductive plug 172 is located on the third portion 221 of the second electrode 220 and electrically connects the second electrode 220 to the conductive material layer 18. The first conductive plug 171 and the second conductive plug 172 are located on both sides of the first groove 161 and electrically connected to the first electrode 210 and the second electrode 220, respectively. The characteristics of the trench semiconductor structure 10, such as the magnitude of the reverse leakage current and the magnitude of the turn-on voltage, depend on the concentration of the first doped region 131, the width W161 of the first groove 161, and the area of ​​the first groove 161 viewed from the top angle of FIG3.

[0059] The first conductive plug 171 and the second conductive plug 172 are located on the shielding metal layer 181 and separated by the metal layer 182, with at least a portion of the metal layer 182 located between the first conductive plug 171 and the second conductive plug 172. Both the first conductive plug 171 and the second conductive plug 172 penetrate the interlayer dielectric layer 16 and the fourth oxide layer 24, and are adjacent to the interlayer dielectric layer 16 and the fourth oxide layer 24, respectively. The first conductive plug 171 and the second conductive plug 172 are separated from each other and are both located between the shielding metal layer 181 and the metal layer 182. The first conductive plug 171, the second conductive plug 172, and at least a portion of the metal layer 182 in the first groove 161 are surrounded by the shielding metal layer 181. In some embodiments, the first conductive plug 171 and the second conductive plug 172 include an arc-shaped top surface. In some embodiments, the top surfaces of the first conductive plug 171 and the second conductive plug 172 are not coplanar with the top surface of the shielding metal layer 181. For example, the top surfaces of the first conductive plug 171 and the second conductive plug 172 are lower than the top surface of the shielding metal layer 181.

[0060] The first conductive plug 171 and the second conductive plug 172 are located above the first surface 11A of the semiconductor material layer 11. Viewed from a top angle in FIG3, the first conductive plug 171 and the second conductive plug 172 are located in the first region R1 and extend in the first direction X. The length L171 of the first conductive plug 171 along the first direction X is less than the length L211 of the first electrode 210 along the first direction X. The length L172 of the second conductive plug 172 along the first direction X is less than the length L221 of the second electrode 220 along the first direction X.

[0061] The second doped region 132 is electrically connected to the metal layer 182. In some embodiments, the third conductive plug 173 is located in the second recess 162 and electrically connects the second doped region 132 and the metal layer 182. The third conductive plug 173 penetrates the interlayer dielectric layer 16 and the fourth oxide layer 24 and is surrounded by the shielding metal layer 181. The third conductive plug 173 extends from above the first surface 11A of the semiconductor material layer 11 along the vertical direction Z toward the second surface 11B. The first gate 213, the third electrode 231, the third gate 233, the second doped region 132, the third doped region 142, and the third conductive plug 173 form an SGT MOSFT. In some embodiments, the top surface of the third conductive plug 173 is not coplanar with the top surface of the shielding metal layer 181; for example, the top surface of the third conductive plug 173 is lower than the top surface of the shielding metal layer 181. Viewed from a top angle in FIG3, the third conductive plug 173 is located in the third region R3 and extends in the first direction X. The length L171 of the first conductive plug 171 along the first direction X is less than the length L173 of the third conductive plug 173 along the first direction X.

[0062] The heavily doped region 152 is located within the second doped region 132. The heavily doped region 152 has the same conductivity type as the second doped region 132, for example, P-type. In some embodiments, the doping concentration of the heavily doped region 152 is greater than the doping concentration of the bulk second doped region 132. In some embodiments, the heavily doped region 152 is located within the second doped region 132 and is separated from the first oxide layer 214 and the third oxide layer 234. In some embodiments, the heavily doped region 152 is disposed between adjacent second doped regions 132 and third doped regions 142. The heavily doped region 152 is located below the third conductive plug 173, with a portion of the heavily doped region 152 located between the third conductive plug 173 and the first trench structure 21, and another portion located between the third conductive plug 173 and the third trench structure 23. In other words, the heavily doped region 152 surrounds the bottom of the third conductive plug 173 disposed within the second doped region 132 to reduce ohmic contact resistance.

[0063] Figure 4 shows a top view of a trench semiconductor structure 10 according to certain embodiments of the present invention. In some embodiments, referring to Figure 4, viewed from a top view of Figure 4, the third gate 233 has a mesh structure. The third gate 233 includes a fifth portion 233x extending along a first direction X and a sixth portion 233y extending along a second direction Y different from the first direction X. In some embodiments, the third gate 233 includes a plurality of fifth portions 233x and a plurality of sixth portions 233y. In some embodiments, the first direction X is orthogonal to the second direction Y.

[0064] In some embodiments, a plurality of fourth doped regions 144 are disposed within the mesh structure, each fourth doped region 144 being surrounded by a fifth portion 233x and a sixth portion 233y of a third gate 233 and a third oxide layer 234. Each fourth doped region 144 is electrically connected to a metal layer 182. In some embodiments, the trench semiconductor structure 10 includes a plurality of fourth conductive plugs 174 corresponding to the plurality of fourth doped regions 144, each fourth doped region 144 being electrically connected to the metal layer 182 by a corresponding fourth conductive plug 174.

[0065] In some embodiments, the length L211 of the first portion 211 of the first electrode 210 along the first direction X and the length L221 of the third portion 221 of the second electrode 220 along the first direction X may be different, for example, the length L211 is greater than the length L221.

[0066] Figure 5 shows a cross-sectional view of a trench semiconductor structure 10 according to certain embodiments of the present invention. In some embodiments, a portion of the mesa between the first trench structure 21 and the second trench structure 22 belongs to the first region R1, and the mesa of the second trench structure 22 and the remaining portion belongs to the second region R2. In some embodiments, the second electrode 220 is located below the second gate 223, and the second electrode 220 has only a fourth portion 222. In some embodiments, the TMBS structure is asymmetrical, such as the single-sided structure shown in Figure 5. A portion of the mesa between the first trench structure 21 and the second trench structure 22 belongs to the TMBS, and another portion belongs to the SGT MOSFET. Compared to the trench semiconductor structure 10 shown in Figures 1-3, the TMBS of the trench semiconductor structure 10 shown in Figure 5 only occupies a portion of the mesa between the first trench structure 21 and the second trench structure 22, thereby reducing the leakage current of the TMBS, increasing the driving voltage, and increasing the channel space of the SGT MOSFET, thereby reducing the on-resistance (Ron) of the SGT MOSFET.

[0067] In some embodiments, when the first doped region 131 of the trench semiconductor structure 10 shown in FIG1-3 and the trench semiconductor structure 10 shown in FIG5 has substantially the same doping concentration, the driving voltages of the TMBS of the trench semiconductor structure 10 shown in FIG1-3 and the trench semiconductor structure 10 shown in FIG5 are 0.3V and 0.35V, respectively.

[0068] The fifth doped region 133 and the first doped region 131 are located between the first trench structure 21 and the second trench structure 22, serving as the bulk doped region of the trench semiconductor structure 10. The fifth doped region 133 is located between the first doped region 131 and the second trench structure 22. In some embodiments, the fifth doped region 133 is disposed between the first surface 11A and the second surface 11B, adjacent to the second oxide layer 224 and separated from the second gate 223. At least a portion of the second oxide layer 224 is located between the second gate 223 and the fifth doped region 133. In some embodiments, the fifth doped region 133 is located in the epitaxial layer 112 and is in contact with the second oxide layer 224. The fifth doped region 133 is located in the semiconductor material layer 11 and adjacent to the first surface 11A, wherein the fifth doped region 133 has a second conductivity type, and the first doped region 131 is located between the first trench structure 21 and the fifth doped region 133.

[0069] At least a portion of the epitaxial layer 112 is disposed between the fifth doped region 133 and the substrate 111. In some embodiments, the fifth doped region 133 has a different conductivity type than the epitaxial layer 112, for example, a conductivity type of type II. In some embodiments, the fifth doped region 133 is P-type, while the epitaxial layer 112 is N-type. The fifth doped region 133 contains a P-type dopant, which may be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the P-type dopant contained in the fifth doped region 133 is boron. The doping concentration of the fifth doped region 133 is greater than the doping concentration of the epitaxial layer 112. In some embodiments, the doping concentration of the fifth doped region 133 is different from the doping concentration of the first doped region 131. In some embodiments, the doping concentration of the fifth doped region 133 is greater than the doping concentration of the first doped region 131, for example, but not limited to, the doping concentration of the fifth doped region 133 being an order of magnitude greater than the doping concentration of the first doped region 131. In some embodiments, the doping concentration of the fifth doped region 133 is substantially the same as the doping concentration of the second doped region 132.

[0070] The depth of the fifth doped region 133 is less than the depth of the bottom surface 213b of the first gate 213. The depth of the fifth doped region 133 may be the same as or different from the depth of the first doped region 131. In some embodiments, the depth of the fifth doped region 133 is greater than the depth of the first doped region 131. The depth of the fifth doped region 133 may be the same as or different from the depth of the second doped region 132. In some embodiments, the depth of the fifth doped region 133 is substantially the same as the depth of the second doped region 132.

[0071] The semiconductor material layer 11 further includes a sixth doped region 143. The fifth doped region 133 and the sixth doped region 143 are located in a second region R2 between the first trench structure 21 and the second trench structure 22. The sixth doped region 143 extends in a first direction X. In some embodiments, the sixth doped region 143 is located between the first surface 11A and the fifth doped region 133, adjacent to the second oxide layer 224 and separated from the second gate 223. The sixth doped region 143 is located in the semiconductor material layer 11 adjacent to the first surface 11A and adjacent to the second trench structure 22. In some embodiments, the sixth doped region 143 is located in the epitaxial layer 112 and in contact with the second oxide layer 224. At least a portion of the second oxide layer 224 is located between the second gate 223 and the sixth doped region 143.

[0072] A sixth doped region 143 is disposed between the second trench structure 21 and the fifth doped region 133, serving as the source of the trench semiconductor structure 10. In some embodiments, the sixth doped region 143 has the same conductivity type as the epitaxial layer 112, for example, a first conductivity type. In some embodiments, the sixth doped region 143 and the epitaxial layer 112 are N-type. The doping concentration of the sixth doped region 143 is greater than the doping concentration of the epitaxial layer 112. The depth of the sixth doped region 143 is less than the depth of the bottom surface 213b of the first gate 213. The depth of the sixth doped region 143 is less than the depth of the fifth doped region 133. The shielding metal layer 181 is in contact with the fifth doped region 133 and the sixth doped region 143.

[0073] In some embodiments, the TMBS is located in a first region, and the first electrode 210, the first doped region 131, and the first conductive plug 171 form the TMBS in the first region R1. The second gate 223, the second electrode 220, the fifth doped region 133, the sixth doped region 143, and the second conductive plug 172 form the SGT MOSFT in the second region R2. In some embodiments, by adjusting the relative doping concentrations of the fifth doped region 133 and the sixth doped region 143, so that the sixth doped region 143 has a relatively high doping concentration, the current of the SGT MOSFT will not flow from the sixth doped region 143 to the second conductive plug 172.

[0074] Figure 6 shows a cross-sectional view of a trench semiconductor structure 10 according to certain embodiments of the present invention. In some embodiments, referring to Figure 6, a shielding metal layer 181 and a third conductive plug 173 in a second trench 162 extend through a second doped region 132 and a heavily doped region 152. The heavily doped region 152 surrounds at least a portion of the shielding metal layer 181 and at least a portion of the third conductive plug 173. The bottoms of the shielding metal layer 181 and the third conductive plug 173 are located in an epitaxial layer 112, and the bottoms of the shielding metal layer 181 and the third conductive plug 173 are in contact with the epitaxial layer 112 having a first conductivity type, forming a Schottky contact area. Compared to the trench semiconductor structure 10 shown in Figures 1-3, the increased Schottky contact area in the third region R3 of the trench semiconductor structure 10 shown in Figure 6 results in a lower startup voltage and an increased possibility of reverse leakage.

[0075] Figure 7 shows a cross-sectional view of a trench semiconductor structure 10 according to certain embodiments of the present invention. In some embodiments, referring to Figure 7, a shielding metal layer 181 and a third conductive plug 173 in a second trench 162 extend through a heavily doped region 152, which surrounds at least a portion of the shielding metal layer 181 and at least a portion of the third conductive plug 173. A second doped region 132 surrounds at least a portion of the sidewalls of the shielding metal layer 181 and at least a portion of the sidewalls of the third conductive plug 173. The bottoms of the shielding metal layer 181 and the third conductive plug 173 are located in an epitaxial layer 112, and the bottom of the third conductive plug 173 contacts the epitaxial layer 112 having a first conductivity type, forming a Schottky contact area. Compared to the trench semiconductor structure 10 shown in Figures 1-3, the increased Schottky contact area in the third region R3 of the trench semiconductor structure 10 shown in Figure 7 leads to a lower startup voltage and an increased possibility of leakage.

[0076] In some embodiments, the second doped region 132 includes a first sub-region 132a and a second sub-region 132b that are separated from each other. The first sub-region 132a is in contact with the first trench structure 21 and the shielding metal layer 181, and the second sub-region 132b is in contact with the second trench structure 22 and the shielding metal layer 181. The third conductive plug 173 is located between the separated first sub-region 132a and the second sub-region 132b. The bottom depth of the first sub-region 132a and the bottom depth of the second sub-region 132b are greater than the bottom depth of the third conductive plug 173. In the trench semiconductor structure 10 shown in FIG. 7, the bottom depth of the third conductive plug 173 is less than the bottom depth of the second doped region 132. By including the separated first sub-region 132a and the second sub-region 132b in the second doped region 132, the bottom of the shielding metal layer 181 and the third conductive plug 173 are in contact with the epitaxial layer 112, thereby forming a Schottky contact area. Comparing Figures 6 and 7, the different depths of the bottom surface of the shielding metal layer 181 and the third conductive plug 173 result in different Schottky contact areas in the third region R3. The Schottky contact area affects the startup voltage and reverse leakage current. The bottom surface depth of the third conductive plug 173 can be adjusted according to the required properties of the trench semiconductor structure 10.

[0077] Figure 8 shows a cross-sectional view of a trench semiconductor structure 10 according to certain embodiments of the present invention. In some embodiments, a first trench 161 includes blocks 161a, 161b, and 161c, and a shielding metal layer 181 is conformally located in blocks 161a, 161b, and 161c. A first conductive plug 171 and a second conductive plug 172 are located in blocks 161a and 161b, respectively, and a fifth conductive plug 175 is located in block 161c. The metal layer 182 is located on the first conductive plug 171, the second conductive plug 172, and the fifth conductive plug 175, and the shielding metal layer 181 surrounds the first conductive plug 171, the second conductive plug 172, and the fifth conductive plug 175. The fifth conductive plug 175 is electrically connected to the shielding metal layer 181, the metal layer 182, and the first doped region 131. In some embodiments, the first conductive plug 171, the second conductive plug 172, and the fifth conductive plug 175 penetrate the interlayer dielectric layer 16 and the fourth oxide layer 24, respectively. The fifth conductive plug 175 extends from above the first surface 11A of the semiconductor material layer 11 along the vertical direction Z toward the second surface 11B. When the first groove 161 comprises independent blocks 161a, 161b, and 161c rather than a single integral groove, the metal layer 182 will not have a recess 183.

[0078] Figure 9 shows a cross-sectional view of a trench semiconductor structure 10 according to certain embodiments of the present invention. In some embodiments, openings 182a, 182b, and 182c penetrate the conductive material layer 18. Openings 182a, 182b, and 182c penetrate the shielding metal layer 181 and the metal layer 182, exposing the interlayer dielectric layer 16 through openings 182a, 182b, and 182c. In some embodiments, openings 182a and 182b are disposed on the first groove 161, and opening 182c is disposed on the first trench structure 21. In some embodiments, the metal layer 182 between openings 182a and 182b and the metal layer 182 on the third conductive plug 173 serve as sources, respectively. The metal layer 182 between openings 182a and 182c and the metal layer 182 on the second conductive plug 172 serve as gates, sources, or floating electrodes, respectively. In some embodiments, when the metal layer 182 between the openings 182a and 182c serves as the gate and is electrically connected to the first conductive plug 171, positive charges accumulate on the first electrode 210, and electrons are attracted to the interface between the bottom of the first trench structure 21 and the epitaxial layer 112 (as shown by the dashed line), which reduces the on-resistance of the SGT MOSFET and increases the capacitance from the drain to the gate, making it suitable for application in trench semiconductor structures 10 with low switching speeds.

[0079] Figures 10 to 34 illustrate one or more stages in a method for manufacturing a trench semiconductor structure according to certain embodiments of this invention. At least some of these figures have been simplified to better understand the nature of this disclosure.

[0080] Referring to FIG10, the semiconductor material layer 11 may include a substrate 111 and an epitaxial layer 112 located on the substrate 111. The manufacturing method includes epitaxial growth of the substrate 111 to form the epitaxial layer 112. The epitaxial layer 112 has a first surface 11A of the semiconductor material layer 11, and the substrate 111 has a second surface 11B of the semiconductor material layer 11, with the first surface 11A and the second surface 11B opposite to each other. In some embodiments, ion implantation is performed simultaneously with the epitaxial growth to implant ions with N-type electrical properties to form an N-type epitaxial layer 112.

[0081] A first patterned shielding layer (not shown) is formed on the epitaxial layer 112 to define the positions of the first trench 219, the second trench 229, and the third trench 239 as shown in FIG. 10. The first trench 219, the second trench 229, and the third trench 239 are formed at intervals by an etching process (e.g., plasma dry etching) on ​​the epitaxial layer 112 through the first patterned shielding layer. The etching process needle is removed from the epitaxial layer 112 from the first surface 11A and stops in the epitaxial layer 112. According to the positions defined by the first patterned shielding layer, the first trench 219, the second trench 229, and the third trench 239 are formed at intervals in the semiconductor material layer 11 along the first direction X and from the first surface 11A to the second surface 11B opposite to the first surface 11A. A portion of the first trench 219 and a portion of the second trench 229 are formed in the first region R1 of the semiconductor material layer 11, a portion of the second trench 229 is formed in the second region R2 of the semiconductor material layer 11, and a third trench 239 is formed in the third region R3 of the semiconductor material layer 11. The first region R1 is located between the second region R2 and the third region R3.

[0082] In some embodiments, the first trench 219, the second trench 229, and the third trench 239 may have vertical sidewalls. The first trench 219, the second trench 229, and the third trench 239 may have an arc-shaped bottom surface. Furthermore, the first trench 219, the second trench 229, and the third trench 239 may be circular, elliptical, rectangular, or polygonal. In some embodiments, the first trench 219, the second trench 229, and the third trench 239 have the same width. In some embodiments, the first trench 219, the second trench 229, and the third trench 239 have the same depth.

[0083] Referring to FIG11, the manufacturing method includes forming an in-trench oxide layer 216 in a first trench 219, a second trench 229, and a third trench 239. In some embodiments, the in-trench oxide layer 216 covers a first surface 11A. In some embodiments, the in-trench oxide layer 216 may be formed by thermal oxidation technology or other deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition methods. In some embodiments, the in-trench oxide layer 216 may be conformally or integrally deposited on the inner surfaces (including opposing sidewalls and a bottom extending between the sidewalls) of the first trench 219, the second trench 229, and the third trench 239. In some embodiments, the oxide layer 216 in the first trench can be filled into the first trench 219, the second trench 229, and the third trench 239 via a deposition process, so that the oxide layer 216 in the first trench forms at least one groove in each of the first trench 219, the second trench 229, and the third trench 239. In some embodiments, the portion of the oxide layer 216 in the first trench 219 is a first oxide layer 214, the portion in the second trench 229 is a second oxide layer 224, and the portion in the third trench 239 is a third oxide layer 234. The first oxide layer 214, the second oxide layer 224, and the third oxide layer 234 are formed simultaneously.

[0084] Referring to FIG12, the manufacturing method includes forming a first electrode 210, a second electrode 220, and a third electrode 231 in a first trench 219, a second trench 229, and a third trench 239, respectively. The first electrode 210, the second electrode 220, and the third electrode 231 are formed simultaneously. A first portion 211 and a second portion 212 of the first electrode 210 are formed simultaneously. A third portion 221 and a fourth portion 222 of the second electrode 220 are formed simultaneously.

[0085] In some embodiments, a first electrode 210 is placed in a first trench 219 and on the top surface of a first oxide layer 214; a second electrode 220 is placed in a second trench 229 and on the top surface of a second oxide layer 224; and a third electrode 231 is placed in a third trench 239 and on the top surface of a third oxide layer 234. The top surfaces of the second portion 212 of the first electrode 210, the fourth portion 222 of the second electrode 220, and the third electrode 231 are coplanar. The first portion 211 of the first electrode 210 and the third portion 221 of the second electrode 220 extend onto the first surface 11A and are connected to each other.

[0086] The oxide layer 216 in the first trench may surround the first electrode 210, the second electrode 220, and the third electrode 231. In some embodiments, the first electrode 210, the second electrode 220, and the third electrode 231 may be formed by physical vapor deposition (PVD), such as sputtering or spraying semiconductor material or electrode material. In some embodiments, the first electrode 210, the second electrode 220, and the third electrode 231 may be formed by electroplating or CVD of semiconductor material or electrode material. In some embodiments, the semiconductor material or electrode material may cover the oxide layer 216 in the first trench, followed by an etching process to remove the semiconductor material or electrode material other than the first trench 219, the second trench 229, and the third trench 239 by methods such as dry etching to form the first electrode 210, the second electrode 220, and the third electrode 231. In some embodiments, the semiconductor material or electrode material includes polycrystalline silicon.

[0087] Referring to FIG13, the manufacturing method includes removing a portion of the first trench oxide layer 216 in the first trench 219, the second trench 229, and the third trench 239, thereby exposing a portion of the inner surface of the first trench 219 and the second trench 229, and the inner surface of the third trench 239. In some embodiments, the manufacturing method includes removing the first trench oxide layer 216 in the first trench 219 that is not in contact with the first electrode 210, removing the first trench oxide layer 216 in the second trench 229 that is not in contact with the second electrode 220, and removing a portion of the first trench oxide layer 216 in the third trench 239 that is not in contact with the third electrode 231. In some embodiments, after removing the oxide layer 216 in the middle portion of the first trench 219, the second trench 229, and the third trench 239, the first trench 219 includes a first electrode 210 and a first oxide layer 214 in contact with the first electrode 210; the second trench 229 includes a second electrode 220 and a second oxide layer 224 in contact with the second electrode 220; and the third trench 239 includes a third electrode 231 located at the bottom of the third trench 239 and a third oxide layer 234 surrounding the third electrode 231.

[0088] Referring to FIG14, the manufacturing method includes forming a second trench oxide layer 217 in a first trench 219, a second trench 229, and a third trench 239. In some embodiments, the second trench oxide layer 217 covers a first electrode 210, a second electrode 220, a third electrode 231, and a first surface 11A. In some embodiments, the second trench oxide layer 217 may be formed by thermal oxidation technology or other deposition processes. In some embodiments, the second trench oxide layer 217 may be filled into the first trench 219, the second trench 229, and the third trench 239 via a deposition process, such that the second trench oxide layer 217 is conformally or integrally deposited on the first electrode 210 in the first trench 219, the second electrode 220 in the second trench 229, and the third electrode 231 in the third trench 239, respectively. In some embodiments, the second trench oxide layer 217 is formed via an isotropic deposition process. In some embodiments, the second trench oxide layer 217 is a sacrificial structure that will be removed in a subsequent step, so that the surface exposed after the removal of the second trench oxide layer 217 has better quality, such as being smoother, which is conducive to the formation of other structures on the exposed surface.

[0089] Referring to FIG15, the manufacturing method includes removing the second trench oxide layer 217. The manufacturing method includes removing the second trench oxide layer 217 located in the first region R1, the second region R2, and the third region R3, that is, removing the second trench oxide layer 217 covering the first electrode 210, the second electrode 220, and the first surface 11A, thereby exposing a portion of the inner surfaces (including opposing sidewalls) of the epitaxial layer 112 in the first region R1, the first trench 219, the second trench 229, and the third trench 239, as well as the connected first electrode 210 and second electrode 220 (not shown). The second trench oxide layer 217 is removed by an etching method. The epitaxial layer 112 exposed after removing the second trench oxide layer 217 has a relatively smooth surface flatness. In some embodiments, the stages shown in FIG14 are omitted.

[0090] The manufacturing method includes forming a third trench oxide layer 218 on the epitaxial layer 112 exposed in the third region R3, and on the top surface and sidewalls of the first electrode 210 and the second electrode 220 located in the first region R1 and the second region R2. The third trench oxide layer 218 is formed in the first region R1, the second region R2, and the third region R3, with at least a portion of the third trench oxide layer 218 located in the first trench 219, the second trench 229, and the third trench 239. In some embodiments, the third trench oxide layer 218 covers the first surface 11A. In some embodiments, the third trench oxide layer 218 may be formed by thermal oxidation technology or other deposition processes. In some embodiments, the third trench oxide layer 218 may be deposited conformally or integrally on the inner surfaces (including opposing sidewalls) of the first trench 219, the second trench 229, and the third trench 239, as well as on the top surface and sidewalls of the first electrode 210 and the second electrode 220.

[0091] In some embodiments, the oxide layer 218 in the third trench can be filled into the first trench 219, the second trench 229, and the third trench 239 via a deposition process, so that the oxide layer 218 in the third trench covers and surrounds the first electrode 210 and the second electrode 220, and forms a groove with the first oxide layer 214 in the first trench 219. In some embodiments, the thickness T218 of the oxide layer 218 in the third trench is less than the thickness T216 of the oxide layer 216 in the first trench.

[0092] Referring to FIG16, the manufacturing method includes forming a first semiconductor material 301, a second semiconductor material 302, and a third semiconductor material 303 in a first trench 219, a second trench 229, and a third trench 239, respectively. In some embodiments, the first semiconductor material 301 is placed in the first trench 219 and on the top surface of the first oxide layer 214, the second semiconductor material 302 is placed in the second trench 229 and on the top surface of the second oxide layer 224, and the third semiconductor material 303 is placed in the third trench 239 and on the top surface of the third oxide layer 234.

[0093] The oxide layer 218 in the third trench may surround the first semiconductor material 301, the second semiconductor material 302, and the third semiconductor material 303. In some embodiments, the first semiconductor material 301, the second semiconductor material 302, and the third semiconductor material 303 may be formed by physical vapor deposition (PVD), such as sputtering or spraying semiconductor materials. In some embodiments, the first semiconductor material 301, the second semiconductor material 302, and the third semiconductor material 303 may be formed by electroplating or CVD semiconductor materials. In some embodiments, the first semiconductor material 301, the second semiconductor material 302, and the third semiconductor material 303 comprise polycrystalline silicon. In some embodiments, the first semiconductor material 301, the second semiconductor material 302, and the third semiconductor material 303 cover the oxide layer 218 in the third trench.

[0094] Figure 17 is a top view of a stage in a method of manufacturing a semiconductor structure 10 according to certain embodiments of the present invention. Figure 18 is a cross-sectional view along tangent B-B' in a stage of a method of manufacturing a semiconductor structure according to certain embodiments of the present invention, at the stage shown in Figure 17.

[0095] Referring to Figures 17 and 18, the manufacturing method includes removing a portion of the first semiconductor material 301 above the first surface 11A and a portion of the first electrode 210 of the semiconductor material layer 11, so that the portion of the first semiconductor material 301 located in the first trench 219 forms a first gate 213. Removing a portion of the second semiconductor material 302 above the first surface 11A and a portion of the second electrode 220 of the semiconductor material layer 11, so that the portion of the second semiconductor material 302 located in the second trench 229 forms a second gate 223. Removing a portion of the third semiconductor material 303 above the first surface 11A of the semiconductor material layer 11, so that the portion of the third semiconductor material 303 located in the third trench 239 forms a third gate 233, and exposing the first surface 11A. Parts of the first semiconductor material 301, part of the second semiconductor material 302, part of the third semiconductor material 303, part of the oxide layer 216 in the first trench, part of the oxide layer 218 in the third trench, part of the first electrode 210 and part of the second electrode 220 can be ground flat, for example, by a chemical-mechanical polishing (CMP) process.

[0096] In some embodiments, a first gate 213, a second gate 223, and a third gate 233 are formed simultaneously. A first electrode 210 is formed before the formation of the first gate 213. A second electrode 220 is formed before the formation of the second gate 223. In some embodiments, after the formation of the first gate 213 in the first trench 219, a first trench structure 21 is formed, comprising a first electrode 210 including a first portion 211 and a second portion 212, a first gate 213 adjacent to the first portion 211, and a first oxide layer 214 surrounding and separating the first electrode 210 and the first gate 213. After the formation of the second gate 223 in the second trench 229, a second trench structure 22 is formed, comprising a second electrode 220 including a third portion 221 and a fourth portion 222, a second gate 223 adjacent to the third portion 221, and a second oxide layer 224 surrounding and separating the second electrode 220 and the second gate 223. In some embodiments, after the third gate 233 is formed in the third trench 239, the third gate 233 is located on the third electrode 231, and the third gate 233, the third electrode 231, and the third oxide layer 234 surrounding the third gate 233 and the third electrode 231 and separating the two form a third trench structure 23. In some embodiments, the first trench structure 21, the second trench structure 22, and the third trench structure 23 are formed simultaneously. In some embodiments, the top surface of the first trench structure 21, the top surface of the second trench structure 22, and the top surface of the third trench structure 23 are coplanar with the first surface 11A.

[0097] Figure 19 is a top view of a stage in a method of manufacturing a semiconductor structure 10 according to certain embodiments of the present invention. Figure 20 is a cross-sectional view along tangent C-C' of a stage in a method of manufacturing a semiconductor structure according to certain embodiments of the present invention, at the stage shown in Figure 19.

[0098] Referring to Figures 19 and 20, the manufacturing method includes forming a fourth oxide layer 24 on the top surface of the first trench structure 21, the top surface of the second trench structure 22, the top surface of the third trench structure 23, and the first surface 11A. The fourth oxide layer 24 is in contact with the first surface 11A of the semiconductor material layer 11, the first trench structure 21, the second trench structure 22, and the third trench structure 23. In some embodiments, the fourth oxide layer 24 may be formed by thermal oxidation technology or other deposition processes, such as ALD, CVD, or other deposition methods.

[0099] Referring to FIG20, the manufacturing method includes forming a first doped region 131 in a semiconductor material layer 11 between a first trench structure 21 and a second trench structure 22, the first doped region 131 having a second conductivity type. The first doped region 131 may be formed in an epitaxial layer 112 via diffusion or ion implantation from a first surface 11A, with ions implanted in the first surface 11A between the first trench structure 21 and the second trench structure 22 in a vertical direction Z. The first doped region 131 is formed in a first region R1, and the depth of the first doped region 131 is less than the depths of the first trench structure 21, the second trench structure 22, and the third trench structure 23. In other words, the bottom of the first doped region 131 is higher than the bottoms of the first trench structure 21, the second trench structure 22, and the third trench structure 23. In some embodiments, an annealing process is performed after the ion implantation process forms the first doped region 131 to allow doped ions to diffuse. In some embodiments, the doped ions are, for example, boron ions, aluminum ions, gallium ions, indium ions, etc. In some embodiments, boron ions are implanted into the first doped region 131.

[0100] In some embodiments, a first patterned shielding layer 113 is formed on the fourth oxide layer 24 to define the position of the first doped region 131, and the conductivity and depth of the first doped region 131 are defined by adjusting the introduced ions, energy, and dose of the diffusion or ion implantation process. In some embodiments, the first patterned shielding layer 113 is formed by photolithography using a photomask with a corresponding pattern.

[0101] Figure 21 is a top view of a stage in a method of manufacturing a semiconductor structure 10 according to certain embodiments of the present invention. Figure 22 is a cross-sectional view along tangent D-D' of the stage shown in Figure 21 in a method of manufacturing a semiconductor structure according to certain embodiments of the present invention.

[0102] Referring to Figures 21 and 22, the manufacturing method includes forming a second doped region 132 in a semiconductor material layer 11 between the second trench structure 22 and the third trench structure 23. The second doped region 132 has a second conductivity type. The second doped region 132 may be formed in the epitaxial layer 112 via diffusion or ion implantation from the first surface 11A, with ions implanted into the first surface 11A in the vertical direction Z. The second doped region 132 is formed in a second region R2 or a third region R3, and the depth of the second doped region 132 is less than the depth of the first trench structure 21, the second trench structure 22, and the third trench structure 23. In other words, the bottom of the second doped region 132 is higher than the bottom of the first trench structure 21, the second trench structure 22, and the third trench structure 23. In some embodiments, an annealing process is performed after the second doped region 132 is formed by ion implantation to diffuse the doped ions. In some embodiments, the doped ions are, for example, boron ions, aluminum ions, gallium ions, indium ions, etc. In some embodiments, boron ions are implanted into the second doped region 132. The bottom of the second doped region 132 will be higher than that of the first doped region 131.

[0103] In some embodiments, a second patterned shielding layer 114 is formed on the fourth oxide layer 24 to define the position of the second doped region 132, and the conductivity and depth of the second doped region 132 are defined by adjusting the introduced ions, energy, and dose of the diffusion or ion implantation process. In some embodiments, the second patterned shielding layer 114 is formed after photolithography using a photomask with a corresponding pattern. The first doped region 131 and the second doped region 132 are formed respectively and have the same or different doping concentrations. In some embodiments, the first doped region 131 is formed before the second doped region 132 is formed. In some embodiments, the doping concentration of the second doped region 132 is greater than the doping concentration of the first doped region 131.

[0104] Figure 23 is a top view of a stage in a method of manufacturing a semiconductor structure 10 according to certain embodiments of the present invention. Figure 24 is a cross-sectional view along tangent E-E' of the stage in the method of manufacturing a semiconductor structure according to certain embodiments of the present invention.

[0105] Referring to Figures 23 and 24, the manufacturing method includes forming a third doped region 142 in the portion of the second doped region 132 adjacent to the first surface 11A of the semiconductor material layer 11. The third doped region 142 is a heavily doped region having a first conductivity type. The third doped region 142 is formed between the second doped region 132 and the fourth oxide layer 24.

[0106] The third doped region 142 may be formed in the epitaxial layer 112 via diffusion or ion implantation from the first surface 11A, with ions implanted into the first surface 11A in the vertical direction Z. The third doped region 142 is formed in the second region R2 or the third region R3, and the depth of the third doped region 142 is less than the depth of the second doped region 132. In other words, the bottom of the third doped region 142 is higher than the bottom of the second doped region 132. In some embodiments, an annealing process is performed after the third doped region 142 is formed by ion implantation to allow the doped ions to diffuse. In some embodiments, the first doped region 131 is formed before the third doped region 132 is formed.

[0107] Referring to FIG25, the manufacturing method includes forming an interlayer dielectric layer 16 on a first surface 11A of a semiconductor material layer 11, wherein the interlayer dielectric layer 16 covers a first trench structure 21, a second trench structure 22, a third trench structure 23, a first doped region 131, and a third doped region 142. The manufacturing method also includes forming the interlayer dielectric layer 16 on a fourth oxide layer 24. The interlayer dielectric layer 16 may be formed by thermal oxidation technology or other deposition processes.

[0108] Referring to Figures 26 and 27, the manufacturing method includes partially removing the interlayer dielectric layer 16 and the fourth oxide layer 24, and partially removing the epitaxial layer 112 to form a second opening 162. The second opening 162 can be formed via one or more etching processes. The second opening 162 is located between the first trench structure 21 and the third trench structure 23, penetrates the third doped region 142, and terminates in the second doped region 132.

[0109] In some embodiments, referring to FIG26, a third patterned shielding layer 115 is formed on the interlayer dielectric layer 16 to define the position of the second opening 162. By adjusting the position of the third patterned shielding layer 115, the interlayer dielectric layer 16 and the fourth oxide layer 24 of the third region R3 are partially removed. In some embodiments, the third patterned shielding layer 115 is formed by photolithography using a photomask with a corresponding pattern. Referring to FIG27, after the interlayer dielectric layer 16 and the fourth oxide layer 24 are partially removed, the third patterned shielding layer 115 is removed. Then, using the interlayer dielectric layer 16 and the fourth oxide layer 24 as a mask, the epitaxial layer 112 is further partially removed to form the second opening 162.

[0110] Referring to FIG28, the manufacturing method includes performing an ion implantation process on the epitaxial layer 112 via a second opening 162 to form a heavily doped region 152 in the third region R3. Ions are implanted into the epitaxial layer 112 at the bottom of the second opening 162 in a vertical direction Z. The heavily doped region 152 is formed in the epitaxial layer 112 adjacent to the bottom of the second opening 162. In some embodiments, an annealing process is performed after the ion implantation process to form the heavily doped region 152 as shown in FIG28.

[0111] Referring to FIG29, the manufacturing method includes partially removing the interlayer dielectric layer 16 and the fourth oxide layer 24 of the first region R1 to form a first opening 161. The first opening 161 may be formed via one or more etching processes. The first opening 161 is located on the electrode structure in the first region R1 between the first trench structure 21 and the second trench structure 22 and stops at the first surface 11A, exposing the first portion 211 of the first electrode 210 and the third portion 221 of the second electrode 220, respectively. The width of the first opening 161 is greater than the width of the second opening 162.

[0112] In some embodiments, a fourth patterned shielding layer 116 is formed on the interlayer dielectric layer 16 to define the position of the first opening 161, and the interlayer dielectric layer 16 and the fourth oxide layer 24 of the first region R1 are partially removed by adjusting the position of the fourth patterned shielding layer 116. In some embodiments, the fourth patterned shielding layer 116 is formed by photolithography using a photomask with a corresponding pattern.

[0113] Referring to FIG30, the manufacturing method includes forming a shielding metal layer 181 on the interlayer dielectric layer 16 and in the first groove 161 and the second groove 162.

[0114] In some embodiments, the shielding metal layer 181 covers the interlayer dielectric layer 16. In some embodiments, the oxide layer 216 in the first trench may be formed by thermal oxidation or other deposition processes, such as ALD, CVD, or other deposition methods. In some embodiments, the shielding metal layer 181 may be deposited conformally or integrally on the inner surfaces (including opposing sidewalls and a bottom extending between the sidewalls) of the first trench 161 and the second trench 162. In some embodiments, the shielding metal layer 181 may be filled into the first trench 161 and the second trench 162 via a deposition process, such that the shielding metal layer 181 forms at least one trench in each of the first trench 161 and the second trench 162.

[0115] Figure 31 is a top view of a stage in a method of manufacturing a semiconductor structure 10 according to certain embodiments of the present invention. Figure 32 is a cross-sectional view along tangent F-F' in the stage shown in Figure 31 of a method of manufacturing a semiconductor structure according to certain embodiments of the present invention.

[0116] Referring to Figures 31 and 32, the manufacturing method includes forming a first conductive plug 171, a second conductive plug 172 in a first opening 161, and a third conductive plug 173 in a second opening 162. The first conductive plug 171 and the second conductive plug 172 are formed on both sides of the first opening 161 and are separated from each other. The first conductive plug 171 is disposed on the first electrode 210 and the first oxide layer 214, and the second conductive plug 172 is disposed on the second electrode 220 and the second oxide layer 224.

[0117] The first conductive plug 171, the second conductive plug 172, and the third conductive plug 173 are formed by electroplating or CVD, respectively filling the first opening 161 and the second opening 162 with conductive material. The first conductive plug 171, the second conductive plug 172, and the third conductive plug 173 are formed on the shielding metal layer 181, and can be formed simultaneously or separately. The material may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys. In some embodiments, a planarization process may be selectively performed after electroplating or CVD. In some embodiments, the top surfaces of the first conductive plug 171, the second conductive plug 172, and the third conductive plug 173 are flush or at approximately the same horizontal height. In some embodiments, the top surfaces of the first conductive plug 171, the second conductive plug 172, and the third conductive plug 173 are slightly lower than the height of the shielding metal layer 181.

[0118] Viewed from a top angle in Figure 31, the configurations of the first conductive plug 171 and the second conductive plug 172 are defined by the first opening 161. The first conductive plug 171 overlaps with the first electrode 210 in the first region R1, and the second conductive plug 172 overlaps with the second electrode 220 in the first region R1. The configuration of the third conductive plug 173 is defined by the configuration of the second opening 162, and therefore will have the same configuration as the second opening 162. The third conductive plug 173 is surrounded by the third doped region 142 and the heavily doped region 152 in the third region R3.

[0119] Figure 33 is a top view of a stage in a method of manufacturing a semiconductor structure 10 according to certain embodiments of the present invention. Figure 34 is a cross-sectional view along tangent G-G' in the stage shown in Figure 33 of a method of manufacturing a semiconductor structure according to certain embodiments of the present invention.

[0120] Referring to Figures 33 and 34, the manufacturing method includes forming a metal layer 182 on the interlayer dielectric layer 16 to form a trench semiconductor structure 10. A shielding metal layer 181 and the metal layer 182 constitute a conductive material layer. The metal layer 182 can be formed by electroplating or CVD, and can be patterned according to electrical properties and operational requirements. The material of the metal layer 182 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. In some embodiments, the metal layer 182 is defined as multiple metal lines using an etching process. In some embodiments, the metal layer 182 is in contact with and electrically connected to the shielding metal layer 181, the first conductive plug 171, the second conductive plug 172, and the third conductive plug 173. The first conductive plug 171, the second conductive plug 172, and the third conductive plug 173 extend from the metal layer 182 in the vertical direction Z. The first conductive plug 171 is formed between the first trench structure 21 and the metal layer 182, the second conductive plug 172 is formed between the second trench structure 22 and the metal layer 18, and the third conductive plug 173 is formed between the second doped region 132 and the metal layer 18.

[0121] The trench semiconductor structure 10 formed by the above steps is substantially the same as the semiconductor structure 10 shown in Figures 1 to 3. The trench semiconductor structure 10 has a first trench structure 21 including a first electrode 210 and a first gate 213, and a second trench structure 22 including a second electrode 220 and a second gate 223. The first electrode 210 includes a first portion 211 adjacent to the first gate 213, and a second portion 212 located below the first portion 211 and the first gate 213 and connected to the first portion 211. A first doped region 131 is disposed between the first electrode 210 and the second electrode 220, and the first electrode 210, the second electrode 220, the first doped region 131, and the upper conductive material layer 18 form a TMBS. The trench semiconductor structure 10 integrates at least a portion of the TMBS and at least a portion of the SGT MOSFET in the same trench, improving chip area utilization and achieving effective space utilization.

[0122] Based on the structure and process described above, under the same purpose and concept, the steps in the above process can be adjusted or their order replaced to achieve the same or similar semiconductor structure.

[0123] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one component or feature as shown in the accompanying drawings and one or more other components or features. In addition to the orientation depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, it may be directly connected to or coupled to the other component, or there may be an intermediate component present.

[0124] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of a given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may refer to two surfaces positioned along the same plane with a positional difference within a few micrometers (μm), such as a positional difference within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values. The foregoing summarizes the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A trench semiconductor structure, characterized in that, include: A semiconductor material layer having a first surface and a second surface opposite to the first surface, wherein the semiconductor material layer has a first conductivity type; A first trench structure extends from the first surface to the second surface, wherein the first trench structure includes a first electrode, a first gate, and a first oxide layer separating the first electrode from the first gate, the first electrode including a first portion adjacent to the first gate, and a second portion located below the first portion and the first gate and in contact with the first portion; A first doped region is located in the semiconductor material layer adjacent to the first surface and adjacent to the first portion of the first electrode, wherein the first doped region has a second conductivity type; An interlayer dielectric layer is located on the first surface of the semiconductor material layer and covers the first trench structure; A shielding metal layer covers the interlayer dielectric layer and the first doped region, and contacts the first electrode; as well as A metal layer is located on the interlayer dielectric layer and the first doped region. The first portion of the first electrode is located between the first doped region and the first gate, and both the first electrode and the first doped region are in contact with the shielding metal layer to be electrically connected to the metal layer.

2. The trench semiconductor structure according to claim 1, wherein the first electrode and the first doped region form a trench MOS barrier Schottky (TMBS) diode.

3. The trench semiconductor structure according to claim 1, wherein the first portion of the first electrode is integrally formed with the second portion.

4. The trench semiconductor structure according to claim 1, wherein the width of the first portion of the first electrode is greater than the width of the second portion of the first electrode.

5. The trench semiconductor structure according to claim 1, further comprising: A groove is located on the first doped region and the shielding metal layer and penetrates the interlayer dielectric layer, with at least a portion of the metal layer and at least a portion of the shielding metal layer located in the groove; as well as A first conductive plug is located in the groove and electrically connects the first electrode to the metal layer.

6. The trench semiconductor structure according to claim 1, further comprising: A second trench structure extends from the first surface to the second surface and is disposed adjacent to the first trench structure. The second trench structure includes a second electrode, a second gate, and a connection between the second electrode and the... The second electrode is separated from the second gate and has a second oxide layer. The second electrode includes a third portion adjacent to the second gate and a fourth portion located below the third portion and the second gate and connected to the third portion. as well as The third portion of the second electrode is located between the second gate and the first doped region, and the second electrode is in contact with the shielding metal layer to be electrically connected to the metal layer.

7. The trench semiconductor structure according to claim 6, wherein the trench depth of the first trench structure is the same as the trench depth of the second trench structure.

8. The trench semiconductor structure according to claim 6, wherein the trench width of the first trench structure is the same as or different from the trench width of the second trench structure.

9. The trench semiconductor structure according to claim 6, wherein the first electrode, the second electrode and the first doped region form a trench MOS barrier Schottky (TMBS) diode.

10. The trench semiconductor structure according to claim 6, further comprising: The groove is located on the first doped region and the shielding metal layer and penetrates the interlayer dielectric layer; as well as The second conductive plug is located in the groove and electrically connects the second electrode to the metal layer. At least a portion of the metal layer and at least a portion of the shielding metal layer are located in the groove and are electrically connected to the second conductive plug.

11. The trench semiconductor structure of claim 1, wherein the width of the first gate is greater than the width of the first portion of the first electrode.

12. The trench semiconductor structure according to claim 1, further comprising: A third trench structure extends from the first surface to the second surface and is disposed adjacent to the first trench structure, wherein the third trench structure includes a third electrode, a third gate located on the third electrode, and a third oxide layer separating the third electrode and the third gate from each other. A second doped region is located in the semiconductor material layer adjacent to the first surface and between the first trench structure and the third trench structure, wherein the second doped region has the second conductivity type; A third doped region is located between the first surface and the second doped region, wherein the third doped region has the first conductivity type; as well as The third conductive plug electrically connects the second doped region to the metal layer. The interlayer dielectric layer further covers the third trench structure and the third doped region.

13. The trench semiconductor structure according to claim 12, wherein the doping concentration of the second doped region is greater than the doping concentration of the first doped region.

14. The trench semiconductor structure according to claim 12, wherein the first gate, the third electrode, the third gate, the second doped region, the third doped region and the third conductive plug form a shielded gate trench metal-oxide-semiconductor field-effect transistor (SGT MOSFT).

15. The trench semiconductor structure of claim 12, wherein at least a portion of the third conductive plug is surrounded by the third doped region and electrically connected to the metal layer.

16. The trench semiconductor structure of claim 15, wherein the third conductive plug extends through the third doped region.

17. The trench semiconductor structure of claim 1, wherein the first oxide layer located between the first portion of the first electrode and the semiconductor material layer has a first thickness, and the first oxide layer located between the first gate and the semiconductor material layer has a second thickness, the second thickness being less than the first thickness.

18. The trench semiconductor structure according to claim 1, further comprising: The fourth oxide layer is located on the first surface of the semiconductor material layer and between the interlayer dielectric layer and the first trench structure.

19. A trench semiconductor structure, characterized in that, include: A semiconductor material layer having a first conductivity type and having a first region and a second region surrounding the first region; The first trench structure is recessed into the semiconductor material layer and includes a first electrode, a first gate, and a first oxide layer surrounding the first electrode and the first gate. The first electrode includes a first portion adjacent to the first gate and a second portion that, when viewed from above, overlaps with and is connected to the first portion and the first gate. The second trench structure is recessed into the semiconductor material layer and includes a second electrode, a second gate, and a second oxide layer surrounding the second electrode and the second gate. as well as A first doped region is disposed within the semiconductor material layer and located between the first trench structure and the second trench structure, wherein the first doped region has a second conductivity type. The first electrode and the second electrode are disposed between the first gate and the second gate. A portion of the first electrode, a portion of the second electrode, and the first doped region located between the first electrode and the second electrode are situated in the first region. The first gate and the second gate are located in the second region.

20. The trench semiconductor structure of claim 19, wherein the first region comprises a trench MOS barrier Schottky (TMBS) diode and the second region comprises a shielded gate trench metal-oxide-semiconductor field-effect transistor (SGT MOSFT).

21. The trench semiconductor structure according to claim 19, further comprising: The third trench structure is recessed into the semiconductor material layer and includes a third electrode, a third gate, and a third oxide layer surrounding the third electrode and the third gate and separating the third electrode and the third gate from each other. The first electrode, the second electrode, and the first gate extend along a first direction, and the third gate has a mesh structure, including a fifth portion extending along the first direction and a sixth portion extending along a second direction different from the first direction.

22. The trench semiconductor structure of claim 19, wherein, viewed from above, the length of the first portion of the first electrode is the same as or different from the length of the third portion of the second electrode.

23. A method for manufacturing a trench semiconductor structure, characterized in that, include: A first trench is formed in a semiconductor material layer, the first trench extending from a first surface to a second surface; A first electrode is formed in the first trench, the first electrode including a first portion and a second portion located below and in contact with the first portion; A first gate is formed in the first trench, the first gate is adjacent to the first portion of the first electrode and located above the second portion of the first electrode, and the first electrode and the first gate form a first trench structure. A first doped region is formed in the semiconductor material layer adjacent to the first surface, wherein the first doped region has a second conductivity type, and the first portion of the first electrode is located between the first doped region and the first gate. An interlayer dielectric layer is formed on the first surface of the semiconductor material layer, and the interlayer dielectric layer covers the first trench structure and the first doped region; A groove is formed that penetrates the interlayer dielectric layer, exposing the first doped region and the first portion of the first electrode; A shielding metal layer is formed in the groove and on the interlayer dielectric layer, the shielding metal layer covering the interlayer dielectric layer and the first doped region, and contacting the first portion of the first electrode; as well as A metal layer is formed in the groove, on the interlayer dielectric layer, and on the shielding metal layer. The first portion of the first electrode and the first doped region are both in contact with the shielding metal layer to be electrically connected to the metal layer.

24. The manufacturing method according to claim 23, wherein the first portion and the second portion of the first electrode are formed simultaneously.

25. The manufacturing method according to claim 23, further comprising: A first conductive plug is formed between the first trench structure and the metal layer, wherein the first conductive plug is formed between the first trench structure and the metal layer. The plug is located in the groove and surrounded by the metal layer and the shielding metal layer, and is located on the first portion of the first electrode; as well as A second conductive plug is formed in the groove and is separate from the first conductive plug and the first groove structure. At least a portion of the metal layer is located between the first conductive plug and the second conductive plug.

26. The manufacturing method according to claim 25, wherein the first conductive plug and the second conductive plug are formed simultaneously.

27. The manufacturing method according to claim 23, further comprising: A second trench is formed in a semiconductor material layer, the second trench extending from the first surface to the second surface and being disposed adjacent to the first trench; A second electrode is formed in the second trench, the second electrode including a third portion and a fourth portion located below and in contact with the third portion; as well as A second gate is formed in the second trench, the second gate is adjacent to the third portion of the second electrode and located above the fourth portion of the second electrode, the third portion, the fourth portion, and the second gate form a second trench structure. The first doped region is located between the first trench structure and the second trench structure, the interlayer dielectric layer covers the second trench structure, and the groove also exposes the third portion.

28. The manufacturing method according to claim 27, wherein the first electrode and the second electrode are formed simultaneously.

29. The manufacturing method of claim 23, wherein forming the first trench structure in the first trench and forming the second trench structure in the second trench further comprises: A first oxide layer is formed in the first trench, wherein the first electrode and the first gate are surrounded by the first oxide layer; as well as A second oxide layer is formed in the second trench, wherein the second electrode and the second gate are surrounded by the second oxide layer.

30. The manufacturing method according to claim 23, further comprising: A third trench is formed in the semiconductor material, the third trench extending from the first surface to the second surface and such that the first trench is located between the third trench and the second trench; as well as A third electrode is formed, a third gate is located on the third electrode, and a third oxide layer surrounds and separates the third electrode and the third gate from each other; The third electrode, the third gate, and the third oxide layer form a third trench structure, and the first trench structure is located between the second trench structure and the third trench structure.

31. The manufacturing method according to claim 30, further comprising: A second doped region is formed in the semiconductor material layer, wherein the second doped region has a second conductivity type and is located between the third gate and the first gate; A third doped region is formed in the second doped region adjacent to the first surface of the semiconductor material layer, the third doped region being heavily doped with a first conductivity type; as well as A third conductive plug is formed between the second doped region and the metal layer, wherein the third conductive plug extends from the metal layer, passes through the third doped region, and contacts the second doped region.

32. The manufacturing method according to claim 31, wherein the formation of the first doped region is prior to the formation of the third doped region.

33. The manufacturing method according to claim 23, wherein the first electrode is formed before the first gate is formed.

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