Semiconductor device

Abstract

Provided is a miniaturized semiconductor device. A semiconductor device according to the present invention includes a first capacitive element and a first transistor on the first capacitive element. The first capacitive element includes a first conductive layer, a second conductive layer, and a first insulating layer. The first transistor includes a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a second insulating layer, and a third insulating layer. In a cross-sectional view, the height of the first conductive layer is greater than the width of the first conductive layer. The first insulating layer abuts a side surface of the first conductive layer. The second conductive layer is disposed so as to face the side surface of the first conductive layer via the first insulating layer. The first insulating layer contains a material that exhibits ferroelectricity. The second insulating layer is disposed on the third conductive layer. The fourth conductive layer is disposed on the second insulating layer. The second insulating layer and the fourth conductive layer are provided with an opening at a position overlapping the third conductive layer. The semiconductor layer, in the opening, abuts a top surface of the third conductive layer and a side surface of the fourth conductive layer. The third insulating layer, in the opening, is located on the semiconductor layer. The fifth conductive layer, in the opening, is located on the third insulating layer. The third conductive layer is connected to the first conductive layer.

Description

Semiconductor Devices

[0001] FIELD OF THE INVENTION One embodiment of the present invention relates to a semiconductor device and a capacitor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] Research and development of memories using ferroelectrics is actively underway (Non-Patent Document 1). In addition, for the next generation of ferroelectric memories, ferroelectric HfO ２ Research on Hf-based materials (Non-Patent Document 2), ０．５ Zr ０．５ O ２ Research on ferroelectricity of thin films (Non-Patent Document 3), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 4), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) and CMOS using hafnium oxide (Non-Patent Document 5).

[0004] A ferroelectric capacitor is an example of a memory or circuit element that uses a ferroelectric material. A ferroelectric capacitor is a type of capacitance element in which a ferroelectric insulating material is sandwiched between a pair of electrodes, and is capable of retaining data by utilizing the hysteresis characteristics of the remanent polarization of the ferroelectric insulating material. This allows data to be retained even without the application of voltage, and therefore the realization of a non-volatile memory (FeRAM) using a ferroelectric capacitor is expected.

[0005] In particular, Patent Documents 1 and 2 disclose a circuit configuration that retains data in a ferroelectric capacitor even when the power supply voltage to a flip-flop circuit is cut off. This circuit configuration makes it possible to back up the data retained in the flip-flop circuit to the ferroelectric capacitor, and to stop the flip-flop circuit.

[0006] Republished Patent Publication No. 03-044953 Japanese Patent Application Laid-Open No. 2013-124290

[0007] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al. , “Ferroelectric HfO2-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016Jun Okuno, et al. , "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2", VLSI 2020. Akira Toriumi, "Ferroelectricity of HfO2 thin film", The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. T. Francois, et al. , "Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications," IEDM 2019. Takashi Koida, "High-mobility transparent conductive film," National Institute of Advanced Industrial Science and Technology (AIST) Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] An object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Another object is to provide a highly integrated semiconductor device. Another object is to provide a semiconductor device with high operation speed. Another object is to provide a semiconductor device with reduced power consumption. Another object is to provide a highly reliable semiconductor device.

[0009] An object of one embodiment of the present invention is to provide a capacitor, a semiconductor device, or a memory device having a novel structure.An object of one embodiment of the present invention is to provide a manufacturing method of a capacitor, a semiconductor device, or a memory device having a novel structure.An object of one embodiment of the present invention is to provide an electronic device having a novel structure.An object of one embodiment of the present invention is to at least alleviate at least one of the problems of the prior art.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention includes a first capacitor and a first transistor over the first capacitor. The first capacitor includes a first conductive layer, a second conductive layer, and a first insulating layer. The first transistor includes a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, the second insulating layer, and a third insulating layer. In a cross-sectional view, the height of the first conductive layer is greater than the width of the first conductive layer. The first insulating layer is in contact with a side surface of the first conductive layer, and the second conductive layer faces the side surface of the first conductive layer with the first insulating layer interposed therebetween. the first insulating layer includes a material exhibiting ferroelectricity; the second insulating layer is disposed on the third conductive layer; the fourth conductive layer is disposed on the second insulating layer; openings are provided in the second insulating layer and the fourth conductive layer at positions where the second insulating layer and the fourth conductive layer overlap with the third conductive layer; the semiconductor layer contacts an upper surface of the third conductive layer and a side surface of the fourth conductive layer within the openings; the third insulating layer is located on the semiconductor layer within the openings; the fifth conductive layer is located on the third insulating layer within the openings; and the third conductive layer is connected to the first conductive layer.

[0012] In the above, it is preferable that the semiconductor device has a plurality of first capacitance elements and a plurality of first transistors arranged in a matrix, the second conductive layer, the fifth conductive layer, and the opening are provided extending in a first direction, and the distance between the first conductive layers provided adjacent to each other in the first direction is shorter than the distance between the first conductive layers provided adjacent to each other in the second direction.

[0013] In the above, it is preferable that one or both of the first conductive layer and the second conductive layer have a thermal expansion coefficient greater than that of the first insulating layer.

[0014] In the above, it is preferable that the first insulating layer has a region exhibiting a ferroelectric phase of 20% or more.

[0015] In the above, the first insulating layer preferably contains hafnium zirconium oxide.

[0016] In the above, it is preferable that one or both of the first conductive layer and the second conductive layer contain titanium nitride.

[0017] In the above, it is preferable that the lower surface of the third conductive layer contacts the upper surface of the first conductive layer.

[0018] In the above, it is preferable that the third conductive layer has a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer having titanium nitride, the second layer having tungsten, and the third layer having indium tin oxide.

[0019] In the above, it is preferable that the first insulating layer and the second conductive layer do not overlap an upper surface of the first conductive layer.

[0020] In the above, it is preferable that the upper end of the first insulating layer and the upper end of the second conductive layer are higher than the upper end of the first conductive layer.

[0021] In the above, the semiconductor layer preferably contains indium oxide.

[0022] In the above, it is preferable that the semiconductor device has a second transistor and a second capacitance element on the second transistor, the channel of the second transistor is formed in a silicon substrate, the second capacitance element is arranged below the first capacitance element, the second capacitance element has a sixth conductive layer, a seventh conductive layer, and a fourth insulating layer, the height of the sixth conductive layer is greater than the width of the sixth conductive layer in a cross-sectional view, the fourth insulating layer is in contact with a side surface of the sixth conductive layer, and the seventh conductive layer is arranged opposite to the side surface of the sixth conductive layer via the fourth insulating layer, and the fourth insulating layer contains a material exhibiting ferroelectricity.

[0023] According to one embodiment of the present invention, a miniaturized semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a highly integrated semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high operation speed can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided.

[0024] According to one embodiment of the present invention, a capacitor, a semiconductor device, or a memory device having a novel structure can be provided. Alternatively, according to one embodiment of the present invention, a manufacturing method of a capacitor, a semiconductor device, or a memory device having a novel structure can be provided. Alternatively, according to one embodiment of the present invention, an electronic device having a novel structure can be provided. Alternatively, according to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] FIGS. 1A and 1B are diagrams illustrating a structural example of a semiconductor device. FIG. 2 is a diagram illustrating a structural example of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating a structural example of a semiconductor device. FIGS. 4A and 4B are diagrams illustrating a structural example of a semiconductor device. FIGS. 5A and 5B are diagrams illustrating a structural example of a semiconductor device. FIGS. 6A and 6B are diagrams illustrating a structural example of a semiconductor device. FIG. 7 is a diagram illustrating a structural example of a semiconductor device. FIGS. 8A and 8B are diagrams illustrating a structural example of a semiconductor device. FIG. 9 is a diagram illustrating a structural example of a semiconductor device. FIG. 10 is a diagram illustrating a structural example of a semiconductor device. FIG. 11 is a diagram illustrating a structural example of a semiconductor device. FIGS. 12A and 12B are diagrams illustrating a structural example of a semiconductor device. FIGS. 13A and 13B are diagrams illustrating a structural example of a semiconductor device. FIG. 14 is a diagram illustrating a structural example of a semiconductor device. FIGS. 15A and 15B are diagrams illustrating a structural example of a semiconductor device. FIGS. 16A1 to 16C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17A1 to 17C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18A1 to 18C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 19A1 to 19C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20A1 to 20C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 21A1 to 21C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 22A1 to 22C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 23A1 to 23C2 are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 24A and 24B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 24C is a cross-sectional view illustrating an indium oxide film. FIG. 25 is a block diagram illustrating an example of a configuration of a semiconductor device. FIG. 26 is a diagram illustrating an example of a circuit configuration of a memory cell array and a memory cell. FIG. 27A is a graph illustrating an example of hysteresis characteristics, and FIG. 27B is a timing chart illustrating an example of a method for driving a memory cell. FIG. 28 is a conceptual diagram illustrating layers of a memory device. FIG. 29A is a block diagram showing a configuration example of a semiconductor device, and FIG. 29B is a schematic perspective view showing the configuration example of the semiconductor device.FIGS. 30A to 30E are diagrams showing an example of a storage device. FIGS. 31A to 31D are diagrams showing an example of an electronic component. FIGS. 32A and 32B are diagrams showing an example of electronic equipment, and FIGS. 32C to 32E are diagrams showing an example of a mainframe computer. FIG. 33A is a diagram showing an example of space equipment. FIG. 33B is a diagram showing an example of a storage system applicable to a data center. FIG. 34 is a schematic diagram of a pillar-type capacitor according to an example. FIG. 35A is a planar TEM image according to an example, and FIG. 35B is a crystalline phase map according to an example. FIG. 36A is a planar TEM image according to an example, and FIG. 36B is a crystalline phase map according to an example.

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0030] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0031] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0033] Furthermore, in this specification, "electrical connection" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows for the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions. In this specification, "connection" includes "electrical connection."

[0034] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0035] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0036] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0037] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a supporting surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "lower" and the laminate side as "upper."

[0038] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0039] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchangeable depending on the situation. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Also, depending on the situation or circumstances, the terms "film" and "layer" may not be used and may be interchangeable with other terms. For example, the terms "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Also, for example, the terms "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Note that, in this specification and the like, the terms "film" and "layer" do not only refer to planar structures but also to three-dimensional structures. For example, the term "conductive layer" may refer to a columnar conductor.

[0040] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0041] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0042] Embodiment 1 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. The semiconductor device exemplified below can be applied to a memory device.

[0043] A semiconductor device according to one embodiment of the present invention includes a plurality of memory cells, each of which includes one transistor and one memory element. The memory element can be any of various elements capable of storing stored data, such as a capacitor, a variable resistance element, a ferroelectric element, a charge trap element, and a floating gate element.

[0044] In a transistor included in a memory cell, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in a height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0045] The capacitor of the memory cell can be provided below the transistor. By stacking the transistor and the capacitor, memory cells can be arranged at high density. The capacitor can be a so-called MIM (Metal-Insulator-Metal) capacitor having a dielectric between a pair of electrodes. In this case, it is preferable that the lower electrode of the transistor is in contact with the inner electrode of the capacitor. It is also preferable that the outer electrode of the capacitor be extended to function as a plate line. Furthermore, by using a ferroelectric material for the dielectric of the capacitor, a ferroelectric capacitor can be formed. This makes it possible to realize a nonvolatile memory device.

[0046] The semiconductor layer of a transistor is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor characteristics. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in a vertical transistor according to one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can form a low-resistance region without doping with such impurities and can provide good connection with the source and drain electrodes. Therefore, a transistor having a three-dimensional structure according to one embodiment of the present invention can be manufactured with high yield.

[0047] A structure of a semiconductor device and a manufacturing method of the semiconductor device will be described below with reference to FIGS.

[0048] [Configuration Example] FIGS. 1A and 2 show perspective views of a semiconductor device 50. FIGS. 3A and 3B show plan views of the semiconductor device 50. FIG. 3A shows the structure of a transistor 10 provided in the upper part of the semiconductor device 50. FIG. 3B shows the structure of a capacitive element 30 provided in the lower part of the semiconductor device 50. FIG. 3B also shows the structure of the transistor 10 with a dashed line. FIG. 4A shows a cross-sectional view of the semiconductor device 50 corresponding to the dashed-dotted line A1-A2 in FIGS. 3A and 3B. FIG. 1A also shows the structure of the semiconductor device 50 cut along the dashed-dotted line A1-A2. FIG. 4B shows a cross-sectional view of the semiconductor device 50 corresponding to the dashed-dotted line B1-B2 in FIGS. 3A and 3B. FIG. 2 also shows the structure of the semiconductor device 50 cut along the dashed-dotted line B1-B2. FIG. 5A shows a cross-sectional view of the semiconductor device 50 corresponding to the dashed-dotted line C1-C2 in FIGS. 3A and 3B. Fig. 5B shows a cross-sectional view of the semiconductor device 50 corresponding to the dashed dotted line D1-D2 in Fig. 3A and Fig. 3B. Fig. 6A and Fig. 6B show an example of an enlarged view of the capacitive element 30 shown in Fig. 4A. Fig. 1B shows a circuit diagram corresponding to the semiconductor device 50. Note that some components (such as insulating layers) are omitted in Fig. 1A, Fig. 2, Fig. 3A, and Fig. 3B. Each figure also shows arrows indicating the X, Y, and Z directions.

[0049] The semiconductor device 50 has a configuration in which a plurality of memory cells 15 are arranged in a matrix in the X and Y directions. While the semiconductor device 50 is shown in FIGS. 1 to 5 as having two rows and two columns, the number of rows and columns can be set as appropriate. As shown in FIGS. 1 and 2 , the memory cell 15 includes a capacitance element 30 and a transistor 10 on the capacitance element 30. Furthermore, as shown in FIG. 1B , the semiconductor device 50 is provided with a plurality of wirings BL extending in the X direction, a plurality of wirings WL extending in the Y direction, and a plurality of wirings PL extending in the Y direction.

[0050] The memory cell 15 includes one transistor 10 and one capacitor 30. The transistor 10 has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor 30. The other electrode of the capacitor 30 is connected to a wiring PL.

[0051] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of the transistor 10 functioning as a switch. The wiring PL functions as a plate line for supplying a predetermined potential to the other electrode of the capacitor 30 in accordance with the timing of writing and reading data.

[0052] 1B shows an example in which the wiring PL is parallel to the wiring WL, but the present invention is not limited to this configuration. The wiring PL can also be parallel to the wiring WL, or can be arranged in a grid pattern. Alternatively, the wiring PL can be a flat conductive film.

[0053] 1 and 2, the transistor 10 and the capacitor 30 are provided on an insulating layer 11 provided on a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0054] The transistor 10 includes a semiconductor layer 21, an insulating layer 22 that functions as a gate insulating layer, a conductive layer 23 that functions as a gate electrode and a word line (wiring WL), a conductive layer 24 that functions as one of a source electrode and a drain electrode, and a conductive layer 25 that functions as the other. Here, an example is shown in which the conductive layer 24 includes a conductive film 24a and a conductive film 24b located thereon, and the conductive layer 25 includes a conductive film 25a and a conductive film 25b located thereon. As shown in FIG. 4A and other figures, when the conductive layer 24 has a stacked structure of the conductive film 24a and the conductive film 24b, the upper conductive film 24b can also function as a connection electrode for connecting the conductive film 24a and the semiconductor layer 21.

[0055] In the transistor 10, an insulating layer 41 is disposed on a conductive layer 24, and a conductive layer 25 is disposed on the insulating layer 41. An opening 20 is provided at a position where the insulating layer 41 and the conductive layer 25 overlap the conductive layer 24. Within the opening 20, the semiconductor layer 21 contacts the top surface of the conductive layer 24 and the side surface of the conductive layer 25. Within the opening 20, the insulating layer 22 is disposed on the semiconductor layer 21, and the conductive layer 23 is disposed on the insulating layer 22. Furthermore, a plug 27 is disposed on the conductive layer 25, and a conductive layer 26 functioning as a bit line (wiring BL) is disposed on the plug 27. Here, the conductive layer 23 functioning as the wiring WL and the opening 20 in which the conductive layer 23 is provided are provided to extend in the Y direction. In other words, the conductive layer 23 is provided in common in the transistors 10 arranged in the Y direction. Furthermore, the conductive layer 26 functioning as the wiring BL is provided to extend in the X direction. That is, the conductive layer 26 is provided in common to the transistors 10 arranged in the X direction.

[0056] As shown in FIG. 3A , it is preferable that the line and space in the Y direction of the semiconductor layer 21 be defined as a minimum feature size F (F stands for "Feature Size"), the width of the opening 20 be defined as a dimension F', and the width of the insulating layer 41 sandwiched between the openings 20 be defined as a minimum feature size F. Here, F is a value determined by exposure equipment, processing equipment, etc., and is a dimension that can be reduced with advances in processing technology. On the other hand, F' is a value determined by the structure. Here, F' is determined by the thicknesses in the X direction of the semiconductor layer 21, insulating layer 22, and conductive layer 23 provided inside the opening 20. In the configuration shown in FIG. 3A , the area S per transistor 10 is 2F × (F + F'). The smaller the area S, the higher the integration density of memory cells can be.

[0057] The capacitor 30 includes a conductive layer 51 that functions as one electrode, a conductive layer 53 that functions as the other electrode, and an insulating layer 52 that is disposed therebetween and functions as a dielectric. The conductive layer 53 also functions as a plate line (wiring PL).

[0058] The insulating layer 52 preferably contains a material exhibiting ferroelectricity, which allows the capacitive element 30 to function as a ferroelectric capacitor and the memory cell 15 to function as an FeRAM.

[0059] Unlike paraelectric materials, ferroelectric materials maintain their internal dielectric polarization even when no voltage is applied (sometimes called remanent polarization). Because the dielectric polarization is maintained, using a ferroelectric capacitor for the capacitive element 30 suppresses data degradation in the memory cells 15, enabling data retention for extended periods of time. This reduces the number of refresh operations for the memory cells 15, thereby reducing the power consumption of the semiconductor device. Furthermore, using a ferroelectric material for the insulating layer 52 may improve the reliability of the memory cells 15.

[0060] In the capacitance element 30, a conductive layer 51 is disposed on an insulating layer 11, and an insulating layer 52 is disposed in contact with a side surface of the conductive layer 51. The conductive layer 53 is disposed opposite the side surface of the conductive layer 51 with the insulating layer 52 interposed therebetween. Here, the conductive layer 51 is preferably in contact with the upper surface of the insulating layer 11. The insulating layer 52 is preferably formed in contact with the upper surface of the insulating layer 11 and the side surface of the conductive layer 51. The conductive layer 53 is preferably formed in the shape of a sidewall on the side surface of a columnar body formed of the conductive layer 51 and the insulating layer 52. The conductive layer 53, which functions as the wiring PL, is provided extending in the Y direction. In other words, the conductive layer 53 is provided in common among the capacitance elements 30 arranged in the Y direction.

[0061] Furthermore, the conductive layer 51 preferably has a circular shape in plan view. Furthermore, in one capacitor element 30, the conductive layer 51, the insulating layer 52, and the conductive layer 53 are preferably arranged in a generally concentric pattern in this order in plan view. In this case, the insulating layer 52 and the conductive layer 53 are preferably provided so as not to overlap the upper surface of the conductive layer 51. With such a structure, the conductive layer 53 is not provided above the conductive layer 51, allowing the conductive layer 51 and the conductive layer 24 to be connected. While an example in which the conductive layer 51 has a circular shape in plan view is shown, the shape of the conductive layer 51 is not limited to a circle and may be an ellipse, a rectangle with rounded corners, or the like. Furthermore, the shape of the conductive layer 51 in plan view may be a regular polygon such as an equilateral triangle, a square, or a regular pentagon, or a polygon other than a regular polygon. Furthermore, a concave polygon, such as a star-shaped polygon, with at least one interior angle exceeding 180°, can increase the channel width. In addition, the shape may be a polygon with rounded corners, a closed curve that combines straight lines and curves, etc. In addition, the shapes of the insulating layer 52 and the conductive layer 53 in a plan view reflect the shape of the conductive layer 51 described above.

[0062] 4A, it is preferable that the upper end of the insulating layer 52 and the upper end of the conductive layer 53 are higher than the upper end of the conductive layer 51. This makes it possible to prevent a short circuit from occurring between the conductive layer 51 and the conductive layer 53, which function as electrodes of the capacitance element 30.

[0063] 6A , the conductive layer 51 has a columnar (or pillar-shaped) shape with a high aspect ratio. Here, the aspect ratio of the conductive layer 51 in a cross-sectional view refers to the ratio of the width W of the conductive layer 51 to the height H of the conductive layer 51. The aspect ratio of the conductive layer 51 is preferably as large as possible without causing the conductive layer 51 to collapse during the manufacturing process of the capacitance element 30. In the conductive layer 51, the height H of the conductive layer 51 is preferably larger than the width W of the conductive layer 51. In this way, the capacitance element 30 is formed around the pillar-shaped conductive layer 51, and therefore can also be called a pillar-type capacitance.

[0064] The region where the side surface of the conductive layer 51 and the side surface of the conductive layer 53 face each other functions as a capacitance element. Therefore, by increasing the aspect ratio of the conductive layer 51, the capacitance value of the capacitance element 30 can be increased. With this configuration, even if the memory cell 15 is miniaturized and the area occupied by the capacitance element 30 is reduced, a sufficiently large remanent polarization can be generated in the insulating layer 52. Therefore, by forming the capacitance element 30 as a pillar-type capacitance, miniaturization and high integration of the semiconductor device can be achieved.

[0065] The conductive layer 51 may have a tapered shape or an inverse tapered shape. In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. Alternatively, it refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the film surface underlying the structure. The angle formed between the inclined side surface and the substrate surface or the film surface is referred to as a taper angle. In this specification, a tapered shape having a taper angle greater than 0 degrees and less than 90 degrees is referred to as a forward tapered shape, and a tapered shape having a taper angle greater than 90 degrees and less than 180 degrees is referred to as a reverse tapered shape.

[0066] As shown in FIG. 3B , the distance between adjacent conductive layers 51 in the X direction is L', and the distance between adjacent conductive layers 51 in the Y direction is L. It is preferable that the distance L is smaller than the distance L'. This configuration allows the sidewall-shaped conductive layer 53 to be formed in a shape that extends in the Y direction and is separated in the X direction. In a plan view, the conductive layer 53 has a circular shape with its Y-direction ends connected to each other. The plurality of capacitive elements 30 can also be considered as circular conductive layers 53 strung together. The conductive layer 53 can also be described as a string of beads.

[0067] Furthermore, it is preferable that the distance L approximately coincides with the width W of the conductive layer 51. In this case, it is preferable that the distance L' is set to dimension F', and the distance L and width W are set to the minimum feature size F. In this case, as shown in FIG. 3B , the conductive layers 53 can be arranged so that the shortest distance between adjacent conductive layers 53 is smaller than the minimum feature size F. This configuration allows the conductive layers 51 to be arranged overlapping the semiconductor layers 21 arranged in a matrix. In other words, the capacitor element 30 can be arranged under the miniaturized transistor 10 without increasing the area occupied by the transistor 10. As an example, when the minimum feature size F = 30 nm and dimension F' = 40 nm, the thickness of the insulating layer 52 can be set to 6 nm and the thickness of the conductive layer 53 can be set to 13 nm. As another example, when the minimum feature size F = 14.4 nm and dimension F' = 30 nm, the thickness of the insulating layer 52 can be set to 6 nm and the thickness of the conductive layer 53 can be set to 8 nm.

[0068] For example, when considering a Hall-type capacitor in which two electrodes and a dielectric film are provided inside a vertical hole, if the diameter of the vertical hole is set to the minimum processing dimension F based on the film thickness of the two electrodes and the film thickness of the dielectric film, there is a risk of inter-electrode leakage or the like occurring in the Hall-type capacitor. In other words, the diameter of the vertical hole needs to be larger than the minimum processing dimension F. In addition, the distance between adjacent vertical holes needs to be equal to or larger than the minimum processing dimension F.

[0069] In contrast to this, in the pillar-type capacitor shown in this embodiment, the line-and-space of the conductive layers 51 adjacent in the Y direction is formed with the minimum processing dimension F, and the distance between the conductive layers 53 adjacent in the X direction can be made smaller than the minimum processing dimension F. Therefore, by arranging the pillar-type capacitors in a matrix, miniaturization and high integration of the semiconductor device can be achieved.

[0070] Here, a material that functions as a ferroelectric and that can be used for the insulating layer 52 of the capacitance element 30 will be described.

[0071] Ferroelectric materials include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use materials in which a Group 3 (IIIa) element is added to these oxides. For example, it is preferable to include one or more of scandium, yttrium, and lanthanoid elements. Yttrium, lanthanum, or scandium are particularly preferable because they are relatively easy to handle and have high compatibility with semiconductor manufacturing processes. Adding such elements not only stabilizes ferroelectricity but also suppresses degradation of characteristics during repeated rewriting, improving reliability. It also improves the breakdown voltage of the insulating layer 52. For example, these elements are preferably added at a ratio of 0.5 at% to 10 at%. Other additive elements include silicon, aluminum, gadolinium, and scandium. The insulating layer 52 can be made of not only ferroelectric materials but also antiferroelectric materials.

[0072] Oxides containing either or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films prepared using thin film deposition methods such as sputtering and atomic layer deposition. This makes them highly compatible with semiconductor manufacturing processes and allows for reduced manufacturing costs.

[0073] Furthermore, the insulating layer 52 may be made of piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or bismuth ferrite (BFO).

[0074] Alternatively, the insulating layer 52 may be made of an organic ferroelectric material such as polyvinylidene fluoride (PVDF) or a copolymer of vinylidene fluoride (VDF) and trifluoroethylene (TrFE).

[0075] The ferroelectric material may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the insulating layer 52 may have a layered structure made of multiple materials selected from the materials listed above.

[0076] Among these, hafnium oxide, a material containing hafnium oxide and zirconium oxide (HZO), and a material containing yttrium in addition to HZO (HZYO) are preferred as materials exhibiting ferroelectricity because they exhibit ferroelectricity even in thin films of only a few nanometers. By using a film containing hafnium oxide, HZO, or HZYO, the film thickness of insulating layer 52 can be set to 1 nm or more and 100 nm or less, preferably 2 nm or more and 50 nm or less, more preferably 3 nm or more and 20 nm or less, and even more preferably 4 nm or more and 10 nm or less.

[0077] Furthermore, hafnium zirconium oxide (HfZrO Ｘ When X (where X is a real number greater than 0) is used, it is preferable to form the film by the ALD method, particularly the thermal ALD method. It is also preferable to use the ALD method (including the thermal ALD method) in which reactivity is enhanced by using plasma (PEALD method: Plasma Enhanced ALD).

[0078] Furthermore, when using the thermal ALD method, a material containing an organometallic compound can be used as a precursor. For example, when using hafnium zirconium oxide, an organometallic compound such as tetrakis(ethylmethylamido)hafnium (TEMAHf) can be used as a precursor containing hafnium, and tetrakis(ethylmethylamido)zirconium (TEMAZr) can be used as a precursor containing zirconium. Alternatively, a material that does not contain hydrocarbons (also called hydrocarbons) can be used. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Note that when hafnium zirconium oxide is used, the precursor can be HfCl. ４ , ZrCl ４ Chlorine-based precursors such as the following can be used.

[0079] When an oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used for the insulating layer 52, the remanent polarization may be increased by adding an appropriate amount of carbon. In this case, it is preferable to add these elements in a ratio of 0.5 at % to 10 at %, for example.

[0080] When hafnium zirconium oxide is used for the insulating layer 52, it is preferable to alternately deposit films of hafnium and zirconium in a 1:1 ratio using a thermal ALD method or an ALD method using plasma.

[0081] The oxidizing agent used in the thermal ALD method or the plasma-based ALD method is H ２ O or O ３ However, the oxidizing agent is not limited to this, and O ２ , O ３ , N ２ O, NO ２ , H ２ O, H ２ O ２ In particular, in order to reduce the hydrogen concentration and nitrogen concentration in the film, O as an oxidizing agent can be used. ２ or O ３ It is preferable to use O ３ It is more preferable to use

[0082] The film used for the insulating layer 52 preferably has a low hydrogen concentration in the film. This prevents hydrogen from diffusing from the insulating layer 52 to the semiconductor layer 21, which can prevent the carrier concentration in the semiconductor layer 21 from increasing. Specifically, the hydrogen concentration in the film is 5×10 ２０ atoms / cm ３ Preferably, 1×10 ２０ atoms / cm ３ The following is more preferred:

[0083] The crystalline structure of the film used for the insulating layer 52 is not particularly limited as long as it is a crystal structure that does not have centrosymmetrical structure and has polarity. For example, a crystal system other than a cubic system may be used. The film used for the insulating layer 52 may have a single crystal structure, a polycrystalline structure, or a composite structure having an amorphous structure and a crystalline structure.

[0084] For example, when hafnium zirconium oxide is used for the insulating layer 52, the space group Pca2 １ For example, in the insulating layer 52, the ratio of the region exhibiting the ferroelectric phase is preferably 10% or more, more preferably 20% or more, and even more preferably 50% or more.

[0085] Here, consider an example in which a conductive layer 51, an insulating layer 52, and a conductive layer 53 are stacked as shown in Figure 7, and a conductive material with a larger thermal expansion coefficient than the insulating layer 52 is used for the conductive layer 51 and the conductive layer 53.

[0086] With the conductive layer 51, insulating layer 52, and conductive layer 53 stacked, thermal film formation or heat treatment is performed, and the substrate is then removed from the film formation or treatment apparatus and slowly cooled. At this time, the conductive layers 51 and 53 have a larger thermal expansion coefficient than the insulating layer 52, so the conductive layers 51 and 53 are significantly deformed. As shown in Figure 7, the insulating layer 52 also deforms, and tensile stress acts within the insulating layer 52. The action of the tensile stress forms a ferroelectric phase within the insulating layer 52.

[0087] On the other hand, when the conductive layer 51, the insulating layer 52, and the conductive layer 53 are arranged in a cylindrical shape as shown in FIG. 1 , it is preferable to use a material with a large thermal expansion coefficient for one or both of the inner conductive layer 51 and the outer conductive layer 53. With this structure, when the temperature rises, one or both of the conductive layers 51 and 53 expand, causing tensile stress to act on the insulating layer 52. The application of tensile stress to the insulating layer 52 changes the crystalline structure of the insulating layer 52, forming a ferroelectric phase in the insulating layer 52. Once the ferroelectric phase is formed in the insulating layer 52, it is believed that the conductive layer 51 or the conductive layer 53 shrinks upon cooling, and the ferroelectric phase in the insulating layer 52 is maintained even when it returns to its original state. In other words, the ferroelectric phase can be controlled by controlling the tensile stress applied to the insulating layer 52.

[0088] Table 1 shows the thermal expansion coefficients of ferroelectric materials and conductive materials. ４ The thermal expansion coefficient of is a value at the film thickness of μm level, and at the film thickness of 10 nm level, it is 5 to 6 [×10 −６ It is estimated that the temperature will be about K.

[0089]

[0090] When hafnium zirconium oxide is used for the insulating layer 52, it is preferable to use a conductive material (for example, titanium nitride) having a larger thermal expansion coefficient than the insulating layer 52 for one or both of the conductive layers 51 and 53. This causes tensile stress to act in the insulating layer 52 due to the difference in thermal expansion coefficient between the conductive layers 51 and 53 and the insulating layer 52. Therefore, the insulating layer 52 contains a material of the space group Pca2, which exhibits a ferroelectric phase. １ In this way, remanent polarization is generated in the capacitance element 30, and data can be retained in the memory cell 15 for a long period of time.

[0091] Furthermore, in the pillar-type capacitor shown in this embodiment, the thickness of the conductive layer 53 can be increased while achieving miniaturization, compared to a hole-type capacitor in which two electrodes and a dielectric are provided in a vertical hole. This allows a larger tensile stress to act on the insulating layer 52. Therefore, in the insulating layer 52, the space group Pca2, which exhibits ferroelectricity, is １ The region of the orthorhombic crystal structure can be made larger.

[0092] Furthermore, a conductive material that does not easily diffuse oxygen can be used for one or both of the conductive layers 51 and 53 that are in contact with or located near the insulating layer 52. This improves the withstand voltage of the insulating layer 52 and improves the rewrite endurance of the ferroelectric capacitor. In particular, it is preferable to use a metal nitride such as titanium nitride or tantalum nitride.

[0093] One or both of the conductive layers 51 and 53 may be made of a conductive material having a function of absorbing oxygen. This allows oxygen to be absorbed from the insulating layer 52, thereby increasing the oxygen vacancy concentration in the insulating layer 52. This increases the remanent polarization of the insulating layer 52. It is preferable to use a metal or an alloy as the conductive material having a function of absorbing oxygen. In particular, it is preferable to use tungsten, molybdenum, titanium, tantalum, or the like. In particular, tungsten is preferable because it easily increases the remanent polarization of the insulating layer 52 from the viewpoint of stress.

[0094] 6A , the conductive layer 51 may have a stacked structure of a conductive layer 51a and a conductive layer 51b on the conductive layer 51a. Similarly, the conductive layer 53 may have a stacked structure of a conductive layer 53a and a conductive layer 53b on the conductive layer 53a. In this case, the conductive layers 51a and 53a may be made of the same conductive materials as those used for the conductive layers 51 and 53. The conductive layers 51b and 53b are preferably made of a conductive material having lower resistance than the conductive layers 51a and 53a. In particular, a metal material is preferably included. For example, a metal or alloy containing one or more elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like can be used. In particular, the use of a high-melting-point material such as tungsten, molybdenum, tantalum, ruthenium, or hafnium is preferable because it allows for a higher temperature for subsequent heat treatment. This structure reduces the wiring resistance of the conductive layer 53b and the conductive layer 51b, thereby improving the operating speed of the semiconductor device. In particular, since the conductive layer 53b is provided extending in the Y direction as the wiring PL, it is preferable to provide a low-resistance conductive layer 53b.

[0095] 6B, the conductive layer 51 may have a single-layer structure, and the conductive layer 53 may have a stacked structure of conductive layers 53a and 53b. Alternatively, the conductive layer 51 may have a stacked structure of conductive layers 51a and 51b, and the conductive layer 53 may have a single-layer structure.

[0096] The insulating layer 11 also functions as a protective insulating layer. The insulating layer 11 has a function of preventing impurities such as hydrogen from diffusing into the capacitor element 30 and the transistor 10 from below the insulating layer 11. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0097] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0098] An insulating layer 46 is provided on the insulating layer 52 and in contact with the side surface of the conductive layer 53. The insulating layer 46 functions as an interlayer insulating layer. The insulating layer 46 can also be considered to have a bead-shaped opening extending in the Y direction. It can also be considered that the conductive layer 53, insulating layer 52, and conductive layer 51 functioning as bead-shaped wiring are formed inside the bead-shaped opening of the insulating layer 46.

[0099] The insulating layer 46 can be used as an interlayer insulating film. Therefore, the insulating layer 46 can be made of an insulating material having a lower dielectric constant than other films, such as silicon oxide or silicon oxynitride. The insulating layer 46 is preferably formed by a film formation method such as sputtering or plasma CVD. In particular, the sputtering method does not require the use of hydrogen in the film formation gas, making it possible to form a film with an extremely low hydrogen content. This can prevent hydrogen from being supplied to the upper semiconductor layer 21, thereby stabilizing the electrical characteristics of the transistor 10.

[0100] Furthermore, since the insulating layer 46 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 46 may be formed by depositing TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC)) by a plasma CVD method. ２ H ５ ) ４ ) may be used as an insulating film, which can improve productivity.

[0101] 6A, the insulating layer 46 may have a laminated structure of an insulating layer 46a and an insulating layer 46b on the insulating layer 46a. The insulating layer 46b is preferably made of a material having a lower dielectric constant than the other films. The insulating layer 46a is preferably made of a film having the same barrier properties against hydrogen as the insulating layer 11. This configuration can prevent impurities such as hydrogen from diffusing from the insulating layer 46b into the capacitor element 30 and the transistor 10.

[0102] Preferably, an insulating layer 61 is disposed on the insulating layer 46, the conductive layer 53, the insulating layer 52, and the conductive layer 51. The insulating layer 46 may also be formed in the recessed portion above the conductive layer 51 and may contact the inner side surface of the insulating layer 52. As shown in FIG. 4A and other figures, the insulating layer 61 is preferably formed using a film having a barrier property against hydrogen similar to that of the insulating layer 11. This configuration can prevent impurities such as hydrogen contained in the capacitor 30 from diffusing into the transistor 10 and the semiconductor layer 21. Furthermore, since oxygen is less likely to diffuse into a film having a barrier property against hydrogen, oxygen in the semiconductor layer 21 and its vicinity can be prevented from being absorbed by the metal material of the capacitor 30.

[0103] It is preferable that an insulating layer 62 is disposed on the insulating layer 61. The insulating layer 62 can be made of an insulating material that can be used for the insulating layer 46. The insulating layer 41 is disposed on the insulating layer 61.

[0104] 4A and other figures, the conductive layer 24 is formed to fill the openings in the insulating layers 61 and 62. This connects the conductive layer 24 to the conductive layer 51. That is, one of the source and drain of the transistor 10 is connected to one of the electrodes of the capacitor 30. The lower surface of the conductive layer 24 is preferably formed in contact with the upper surface of the conductive layer 51.

[0105] The conductive film 24a is preferably made of a conductive material having lower resistance than the conductive film 24b. It is particularly preferable that the conductive film 24a contains a metal material. For example, a metal or alloy containing one or more selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. can be used. High-melting-point materials such as tungsten, molybdenum, tantalum, ruthenium, and hafnium are particularly preferable because they allow for higher temperatures in subsequent heat treatments.

[0106] 6A, the conductive film 24a may have a stacked structure of a conductive film 24a1 and a conductive film 24a2 on the conductive film 24a1. The conductive film 24a1 is preferably made of a conductive material that does not easily diffuse oxygen. For example, a metal nitride such as titanium nitride or tantalum nitride is preferably used. The conductive film 24a2 is preferably made of the low-resistance conductive material described above. In addition to the low-resistance conductive materials described above, oxide materials such as indium tin oxide, indium tin oxide with added silicon, indium zinc oxide, and indium gallium zinc oxide can also be used.

[0107] The conductive film 24b is preferably made of a conductive metal oxide (oxide conductor). Using a conductive metal oxide for the conductive film 24b in contact with the metal oxide-containing semiconductor layer 21 reduces the contact resistance between them and the wiring load, which is preferable. In particular, it is preferable for the conductive film 24b to contain the same metal element as the metal element contained in the semiconductor layer 21, since this further reduces the contact resistance. Specifically, it is preferable that both the semiconductor layer 21 and the conductive film 24b contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. In particular, it is preferable that the semiconductor layer 21 and the conductive film 24b contain In. Furthermore, using a metal material with lower resistance than the conductive film 24b for the conductive film 24a reduces both the contact resistance and the wiring resistance, thereby further reducing the wiring load.

[0108] An insulating layer 41 is provided above the conductive layer 24 and the insulating layer 52 .

[0109] It is preferable to use an oxide insulating film for the insulating layer 41 in contact with the semiconductor layer 21. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. With such a structure, oxygen vacancies in the semiconductor layer 21 can be reduced.

[0110] Similarly to the insulating layer 46, the insulating layer 41 is preferably made of a material having a lower dielectric constant than the other films. For example, silicon oxide or silicon oxynitride can be used. The insulating layer 46 is preferably formed by a film formation method such as sputtering or plasma CVD. In particular, the sputtering method does not require the use of hydrogen in the film formation gas, making it possible to form a film with an extremely low hydrogen content. This prevents hydrogen from being supplied to the upper semiconductor layer 21, thereby stabilizing the electrical characteristics of the transistor 10.

[0111] Furthermore, since the insulating layer 46 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a higher film formation rate than other insulating layers. For example, an insulating film formed using TEOS by a plasma CVD method may be used as the insulating layer 46. This can improve productivity.

[0112] Furthermore, it is preferable to sandwich the insulating layer 41 between insulating layers having a barrier property against oxygen. This allows the oxygen contained in the insulating layer 41 to be confined in a region surrounded by the insulating layers having a barrier property against oxygen. Furthermore, it is possible to prevent the oxygen in the insulating layer 41 from being desorbed and reduced during the process. This allows oxygen to be supplied to the semiconductor layer 21 more efficiently. In this case, the portion of the semiconductor layer 21 in contact with the insulating layer 41 is a region with reduced oxygen vacancies and can be said to be an i-type region. On the other hand, it is preferable that the portion in contact with the insulating layer having a barrier property against oxygen be an n-type region containing many carriers. That is, the portion of the semiconductor layer 21 in contact with the insulating layer 41 can be called a channel formation region, and the region outside it can be called a low-resistance region (also called a source region or a drain region).

[0113] As the insulating layer having a barrier property against oxygen, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. In particular, silicon nitride and silicon nitride oxide are preferably used because they have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate.

[0114] The insulating layer 41 has a strip-shaped opening 20 (which can also be called a slit-shaped, trench-shaped, or groove-shaped opening) extending in the Y direction. The side surfaces of the insulating layer 41 within the opening 20 are preferably approximately perpendicular to the substrate surface. The height of the insulating layer 41 is preferably greater than its width in the X direction. Also, as shown in FIG. 4A , a portion of the opening 20 can be considered to be formed in the conductive layer 25.

[0115] The conductive layer 25 is provided on the insulating layer 41. As shown in FIG. 5B , the conductive layer 25 is preferably provided so as to be embedded in the insulating layer 42 on the insulating layer 41. Here, an example is shown in which the conductive layer 25 has a laminated structure of a conductive film 25a and a conductive film 25b thereon. A part of the opening 20 is formed in the conductive layer 25, and the conductive layer 25 is divided by the opening 20. That is, a pair of conductive layers 25 is provided on the insulating layer 41 so as to sandwich one opening 20 therebetween. As shown in FIG. 5B , island-shaped conductive layers 25 are arranged at equal intervals along the extension direction (Y direction) of the opening 20.

[0116] The semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have portions located within the opening 20. The semiconductor layer 21 and the insulating layer 22 are provided along the side surfaces of the conductive layer 25, the side surfaces of the insulating layer 41, and the top surface of the conductive layer 24 within the opening 20. The conductive layer 23 is provided so as to fill the recessed portion of the insulating layer 22.

[0117] The semiconductor layer 21 has a portion in contact with the upper surface and side surfaces of the conductive layer 25, a portion in contact with the side surfaces of the insulating layer 41 in the opening 20, and a portion in contact with the upper surface of the conductive film 24b. It is preferable to use a conductive metal oxide similar to the conductive film 24b described above for one of the conductive films 25a and 25b of the conductive layer 25. It is also preferable to use a low-resistance metal material for the other. By stacking a conductive film with low contact resistance with the semiconductor layer 21 and a conductive film with low wiring resistance, it is possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the wiring load.

[0118] Because the semiconductor layer 21 and the insulating layer 22 are formed along the inner walls of the opening 20 of the insulating layer 41 and the conductive layer 25, the thickness of these portions may be thin depending on the film formation method. For example, in film formation methods such as sputtering or plasma CVD (chemical vapor deposition), films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface. On the other hand, film formation methods such as atomic layer deposition (ALD) or thermal CVD can form films of uniform thickness regardless of the angle of the surface to be formed. For example, when the angle of the sidewall of the opening 20 relative to the substrate surface is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0119] It is preferable that the conductive film 25b contains the same metal element as the metal element contained in the semiconductor layer 21, because this can further reduce contact resistance. Specifically, it is preferable that the conductive film 25b and the semiconductor layer 21 contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. It is particularly preferable that the conductive film 25b and the semiconductor layer 21 contain In.

[0120] In the transistor 10, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the height direction through the semiconductor. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, or the like. Since the transistor 10 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0121] Furthermore, the channel length of the transistor 10 can be precisely controlled by the thickness of the insulating layer 41, which functions as a spacer. This significantly reduces the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0122] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a high on-state current and an extremely low off-state current can be realized at low cost. Unless otherwise specified, a configuration example in which an oxide semiconductor is used for the semiconductor layer 21 will be described.

[0123] 4A and other figures show an example in which the upper surface of the conductive film 24b in the region overlapping the opening 20 has a rounded recess (concave surface). As a result, within the opening 20, the bottoms of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are each provided along the concave surface of the conductive film 24b, forming a rounded protrusion (convex surface). This allows for a configuration in which electric fields are less likely to concentrate, similar to the conductive layer 51 of the capacitive element 30. Therefore, a transistor with low leakage current and high reliability can be realized. Note that, as shown in FIG. 5A , in the region where the conductive layer 24 is not provided, the upper surface of the insulating layer 41 in the region overlapping the opening 20 has a rounded recess (concave surface). In this region, within the opening 20, the bottoms of the insulating layer 22 and the conductive layer 23 are each provided along the concave surface of the insulating layer 41, forming a rounded protrusion (convex surface).

[0124] An insulating layer 44 that functions as an interlayer insulating layer is provided to cover the insulating layer 22 and the conductive layer 23. A conductive layer 26 that functions as a bit line is provided on the insulating layer 44. A plug 27 that connects the conductive layer 25 and the conductive layer 26 is provided in an opening provided in the insulating layer 44, the insulating layer 22, and the semiconductor layer 21. This allows the conductive layer 26 to connect the multiple conductive layers 25 arranged in the X direction with the opening 20 sandwiched between them.

[0125] Here, an example is shown in which the plug 27 penetrates the conductive film 25b and is provided so as to be in contact with the conductive film 25a. This configuration in which the low-resistance conductive film 25a and the plug 27 are in contact with each other is preferable because it reduces the contact resistance between them and reduces the load on the wiring. It should be noted that the bottom surface of the plug 27 may also be configured to be in contact with the conductive film 25b or the semiconductor layer 21.

[0126] 8A and 8B show a memory array 50a and a drive circuit 50b included in the semiconductor device 50. The drive circuit 50b has a function of applying a predetermined potential to the wiring PL. Here, FIG. 8A is a plan view including the capacitance element 30 corresponding to FIG. 3B, and FIG. 8B is a cross-sectional view in the Y direction corresponding to FIG. 4B, which corresponds to the dashed dotted line B1-B3 shown in FIG. 8A. Note that parts that overlap with those described above are given the same reference numerals, and descriptions thereof will be omitted.

[0127] The memory array 50a has the same structure as the semiconductor device 50 described above. Therefore, the conductive layer 51a, insulating layer 52a, and conductive layer 53a in the memory array 50a are the same as the conductive layer 51, insulating layer 52, and conductive layer 53. The conductive layer 51b, insulating layer 52b, and conductive layer 53b in the drive circuit 50b are also the same as the conductive layer 51, insulating layer 52, and conductive layer 53, except that the conductive layer 51b is not connected to wiring or the like. Therefore, the conductive layer 51b, insulating layer 52b, and conductive layer 53b are dummies that do not function as capacitance elements.

[0128] Here, the conductive layer 53b is a wiring formed by extending the conductive layer 53a of the memory array 50a to the drive circuit 50b. In other words, the conductive layer 53a and the conductive layer 53b function as the wiring PL of the capacitance element 30. The conductive layer 53a and the conductive layer 53b can be fabricated in the same process. In this process, the conductive layer 53a and the insulating layer 52a are formed in the memory array 50a, and simultaneously, the conductive layer 53b and the insulating layer 52b are formed in the drive circuit 50b.

[0129] As shown in FIG. 8B , it is also preferable to provide a plug 70 and a conductive layer 71 connected to the conductive layer 53b in the drive circuit 50b. For example, the plug 70 may be provided penetrating the insulating layers 61, 62, 41, 42, 22, and 44, and the conductive layer 71 may be provided on the insulating layer 44. However, this is not limiting, and the conductive layer 71 may be provided on a different layer. As shown in FIG. 8A , the plug 70 may extend beyond the conductive layer 53b. In this case, the plug 70 may contact the side surface of the conductive layer 53b, the top surface of the insulating layer 52b, and the top surface of the insulating layer 11 in the region outside the conductive layer 53b. By configuring the plug 70 to contact the side surface of the conductive layer 53b in this way, the contact area between the plug 70 and the conductive layer 53b can be increased, thereby reducing contact resistance.

[0130] Here, the semiconductor device 50 may be provided by stacking a layer in which the memory cells 15 are provided and a layer in which the functional circuits are provided. The functional circuits may include, for example, a drive circuit for driving the memory cells 15, an arithmetic circuit, a power supply circuit, etc. The drive circuit may include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This not only reduces the footprint of the semiconductor chip including the semiconductor device 50, but also shortens the wiring length compared to when the functional circuits and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

[0131] 9 shows an example in which a layer 80 in which a memory cell 15 is provided and a transistor 90 constituting a functional circuit are arranged below the layer 80. In this example, one of a source electrode and a drain electrode of the transistor 90 is connected to a conductive layer 26 that functions as a bit line.

[0132] The transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. The substrate 91 can typically be made of single-crystal silicon. The substrate 91 can be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, the substrate 91 can be a semiconductor substrate having an insulator region therein, such as an SOI (Silicon On Insulator) substrate.

[0133] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95a and 95b functioning as source and drain regions. The transistor 90 can be either a p-channel type or an n-channel type. An element isolation layer 98 is provided in the substrate 91 between two adjacent transistors 90.

[0134] The transistor 90 has a semiconductor region 92 in which a channel is formed that has a convex shape (fin shape). Although not shown in Fig. 9, a conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 in the Y direction via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0135] An insulating layer 96 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 96, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 88 is provided covering the conductive layer 81 and the insulating layer 87, an insulating layer 45 is provided on the insulating layer 88, and an insulating layer 11 is provided on the insulating layer 45. A plug 82 is provided inside an opening provided in the insulating layer 96 and the insulating layer 86, and the plug 82 connects the conductive layer 81 to the low-resistance region 95b. A conductive layer 84 is provided on the insulating layer 45, and a plug 83 is provided inside an opening provided in the insulating layer 45 and the insulating layer 88, connecting the conductive layer 84 to the conductive layer 81. The conductive layer 84 and the conductive layer 26 are connected via a plug 85 provided inside an opening provided in each insulating layer between them. This connects one of the source and drain of the transistor 90 to the conductive layer 26. Furthermore, an insulating layer 47 is provided on the conductive layer 26 .

[0136] Note that although an example of providing a conductive layer 81 as a wiring layer has been shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) can be used between the layer in which the transistor 90 is provided and the layer 80 in which the memory cell 15 is provided.

[0137] The above-described films having a barrier property against hydrogen can be used for the insulating layers 45 and 47. In particular, a silicon nitride film or a silicon nitride oxide film is preferably used.

[0138] Furthermore, the insulating layer 45 and the insulating layer 47 preferably have a stacked structure in which an insulating film functioning as the above-described barrier film and an insulating film having a function of capturing or fixing hydrogen are stacked inside the insulating film (on the transistor 10 side). For example, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, a hafnium zirconium oxide film, or the like is preferably used.

[0139] This reduces the diffusion of hydrogen from the outside into the region sandwiched between insulating layers 45 and 47, and further reduces the concentration of hydrogen contained inside, thereby effectively reducing hydrogen that can diffuse into semiconductor layer 21 of transistor 10, and realizing a highly reliable transistor 10.

[0140] 10, a structure may be adopted in which a plurality of memory cells each having a transistor and a capacitor element are provided under an insulating layer 88. In FIG. 10, a capacitor element 30 is provided on a transistor 90.

[0141] The transistor 90 shown in FIG. 10 has a different structure from the transistor 90 shown in FIG.

[0142] 10 has a configuration in which an insulating layer 93 functioning as a gate insulating layer and a conductive layer 94 functioning as a gate electrode are provided in a trench portion formed in a substrate 91. Furthermore, an insulating layer 97 is formed on the conductive layer 94 in the trench.

[0143] A semiconductor region 92 is formed in the region corresponding to the side surface and bottom surface of the trench portion in the substrate 91. Above the semiconductor region 92, a low resistance region 95a and a low resistance region 95b are formed.

[0144] The transistor 90 shown in FIG. 10 has a semiconductor region 92 that is U-shaped in cross section, and low-resistance regions 95a and 95b that face each other across a trench portion in plan or cross section.

[0145] The insulating layer 97 functions as an insulating layer to prevent the low resistance region 95a and the low resistance region 95b from coming into direct contact with each other.

[0146] The transistors 90 shown in FIG. 10 are provided in pairs, with an element isolation layer 98 provided around the two transistors 90 .

[0147] An insulating layer 96a is provided on the substrate 91 and the element isolation layer 98, an insulating layer 96b is provided on the insulating layer 96a, an insulating layer 86 is provided on the insulating layer 96b, an insulating layer 87a is provided on the insulating layer 86, and an insulating layer 87b is provided on the insulating layer 87a. Here, it is preferable that the insulating layer 96b and the insulating layer 87b are made of an insulating film having barrier properties similar to the insulating layer 45.

[0148] Furthermore, a conductive layer 81a is provided between the insulating layer 96b and the insulating layer 86, and a conductive layer 81b is provided between the insulating layer 86 and the insulating layer 87a. Furthermore, plugs 82 are provided inside the openings of the insulating layer 96a, the insulating layer 96b, and the insulating layer 86. The conductive layer 81a is connected to the low resistance region 95a via the plug 82, and the conductive layer 81b is connected to the low resistance region 95b via the plug 82.

[0149] 10 has the same configuration as the capacitor 30 shown in FIG. 1 and includes a conductive layer 51, an insulating layer 52, and a conductive layer 53. Here, the insulating layer 52 is provided in contact with the side surface of the conductive layer 51. The conductive layer 53 is disposed opposite the side surface of the conductive layer 51 with the insulating layer 52 interposed therebetween. In a cross-sectional view, the height of the conductive layer 51 is greater than the width of the conductive layer 51.

[0150] 1, the capacitor 30 shown in Fig. 10 has a structure in which the upper surface of the conductive layer 51 is covered with an insulating layer 52 and a conductive layer 53. In addition, a part of the conductive layer 51 is provided to be embedded in an insulating layer 87a and an insulating layer 87b, and the conductive layer 51a is connected to a conductive layer 81b.

[0151] 10, the memory cell including the transistor 90 and the capacitor 30 can have a nonvolatile structure by using a ferroelectric insulating layer for the insulating layer 52. This allows the memory cell to retain data for a long period of time. Furthermore, using a ferroelectric insulating layer for the insulating layer 52 can improve the reliability of the memory cell.

[0152] 11 shows an example in which layers 80 each having a memory cell 15 are stacked. In FIG. 11, an example in which three layers 80 (layers 80[1] to [3] from the substrate 91 side) are stacked is shown, but two layers or four or more layers may be stacked.

[0153] The plug 85 connects the conductive layer 84 to the conductive layer 26 of the layer 80[1]. The plug 89 connects the conductive layers 26 of the two layers 80 to each other. As a result, the three conductive layers 26 of the layers 80[1] to 80[3] are connected to one of the source and drain of the transistor 90.

[0154] The insulating layer 47 is provided on the layers 80[1] to 80[3]. However, the present invention is not limited to this, and the insulating layer 47 may be provided for each layer 80.

[0155] Although the configuration shown here is one in which the layer 80 is stacked directly on the substrate 91 on which the transistor 90 is provided, the present invention is not limited to this. For example, the substrate 91 on which the transistor 90 is provided and the substrate on which the memory cell 15 is provided may be bonded together. For example, the two substrates may be bonded together by direct bonding (hybrid bonding) using a direct bonding technique, such as Cu-Cu bonding. Alternatively, a method may be used in which two or more layers are bonded together with their insulating films, and then through electrodes are formed to connect the electrodes provided on each layer. In particular, using a method using direct bonding or through electrodes allows the pitch of the connection electrodes to be extremely narrow, making it possible to arrange a large number of connection electrodes at a high density, which is preferable because it increases the amount of data transmitted between layers.

[0156] When bonding two layers, any of CoC (chip-on-chip) bonding, CoW (chip-on-wafer) bonding, and WoW (wafer-on-wafer) bonding may be used. WoW bonding is superior in productivity because wafers are bonded together, but since all chips, including both good and bad, are bonded together, the yield may be reduced. On the other hand, CoW bonding, which bonds a chip to a wafer, and CoC bonding, which bonds chips together, are inferior to WoW bonding in terms of productivity, but the yield is significantly improved because good chips can be bonded together. Furthermore, CoC bonding is inferior in productivity to the other two, but is highly versatile because it can bond two layers even when the sizes of the two layers are significantly different.

[0157] A wiring layer such as an interposer may be provided between the two layers, which eliminates the need to align the positions of bonding electrodes between two adjacent layers, increasing the degree of freedom in designing each layer and enabling the realization of a semiconductor device with higher performance.

[0158] [Regarding Components] <Substrate> Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of substrates include an insulating substrate with a conductive layer or semiconductor layer, a semiconductor substrate with a conductive layer or insulating layer, and a conductive substrate with a semiconductor layer or insulating layer. Alternatively, a substrate provided with elements may be used, such as a capacitor, a resistor, a switch (including a transistor), a light-emitting element, a memory element, or the like.

[0159] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0160] Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide. Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide containing In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0161] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0162] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0163] The semiconductor layer 21 can be made of, for example, In oxide. Alternatively, the semiconductor layer 21 can be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, or In—Ga—Al—Zn oxide. Ga—Zn oxide may also be used. A material containing Zn is preferred because it is easy to increase crystallinity.

[0164] Using a material that does not contain Zn, such as indium oxide, is preferable because it has a high compatibility with the LSI manufacturing process. By using indium oxide for the semiconductor layer 21, the on-state current or field-effect mobility of the transistor can be increased. By using such a semiconductor layer 21, the operating speed of the transistor 10 and the semiconductor device 50 can be improved.

[0165] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0166] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0167] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coating properties. When forming the metal oxide by the sputtering method, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0168] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0169] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0170] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0171] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0172] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0173] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0174] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a normally-off transistor with a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0175] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0176] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is contained, or the content of that element, also affects the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn=4:3:2 [atomic ratio] and materials in the vicinity thereof, In:Zn=1:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=2:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=4:1 [atomic ratio] and materials in the vicinity thereof, and In:Sn:Zn=40:X:10 [atomic ratio] (X is 0.1 or more and 5 or less, typically X=1) and materials in the vicinity thereof. On the other hand, examples of materials having lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn=1:3:2 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:3:4 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=2:2:1 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:1:1 [atomic ratio] and materials in the vicinity thereof, and In:Ga:Zn=1:1:2 [atomic ratio] and materials in the vicinity thereof.

[0177] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0178] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0179] An OS transistor has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, since an OS transistor has an extremely low off-state current, the frequency of refresh operations can be reduced, leading to reduced power consumption of a semiconductor device.

[0180] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0181] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0182] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0183] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0184] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0185] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0186] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0187] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0188] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0189] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0190] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials, and preferably by using a laminate structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating film (also referred to as ZAZA) can be formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0191] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ｘ It is also possible to use a metal oxide in which Y (yttrium) is added to HfZrO. ＸBy adding Y to the above, the ferroelectricity can be enhanced.

[0192] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0193] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0194] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0195] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material with a lower dielectric constant than the other films for the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen for the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen for the film located between them. Silicon oxide or silicon oxynitride can be used as the material with a low dielectric constant. With this configuration, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0196] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0197] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, an insulating film made of a material with a lower dielectric constant than the other films for the film next closest to the semiconductor layer 21, an insulating film having the function of capturing or fixing hydrogen for the film next closest to the semiconductor layer 21, and an insulating film having a barrier property against hydrogen and oxygen for the film closest to the conductive layer 23. That is, in addition to the above-described three-layer structure, a configuration can be adopted in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, oxygen desorption from the semiconductor layer 21 can be suppressed. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has the function of capturing or fixing hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 21.

[0198] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0199] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0200] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0201] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include insulating films containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and the insulating films can be used in a single layer or a stacked layer. Specifically, examples of materials that can be used for the insulating film that has a function of suppressing the permeation of impurities and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0202] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

[0203] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0204] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0205] As the conductive film in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferable.

[0206] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0207] For example, the conductive layer 24 and the conductive layer 25 can each be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0208] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element, may be used. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0209] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 .

[0210] Since the conductive layers 23, 24, and 25 also function as wirings, it is preferable to use a stack of low-resistance conductive materials. For example, the conductive films 24a and 25b can also be made of the low-resistance conductive material that can be used for the conductive layer 23.

[0211] <Insulating Layer> The insulating layer 41 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0212] The insulating layer 41 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the gate insulating layer can be used as the insulating layer 41.

[0213] Furthermore, since the insulating layer 41 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 41 is formed by using a plasma CVD method to form TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film (also called a TEOS film) formed using TEOS may be used. This can improve productivity.

[0214] The insulating layer 11, the insulating layer 62, the insulating layer 42, the insulating layer 44, the insulating layer 46, and the insulating layer 47 each function as an interlayer insulating layer. The insulating layer 11, the insulating layer 62, the insulating layer 42, the insulating layer 44, the insulating layer 46, and the insulating layer 47 can be made of the same insulating material as can be used for the insulating layer 41.

[0215] Although the above description has been given of a configuration in which the insulating layer 52 uses a material exhibiting ferroelectricity, the present invention is not limited to this. For example, the insulating layer 52 may be configured to use a dielectric material with relatively high polarization volatility. The dielectric material may be an insulating material that can be used for the insulating layer 22, such as a high-dielectric-constant (high-k) material. Specifically, for example, the insulating layer 52 may be made of a high-dielectric-constant material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide.

[0216] Here, a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has a significantly small source-drain leakage current in an off state (hereinafter also referred to as an off-state current). Therefore, even if a capacitor using the above-described dielectric material is connected in series to the transistor, charge stored in the capacitor can be held for a long period of time. Therefore, a memory cell including a capacitor using the above-described dielectric material can also hold data for a long period of time.

[0217] This concludes the description of the components.

[0218] [Modification] The following describes an example in which the configuration is partially different from the above-described configuration example. Note that the same reference numerals are used to designate the same parts as those described above, and descriptions thereof will be omitted.

[0219] 1 and the like, the conductive layer 51 is provided in contact with the upper surface of the insulating layer 11, but the present invention is not limited to this. As shown in Fig. 12A, a configuration in which the conductive layer 51 is provided so as to penetrate the insulating layer 11 is also possible. Here, Fig. 12A corresponds to Fig. 4A.

[0220] 12A , in a configuration in which conductive layer 51 is provided so as to penetrate insulating layer 11, a portion of conductive layer 51 may be embedded in insulating layer 75 below insulating layer 11. In this case, as shown in FIG. 12A , a concave curved surface may be formed on the upper part of insulating layer 75. However, this is not limited to this, and the lower surface of conductive layer 51 may also be flat.

[0221] In this way, by adopting a structure in which the side surface of the insulating layer 11 contacts the side surface of the conductive layer 51, it is possible to prevent the conductive layer 51 from collapsing during the manufacturing process of the capacitance element 30. This allows the semiconductor device to be manufactured with a high yield.

[0222] [Variation 2] In the configuration shown in Fig. 6 and other figures, the height of the upper end of the conductive layer 51a is approximately the same as the height of the upper end of the conductive layer 51b, but the present invention is not limited to this. As shown in Fig. 12B, the upper end of the conductive layer 51a may be higher than the upper end of the conductive layer 51b. Here, Fig. 12B corresponds to Fig. 4A and Fig. 6.

[0223] 12B , the height of the upper end of conductive layer 51a is approximately the same as the height of the upper end of insulating layer 52 and the height of the upper end of conductive layer 53. In contrast, the upper end of conductive layer 51b is lower than the upper end of conductive layer 51a, and conductive layers 51a and 51b form a recess in the upper part of conductive layer 51. Part of conductive film 24a and part of insulating layer 61 are formed in this recess. Part of insulating layer 61 contacts the inner side surface of conductive layer 51a. In this way, when conductive layer 51 has a layered structure of conductive layers 51a and 51b, there are cases where only the upper part of conductive layer 51a is removed and the upper part of conductive layer 51b is not removed.

[0224] 1 and the like, the region that does not overlap with the conductive layer 51 is covered with the insulating layer 52, but the present invention is not limited to this. As shown in Fig. 13A, a configuration may also be adopted in which the side surface of the insulating layer 52 roughly coincides with the side surface of the conductive layer 53. Here, Fig. 13A corresponds to Fig. 4A.

[0225] 13A , the outer side surface of insulating layer 52 roughly coincides with the outer side surface of conductive layer 53. In other words, insulating layer 52 is disposed so as to overlap conductive layer 53. In this case, in the region outside insulating layer 52, insulating layer 46 contacts insulating layer 11.

[0226] 1 and the like, the conductive layer 53 is provided extending in the Y-axis direction, but the present invention is not limited to this. As shown in FIG. 13B , the conductive layer 53 may be formed so as to cover the insulating layer 52.

[0227] 13B, since the insulating layer 52 is covered with the conductive layer 53, the insulating layer 46 does not come into contact with the insulating layer 52 in the structure shown in Fig. 13B. In this case, the wiring PL is provided in common throughout the entire memory array.

[0228] 1 and the like in that two transistors (transistors 10a) are provided in one opening 20. Here, Fig. 14 corresponds to Fig. 4A.

[0229] The semiconductor layer 21, the insulating layer 22, the conductive layer 23, and the conductive layer 24 are divided into two parts within the opening 20 and its vicinity along the extension direction of the opening 20. The semiconductor layer 21 and the insulating layer 22 are provided along one of a pair of side surfaces of the insulating layer 41 within the opening 20.

[0230] A pair of conductive layers 23 provided in the opening 20 each extend in the Y direction and function as a word line, while a conductive layer 26 extending in the X direction functions as a bit line.

[0231] A capacitor element 30 is provided in each of the pair of divided conductive layers 24. This allows one opening 20 to be shared by two memory cells 15.

[0232] Furthermore, an insulating layer 48 is provided along the side surfaces of the conductive layer 23, the insulating layer 22, the semiconductor layer 21, and the conductive layer 24, and along the top surface of the insulating layer 62, the top surface of the conductive layer 23, and the top surface of the insulating layer 22. A recess is formed in the top surface of the insulating layer 48, and the insulating layer 44 is provided on the insulating layer 48 so as to fill the recess. Similar to the insulating layer 61, the insulating layer 48 preferably functions as a barrier film against impurities. This makes it possible to prevent impurities such as hydrogen contained in the insulating layer 44 from diffusing into the semiconductor layer 21.

[0233] 1 and other figures, multiple transistors 10 are provided in the openings 20 extending in a slit shape, but the present invention is not limited to this. As shown in Figures 15A and 15B, the openings 20 may be formed in a vertical cavity shape (which may also be called a hole shape), and one transistor 10 may be provided in each opening 20. Here, Figure 15A corresponds to Figure 4A, and Figure 15B corresponds to Figure 4B.

[0234] 15B , in the transistor 10, the opening 20 is formed in the shape of a vertical hole, and therefore, even in a cross section in the Y-axis direction, the semiconductor layer 21 is formed in contact with the sidewall of the opening 20, and the insulating layer 22 is formed along the sidewall. Also, as shown in FIG. 15B , the upper part of the conductive layer 23 is formed over the conductive layer 25, and the conductive layer 23 is provided extending in the Y-axis direction. Note that, although the conductive layer 25 is not embedded in the interlayer insulating film in FIG. 15B , a structure in which the conductive layer 25 is embedded in the insulating layer 42 may also be used, similar to FIG. 5B and the like.

[0235] Furthermore, since the opening 20 is formed in the shape of a vertical hole, the conductive layer 25 can be provided extending in the X-axis direction, bypassing the opening 20. In this case, the conductive layer 25 is formed so as to surround the periphery of the opening 20. Furthermore, since the conductive layer 25 can function as wiring, a configuration can be achieved in which the conductive layer 26 and the plug 27 are not provided.

[0236] The above is a description of the modified example.

[0237] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking a semiconductor device including the memory cell 15 exemplified in the above structure example as an example.

[0238] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition, or the like.

[0239] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0240] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming films using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0241] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0242] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0243] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0244] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0245] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0246] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0247] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0248] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0249] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0250] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0251] 16A1 to 23C2 are cross-sectional views corresponding to the steps in the fabrication method exemplified below. Each of the figures (A1), (B1), and (C1) shows a cross section corresponding to FIG. 4A, and each of the figures (A2), (B2), and (C2) shows a cross section corresponding to FIG. 4B.

[0252] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0253] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0254] The insulating layer 11 can be an inorganic insulating film such as a silicon nitride film or a silicon nitride oxide film. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon nitride film can be formed as the insulating layer 11 by a PEALD method. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 is flat.

[0255] Subsequently, an insulating layer 63 is formed on the insulating layer 11. The insulating layer 63 is a sacrificial layer that will be removed in a later step.

[0256] The insulating layer 63 can be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. The insulating layer 63 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Here, when an opening is formed in the insulating layer 63 in a later process, the insulating layer 11 functions as an etching stopper. Therefore, it is preferable to select materials for the insulating layer 63 and the insulating layer 11 so that the etching selectivity of the insulating layer 63 is higher than that of the insulating layer 11. For example, the insulating layer 63 can be formed of silicon oxide by plasma CVD using TEOS. If the surface on which the insulating layer 63 is to be formed is not flat, a planarization process may be performed after the insulating layer 63 is formed to flatten the upper surface of the insulating layer 63.

[0257] Next, an opening reaching the insulating layer 11 is formed in the insulating layer 63 using photolithography (FIGS. 16A1 and 16A2). At this time, a portion of the upper surface of the insulating layer 11 may be etched. In a later process, a columnar conductive layer 51 having a width W and a height H and a high aspect ratio is formed inside the opening. Therefore, since the opening also has a high aspect ratio, it is preferable to form it by anisotropic etching. When performing anisotropic etching, it is preferable to use a dry etching method. For example, it is preferable to perform reactive ion etching, which generates a self-bias potential. The shape of the opening in plan view can be a circle, a nearly circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape with rounded corners such as a rectangle.

[0258] 3B, the distance between adjacent openings is L' in the X-axis direction and L in the Y-axis direction. In particular, it is preferable that the distance L' is set to dimension F' and the distance L is set to the minimum processing dimension F. It is also preferable that the width W of the openings is set to the minimum processing dimension F. By adopting such a configuration, it is possible to achieve miniaturization and high integration of semiconductor devices.

[0259] The opening can also be formed through the insulating layer 11. With this configuration, the conductive layer 51 to be formed later can be supported by the insulating layer 11, thereby increasing the yield even when the capacitor element 30 has a high aspect ratio. In this case, as shown in FIG. 12A , a recess may be formed in the insulating layer 75 provided below the insulating layer 11.

[0260] Next, a conductive film 51f that will become the conductive layer 51 is formed so as to cover the upper surface of the insulating layer 63 and fill the opening (FIGS. 16A1 and 16A2). The conductive film 51f can be formed using a conductive material corresponding to the conductive layer 51 described above. The conductive film 51f can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoint of coverage, the CVD method is particularly preferable. For example, the conductive film 51f can be formed of titanium nitride using a CVD method. Alternatively, the conductive film 51f can be formed of titanium nitride using a CVD method, and then a tungsten film can be formed thereon using a CVD method.

[0261] Next, a planarization process is performed until the upper surface of the insulating layer 63 is exposed, and the upper portion of the conductive film 51f is removed to form the conductive layer 51A inside the opening (FIGS. 16B1 and 16B2). The planarization process can be performed by, for example, a chemical mechanical polishing (CMP) method or a dry etching method.

[0262] Next, the upper portion of the conductive layer 51A is etched to form the conductive layer 51 (FIGS. 16C1 and 16C2). The etching can be performed by dry etching or wet etching. For example, it is preferable to remove the upper portion of the conductive layer 51A by wet etching. As shown in FIG. 12B, when the conductive layer 51 has a stacked structure of conductive layers 51a and 51b, it is also possible to etch only the conductive layer 51b and not the conductive layer 51a.

[0263] Next, an insulating film 64f, which will become the insulating layer 64 in a later step, is formed so as to cover the upper surface of the insulating layer 63 and fill the opening above the conductive layer 51 (FIGS. 17A1 and 17A2). The insulating film 64f can be made of an insulating material that can be used for the insulating layer 11. The insulating film 64f can be formed by a CVD method, an ALD method, a sputtering method, or the like. For example, the insulating film 64f can be made of silicon nitride using a PEALD method.

[0264] Next, a planarization process is performed until the top surface of the insulating layer 63 is exposed, and the upper portion of the insulating film 64f is removed to form an insulating layer 64 inside the opening ( FIGS. 17B1 and 17B2 ). The planarization process can be performed using, for example, CMP or dry etching. The insulating layer 64 is a sacrificial layer that will be removed in a later step. By forming the insulating layer 64 on the conductive layer 51 in this manner, the top ends of the insulating layer 52 and the conductive layer 53 can be made higher than the top end of the conductive layer 51. This prevents short circuits from occurring between the electrodes of the capacitor element 30.

[0265] Next, the insulating layer 63 is etched and removed to expose the side surfaces of the insulating layer 64, the side surfaces of the conductive layer 51, and the top surface of the insulating layer 11 ( FIGS. 17C1 and 17C2 ). This etching can be performed by dry etching or wet etching. For example, it is preferable to remove the insulating layer 63 by wet etching. Note that, as shown in FIG. 12A , if the conductive layer 51 is configured to penetrate the insulating layer 11, the insulating layer 11 can support the conductive layer 51 even after the insulating layer 63 is removed. This prevents the conductive layer 51 from collapsing in this process, thereby improving the manufacturing yield of semiconductor devices.

[0266] Next, an insulating film 52f is formed to cover the insulating layer 11, the conductive layer 51, and the insulating layer 64 (FIGS. 18A1 and 18A2). The insulating film 52f is preferably made of a ferroelectric material that can be used for the insulating layer 52. The insulating film 52f can be formed by a method such as CVD, ALD, or sputtering. To form the insulating film 52f on the side surfaces of the conductive layer 51, which has a high aspect ratio, it is preferable to use a thermal ALD method or a PEALD method, which have good coverage. For example, the insulating film 52f can be formed of hafnium zirconium oxide by a thermal ALD method.

[0267] For example, when hafnium zirconium oxide is used for the insulating film 52f, the precursor is HfCl ４ , ZrCl ４ In addition, organometallic compounds such as tetrakis(ethylmethylamido)hafnium (TEMAHf) as a precursor containing hafnium and tetrakis(ethylmethylamido)zirconium (TEMAZr) as a precursor containing zirconium can be used.

[0268] The oxidizing agent used in the thermal ALD method or the plasma-based ALD method is O ２ , O ３ , N ２ O, NO ２ , H ２ O, H ２ O ２ For example, one or more of the following can be used: ２ O or H ２ O ２ This makes it possible to increase the proportion of the region exhibiting the ferroelectric phase in the insulating layer 52.

[0269] Next, a conductive film 53f that will become the conductive layer 53 is formed to cover the upper surface of the insulating film 52f (FIGS. 18A1 and 18A2). The conductive film 53f can be formed using a conductive material corresponding to the conductive layer 53 described above. The conductive film 53f can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoint of coverage, it is particularly preferable to form the conductive film 53f by a CVD method. For example, the conductive film 53f can be formed of titanium nitride by a CVD method. Alternatively, the conductive film 53f can be formed of titanium nitride by a CVD method, and then a tungsten film can be formed thereon by a CVD method.

[0270] The conductive film 53f is preferably formed while heating the substrate. For example, the substrate temperature can be set to 200°C or higher and 600°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 350°C or higher and 450°C or lower. Alternatively, a heat treatment may be performed within the above temperature range after the conductive film 53f is formed. When performing the heat treatment, an apparatus that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element or a medium such as a heated gas can be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used.

[0271] By performing the heat treatment, the insulating film 52f containing the ferroelectric material is heated and slowly cooled while the conductive layer 51 and the conductive film 53f are in contact with each other. It is preferable to use a conductive material (e.g., titanium nitride) with a higher thermal expansion coefficient than the insulating film 52f for one or both of the conductive layer 51 and the conductive film 53f. This configuration causes tensile stress to act in the insulating film 52f due to the difference in thermal expansion coefficient between the conductive layer 51 and the conductive film 53f and the insulating film 52f. This allows the insulating film 52f to have a structure of the space group Pca2, which exhibits ferroelectricity. １ The orthorhombic crystal structure of the crystalline structure can be increased.

[0272] Next, the conductive film 53f is anisotropically etched to form the conductive layer 53A (FIGS. 18B1 and 18B2). When performing anisotropic etching, it is preferable to use a dry etching method. For example, it is preferable to perform reactive ion etching that generates a self-bias potential. For example, it is preferable to remove a portion of the conductive film 53f using the dry etching method.

[0273] In the anisotropic etching, regions of the conductive film 53f that are generally parallel to the substrate surface are removed. For example, as shown in FIGS. 18B1 and 18B2, regions of the conductive film 53f above the portion of the insulating film 52f that overlaps with the insulating layer 64 are removed. Also, for example, as shown in FIG. 18B1, in a region where adjacent conductive layers 51 are spaced apart by a distance L', regions where the conductive film 53f is formed generally parallel to the substrate surface are removed. On the other hand, for example, as shown in FIG. 18B2, in a region where adjacent conductive layers 51 are spaced apart by a distance L, the conductive film 53f is not formed generally parallel to the substrate surface. As a result, the conductive film 53f is not removed in that region.

[0274] In this manner, the conductive layer 53A is formed in a sidewall-like manner in contact with the side surface of the pillar-shaped body made up of the conductive layer 51, the insulating layer 64, and the insulating film 52f. That is, as shown in Figures 18B1 and 18B2, the sidewall-like conductive layer 53A is formed extending in the Y-axis direction.

[0275] With the above configuration, the conductive layer 53 of the beaded wiring can be formed in a self-aligned manner without using a mask. This simplifies the manufacturing process of the capacitance element 30, and enables semiconductor devices to be manufactured with high productivity. Furthermore, compared to when the conductive layer 53 is formed in a line-and-space pattern using a mask, the spacing between adjacent conductive layers 53 can be narrowed. This allows for miniaturization and high integration of semiconductor devices.

[0276] 13A, the insulating layer 52 can be formed on the conductive layer 53. Therefore, the outer side surface of the conductive layer 53 and the outer side surface of the insulating layer 52 are substantially aligned with each other.

[0277] Next, an insulating film 46f is formed to cover the conductive layer 53A and the insulating film 52f (FIGS. 18C1 and 18C2). The insulating film 46f may be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. The insulating film 46f may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the insulating film 46f may be formed of silicon oxide by a plasma CVD method using TEOS.

[0278] Next, a planarization process is performed until the top surface of the insulating layer 64 is exposed, and the insulating film 46f, the conductive layer 53A, and the upper portions of the insulating film 52f are removed to form the insulating layer 46, the conductive layer 53, and the insulating layer 52 (FIGS. 19A1 and 19A2). The planarization process can be performed by, for example, a CMP method or a dry etching method.

[0279] 19A1 and 19A2 show the conductive layer 53 extending in the Y-axis direction, but this is not limited to the memory array. Using the above method, as shown in FIGS. 8A and 8B, dummy conductive layers 51b and dummy insulating layers 52b can also be formed in the drive circuit. This allows the sidewall-shaped conductive layer 53b to be extended in the drive circuit as well. Therefore, the conductive layer 53 that functions as the wiring PL can be extended from the memory array to the drive circuit.

[0280] Next, the insulating layer 64 is etched and removed (FIGS. 19B1 and 19B2). This etching can be performed by dry etching or wet etching. As shown in FIGS. 19B1 and 19B2, the upper ends of the insulating layer 52 and the conductive layer 53 can be made higher than the upper end of the conductive layer 51. This can prevent short circuits from occurring between the electrodes of the capacitance element 30.

[0281] Next, an insulating layer 61 is formed to cover the insulating layer 46, the conductive layer 53, the insulating layer 52, and the conductive layer 53 (FIGS. 19C1 and 19C2). The insulating layer 61 can be formed using an insulating material that can be used for the insulating layer 11. The insulating layer 61 can be formed using a CVD method, an ALD method, a sputtering method, or the like. For example, the insulating layer 61 can be formed using a silicon nitride film using a PEALD method.

[0282] Next, an insulating layer 62 is formed on the insulating layer 61 (FIGS. 19C1 and 19C2). Preferably, the insulating layer 62 is formed so as to fill the recesses on the conductive layer 51. The insulating layer 62 may be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. The insulating layer 62 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the insulating layer 62 may be formed of silicon oxide by a sputtering method. If the surface on which the insulating layer 62 is to be formed is not flat, a planarization process may be performed after the insulating layer 62 is formed to flatten the upper surface of the insulating layer 62.

[0283] Next, openings are formed in the insulating layers 61 and 62 by photolithography, reaching the conductive layer 51 (FIGS. 20A1 and 20A2). Here, a coating type insulating film such as an SOC (Spin On Carbon) film or an SOG (Spin On Glass) film can be used as the mask.

[0284] The opening can be formed by dry etching or wet etching. Since the opening has a high aspect ratio, it is preferable to form it by anisotropic etching. When anisotropic etching is performed, it is preferable to use dry etching. For example, it is preferable to perform reactive ion etching, which generates a self-bias potential. The shape of the opening in plan view can be a circle, a nearly circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape with rounded corners such as a rectangle.

[0285] Next, a conductive film 24af that will become the conductive film 24a is formed on the insulating layer 62 so as to fill the openings in the insulating layer 61 and the insulating layer 62. Thereafter, the top surface of the conductive film 24af may be planarized as necessary. The conductive film 24af can be formed using a conductive material corresponding to the conductive layer 24 described above. The conductive film 24af can be formed by a CVD method, an ALD method, a sputtering method, or the like. From the viewpoint of coverage, the CVD method is particularly preferable. For example, titanium nitride can be formed as the conductive film 24af by a CVD method. Alternatively, titanium nitride can be formed as the conductive film 24af by a CVD method, and then tungsten can be formed thereon by a CVD method.

[0286] Next, a conductive film 24bf that will become the conductive film 24b is formed on the conductive film 24af (FIGS. 20B1 and 20B2). The conductive film 24bf can be formed by a CVD method, an ALD method, a sputtering method, or the like. For example, the conductive film 24bf can be formed by sputtering using indium tin oxide or indium tin oxide doped with silicon.

[0287] Next, the conductive films 24af and 24bf are processed into island shapes using photolithography to form the conductive films 24a and 24b (FIGS. 20C1 and 20C2). A coating-type insulating film such as an SOC film or an SOG film can be used as a mask. The above processing can be performed by dry etching or wet etching.

[0288] In this manner, the capacitor 30 including the conductive layer 51, the insulating layer 52, and the conductive layer 53 can be formed. Here, the top surface of the conductive layer 51 functioning as one electrode of the capacitor 30 is in contact with the bottom surface of the conductive layer 24 functioning as one of the source and drain electrodes of the transistor 10.

[0289] Subsequently, an insulating layer 41 is formed to cover the conductive layer 24, and a planarization process is performed on the upper surface of the insulating layer 41. The insulating layer 41 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0290] The insulating layer 41 is preferably an oxide film containing a large amount of oxygen to such an extent that oxygen is released by heating and a small amount of hydrogen. The insulating layer 41 can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but is preferably formed by a sputtering method. In particular, by forming the insulating layer 41 using a gas containing oxygen and not a gas containing hydrogen as a film formation gas, an insulating film containing an extremely small amount of hydrogen and an excess amount of oxygen can be formed. By forming the insulating layer 41 in this manner, oxygen can be supplied from the insulating layer 41 to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0291] Subsequently, heat treatment may be performed. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen after the heat treatment in the nitrogen gas or inert gas atmosphere. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0292] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 41 and the like as much as possible.

[0293] A process for supplying oxygen may be performed after the insulating layer 41 is formed. This allows oxygen to be supplied from the insulating layer 41 to the semiconductor film 21f by heat or the like applied after the semiconductor film 21f is formed.

[0294] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0295] Subsequently, a conductive film to become the conductive film 25a and a conductive film to become the conductive film 25b are stacked on the insulating layer 41. The conductive film to become the conductive film 25a and the conductive film to become the conductive film 25b can each be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0296] Next, a resist mask is formed on the conductive film that will become conductive film 25b, and unnecessary portions of each conductive film are removed to form conductive films 25a and 25b. Next, an insulating film that will become insulating layer 42 is formed, and planarization processing is performed until the top surface of conductive film 25b is exposed, thereby forming insulating layer 42 (FIGS. 21A1 and 21A2). This allows conductive film 25a and conductive film 25b to be embedded in insulating layer 42.

[0297] The insulating layer 42 may not be provided if it is not necessary.

[0298] Next, a resist mask is formed on the conductive film 25b and the insulating layer 42, and an opening 20 extending in the Y-axis direction is formed in the conductive film 25b, the conductive film 25a, the insulating layer 42, and the insulating layer 41 ( FIGS. 21B1 and 21B2 ). When forming the opening 20, it is preferable to etch a portion of the conductive film 24a located at the bottom of the opening 20 to form a recess in the conductive film 24b. At this time, it is preferable to perform etching so that a concave surface is formed on the upper part of the conductive film 24a. It is also preferable to form a concave surface on the upper surface of the insulating layer 41 in areas where the conductive layer 24 is not provided.

[0299] When forming the opening 20, it is preferable to process the opening 20 by anisotropic dry etching so that the sidewalls of the opening 20 (the side surfaces of the conductive film 25b, the conductive film 25a, the insulating layer 42, and the insulating layer 41) are each approximately vertical. Depending on the processing conditions, the sidewalls of the opening 20 may be inclined with respect to the direction perpendicular to the surface to be formed, resulting in a tapered shape.

[0300] Subsequently, a semiconductor film 21f that will become the semiconductor layer 21 is formed to cover the upper and side surfaces of the conductive film 25b, the side surfaces of the conductive film 25a, and the upper and side surfaces of the insulating layer 41 (FIGS. 21C1 and 21C2).

[0301] The semiconductor film 21f may be a metal oxide (oxide semiconductor) film having semiconductor properties. The metal oxide film may be formed by a suitable method such as sputtering, CVD, MBE, PLD, or ALD. The metal oxide film is preferably formed in contact with the substantially vertical side surfaces of the insulating layer 41. Therefore, the metal oxide film is preferably formed by a method with good coverage, and more preferably by ALD.

[0302] The metal oxide film preferably has crystallinity. In particular, the metal oxide film of one embodiment of the present invention preferably contains a metal oxide having a CAAC structure.

[0303] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0304] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time a metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0305] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering can be used for each. In particular, depositing the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layer constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when the layer contains silicon, carbon, or the like). Furthermore, the first metal oxide film and the second metal oxide film may have different compositions. Although a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited thereto. Similar processes can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0306] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0307] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0308] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0309] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0310] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0311] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0312] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0313] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0314] The conditions for forming the metal oxide film include a substrate temperature of room temperature or higher and 250° C. or lower, preferably room temperature or higher and 200° C. or lower, and more preferably room temperature or higher and 140° C. or lower. For example, a substrate temperature of room temperature or higher and lower than 140° C. is preferred because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0315] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or a PEALD method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0316] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0317] For example, when forming an indium oxide film, a precursor containing indium may be used. Furthermore, when forming an In—Ga—Zn oxide film, three precursors, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, may be used. Alternatively, two precursors, a precursor containing indium and a precursor containing both gallium and zinc, may be used.

[0318] Examples of precursors that can be used that contain indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0319] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0320] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0321] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0322] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0323] After the metal oxide film is formed, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, and is preferably performed at 250° C. or higher and 650° C. or lower, and more preferably at 400° C. or higher and 600° C. or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for the desorbed oxygen.

[0324] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0325] Although the semiconductor film 21f is shown as a single layer in the drawings, it may have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by the sputtering method. Note that the semiconductor film 21f may have a laminated structure of four or more layers.

[0326] Next, a resist mask is formed on the semiconductor film 21f. At this time, in order to suppress variations in the thickness of the resist mask, an organic or inorganic material formed by a coating method may be provided between the resist mask and the semiconductor film 21f as a planarizing film that fills the opening 20. More specifically, a coating type insulating film such as an SOC (Spin On Carbon) film or an SOG (Spin On Glass) film may be used.

[0327] Next, the portions of the semiconductor film 21f that are not covered by the resist mask are removed by etching, and then the resist mask is removed, thereby forming the semiconductor layer 21 (FIGS. 22A1 and 22A2). Because it is difficult to remove the portions of the semiconductor layer 21 that are in contact with the side surfaces of the insulating layer 41 by anisotropic dry etching alone, it is preferable to perform etching by combining isotropic dry etching and wet etching. Alternatively, the regions of the semiconductor film 21f that are not covered by the resist mask may be treated in advance to modify part of the semiconductor film 21f so that it is easier to etch. Examples of such treatment include plasma treatment, doping (including ion implantation), and wet treatment.

[0328] Next, an insulating layer 22 is formed to cover the semiconductor layer 21 and the insulating layer 41 (FIGS. 22B1 and 22B2). The insulating layer 22 can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable that the insulating layer 22 be provided on the surface of the vertical portion of the semiconductor layer 21 with as uniform a thickness as possible. Therefore, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. Note that when the sidewalls of the insulating layer 41 are tapered, the insulating layer 22 can be formed by a film formation method such as sputtering or CVD.

[0329] Next, a conductive film 23f, which will later become the conductive layer 23, is formed to cover the insulating layer 22 (FIGS. 22C1 and 22C2). The conductive film 23f can be formed by a method such as CVD, ALD, or sputtering. From the viewpoint of coverage, it is particularly preferable to form the conductive film 23f by CVD.

[0330] Next, without using a photomask, the upper part of the conductive film 23f is etched until the upper surface of the insulating layer 22 is exposed, thereby forming a conductive layer 23 that is embedded inside the opening 20 (Figures 23A1 and 23A2).

[0331] At this time, it is preferable to process the conductive film 23f so that the upper surface of the conductive layer 23 is located higher than the lower surface of the conductive film 25a. If the height of the upper surface of the conductive layer 23 is lower than the height of the lower surface of the conductive film 25a, a so-called offset region is formed in which a gate electric field is not applied to the semiconductor layer 21. On the other hand, if the height of the upper surface of the conductive layer 23 is higher than the lower surface of the conductive layer 25a, no offset region is formed, and a transistor with a high on-current can be realized.

[0332] At this point, transistor 10 can be formed.

[0333] Subsequently, an insulating layer 44 is formed to cover the conductive film 25b, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 (FIGS. 23B1 and 23B2). The insulating layer 44 can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0334] Next, an opening reaching the conductive film 25 a is formed in the insulating layer 44, the insulating layer 22, the semiconductor layer 21, and the conductive film 25 b. Thereafter, a conductive film is formed to fill the opening, and a planarization process is performed until the top surface of the insulating layer 44 is exposed, thereby forming the plug 27.

[0335] Subsequently, a conductive film is formed on the insulating layer 44 and the plugs 27, and unnecessary portions are removed by etching to form the conductive layer 26 (FIGS. 23C1 and 23C2).

[0336] Through the above steps, a semiconductor device including a memory cell 15 including the transistor 10 and the capacitor 30 can be manufactured. By manufacturing the transistor 10 over the capacitor 30 in this manner, the semiconductor layer 21 including an oxide semiconductor is not exposed to heat treatment in the manufacturing process of the capacitor 30. This can reduce the thermal history of the semiconductor layer 21, thereby enabling the manufacture of a highly reliable semiconductor device.

[0337] The above is a description of an example of the manufacturing method.

[0338] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0339] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0340] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0341] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0342] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 24A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 24B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0343] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 24B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 24A (see Non-Patent Document 6). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 24A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 24A.

[0344] 24A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0345] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0346] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0347] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0348] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 24A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0349] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0350] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 24B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 24A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0351] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0352] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0353] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0354] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0355] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0356] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0357] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0358] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0359] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0360] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0361] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0362] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0363] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 24C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0364] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0365] Furthermore, as shown in FIG. 24C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0366] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0367] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0368]

[0369] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0370] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0371] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0372] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0373] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0374] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0375] Embodiment 3 In this embodiment, structural examples of a memory device which is a semiconductor device of one embodiment of the present invention and a peripheral circuit included in the memory device will be described with reference to FIGS. 25 to 27B.

[0376] 25 shows an example of the configuration of a memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0377] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above wiring is connected to the memory cell of the memory cell array 1470. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, a plate line driver circuit, etc., and can select the row to access.

[0378] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside as power supply voltages. Control signals (CE, WEN, RES), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0379] The control logic circuit 1460 processes control signals (CE, WEN, RES) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WEN is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0380] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0381] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary. The memory device of one embodiment of the present invention has high operating speed and can retain data for a long period of time.

[0382] FIG. 26 shows an example of the configuration of the memory cell array 1470 and memory cells MC.

[0383] The memory cell array 1470 shown in Fig. 26 has memory cells 1480 arranged in a matrix of m / 2 rows and n columns (m is an even number greater than or equal to 1, and n is an integer greater than or equal to 1). The memory cell 1480 shown in Fig. 26 is a memory circuit applicable to the memory cell MC described above, and is an example of a circuit configuration of a memory cell using a ferroelectric capacitor. Fig. 26 also shows a row circuit 1420 and a column circuit 1430.

[0384] 26, a memory cell 1480 includes a transistor M9 and a capacitance element Cfe. In the memory cell 1480, the transistor M9 can correspond to the transistor 10 described in the first embodiment, and the capacitance element Cfe can correspond to the capacitance element 30 described in the first embodiment.

[0385] In the memory cell array 1470 of FIG. 26, m memory cells 1480 are connected to one wiring BL.

[0386] In the following, the description will be focused on one of the memory cells 1480 shown in FIG.

[0387] One of the source and drain of the transistor M9 is connected to a wiring BL (e.g., one of the wirings BL[1] to BL[n]). The other of the source and drain of the transistor M9 is connected to one of a pair of electrodes of a capacitor Cfe. The gate of the transistor M9 is connected to a wiring WL (e.g., one of the wirings WL[1] to WL[m]). The other of the pair of electrodes of the capacitor Cfe is connected to a wiring PL (e.g., one of the wirings PL[1] to PL[m]).

[0388] The wiring WL functions as a word line, and can control switching between an on state and an off state of the transistor M9 by applying a potential to the wiring WL as a selection signal or a non-selection signal. For example, the transistor M9 can be turned on by setting a selection signal applied to the wiring WL to a high potential (H), and the transistor M9 can be turned off by setting a non-selection signal applied to the wiring WL to a low potential (L). The wiring WL is connected to a word line driver circuit included in the row circuit 1420, and the word line driver circuit can apply a selection signal or a non-selection signal to the wiring WL.

[0389] The wiring BL functions as a bit line, and when the transistor M9 is on, a potential corresponding to a data signal applied to the wiring BL is applied to one of a pair of electrodes of the capacitor Cfe. The wiring BL is connected to a bit line driver circuit included in the column circuit 1430. The bit line driver circuit has a function of generating a data signal to be written to the memory cell MC. The bit line driver circuit also has a function of reading data output from the memory cell MC. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell MC can be read using the sense amplifier.

[0390] The wiring PL has the function as a plate line. To the other of the pair of electrodes of the capacitor element Cfe, a predetermined potential applied to the wiring PL is supplied. The wiring PL is connected to a plate line driver circuit included in the row circuit 1420, and the plate line driver circuit is a circuit that can apply the potential to the wiring PL during, for example, a write operation or a read operation.

[0391] The capacitor element Cfe has a material that can have ferroelectricity as a dielectric layer between two electrodes. By using a ferroelectric layer that can be thinned as a dielectric layer of the capacitor element and combining it with a miniaturized transistor, a memory device with high integration can be achieved. Hereinafter, the dielectric layer included in the capacitor element Cfe is referred to as a ferroelectric layer.

[0392] The ferroelectric layer included in the capacitor element Cfe has hysteresis characteristics. FIG. 27A is a graph showing an example of the hysteresis characteristics. In FIG. 27A, the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one of the pair of electrodes of the capacitor element Cfe and the potential of the other of the pair of electrodes of the capacitor element Cfe.

[0393] Further, in FIG. 27A, the vertical axis represents the polarization of the ferroelectric layer. When the value is positive, it indicates that positive charges are biased to one side of the pair of electrodes of the capacitor element Cfe and negative charges are biased to the other electrode side of the pair of electrodes of the capacitor element Cfe. On the other hand, when the polarization has a negative value, it indicates that positive charges are biased to the other side of the pair of electrodes of the capacitor element Cfe and negative charges are biased to one side of the pair of electrodes of the capacitor element Cfe.

[0394] Note that the voltage shown on the horizontal axis of the graph in FIG. 27A may be the difference between the potential of the other electrode of the pair of electrodes of the capacitor element Cfe and the potential of one electrode of the pair of electrodes of the capacitor element Cfe. Also, the polarization shown on the vertical axis of the graph in FIG. 27A may be set to a positive value when positive charges are biased to the other electrode side of the pair of electrodes of the capacitor element Cfe and negative charges are biased to one electrode side of the pair of electrodes of the capacitor element Cfe, and a negative value when positive charges are biased to one electrode side of the pair of electrodes of the capacitor element Cfe and negative charges are biased to the other electrode side of the pair of electrodes of the capacitor element Cfe.

[0395] 27A, the hysteresis characteristic of the ferroelectric layer can be represented by a curve 65 and a curve 66. The voltages at the intersections of the curve 65 and the curve 66 are defined as VSP and −VSP. It can be said that VSP and −VSP have opposite polarities.

[0396] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 65. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 66. Therefore, VSP and -VSP can each be referred to as a saturation polarization voltage. Note that, for example, VSP may be referred to as the first saturation polarization voltage, and -VSP may be referred to as the second saturation polarization voltage. Also, while FIG. 27A shows a case where the absolute values ​​of the first and second saturation polarization voltages are equal, the absolute values ​​of the two may be different.

[0397] Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 65 and the polarization of the ferroelectric layer is 0. Furthermore, −Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 66 and the polarization of the ferroelectric layer is 0. Vc and Vc can be referred to as coercive voltages, respectively. The values ​​of Vc and Vc can be referred to as values ​​between −VSP and VSP. For example, Vc may be referred to as the first coercive voltage, and −Vc may be referred to as the second coercive voltage. Although FIG. 27A shows that the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, their absolute values ​​may be different.

[0398] Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called "remanent polarization Pr" and the minimum value is called "remanent polarization -Pr". Furthermore, the difference between the remanent polarization Pr and the remanent polarization -Pr is called "remanent polarization 2Pr".

[0399] As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be expressed by the difference between the potential of one of the pair of electrodes of the capacitance element Cfe and the potential of the other of the pair of electrodes of the capacitance element Cfe. Also, as described above, the other of the pair of electrodes of the capacitance element Cfe is connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be controlled.

[0400] 26 , an example of a method for driving the memory cell 1480 will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitor Cfe is the difference (potential difference) between the potential of one of the pair of electrodes of the capacitor Cfe and the potential of the other of the pair of electrodes (wiring PL) of the capacitor Cfe. Furthermore, the transistor M9 is an n-channel transistor.

[0401] 27B is a timing chart showing an example of a method for driving the memory cell 1480. Fig. 27B shows an example of writing and reading binary digital data to the memory cell 1480. Specifically, Fig. 27B shows an example in which data "1" is written to the memory cell 1480 from time T01 to time T02, reading and rewriting are performed from time T03 to time T05, reading and writing data "0" to the memory cell 1480 from time T11 to time T13, reading and rewriting are performed from time T14 to time T16, and reading and writing data "1" to the memory cell 1480 from time T17 to time T19.

[0402] A reference potential Vref is supplied to the sense amplifier electrically connected to the wiring BL. In the read operation shown in Figure 27B, when the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0403] Between time T01 and time T02, the word line driver circuit applies a high potential to the wiring WL as a selection signal. This turns on transistor M9. Also, the potential of wiring BL is set to Vw. Because transistor M9 is on, the potential of one of the pair of electrodes of capacitance element Cfe becomes Vw. Furthermore, GND is applied to wiring PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to memory cell 1480. Therefore, the period from time T01 to time T02 can be said to be a period during which a write operation is performed.

[0404] Here, Vw is preferably equal to or greater than VSP, for example. Although GND is a ground potential in this specification, it is not necessarily the ground potential as long as the memory cell 1480 can be driven to satisfy the spirit of one embodiment of the present invention. For example, if the absolute values ​​of the first and second saturation polarization voltages are different and the absolute values ​​of the first and second coercive voltages are different, GND can be a potential other than ground.

[0405] Between time T02 and time T03, GND is applied to the wiring BL by the bit line driver circuit, and GND is applied to the wiring PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Between time T01 and time T02, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe can be made equal to or higher than VSP, and therefore, between time T02 and time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 66 shown in FIG. 27A. As a result, between time T02 and time T03, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe.

[0406] After applying GND to both the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal, thereby turning off the transistor M9. This completes the write operation, and data "1" is stored in the memory cell 1480. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or greater than the second coercive voltage -Vc.

[0407] Between time T03 and time T04, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on the transistor M9. Furthermore, the plate line driver circuit applies Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" between time T01 and time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. During polarization reversal, a current flows through the line BL, and the potential of the line BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in the memory cell 1480. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may also be higher than Vw, for example.

[0408] Since the above read is a destructive read, the data "1" held in memory cell 1480 is lost. Therefore, from time T04 to time T05, Vw is applied to the wiring BL by the bit line driver circuit, and GND is applied to the wiring PL by the plate line driver circuit. This rewrites the data "1" to memory cell 1480. Therefore, the period from time T04 to time T05 can be said to be the period during which the rewrite operation is performed.

[0409] From time T05 to time T11, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. Then, the word line driver circuit applies a low potential as a non-selection signal to the wiring WL. This completes the rewrite operation, and data "1" is held in the memory cell 1480.

[0410] Between time T11 and time T12, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Also, the plate line driver circuit applies a potential Vw to the wiring PL. Since data "1" is stored in the memory cell 1480, the potential of the wiring BL becomes higher than Vref, and the data "1" stored in the memory cell 1480 is read. Therefore, the period from time T11 to time T12 can be said to be a period during which a read operation is performed.

[0411] Between time T12 and time T13, the bit line driver circuit applies GND to the wiring BL. Since the transistor M9 is in the on state, the potential of one of the pair of electrodes of the capacitance element Cfe becomes GND. In addition, the plate line driver circuit applies a potential Vw to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." This allows data "0" to be written to the memory cell 1480. Therefore, the period from time T12 to time T13 can be said to be a period during which a write operation is performed.

[0412] From time T13 to time T14, GND is applied to the line BL by the bit line driver circuit, and GND is applied to the line PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe from time T12 to time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 65 shown in FIG. 27A from time T13 to time T14. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe from time T13 to time T14.

[0413] After applying GND to the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal, thereby turning off the transistor M9. This completes the write operation, and data "0" is stored in the memory cell 1480. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

[0414] Between time T14 and time T15, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on the transistor M9. The plate line driver circuit also applies a potential Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" between time T12 and time T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. As a result, the increase in the potential of the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Specifically, the potential of the line BL is equal to or lower than Vref. Therefore, the bit line driver circuit can read the data "0" stored in the memory cell 1480. Therefore, the period from time T14 to time T15 can be said to be a period during which a read operation is performed.

[0415] From time T15 to time T16, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies a potential Vw to the wiring PL, thereby rewriting data "0" to the memory cell 1480. Therefore, the period from time T15 to time T16 can be said to be a period during which a rewrite operation is performed.

[0416] Between time T16 and time T17, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. After that, the word line driver circuit applies a low potential as a non-selection signal to the wiring WL. This completes the rewrite operation, and data "0" is held in the memory cell 1480.

[0417] Between time T17 and time T18, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Furthermore, the plate line driver circuit applies a potential Vw to the wiring PL. Since data "0" is stored in the memory cell 1480, the potential of the wiring BL becomes lower than Vref, and the data "0" stored in the memory cell 1480 is read out. Therefore, the period from time T17 to time T18 can be considered a period during which a read operation is performed.

[0418] Between time T18 and time T19, the bit line driver circuit applies a potential Vw to the wiring BL. Because the transistor M9 is on, the potential of one electrode of the capacitance element Cfe becomes Vw. In addition, the plate line driver circuit applies a potential GND to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T18 to time T19 can be said to be the period during which the write operation is performed.

[0419] After time T19, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential to the line WL as a non-selection signal. This completes the write operation, and data "1" is stored in the memory cell 1480.

[0420] A semiconductor device using a ferroelectric layer for the capacitance element Cfe functions as a nonvolatile memory element that can retain written information even when the power supply is stopped.

[0421] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. A semiconductor device using a ferroelectric layer for the capacitance element Cfe does not require refresh operations, so power consumption can be reduced.

[0422] In this specification and the like, a memory element or a memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Therefore, a semiconductor device according to one embodiment of the present invention is both a ferroelectric memory and an FE memory. The FE memory has a capacitance of 1×10 １０ or more, preferably 1×10 １２ or more, more preferably 1×10 １５ Furthermore, the FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0423] Furthermore, in FE memory, there is a correlation between the remanent polarization 2Pr and data retention capacity, and as the remanent polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remanent polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of one day or more, preferably ten days or more, more preferably one year or more, and even more preferably ten years or more in a temperature environment of 150°C or 200°C.

[0424] The FE memory can also be applied to cache memories and registers of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc. By combining the FE memory with the cache memory and registers of a CPU, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining the FE memory with the cache memory and registers of a GPU, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

[0425] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0426] 28 , a memory device according to one embodiment of the present invention includes a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor. Since the off-state current of an OS transistor is extremely small, a memory device including an OS transistor has excellent data retention characteristics and can function as a nonvolatile memory.

[0427] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 28 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 28, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0428] In FIG. 28 , from the top layer of the triangle, there are shown memories integrated as registers in arithmetic processing units such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an NPU (Neural Processing Unit), cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs (Dynamic Random Access Memory), and storage memories such as 3D NANDs and hard disks (also called HDDs: Hard Disk Drives).

[0429] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0430] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0431] The memory device of one embodiment of the present invention can be used as a DRAM.

[0432] 28 illustrates only up to the L3 cache as a cache memory, but the present invention is not limited to this. For example, the storage device of one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0433] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0434] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0435] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0436] The memory device of one embodiment of the present invention can be monolithically structured with peripheral circuits by using OS transistors. Furthermore, the use of OS transistors allows monolithic stacking with peripheral circuits. Therefore, this has advantages in terms of data access with peripheral circuits. Furthermore, the degree of integration can be increased by stacking with peripheral circuits. Furthermore, the use of OS transistors enables the memory device of one embodiment of the present invention to retain data for a long period of time. Therefore, when used as a DRAM, the frequency of refresh can be reduced.

[0437] Furthermore, the storage device of one embodiment of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, data can be sufficiently stored even if the capacitance value of a capacitor is small. Therefore, for example, by using the storage device of one embodiment of the present invention as a DRAM, the operation speed of the DRAM, for example, the speed of rewriting, can be increased in some cases.

[0438] Furthermore, since the memory device of one embodiment of the present invention includes a capacitor including a ferroelectric material, data can be retained for a long time. Therefore, when the memory device is used as a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0439] The storage device of one embodiment of the present invention can be used for the Target2 region and the Target1 region shown in Figure 28. In particular, the storage device can be suitably used for the Target1 region.

[0440] 28, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC mentioned above.

[0441] By replacing the storage device of one embodiment of the present invention with a DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth, and even more preferably one-thousandth or less, compared to a configuration using a DRAM. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target 1.

[0442] Furthermore, the storage device of one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying the storage device of one embodiment of the present invention to Target1_1, the reliability of the storage device can be improved. Furthermore, the degree of integration of the storage device can be increased. Furthermore, the power consumption of the storage device can be reduced.

[0443] Furthermore, the storage device of one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and therefore can be suitably used for Target1_2, which is rewritten more frequently than Target1. By applying the storage device of one embodiment of the present invention to Target1_2, the calculation efficiency of the storage device can be improved and power consumption can be reduced.

[0444] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM or an FeRAM (including the semiconductor device of one embodiment of the present invention) is stacked on an arithmetic processing device such as a CPU, a GPU, or an NPU. A configuration in which an arithmetic processing device and a storage device are stacked is called a monolithic stack. By configuring the arithmetic processing device and the storage device as a monolithic stack, for example, the power consumption required for data access between the arithmetic processing device and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like to which such a configuration is applied throughout the world, global warming can be suppressed.

[0445] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0446] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0447] 29A and 29B show an example of a chip 1200 on which a semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0448] As shown in FIG. 29A , the chip 1200 includes a CPU 1211 , a GPU 1212 , one or more analog arithmetic units 1213 , one or more memory controllers 1214 , one or more interfaces 1215 , and one or more network circuits 1216 .

[0449] 29B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the package substrate 1201 opposite the first surface, which is connected to a motherboard 1203.

[0450] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 and the flash memory 1222 can be replaced with the semiconductor devices described in the first embodiment.

[0451] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The semiconductor device described above may be used for this memory. The GPU 1212 is suitable for parallel calculation of a large amount of data and may be used for image processing or multiply-and-accumulate operations.

[0452] Furthermore, since the CPU 1211 and GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0453] The analog calculation unit 1213 has one or both of an AD (analog-digital) conversion circuit and a DA (digital-analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0454] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0455] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0456] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0457] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0458] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204 .

[0459] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit included in the GPU 1212 enables calculations such as deep neural networks (DNNs), which are AI models. Representative examples of AI models include convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0460] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0461] Embodiment 6 In this embodiment, an application example of a semiconductor device using a storage device according to one embodiment of the present invention will be described. The semiconductor device described in the above embodiment can be applied to various removable storage devices such as a memory card (e.g., an SD card), a USB memory, and an SSD (Solid State Drive) as a cache memory or a main memory. Some configuration examples of removable storage devices are schematically shown in FIGS. 30A to 30E . The semiconductor device according to one embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

[0462] 30A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1105 or the like.

[0463] FIG. 30B is a schematic diagram of the appearance of an SD card, and FIG. 30C is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1114 or the like.

[0464] FIG. 30D is a schematic diagram of the appearance of an SSD, and FIG. 30E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. By providing a memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1154 or the like.

[0465] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0466] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0467] [Electronic Component] Fig. 31A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 31A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that in Fig. 31A, some parts of electronic component 700 are omitted in order to show the inside of electronic component 700.

[0468] The substrate 701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0469] Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered with mold 711, and another portion of lead frame 712 is exposed to the outside of mold 711. In particular, lead frame 712 exposed to the outside of mold 711 functions as, for example, a terminal for mounting electronic component 700 on a printed circuit board.

[0470] Within mold 711, electrode pads 713 are provided on lead frame 712, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on a printed circuit board, for example, by contacting lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0471] Next, the semiconductor device 710 will be described. For example, as shown in FIG. 31B , the semiconductor device 710 has a drive circuit layer 715 and a memory layer 716. The memory layer 716 can be configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. Configurations other than the monolithic stacked configuration include a configuration in which a plurality of memory layers 716 are stacked using through-electrode technology (e.g., TSV (Through Silicon Via)) and Cu-Cu direct bonding technology. By stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

[0472] Furthermore, the semiconductor device 710 has a configuration in which multiple memory cell arrays are stacked, which can improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange.

[0473] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0474] Next, Fig. 31C shows a modified example of electronic component 700. Electronic component 700A shown in Fig. 31C differs from electronic component 700 in that it does not use lead frame 712, but has electrodes 733 provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

[0475] 31C shows an example in which electrodes 733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, substrate 701 is provided with through-hole vias, and conductive layers 732 that function as wiring are provided in these vias. Electrode pads 713 are provided above conductive layer 732 on substrate 701 so as to be in contact with them, and electrodes 733 are provided below conductive layer 732 below substrate 701 so as to be in contact with them.

[0476] Furthermore, the electrodes 733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0477] Furthermore, electronic component 700A can be mounted on other substrates using various mounting methods other than BGA and PGA, such as staggered pin grid array (SPGA), land grid array (LGA), quad flat package (QFP), quad flat J-leaded package (QFJ), and quad flat non-leaded package (QFN).

[0478] The electronic component of one embodiment of the present invention may be in the form of a system in package (SiP) or a multi-chip module (MCM). For example, an electronic component 700C illustrated in FIG. 31D includes an interposer 731 over a package substrate 734 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 over the interposer 731.

[0479] 31D shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0480] The package substrate 734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 701. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0481] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0482] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0483] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0484] Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 700C so that the heat sink overlaps the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[0485] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 32A . The electronic device 6500 shown in FIG. 32A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6500 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in, for example, the display portion 6502, the control device 6509, or the like.

[0486] 32B is an information terminal that can be used as a notebook computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more components selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6600 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in the display portion 6615, the control device 6616, or the like.

[0487] The semiconductor device of one embodiment of the present invention is preferably provided in the electronic devices 6500 and 6600 because power consumption can be reduced.

[0488] [Mainframe] Next, Fig. 32C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 32C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0489] The computer 5620 can have the configuration shown in the perspective view in Fig. 32D, for example. In Fig. 32D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0490] PC card 5621 shown in Figure 32E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 32E illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, please refer to the descriptions of semiconductor devices 5626, 5627, and 5628 described below.

[0491] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0492] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0493] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0494] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 700 can be used as the semiconductor device 5627.

[0495] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wirings of the board 5622. For example, the semiconductor device 5628 can be a memory device which is a semiconductor device of one embodiment of the present invention. For example, the electronic component 700 described above can be used for the semiconductor device 5628.

[0496] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0497] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0498] Fig. 33A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 33A, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0499] Although not shown in FIG. 33A, the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit.

[0500] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0501] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0502] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0503] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably formed using a semiconductor device which is one embodiment of the present invention.

[0504] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0505] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0506] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0507] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0508] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0509] Fig. 33B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 33B has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0510] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0511] The storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0512] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0513] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0514] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0515] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0516] In this example, a pillar-type capacitor having a ferroelectric substance was fabricated, and the crystal structure was analyzed by electron diffraction. The results will be described.

[0517] FIG. 34 shows a schematic diagram of Sample 1 according to this example. The pillar-type capacitor of Sample 1 includes a substrate 550, an insulator 540, a first conductor, a ferroelectric layer 520, and a second conductor. Here, the first conductor has a layered structure of conductors 510 and 515, and the second conductor has a layered structure of conductors 530 and 535. As shown in FIG. 34 , the insulator 540 is provided on the substrate 550 and has a substantially circular opening. The first conductor is provided in the opening of the insulator 540 and has a cylindrical shape. The ferroelectric layer 520 is provided so as to cover the first conductor and the insulator 540. The second conductor is provided so as to cover the ferroelectric layer 520. Furthermore, in Sample 1, multiple pillar-type capacitors were fabricated on the substrate surface.

[0518] A p-type single crystal silicon substrate was prepared as the substrate 550. The insulator 540 was formed by CVD using TEOS (tetraethyl orthosilicate) gas. A substantially circular opening with a diameter of 140 nm was formed in the insulator 540.

[0519] The conductor 510 was made of titanium nitride with a thickness of 10 nm and was deposited using a CVD method. The conductor 515 was made of cylindrical tungsten and was deposited using a CVD method. The substrate temperature was set to 340°C when the conductor 510 was deposited, and to 345°C when the conductor 515 was deposited. The first conductor, which was a stack of the conductors 510 and 515, had a cylindrical structure with a height of 550 nm and a diameter of 140 nm. After the formation of the first conductor, the insulator 540 was etched back to a thickness of 100 nm.

[0520] The ferroelectric layer 520 is a hafnium zirconium oxide having a thickness of 10 nm, and is formed so that the ratio of the number of Hf and Zr atoms is approximately 1:1. The ferroelectric layer 520 is formed by a thermal ALD method. The ferroelectric layer 520 is formed using hafnium chloride and zirconium chloride as precursors and H as an oxidizing agent. ２ O was used and the substrate temperature was set to 300°C.

[0521] The conductor 530 is made of titanium nitride and has a thickness of 5 nm, and is deposited by CVD. The conductor 535 is made of tungsten and has a thickness of 50 nm, and is deposited by CVD. The substrate temperature was set to 400° C. when depositing the conductors 530 and 535. The second conductor is a stacked film of the conductor 530 and the conductor 535 on the conductor 530. Although not shown in FIG. 34 , in Sample 1, a silicon nitride film and a silicon oxide film were deposited to cover the second conductor.

[0522] Planar TEM images were taken and crystalline phase maps were prepared for the two pillar-type capacitors in Sample 1 fabricated as described above. Planar TEM images of the respective pillar-type capacitors are shown in Figures 35A and 36A, and crystalline phase maps are shown in Figures 35B and 36B.

[0523] The planar TEM images were taken using a JEOL "JEM-ARM200F" at an acceleration voltage of 200 kV. Although distortions can be seen in the shapes in both Figures 35A and 36A, the conductor 515, the conductor 510, the ferroelectric layer 520, the conductor 530, and the conductor 535 are arranged in a substantially concentric shape.

[0524] The crystalline phase map was created as follows. First, a diffraction pattern was obtained at each point of the ferroelectric layer 520 of Sample 1 using electron diffraction (ED). The electron diffraction measurement was performed using a JEOL "JEM-ARM200F" at an acceleration voltage of 200 kV. The measurement was performed by scanning an electron beam with a beam diameter of approximately 3 nm in 1 nm increments in a measurement area of ​​250 nm x 250 nm. Next, the diffraction pattern at each point was classified into a cubic system (Cubic), a tetragonal system (Tetragonal), an orthorhombic system with space group Pbca, and a space group Pca2. １ The orthorhombic part of the space group Pbca is an antiferroelectric (anti-FE (Ferroelectric)), and the space group Pca2 １ The orthorhombic portion of the ferroelectric layer 520 is a ferroelectric (FE). Figures 35B and 36B are crystalline phase maps created in the regions corresponding to the planar TEM images of the ferroelectric layer 520 in Figures 35A and 36A, and are color-coded according to the crystalline structures shown in the legends.

[0525] For the entire crystal structure identified in Figures 35B and 36B, the space group Pca2 exhibits a ferroelectric phase. １ The proportion of the orthorhombic phase in the film was 23.0%. This proportion of the region exhibiting the ferroelectric phase was significantly larger than that of a Hall-type capacitor of the same order of magnitude.

[0526] In this way, by using the ferroelectric layer for a pillar-type capacitor, the proportion of the ferroelectric phase can be increased.Furthermore, by depositing a titanium nitride film while heating the substrate after depositing the ferroelectric layer, the proportion of the ferroelectric phase can be increased.

[0527] 10: transistor, 10a: transistor, 11: insulating layer, 15: memory cell, 20: opening, 21: semiconductor layer, 21f: semiconductor film, 22: insulating layer, 23: conductive layer, 23f: conductive film, 24: conductive layer, 24a: conductive film, 24af: conductive film, 24b: conductive film, 24bf: conductive film, 25: conductive layer, 25a: conductive film, 25b: conductive film, 26: conductive layer, 27: plug, 30: capacitor, 41: insulating layer, 42: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 46a: insulating layer, 46b: insulating layer, 46f: insulating film, 47: insulating layer, 48: insulating layer, 50: semiconductor device device, 50a: memory array, 50b: driver circuit, 51: conductive layer, 51A: conductive layer, 51a: conductive layer, 51b: conductive layer, 51f: conductive film, 52: insulating layer, 52a: insulating layer, 52b: insulating layer, 52f: insulating film, 53: conductive layer, 53A: conductive layer, 53a: conductive layer, 53b: conductive layer, 53f: conductive film, 61: insulating layer, 62: insulating layer, 63: insulating layer, 64: insulating layer, 64f: insulating film, 65: curve, 66: curve, 70: plug, 71: conductive layer, 75: insulating layer, 80: layer, 81: conductive layer, 81a: conductive layer, 81b: conductive layer, 82: plug, 83: plug, 84: conductive layer, 5: plug, 86: insulating layer, 87: insulating layer, 87a: insulating layer, 87b: insulating layer, 88: insulating layer, 89: plug, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 96: insulating layer, 96a: insulating layer, 96b: insulating layer, 97: insulating layer, 98: element isolation layer, 510: conductor, 515: conductor, 520: ferroelectric layer, 530: conductor, 535: conductor, 540: insulator, 550: substrate, 700: electronic component, 700A: electronic component, 700C: electronic component, 701: substrate, 710: semiconductor device 711: mold, 712: lead frame, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 731: interposer, 732: conductive layer, 733: electrode, 734: package substrate, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip,1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog calculation unit, 1214: memory controller, 1215: interface, 121 6: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device, 1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory cell array, 1480: memory cell, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal , 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: key board, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device,

Claims

a first capacitance element and a first transistor on the first capacitance element; the first capacitance element has a first conductive layer, a second conductive layer, and a first insulating layer; the first transistor has a semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a second insulating layer, and a third insulating layer; In a cross-sectional view, a height of the first conductive layer is greater than a width of the first conductive layer; the first insulating layer is in contact with a side surface of the first conductive layer; the second conductive layer is disposed opposite a side surface of the first conductive layer with the first insulating layer interposed therebetween; the first insulating layer includes a material exhibiting ferroelectricity; the second insulating layer is disposed on the third conductive layer; the fourth conductive layer is disposed on the second insulating layer; the second insulating layer and the fourth conductive layer have openings at positions where they overlap with the third conductive layer; the semiconductor layer contacts an upper surface of the third conductive layer and a side surface of the fourth conductive layer within the opening; the third insulating layer is located in the opening and on the semiconductor layer; the fifth conductive layer is located in the opening and on the third insulating layer; the third conductive layer is connected to the first conductive layer; Semiconductor device. 　 In claim 1, a plurality of the first capacitance elements and a plurality of the first transistors arranged in a matrix; the second conductive layer, the fifth conductive layer, and the opening are provided to extend in a first direction; a distance between the first conductive layers provided adjacent to each other in the first direction is shorter than a distance between the first conductive layers provided adjacent to each other in the second direction; Semiconductor device. 　 In claim 1, one or both of the first conductive layer and the second conductive layer has a thermal expansion coefficient greater than that of the first insulating layer; Semiconductor device. 　 In claim 1, the first insulating layer has a region exhibiting a ferroelectric phase of 20% or more; Semiconductor device. 　 In claim 1, the first insulating layer comprises hafnium zirconium oxide; Semiconductor device. 　 In claim 5, one or both of the first conductive layer and the second conductive layer comprises titanium nitride; Semiconductor device. 　 In claim 1, a lower surface of the third conductive layer contacting an upper surface of the first conductive layer; Semiconductor device. 　 In claim 7, the third conductive layer includes a first layer, a second layer on the first layer, and a third layer on the second layer; the first layer comprises titanium nitride; the second layer comprises tungsten; the third layer comprises indium tin oxide; Semiconductor device. 　 In claim 1, the first insulating layer and the second conductive layer do not overlap a top surface of the first conductive layer; Semiconductor device. 　 In claim 9, an upper end of the first insulating layer and an upper end of the second conductive layer are higher than an upper end of the first conductive layer; Semiconductor device. 　 In claim 1, The semiconductor layer comprises a metal oxide. Semiconductor device. 　 In claim 1, the semiconductor layer comprises indium oxide; Semiconductor device. 　 In any one of claims 1 to 12, a second transistor and a second capacitive element on the second transistor; the channel of the second transistor is formed in a silicon substrate; the second capacitive element is disposed below the first capacitive element; the second capacitance element has a sixth conductive layer, a seventh conductive layer, and a fourth insulating layer; In a cross-sectional view, a height of the sixth conductive layer is greater than a width of the sixth conductive layer; the fourth insulating layer contacts a side surface of the sixth conductive layer, the seventh conductive layer is disposed opposite a side surface of the sixth conductive layer with the fourth insulating layer interposed therebetween; the fourth insulating layer contains a material exhibiting ferroelectricity; Semiconductor device.

Images