Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor wherein even in the case of a multi-terminal multilayer ceramic capacitor, the capacitance of the multilayer ceramic capacitor can be increased without increasing the size of the multilayer ceramic capacitor. A multilayer ceramic capacitor 1 having three or more external electrodes, wherein a first opposing portion EA has a first region EA1, a second region EA2, and a first central region EA0 having higher coverage than the first region EA1 and the second region EA2, and a second opposing portion EB has a third region EB1, a fourth region EB2, and a second central region EB0 having higher coverage than the third region EB1 and the fourth region EB2.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multi-terminal multilayer ceramic capacitors having three or more external electrodes have been known. For example, multi-terminal multilayer ceramic capacitors have low equivalent series inductance and excellent high-frequency characteristics, making them suitable for power supply decoupling in high-speed electronic devices (see Patent Document 1).

[0003] JP 2016-127262 A

[0004] Even in such multi-terminal type laminated ceramic capacitors, there are cases where an improvement in capacitance is required.

[0005] An object of the present invention is to provide a multi-terminal multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0006] The multilayer ceramic capacitor of the present invention has a laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having first and second main surfaces opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction perpendicular to the lamination direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the lamination direction and the length direction, and three or more external electrodes, wherein the plurality of internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers, the first internal electrode layer having a first opposing portion opposing the second internal electrode layer via the dielectric layer, a first lead portion extending from the first opposing portion and drawn to a first end face of the laminate, and a second lead portion extending from the first opposing portion and drawn to a second end face of the laminate, the three or more external electrodes include a first external electrode connected to the first extension portion, a second external electrode connected to the second extension portion, and a third external electrode connected to the third extension portion; the first opposing portion includes a first region which is a region on the first end face side, a second region which is a region on the second end face side, and a first central region which is a region located between the first region and the second region and has higher coverage than the coverage of the first region and the second region; and the second opposing portion includes a third region which is a region on the first end face side, a fourth region which is a region on the second end face side, and a second central region which is a region located between the third region and the fourth region and has higher coverage than the coverage of the third region and the fourth region.

[0007] According to the present invention, it is possible to provide a multi-terminal multi-layer ceramic capacitor that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0008] 4A is a perspective view of the appearance of the multilayer ceramic capacitor according to the first embodiment. FIG. 4A is an arrow view of the multilayer ceramic capacitor shown in FIG. 1 when viewed from the first side surface side along the direction of arrow II. FIG. 4B is an arrow view of the multilayer ceramic capacitor shown in FIG. 2 when viewed from the first main surface side along the direction of arrow III. FIG. 4A is a IV-IV cross-sectional view of FIG. 1, illustrating a schematic configuration of a laminate. FIG. 4B is an IV-IV cross-sectional view of FIG. 1, illustrating details of internal electrode layers of the laminate. FIG. 4A is a V-V cross-sectional view of FIG. 4A, illustrating a schematic configuration of a laminate. FIG. 4A is a V-V cross-sectional view of FIG. 4A, mainly illustrating the shape inside the laminate. FIG. 4A is a V-V cross-sectional view of FIG. 4A, mainly illustrating the relationship between thicknesses inside the laminate. FIG. 4A is a VIA-VIA cross-sectional view of FIG. 4A, illustrating a cross-sectional view along the first internal electrode layer. FIG. 4B is a VIB-VIB cross-sectional view of FIG. 4A, illustrating a cross-sectional view along the second internal electrode layer. FIG. 4C is a diagram illustrating an example of an enlarged image of an exposed internal layer cross-section by SEM. FIG. 4D is a schematic view showing a cross-section of a dielectric sheet when a conductive paste P1 is printed. 9 is a schematic diagram showing a cross section of the dielectric sheet when the conductive paste P2 is printed on the dielectric sheet of FIG. 8. FIG. 9 is a schematic diagram showing a part of a laminate sheet in which a portion that will become a first main surface side outer layer portion and a portion that will become a second main surface side outer layer portion are formed above and below a portion that will become an inner layer portion. FIG. 10 is a perspective view of the appearance of a multilayer ceramic capacitor according to a second embodiment. FIG. 11 is a diagram corresponding to FIG. 5A in the multilayer ceramic capacitor according to the second embodiment. FIG. 12 is a diagram corresponding to FIG. 6A in the multilayer ceramic capacitor according to the second embodiment. FIG. 13 is a diagram corresponding to FIG. 6B in the multilayer ceramic capacitor according to the second embodiment.

[0009] A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of the present disclosure will be described with reference to the drawings, using FIGS. 1 to 6B. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. FIG. 2 is an arrow view of the multilayer ceramic capacitor 1 shown in FIG. 1 , viewed from a first side surface along the direction of arrow II. FIG. 3 is an arrow view of the multilayer ceramic capacitor 1 shown in FIG. 2 , viewed from a first main surface along the direction of arrow III. FIG. 4A is a cross-sectional view taken along line IV-IV in FIG. 1 , illustrating the schematic configuration of the laminate. FIG. 4B is a cross-sectional view taken along line IV-IV in FIG. 1 , illustrating the details of the internal electrode layers of the laminate.

[0010] Fig. 5A is a V-V cross-sectional view of Fig. 4A and is a view for explaining the schematic configuration of the laminate. Fig. 5B is a V-V cross-sectional view of Fig. 4A and is a view for mainly explaining the shape inside the laminate. Fig. 5C is a V-V cross-sectional view of Fig. 4A and is a view for mainly explaining the relationship between thicknesses inside the laminate. Fig. 6A is a VIA-VIA cross-sectional view of Fig. 4A and is a cross-sectional view along the first internal electrode layer. Fig. 6B is a VIB-VIB cross-sectional view of Fig. 4A and is a cross-sectional view along the second internal electrode layer.

[0011] The drawings may be drawn in a simplified schematic form to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings, or the number of components may be reduced.

[0012] For example, the number of internal electrode layers described in Figures 4A to 5C is 10 for the sake of convenience of explanation, but this does not indicate the actual number of internal electrode layers 30. Note that the terms used in the present invention that specify the shape and geometric conditions and their degrees, such as terms such as "parallel," "orthogonal," and "same," and values ​​of length and angle, are not bound by strict meanings but are interpreted to include a range within which similar functions can be expected.

[0013] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and three or more external electrodes 40. The multilayer ceramic capacitor 1 according to the embodiment includes the laminate 10 having a substantially rectangular parallelepiped shape and four external electrodes 40: a pair of external electrodes arranged spaced apart at both ends of the laminate 10 in the length direction L, and a pair of external electrodes arranged spaced apart at both ends of the laminate 10 in the width direction W.

[0014] In Fig. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In Fig. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In Fig. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L.

[0015] The three or more external electrodes 40 are respectively arranged at one end and the other end of the laminate 10 in the length direction L and at least one end of the laminate 10 in the width direction W. The external electrodes 40 in the multilayer ceramic capacitor 1 according to this embodiment are respectively arranged at one end and the other end of the laminate 10 in the length direction L and one end and the other end of the laminate 10 in the width direction W. Details of the external electrodes 40 will be described later.

[0016] An XYZ Cartesian coordinate system is shown in Figures 1 to 6B and Figures 11 to 13B described below. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross sections shown in Figures 4A and 4B are also referred to as LT cross sections. The cross sections shown in Figures 5A to 5C and 12 are also referred to as WT cross sections. The cross sections shown in Figures 6A, 6B, 13A and 13B are also referred to as LW cross sections.

[0017] As shown in Figures 1 to 6B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T and the length direction L.

[0018] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0019] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0020] As shown in Figures 4A to 5C, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0021] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers alternately stacked in the stacking direction T. The internal layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2 in the stacking direction T. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0022] The thickness of the inner layer portion 11 in the stacking direction T varies along the length direction L and the width direction W depending on the shape of the internal electrode layer 30 located closest to the first main surface TS1 and the shape of the internal electrode layer 30 located closest to the second main surface TS2.

[0023] The dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as BaTiO as the main component. The dielectric material may also be a material containing these main components to which subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added. The dielectric material may be a material containing BaTiO as the main component. ３ It is particularly preferred that the material contains:

[0024] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0025] The internal electrode layers 30 include a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with the dielectric layer 20 sandwiched therebetween.

[0026] The first internal electrode layer 31 is disposed on the plurality of dielectric layers 20 and extends to the first end face LS1 and the second end face LS2. The second internal electrode layer 32 is disposed on the plurality of dielectric layers 20 and extends to the first side face WS1 and the second side face WS2. The second internal electrode layer 32 may extend to only either the first side face WS1 or the second side face WS2, rather than to both the first side face WS1 and the second side face WS2. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately disposed in the stacking direction T of the laminate 10 with the dielectric layers 20 interposed therebetween.

[0027] In the following, when there is no need to distinguish between the first internal electrode layer 31 and the second internal electrode layer 32, the first internal electrode layer 31 and the second internal electrode layer 32 may be collectively referred to as the internal electrode layer 30.

[0028] 6A , the first internal electrode layer 31 has a first opposing portion EA, a first lead portion D1, and a second lead portion D2. The first opposing portion EA is a region facing the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. In other words, the first opposing portion EA faces the second internal electrode layer 32 via the dielectric layer 20. The first lead portion D1 is a portion extending from the first opposing portion EA and drawn to the first end face LS1 of the laminate 10, and is exposed at the first end face LS1. The second lead portion D2 is a portion extending from the first opposing portion EA and drawn to the second end face LS2 of the laminate 10, and is exposed at the second end face LS2.

[0029] 6A , the second internal electrode layer 32 has a second opposing portion EB, a third lead portion D3, and a fourth lead portion D4. The second opposing portion EB is a region facing the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. In other words, the second opposing portion EB faces the first internal electrode layer 31 via the dielectric layer 20. The third lead portion D3 is a portion extending from the second opposing portion EB and drawn to the first side surface WS1 of the laminate 10, and is exposed at the first side surface WS1. The fourth lead portion D4 is a portion extending from the second opposing portion EB and drawn to the second side surface WS2 of the laminate 10, and is exposed at the second side surface WS2.

[0030] In this embodiment, the first opposing portion EA and the second opposing portion EB face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0031] The shapes of the first opposing portion EA and the second opposing portion EB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or may be oblique. The shapes of the first lead portion D1, the second lead portion D2, the third lead portion D3, and the fourth lead portion D4 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or may be oblique.

[0032] The width direction W dimensions of the first opposing portion EA, the first lead portion D1, and the second lead portion D2 may be the same, or one of the dimensions may be smaller. The length direction L dimensions of the second opposing portion EB, the third lead portion D3, and the fourth lead portion D4 may be the same, or one of the dimensions may be smaller. In this embodiment, the width direction W dimensions of the first lead portion D1 and the width direction W dimensions of the second lead portion D2 are smaller than the width direction W dimension of the first opposing portion EA. The length direction L dimensions of the third lead portion D3 and the fourth lead portion D4 are smaller than the length direction L dimension of the second opposing portion EB.

[0033] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0034] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 1000 or less.

[0035] As shown in Figures 4A to 5C, the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0036] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where a first counter portion EA of the first internal electrode layer 31 and a second counter portion EB of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Figures 6A and 6B show the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0037] The laminate 10 has a side surface outer layer portion. The side surface outer layer portion has a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion that includes the dielectric layer 20 and the third lead portion D3 located between the counter electrode portion 11E and the first side surface WS1. In other words, the first side surface outer layer portion WG1 is an assembly of the portions of the multiple dielectric layers 20 on the first side surface WS1 side and multiple third lead portions D3.

[0038] The second side surface side outer layer portion WG2 is a portion that includes the dielectric layer 20 and the fourth lead portion D4 located between the counter electrode portion 11E and the second side surface WS2. In other words, the second side surface side outer layer portion WG2 is an aggregate of the portions of the multiple dielectric layers 20 on the second side surface WS2 side and multiple fourth lead portions D4. Figures 5A to 6B show the ranges in the width direction W of the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2. The side surface side outer layer portion is also referred to as a W gap or a side gap.

[0039] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2.

[0040] The first end surface side outer layer portion LG1 is a portion located between the counter electrode portion 11E and the first end surface LS1, and includes the dielectric layer 20 and the first lead portion D1. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the plurality of dielectric layers 20 on the first end surface LS1 side and the plurality of first lead portions D1.

[0041] The second end surface side outer layer portion LG2 is a portion located between the counter electrode portion 11E and the second end surface LS2, including the dielectric layer 20 and the second lead portion D2. That is, the second end surface side outer layer portion LG2 is an aggregate of the portions of the multiple dielectric layers 20 on the second end surface LS2 side and the multiple second lead portions D2. Figures 4A, 4B, 6A, and 6B show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portion is also referred to as an L gap or end gap.

[0042] As shown in Figures 1 to 4B, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, a second external electrode 40B arranged on the second end face LS2 side of the laminate 10, a third external electrode 40C arranged on the first side face WS1 side of the laminate 10, and a fourth external electrode 40D arranged on the second side face WS2 side of the laminate 10.

[0043] The first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D have the same basic layer structure. Hereinafter, when it is not necessary to distinguish between the first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D, the first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D may be collectively referred to as the external electrodes 40.

[0044] The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetrical with respect to a WT cross section at the center in the length direction L of the multilayer ceramic capacitor 1. The third external electrode 40C and the fourth external electrode 40D have shapes that are approximately plane-symmetrical with respect to an LT cross section at the center in the width direction W of the multilayer ceramic capacitor 1.

[0045] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. This allows the first external electrode 40A to be in electrical contact with and connected to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0046] In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0047] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with and connected to the second lead portions D2 of each of the first internal electrode layers 31 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the first internal electrode layers 31. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0048] In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0049] The third external electrode 40C is disposed on the first side surface WS1. The third external electrode 40C is in contact with and connected to the third lead portions D3 of each of the second internal electrode layers 32 exposed on the first side surface WS1. This electrically connects the third external electrode 40C to the second internal electrode layers 32. The third external electrode 40C may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2. In this embodiment, the third external electrode 40C is formed on the first main surface TS1 and a portion of the second main surface TS2.

[0050] The fourth external electrode 40D is disposed on the second side surface WS2. The fourth external electrode 40D is in contact with and connected to the fourth lead portions D4 of each of the second internal electrode layers 32 exposed on the second side surface WS2. This electrically connects the fourth external electrode 40D to the second internal electrode layers 32. The fourth external electrode 40D may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2. In this embodiment, the fourth external electrode 40D is formed on the first main surface TS1 and a portion of the second main surface TS2.

[0051] As described above, in the laminate 10, the first opposing portion EA of the first internal electrode layer 31 and the second opposing portion EB of the second internal electrode layer 32 face each other via the dielectric layer 20, thereby forming a capacitance. Therefore, capacitor characteristics are exhibited between the first external electrode 40A and the second external electrode 40B to which the first internal electrode layer 31 is connected, and the third external electrode 40C and the fourth external electrode 40D to which the second internal electrode layer 32 is connected. Note that if the second internal electrode layer 32 is extended only to the first side surface WS1, the fourth external electrode 40D may not be provided.

[0052] 4A, 4B, 6A, and 6B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0053] 5A, 5B, 5C, 6A, and 6B, the third external electrode 40C has a third base electrode layer 50C and a third plating layer 60C disposed on the third base electrode layer 50C. The fourth external electrode 40D has a fourth base electrode layer 50D and a fourth plating layer 60D disposed on the fourth base electrode layer 50D.

[0054] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0055] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions D2 of each of the first internal electrode layers 31 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0056] The third base electrode layer 50C is disposed on the first side surface WS1. The third base electrode layer 50C is in contact with the third lead portions D3 of the plurality of second internal electrode layers 32 exposed on the first side surface WS1. In this embodiment, the third base electrode layer 50C is formed to extend from the first side surface WS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0057] The fourth base electrode layer 50D is disposed on the second side surface WS2. The fourth base electrode layer 50D is in contact with the fourth lead portions D4 of each of the plurality of second internal electrode layers 32 exposed at the second side surface WS2. In this embodiment, the fourth base electrode layer 50D is formed to extend from the second side surface WS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0058] The first underlying electrode layer 50A, the second underlying electrode layer 50B, the third underlying electrode layer 50C and the fourth underlying electrode layer 50D each include at least one selected from a baked layer, a thin film layer and the like.

[0059] In this embodiment, the first base electrode layer 50A, the second base electrode layer 50B, the third base electrode layer 50C, and the fourth base electrode layer 50D are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both.

[0060] The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. For example, the ceramic component may be BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0061] The baked layer is formed by, for example, applying and baking a conductive paste containing glass and metal to the laminate 10. The baked layer can be formed by simultaneously firing the unfired laminated chip, which is the material for the laminate 10 having a plurality of internal electrodes and dielectric layers, with the conductive paste applied to the laminated chip. Alternatively, the baked layer can be formed by first firing the laminated chip to obtain the laminate 10, and then applying and baking the conductive paste to the laminate 10.

[0062] In the above-described configuration, the baked layer is preferably formed by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the added ceramic material. The baked layer may be a multi-layered layer.

[0063] The thickness of the first base electrode layer 50A located on the first end surface LS1 in the longitudinal direction L is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0064] The thickness corresponding to the length direction L of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0065] The thickness corresponding to the width direction W of the third base electrode layer 50C located on the first side surface WS1 is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the stacking direction T and length direction L of the third base electrode layer 50C.

[0066] The thickness corresponding to the width direction W of the fourth base electrode layer 50D located on the second side surface WS2 is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the stacking direction T and length direction L of the fourth base electrode layer 50D.

[0067] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A provided in this portion, corresponding to the stacking direction T, is, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this portion.

[0068] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the first base electrode layer 50A provided in this portion be, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and stacking direction T of the first base electrode layer 50A provided in this portion.

[0069] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B provided on this portion, corresponding to the stacking direction T, is, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0070] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the second base electrode layer 50B provided in this portion be, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 50B provided in this portion.

[0071] When the third base electrode layer 50C is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the third base electrode layer 50C provided in this portion, corresponding to the stacking direction T, is preferably, for example, approximately 3 μm or more and 25 μm or less, at the center in the length direction L and width direction W of the first base electrode layer 50A provided in this portion.

[0072] When a fourth base electrode layer 50D is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the fourth base electrode layer 50D provided in this portion, corresponding to the stacking direction T, is, for example, approximately 3 μm or more and 25 μm or less at the center in the length direction L and width direction W of the first base electrode layer 50A provided in this portion.

[0073] In this embodiment, the first base electrode layer 50A, the second base electrode layer 50B, the third base electrode layer 50C, and the fourth base electrode layer 50D may be thin film layers. The thin film layers are layers on which metal particles are deposited.

[0074] When the first base electrode layer 50A, the second base electrode layer 50B, the third base electrode layer 50C, and the fourth base electrode layer 50D are formed as thin film layers, they are preferably formed by a thin film formation method such as a sputtering method or a vapor deposition method. Here, sputtered electrodes formed by a sputtering method will be described.

[0075] In this embodiment, the first base electrode layer 50A is composed of a first thin film layer formed by a sputtering electrode. The second base electrode layer 50B is composed of a second thin film layer formed by a sputtering electrode. The third base electrode layer 50C is composed of a third thin film layer formed by a sputtering electrode. The fourth base electrode layer 50D is composed of a fourth thin film layer formed by a sputtering electrode.

[0076] When forming the base electrode layer using a sputtered electrode, it is preferable to form the sputtered electrode directly on a portion of at least one of the first main surface TS1 and the second main surface TS2 of the laminate 10. In this embodiment, the first thin film layer formed using the sputtered electrode is disposed on a portion of the first side surface WS1 on the first main surface TS1. The second thin film layer formed using the sputtered electrode is disposed on a portion of the second side surface WS2 on the first main surface TS1. The third thin film layer formed using the sputtered electrode is disposed on a portion of the second side surface WS2 on the first main surface TS1. The fourth thin film layer formed using the sputtered electrode is disposed on a portion of the second side surface WS2 on the first main surface TS1.

[0077] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesive strength of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a layer of Ni—Cr alloy and a layer of Ni—Cu alloy.

[0078] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0079] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0080] The third plating layer 60C is disposed so as to cover the third base electrode layer 50C.

[0081] The fourth plating layer 60D is disposed so as to cover the fourth base electrode layer 50D.

[0082] The first plating layer 60A, the second plating layer 60B, the third plating layer 60C, and the fourth plating layer 60D may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The first plating layer 60A, the second plating layer 60B, the third plating layer 60C, and the fourth plating layer 60D may each be formed of multiple layers. The first plating layer 60A, the second plating layer 60B, the third plating layer 60C, and the fourth plating layer 60D preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0083] In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0084] In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0085] In this embodiment, the third plating layer 60C includes a third Ni plating layer 61C and a third Sn plating layer 62C located on the third Ni plating layer 61C.

[0086] In this embodiment, the fourth plating layer 60D has a fourth Ni plating layer 61D and a fourth Sn plating layer 62D located on the fourth Ni plating layer 61D.

[0087] The Ni plating layer prevents the first base electrode layer 50A, the second base electrode layer 50B, the third base electrode layer 50C, and the fourth base electrode layer 50D from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating the mounting of the multilayer ceramic capacitor 1.

[0088] The thickness of each of the first Ni plating layer 61A and the first Sn plating layer 62A is preferably 2 μm or more and 10 μm or less, and the thickness of each of the second Ni plating layer 61B and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0089] The thickness of each of the third Ni plating layer 61C and the third Sn plating layer 62C is preferably 2 μm or more and 10 μm or less, and the thickness of each of the fourth Ni plating layer 61D and the fourth Sn plating layer 62D is preferably 2 μm or more and 10 μm or less.

[0090] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B, third plating layer 60C, and fourth plating layer 60D). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0091] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0092] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0093] The conductive particles may also be metal powder whose surface is coated with Ag. When using metal powder whose surface is coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powder.

[0094] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder in which the surface of metal powder is coated with Sn, Ni, or Cu. When using metal powder in which the surface of Sn, Ni, or Cu is coated, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0095] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0096] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the contact between the conductive particles forms an electrical path within the conductive resin layer.

[0097] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0098] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0099] Alternatively, the first, second, third, and fourth base electrode layers 50A, 50B, 50C, and 50D may be omitted, and a first plating layer 60A, a second plating layer 60B, a third plating layer 60C, and a fourth plating layer 60D, which will be described later, may be disposed directly on the laminate 10. That is, the multilayer ceramic capacitor 1 may include plating layers that are directly and electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, a catalyst may be disposed on the surface of the laminate 10 as a pretreatment, and then the plating layers may be formed.

[0100] Even in this case, the plating layer preferably comprises multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which have good solder wettability.

[0101] For example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may be composed of only the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or another plating layer may be formed on the surface of the upper plating layer.

[0102] The thickness of each plating layer disposed without a base electrode layer is preferably 2 μm or more and 10 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0103] Note that, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the multilayer ceramic capacitor 1 in the height direction T can be reduced by the amount of the reduced thickness of the base electrode layer, thereby making it possible to reduce the height of the multilayer ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased by the amount of the reduced thickness of the base electrode layer, thereby improving the thickness of the element body. In this way, by forming the plating layer directly on the laminate 10, the design freedom of the multilayer ceramic capacitor can be improved.

[0104] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, the L dimension is preferably 0.2 mm or more and 6 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, the T dimension is preferably 0.05 mm or more and 5 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0105] Here, the inventors of the present application have found, through repeated studies, experiments, and simulations, that it is desirable to appropriately set the dimensions and coverage of each component included in the multilayer ceramic capacitor in order to increase the capacitance without increasing the size of the multilayer ceramic capacitor. Note that the internal electrode layers 30 contain, in addition to the metal material, hollow portions where no metal material is present, and the ratio of the metal material to the internal electrode layers 30 will be described as the coverage. Coverage is also referred to as the coverage rate of the internal electrode layers 30 relative to the dielectric layers 20.

[0106] The hollow portion where no metal material is present may contain a ceramic component such as a dielectric or a glass component such as silica. Alternatively, it may be a void. This embodiment will be described in detail below with reference to FIGS. 1 to 7.

[0107] As shown in Figures 4A to 5C, the inner layer portion 11 has a first main surface side inner layer portion 112, a second main surface side inner layer portion 113, and a central inner layer portion 111 disposed between the first main surface side inner layer portion and the second main surface side inner layer portion. As described above, Figures 4A to 5C are schematic diagrams, and for the sake of convenience of explanation, a small number of internal electrode layers 30 are shown.

[0108] The first main surface side inner layer portion 112 is a portion on the first main surface TS1 side of the inner layer portion 11. The first main surface side inner layer portion 112 is, for example, a portion on the first main surface TS1 side of the inner layer portion 11, and is a portion including at least the fifth internal electrode layer 30 from the internal electrode layer 30 closest to the first main surface TS1. The first main surface side inner layer portion 112 is, for example, 25% of the inner layer portion 11 on the first main surface TS1 side in the stacking direction.

[0109] The second main surface side inner layer portion 113 is a portion on the second main surface TS2 side of the inner layer portion 11. The second main surface side inner layer portion 113 is, for example, a portion on the second main surface TS2 side of the inner layer portion 11, and is a portion including at least the fifth internal electrode layer 30 from the internal electrode layer 30 closest to the second main surface TS2. The second main surface side inner layer portion 113 is, for example, 25% of the inner layer portion 11 on the second main surface TS2 side in the stacking direction.

[0110] The central inner layer portion 111 is a portion of the inner layer portion 11 that is located on the central side in the stacking direction T of the laminate 10. The central inner layer portion 111 is, for example, a portion that includes at least the internal electrode layer 30 arranged in the central region of the laminate in the stacking direction T. The thicknesses of the central inner layer portion 111, the first main surface side internal layer portion 112, and the second main surface side internal layer portion 113 in the stacking direction T each vary along the length direction L and the width direction W in accordance with the shape of the internal electrode layer 30.

[0111] As shown in FIGS. 6A and 6B, the opposing electrode portion 11E of the inner layer portion 11 has a first side surface opposing electrode portion 112E, a second side surface opposing electrode portion 113E, and a central opposing electrode portion 111E.

[0112] The first side surface side opposing electrode portion 112E is a portion of the opposing electrode portion 11E on the first side surface WS1 side. For example, the first side surface side opposing electrode portion 112E is 25% of the opposing electrode portion 11E on the first side surface WS1 side in the width direction W. The first side surface side opposing electrode portion 112E has an area that overlaps with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and parts of the central inner layer portion 111.

[0113] The second side surface side opposing electrode portion 113E is a portion of the opposing electrode portion 11E on the second side surface WS2 side. For example, the second side surface side opposing electrode portion 113E is 25% of the opposing electrode portion 11E on the second side surface WS2 side in the width direction W. The second side surface side opposing electrode portion 113E has an area that overlaps with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and parts of the central inner layer portion 111.

[0114] The central opposing electrode portion 111E is disposed between the first side surface side opposing electrode portion 112E and the second side surface side opposing electrode portion 113E. The central opposing electrode portion 111E is a portion of the opposing electrode portion 11E that includes a central region in the width direction W. The central opposing electrode portion 111E has regions that overlap with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and parts of the central inner layer portion 111.

[0115] Next, the internal electrode layer 30 will be described in detail with reference to FIGS. 4A to 6B.

[0116] 4B and 6A , the first opposing portion EA of the first internal electrode layer 31 includes a first region EA1 on the first end face LS1 side, a second region EA2 on the second end face LS2 side, and a first central region EA0 as a first high-coverage region located between the first region EA1 and the second region EA2 and having higher coverage than the first region EA1 and the second region EA2. The first central region EA0 as the first high-coverage region has higher coverage than the first lead portion D1 and the second lead portion D2. That is, the coverage of the first lead portion D1 and the second lead portion D2 is lower than that of the first central region EA0 as the first high-coverage region. The first central region EA0 is disposed more outside the stack 10 than the first lead portion D1 and the second lead portion D2.

[0117] In this embodiment, the first facing portion EA has a first side surface area EWA1 on the first side surface WS1 side of the first central area EA0, the first side surface area EWA1 having lower coverage than the coverage of the first central area EA0, and a second side surface area EWA2 on the second side surface WS2 side of the first central area EA0, the second side surface area EWA2 having lower coverage than the coverage of the first central area EA0.

[0118] The lengths of the first side surface region EWA1 and the second side surface region EWA2 in the longitudinal direction L may be shorter than the length of the first central region EA0 in the longitudinal direction L. In this case, in the LW cross section (a cross section parallel to the longitudinal direction L and the width direction W) viewed in the stacking direction shown in FIG. 6A , the shape of the first central region EA0 is approximately H-shaped. This allows the area with high coverage in the first internal electrode layer 31 to be increased without increasing the size of the multilayer ceramic capacitor 1, thereby increasing the capacitance. However, the shape of the first central region EA0 is not limited thereto. The lengths of the first side surface region EWA1 and the second side surface region EWA2 in the longitudinal direction L may be the same as the length of the first central region EA0 in the longitudinal direction L. In this case, the shape of the first central region EA0 is approximately rectangular.

[0119] The first facing portion EA may have a first inclined portion FA1 connecting the first region EA1 and the first central region EA0 and a second inclined portion FA2 connecting the second region EA2 and the first central region EA0. The first facing portion EA may also have a first side inclined portion FWA1 connecting the first side region EWA1 and the first central region EA0 and a second side inclined portion FWA2 connecting the second side region EWA2 and the first central region EA0. These inclined portions will be described later.

[0120] As shown in Fig. 4B, the first central region EA0 is disposed closer to the outside of the laminate 10 than the first region EA1 and the second region EA2. As shown in Fig. 5B, the first central region EA0 is disposed closer to the outside of the laminate 10 than the first lateral side region EWA1 and the second lateral side region EWA2.

[0121] Specifically, in the first main surface side inner layer portion 112, the first central region EA0 of the first internal electrode layer 31 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the first region EA1 and the second region EA2. In the first main surface side inner layer portion 112, the first central region EA0 of the first internal electrode layer 31 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the first side surface side region EWA1 and the second side surface side region EWA2.

[0122] In the present embodiment, in the second main surface side inner layer portion 113, the first central region EA0 of the first internal electrode layer 31 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the first region EA1 and the second region EA2. In the second main surface side inner layer portion 113, the first central region EA0 of the first internal electrode layer 31 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the first side surface side region EWA1 and the second side surface side region EWA2.

[0123] In at least one of the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113, the first central region EA0 may be positioned more outward of the laminate 10 than the first region EA1 and the second region EA2. In at least one of the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113, the first central region EA0 may be positioned more outward of the laminate 10 than the first lateral surface side region EWA1 and the second lateral surface side region EWA2.

[0124] 4B and 6B , the second opposing portion EB of the second internal electrode layer 32 includes a third region EB1 located on the first end face LS1 side, a fourth region EB2 located on the second end face LS2 side, and a second central region EB0 serving as a second high coverage region located between the third region EB1 and the fourth region EB2 and having higher coverage than the third region EB1 and the fourth region EB2. The second central region EB0 serving as the second high coverage region has higher coverage than the third lead portion D3 and the fourth lead portion D4. That is, the coverage of the third lead portion D3 and the fourth lead portion D4 is lower than that of the second central region EB0 serving as the second high coverage region. The second central region EB0 is disposed more outside the stack 10 than the third lead portion D3 and the fourth lead portion D4.

[0125] In this embodiment, the second facing portion EB has a third side surface region EWB1 on the first side surface WS1 side of the second central region EB0, the third side surface region EWB1 having lower coverage than the coverage of the second central region EB0, and a fourth side surface region EWB2 on the second side surface WS2 side of the second central region EB0, the fourth side surface region EWB2 having lower coverage than the coverage of the second central region EB0.

[0126] The lengths of the third side surface region EWB1 and the fourth side surface region EWB2 in the longitudinal direction L may be shorter than the length of the second central region EB0 in the longitudinal direction L. In this case, in the LW cross section (a cross section parallel to the longitudinal direction L and the width direction W) viewed in the stacking direction shown in FIG. 6B , the shape of the second central region EB0 is approximately H-shaped. This allows the area with high coverage in the second internal electrode layer 32 to be increased without increasing the size of the multilayer ceramic capacitor 1, thereby increasing the capacitance. However, the shape of the second central region EB0 is not limited to this. The lengths of the third side surface region EWB1 and the fourth side surface region EWB2 in the longitudinal direction L may be the same as the length of the second central region EB0 in the longitudinal direction L. In this case, the shape of the second central region EB0 is approximately rectangular.

[0127] The second facing portion EB may have a third inclined portion FB1 connecting the third region EB1 and the second central region EB0 and a fourth inclined portion FB2 connecting the fourth region EB2 and the second central region EB0. The second facing portion EB may also have a third side inclined portion FWB1 connecting the third side region EWB1 and the second central region EB0 and a fourth side inclined portion FWB2 connecting the fourth side region EWB2 and the second central region EB0. These inclined portions will be described later.

[0128] 4B, the second central region EB0 is positioned more outwardly of the laminate 10 than the third region EB1 and the fourth region EB2. As shown in FIG. 4B, the second central region EB0 is positioned more outwardly of the laminate 10 than the third side region EWB1 and the fourth side region EWB2.

[0129] Specifically, in the first main surface side inner layer portion 112, the second central region EB0 of the second internal electrode layer 32 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the third region EB1 and the fourth region EB2. In the first main surface side inner layer portion 112, the second central region EB0 of the second internal electrode layer 32 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the third side surface side region EWB1 and the fourth side surface side region EWB2.

[0130] In the present embodiment, in the second main surface side inner layer portion 113, the second central region EB0 of the second internal electrode layer 32 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the third region EB1 and the fourth region EB2. In the second main surface side inner layer portion 113, the second central region EB0 of the second internal electrode layer 32 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the third side surface side region EWB1 and the fourth side surface side region EWB2.

[0131] In at least one of the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113, the second central region EB0 may be positioned more outward of the laminate 10 than the third region EB1 and the fourth region EB2. In at least one of the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113, the second central region EB0 may be positioned more outward of the laminate 10 than the third side surface side region EWB1 and the fourth side surface side region EWB2.

[0132] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0133] The first central region EA0 preferably has a portion that is substantially parallel to a plane perpendicular to the stacking direction T. The first central region EA0, the first region EA1, and the second region EA2 preferably have substantially parallel portions. More preferably, the first central region EA0, the first region EA1, and the second region EA2 have portions that are substantially parallel to a plane perpendicular to the stacking direction T.

[0134] The first central region EA0, the first lateral side region EWA1, and the second lateral side region EWA2 preferably have substantially parallel portions, and more preferably have substantially parallel portions to a plane perpendicular to the stacking direction T.

[0135] The second central region EB0 preferably has a portion that is substantially parallel to a plane perpendicular to the stacking direction T. The second central region EB0, the third region EB1, and the fourth region EB2 preferably have substantially parallel portions. More preferably, the second central region EB0, the third region EB1, and the fourth region EB2 have portions that are substantially parallel to a plane perpendicular to the stacking direction T.

[0136] The second central region EB0, the third side region EWB1, and the fourth side region EWB2 preferably have portions that are substantially parallel to each other. More preferably, the second central region EB0, the third side region EWB1, and the fourth side region EWB2 have portions that are substantially parallel to a plane perpendicular to the stacking direction T.

[0137] This makes it possible to prevent the formation of portions of the multilayer ceramic capacitor 1 that are locally large in size, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0138] As shown in FIG. 4B , in the longitudinal direction L in the LT cross section (a cross section on a plane parallel to the stacking direction T and the longitudinal direction L) at the center of the width direction W, the distance Le0 of the first central region EA0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. Also, in the longitudinal direction L, the distance Le0 of the second central region EB0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. It is preferable, but not limited to, that the distances of the first central region EA0 and the second central region EB0 be approximately equal in the longitudinal direction L. It is preferable that the first central region EA0 and the second central region EB0 are disposed within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B in the longitudinal direction L.

[0139] As shown in FIG. 5B , in the width direction W of a WT cross section (a cross section on a plane parallel to the stacking direction T and the width direction W) at the center of the length direction L, the distance Lwe0 of the first central region EA0 is shorter than the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D. Furthermore, in the width direction W, the distance Lwe0 of the second central region EB0 is shorter than the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D. It is preferable, but not limited to, that the distances of the first central region EA0 and the second central region EB0 be approximately equal in the width direction W. It is preferable that the first central region EA0 and the second central region EB0 are disposed within the range of the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D in the width direction W.

[0140] In the longitudinal direction L, the ends of the first central region EA0 and the second central region EB0 on ​​the first end face LS1 side are located closer to the second end face LS2 than the ends 40AE of the first external electrodes 40A on the stack center side, which are located on the first main surface TS1 and the second main surface TS2. In the longitudinal direction L, the ends of the first central region EA0 and the second central region EB0 on ​​the second end face LS2 side are located closer to the first end face LS1 than the ends 40BE of the second external electrodes 40B on the stack center side, which are located on the first main surface TS1 and the second main surface TS2.

[0141] In the width direction W, the ends of the first central region EA0 and the second central region EB0 on ​​the first side surface WS1 side are located closer to the second side surface WS2 than the end 40CE on the stack center side of the third external electrode 40C, which is located on the first main surface TS1 and the second main surface TS2. In the width direction W, the ends of the first central region EA0 and the second central region EB0 on ​​the second side surface WS2 side are located closer to the first side surface WS1 than the end 40DE on the stack center side of the fourth external electrode 40D, which is located on the first main surface TS1 and the second main surface TS2.

[0142] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0143] In the longitudinal direction L, the ends of the first region EA1 and the third region EB1 on the first end face LS1 side (see FIG. 4B ) are located closer to the first end face LS1 than the end 40AE (see FIG. 4A ) of the first external electrode 40A on the stack center side, which is located on the first main surface TS1 and the second main surface TS2. In the longitudinal direction L, the ends of the second region EA2 and the fourth region EB2 on the second end face LS2 side (see FIG. 4B ) are located closer to the second end face LS2 than the end 40BE (see FIG. 4A ) of the second external electrode 40B on the stack center side, which is located on the first main surface TS1 and the second main surface TS2.

[0144] In the width direction W, the ends of the first side surface side region EWA1 and the third side surface side region EWB1 on the first side surface WS1 side (see FIG. 5B ) are located closer to the first side surface WS1 than the end 40CE (see FIG. 5A ) of the third external electrode 40C on the stack center side, which is located on the first main surface TS1 and the second main surface TS2. In the width direction W, the ends of the second side surface side region EWA2 and the fourth side surface side region EWB2 on the second side surface WS2 side (see FIG. 5B ) are located closer to the second side surface WS2 than the end 40DE (see FIG. 5A ) of the fourth external electrode 40D on the stack center side, which is located on the first main surface TS1 and the second main surface TS2.

[0145] This makes it possible to prevent the size of the multilayer ceramic capacitor 1 from increasing, while ensuring a large area for the opposing electrode portion 11E and increasing the capacitance.

[0146] The thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the first region EA1 and the thickness of the second region EA2 in the stacking direction T.

[0147] For example, the thickness of the first central region EA0 is preferably 101% to 111% of the thickness of the first region EA1 and the thickness of the second region EA2. The thickness of the first central region EA0 may be 101% to 110% of the thickness of the first region EA1 and the thickness of the second region EA2, and more preferably 102% to 110%. For example, the thickness of the first central region EA0 is even more preferably 103% to 110% of the thickness of the first region EA1 and the thickness of the second region EA2.

[0148] The thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the first side surface region EWA1 and the thickness of the second side surface region EWA2 in the stacking direction T.

[0149] For example, the thickness of the first central region EA0 is preferably 101% to 111% of the thickness of the first lateral side region EWA1 and the second lateral side region EWA2. The thickness of the first central region EA0 may be 101% to 110% of the thickness of the first lateral side region EWA1 and the second lateral side region EWA2, and more preferably 102% to 110%. For example, the thickness of the first central region EA0 is even more preferably 103% to 110% of the thickness of the first lateral side region EWA1 and the second lateral side region EWA2.

[0150] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is greater than the thickness of the third region EB1 and the thickness of the fourth region EB2.

[0151] For example, the thickness of the second central region EB0 is preferably 101% to 111% of the thickness of the third region EB1 and the thickness of the fourth region EB2. The thickness of the second central region EB0 may be 101% to 110% of the thickness of the third region EB1 and the thickness of the fourth region EB2, and more preferably 102% to 110%. For example, the thickness of the second central region EB0 is even more preferably 103% to 110% of the thickness of the third region EB1 and the thickness of the fourth region EB2.

[0152] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is greater than the thickness of the third side surface region EWB1 and the thickness of the fourth side surface region EWB2.

[0153] For example, the thickness of the second central region EB0 is preferably 101% to 111% of the thickness of the third lateral side region EWB1 and the fourth lateral side region EWB2. The thickness of the second central region EB0 may be 101% to 110% of the thickness of the third lateral side region EWB1 and the fourth lateral side region EWB2, and more preferably 102% to 110%. For example, the thickness of the second central region EB0 is even more preferably 103% to 110% of the thickness of the third lateral side region EWB1 and the fourth lateral side region EWB2.

[0154] To collectively describe the first internal electrode layer 31 and the second internal electrode layer 32, the thickness of the first central region EA0 and the second central region EB0 is thicker than the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0155] The thicknesses of the first central region EA0 and the second central region EB0 are preferably 101% to 111% of the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. The thicknesses of the first central region EA0 and the second central region EB0 may be 101% to 110% of the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, and more preferably 102% to 110%. For example, the thicknesses of the first central region EA0 and the second central region EB0 are more preferably 103% to 110% of the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0156] The thickness of the first central region EA0 and the second central region EB0 is greater than the thickness of the first lateral side region EWA1, the second lateral side region EWA2, the third lateral side region EWB1 and the fourth lateral side region EWB2.

[0157] The thicknesses of the first central region EA0 and the second central region EB0 are preferably 101% to 111% of the thicknesses of the first lateral side region EWA1, the second lateral side region EWA2, the third lateral side region EWB1, and the fourth lateral side region EWB2. The thicknesses of the first central region EA0 and the second central region EB0 may be 101% to 110%, and more preferably 102% to 110%, of the thicknesses of the first lateral side region EWA1, the second lateral side region EWA2, the third lateral side region EWB1, and the fourth lateral side region EWB2. For example, it is more preferable that the thickness of the first central region EA0 and the second central region EB0 be 103% or more and 110% or less of the thickness of the first side region EWA1, the second side region EWA2, the third side region EWB1 and the fourth side region EWB2.

[0158] The thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the first lead portion D1.

[0159] For example, the thickness of the first central region EA0 is preferably 101% to 111% of the thickness of the first lead portion D1. For example, the thickness of the first central region EA0 may be 101% to 110% of the thickness of the first lead portion D1, and more preferably 102% to 110%. For example, the thickness of the first central region EA0 is even more preferably 103% to 110% of the thickness of the first lead portion D1.

[0160] The thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the second lead portion D2.

[0161] For example, the thickness of the first central region EA0 is preferably 101% to 111% of the thickness of the second lead portion D2. For example, the thickness of the first central region EA0 may be 101% to 110% of the thickness of the second lead portion D2, and more preferably 102% to 110%. For example, the thickness of the first central region EA0 is even more preferably 103% to 110% of the thickness of the second lead portion D2.

[0162] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is greater than the thickness of the third lead portion D3.

[0163] For example, the thickness of the second central region EB0 is preferably 101% to 111% of the thickness of the third lead portion D3. For example, the thickness of the second central region EB0 may be 101% to 110% of the thickness of the third lead portion D3, and more preferably 102% to 110%. For example, the thickness of the second central region EB0 is even more preferably 103% to 110% of the thickness of the third lead portion D3.

[0164] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is greater than the thickness of the fourth lead portion D4.

[0165] For example, the thickness of the second central region EB0 is preferably 101% to 111% of the thickness of the fourth lead portion D4. For example, the thickness of the second central region EB0 may be 101% to 110% of the thickness of the fourth lead portion D4, and more preferably 102% to 110%. For example, the thickness of the second central region EB0 is even more preferably 103% to 110% of the thickness of the fourth lead portion D4.

[0166] The first central area EA0 has a higher coverage than the first area EA1 and the second area EA2.

[0167] The difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is preferably 2 percentage points or more, and the difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is preferably 2 percentage points or more and 11 percentage points or less.

[0168] The difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is preferably 3 to 11 percentage points, which is more effective, and the difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is more preferably 4 to 11 percentage points.

[0169] The first central area EA0 has a higher coverage than the first side area EWA1 and the second side area EWA2.

[0170] The difference between the coverage of the first central region EA0 and the coverage of the first and second lateral side regions EWA1 and EWA2 is preferably 2 percentage points or more, and the difference between the coverage of the first central region EA0 and the coverage of the first and second lateral side regions EWA1 and EWA2 is preferably 2 percentage points or more and 11 percentage points or less.

[0171] The difference between the coverage of the first central region EA0 and the coverage of the first and second lateral side regions EWA1 and EWA2 is preferably 3 to 11 percentage points, which is more effective.The difference between the coverage of the first central region EA0 and the coverage of the first and second lateral side regions EWA1 and EWA2 is more preferably 4 to 11 percentage points.

[0172] The second central region EB0 has a higher coverage than the third region EB1 and the fourth region EB2.

[0173] The difference between the coverage of the second central region EB0 and the coverage of the third region EB1 and the coverage of the fourth region EB2 is preferably 2 percentage points or more, and the difference between the coverage of the second central region EB0 and the coverage of the third region EB1 and the coverage of the fourth region EB2 is preferably 2 percentage points or more and 11 percentage points or less.

[0174] The difference between the coverage of the second central region EB0 and the coverage of the third and fourth regions EB1 and EB2 is preferably 3 to 11 percentage points, which is more preferable for achieving a higher effect. Furthermore, the difference between the coverage of the second central region EB0 and the coverage of the third and fourth regions EB1 and EB2 is more preferably 4 to 11 percentage points.

[0175] The second central region EB0 has a higher coverage than the third side region EWB1 and the fourth side region EWB2.

[0176] The difference between the coverage of the second central region EB0 and the coverage of the third and fourth lateral side regions EWB1 and EWB2 is preferably 2 percentage points or more, and the difference between the coverage of the second central region EB0 and the coverage of the third and fourth lateral side regions EWB1 and EWB2 is preferably 2 percentage points or more and 11 percentage points or less.

[0177] The difference between the coverage of the second central region EB0 and the coverage of the third and fourth lateral side regions EWB1 and EWB2 is preferably 3 to 11 percentage points, which is more preferable for achieving a higher effect. Furthermore, the difference between the coverage of the second central region EB0 and the coverage of the third and fourth lateral side regions EWB1 and EWB2 is more preferably 4 to 11 percentage points.

[0178] To collectively describe the first internal electrode layer 31 and the second internal electrode layer 32, the coverage of the first central region EA0 and the second central region EB0 is higher than the coverage of the first region EA1, the second region EA2, the third region EB1 and the fourth region EB2.

[0179] The coverage of the first central region EA0 and the second central region EB0 is preferably 2 percentage points or more higher than the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Furthermore, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is preferably 2 percentage points or more and 11 percentage points or less.

[0180] The difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is preferably 3 to 11 percentage points, inclusive, which is expected to produce a greater effect.Furthermore, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is even more preferably 4 to 11 percentage points, inclusive.

[0181] The coverage of the first central area EA0 and the second central area EB0 is higher than the coverage of the first side area EWA1, the second side area EWA2, the third side area EWB1 and the fourth side area EWB2.

[0182] The coverage of the first central region EA0 and the second central region EB0 is preferably 2 percentage points or more higher than the coverage of the first lateral side region EWA1, the second lateral side region EWA2, the third lateral side region EWB1, and the fourth lateral side region EWB2. Also, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first lateral side region EWA1, the second lateral side region EWA2, the third lateral side region EWB1, and the fourth lateral side region EWB2 is preferably 2 percentage points or more and 11 percentage points or less.

[0183] The difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first lateral side region EWA1, the second lateral side region EWA2, the third lateral side region EWB1, and the fourth lateral side region EWB2 is preferably 3 to 11 percentage points, which is expected to produce a greater effect. Furthermore, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first lateral side region EWA1, the second lateral side region EWA2, the third lateral side region EWB1, and the fourth lateral side region EWB2 is more preferably 4 to 11 percentage points.

[0184] This allows the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to be increased, thereby sufficiently increasing the coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0185] The first internal electrode layer 31 further has a first inclined portion FA1 connecting the first region EA1 and the first central region EA0, and a second inclined portion FA2 connecting the second region EA2 and the first central region EA0, as shown in FIG. 4B.

[0186] The first internal electrode layer 31 further has, as shown in FIG. 5B, a first side inclined portion FWA1 connecting the first side region EWA1 and the first central region EA0, and a second side inclined portion FWA2 connecting the second side region EWA2 and the first central region EA0.

[0187] The second internal electrode layer 32 further has a third inclined portion FB1 connecting the third region EB1 and the second central region EB0, and a fourth inclined portion FB2 connecting the fourth region EB2 and the second central region EB0, as shown in FIG. 4B.

[0188] The second internal electrode layer 32 further has, as shown in FIG. 5B, a third side surface inclined portion FWB1 connecting the third side surface region EWB1 and the second central region EB0, and a fourth side surface inclined portion FWB2 connecting the fourth side surface region EWB2 and the second central region EB0.

[0189] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0190] 4B , the distance Le3 in the length direction L of the first inclined portion FA1 and the distance Le4 in the length direction L of the second inclined portion FA2 are shorter than the distance Le0 in the length direction L of the first central region EA0. Also, as shown in FIG. 4B , the distance Le3 in the length direction L of the third inclined portion FB1 and the distance Le4 in the length direction L of the fourth inclined portion FB2 are shorter than the distance Le0 in the length direction L of the second central region EB0.

[0191] 5B, the distance Lwe3 in the width direction W of the first side inclined portion FWA1 and the distance Lwe4 in the width direction W of the second side inclined portion FWA2 are shorter than the distance Lwe0 in the width direction W of the first central region EA0. Also, as shown in FIG. 5B, the distance Lwe3 in the width direction W of the third side inclined portion FWB1 and the distance Lwe4 in the width direction W of the fourth side inclined portion FWB2 are shorter than the distance Lwe0 in the width direction W of the second central region EB0.

[0192] This makes it possible to ensure the areas of the first central region EA0 and the second central region EB0 with high coverage, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0193] The distance Le1 in the length direction L of the first region EA1 and the distance Le2 in the length direction L of the second region EA2 may be shorter than the distance Le0 in the length direction L of the first central region EA0. The distance Le1 in the length direction L of the third region EB1 and the distance Le2 in the length direction L of the fourth region EB2 may be shorter than the distance Le0 in the length direction L of the second central region EB0.

[0194] The distance Lwe1 in the width direction W of the first lateral side region EWA1 and the distance Lwe2 in the width direction W of the second lateral side region EWA2 may be shorter than the distance Lwe0 in the width direction W of the first central region EA0. The distance Lwe1 in the width direction W of the third lateral side region EWB1 and the distance Lwe2 in the width direction W of the fourth lateral side region EWB2 may be shorter than the distance Lwe0 in the width direction W of the second central region EB0.

[0195] The ratio of the area of ​​the first central region EA0 to the area of ​​the first facing portion EA is preferably 30% to 90% and may be 40% to 85%. It is more preferably 50% to 80%, for example, 50%. The ratio of the area of ​​the second central region EB0 to the area of ​​the second facing portion EB is preferably 30% to 90% and may be 40% to 85%. It is more preferably 50% to 80% and may be 50% to 50%.

[0196] This allows a large area to be secured for the opposing electrode portion 11E, while also securing an area for arranging the first external electrode 40A and the second external electrode 40B, and further allows the areas of the first central region EA0 and the second central region EB0, which have high coverage, to be appropriately secured, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0197] It is preferable that the distance Le3 in the longitudinal direction L between the first inclined portion FA1 and the third inclined portion FB1, and the distance Le4 in the longitudinal direction L between the second inclined portion FA2 and the fourth inclined portion FB2 are approximately equal, but this is not limited to this.

[0198] It is preferable that the distance Lwe3 in the width direction W between the first side inclined portion FWA1 and the third side inclined portion FWB1, and the distance Lwe4 in the width direction W between the second side inclined portion FWA2 and the fourth side inclined portion FWB2 are approximately equal, but this is not limited to this.

[0199] In addition, in the longitudinal direction L, it is preferable that the first central region EA0 and the second central region EB0 are arranged within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B, and that the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, and the fourth inclined portion FB2 are also arranged.

[0200] The sum of the distance Le0 in the length direction L between the first central region EA0 and the second central region EB0, the distance Le3 in the length direction L between the first inclined portion FA1 and the third inclined portion FB1, and the distance Le4 in the length direction L between the second inclined portion FA2 and the fourth inclined portion FB2 (=Le0+Le3+Le4) is preferably shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B, although this is not limited to this.

[0201] In addition, in the width direction W, it is preferable that the first central region EA0 and the second central region EB0 are arranged within the range of the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D, and that the first side surface inclined portion FWA1, the second side surface inclined portion FWA2, the third side surface inclined portion FWB1, and the fourth side surface inclined portion FWB2 are also arranged.

[0202] The sum of the distance Lwe0 in the width direction W between the first central region EA0 and the second central region EB0, the distance Lwe3 in the width direction W between the first side surface inclined portion FWA1 and the third side surface inclined portion FWB1, and the distance Lwe4 in the width direction W between the second side surface inclined portion FWA2 and the fourth side surface inclined portion FWB2 (=Lwe0+Lwe3+Lwe4) is preferably shorter than the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D, although this is not limited to this.

[0203] The inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 is preferably 1° or greater. For example, the inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 may be 2° or greater and 10° or less.

[0204] The inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 is preferably 1° or greater. For example, the inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 may be 2° or greater and 10° or less.

[0205] The inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 is preferably 1° or greater. For example, the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 may be 2° or greater and 10° or less.

[0206] The inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 is preferably 1° or greater. For example, the inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 may be 2° or greater and 10° or less.

[0207] The inclination angle θ3 of the first side surface inclined portion FWA1 with respect to the first central region EA0 is preferably 1° or more. For example, the inclination angle θ3 of the first side surface inclined portion FWA1 with respect to the first central region EA0 may be 1° or more and 12° or less. More preferably, the inclination angle θ3 of the first side surface inclined portion FWA1 with respect to the first central region EA0 may be 2° or more and 10° or less.

[0208] The inclination angle θ3 of the second lateral inclined portion FWA2 with respect to the first central region EA0 is preferably 1° or greater. For example, the inclination angle θ3 of the second lateral inclined portion FWA2 with respect to the first central region EA0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ3 of the second lateral inclined portion FWA2 with respect to the first central region EA0 may be 2° or greater and 10° or less.

[0209] The inclination angle θ3 of the third side surface inclined portion FWB1 with respect to the second central region EB0 is preferably 1° or more. For example, the inclination angle θ3 of the third side surface inclined portion FWB1 with respect to the second central region EB0 may be 1° or more and 12° or less. More preferably, the inclination angle θ3 of the third side surface inclined portion FWB1 with respect to the second central region EB0 may be 2° or more and 10° or less.

[0210] The inclination angle θ3 of the fourth side surface inclined portion FWB2 with respect to the second central region EB0 is preferably 1° or greater. For example, the inclination angle θ3 of the fourth side surface inclined portion FWB2 with respect to the second central region EB0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ3 of the fourth side surface inclined portion FWB2 with respect to the second central region EB0 may be 2° or greater and 10° or less.

[0211] FIG. 4B shows the inclination angle θ of the second inclined portion FA2 with respect to the first central area EA0 in the first internal electrode layer 31 as a representative of the inclination angle θ.

[0212] FIG. 5B shows the inclination angle θ3 of the fourth side surface inclined portion FWB2 with respect to the second central region EB0 in the second internal electrode layer 32 as a representative of the inclination angle θ3 described above.

[0213] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0214] Specifically, by setting the inclination angle θ to 1° or more, preferably 2° or more, it is possible to ensure an area for increasing the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0. Furthermore, by setting the inclination angle θ to 12° or less, preferably 10° or less, it is possible to prevent the surface of the laminate 10 from expanding too much in the stacking direction T and protruding outward beyond the surfaces of the external electrodes 40.

[0215] More specifically, by setting the inclination angle θ within the above-mentioned range, it becomes easy to set the relationship between the respective thicknesses of the first central region EA0 and the second central region EB0 and the respective thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 within the range of this embodiment.

[0216] Specifically, by setting the inclination angle θ3 to 1° or more, preferably 2° or more, it is possible to ensure an area for increasing the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0. Furthermore, by setting the inclination angle θ3 to 12° or less, preferably 10° or less, it is possible to prevent the surface of the laminate 10 from expanding too much in the stacking direction T and protruding outward beyond the surfaces of the external electrodes 40.

[0217] More specifically, by setting the inclination angle θ3 within the above-mentioned range, it becomes easy to set the relationship between the respective thicknesses of the first central region EA0 and the second central region EB0 and the respective thicknesses of the first side region EWA1, the second side region EWA2, the third side region EWB1, and the fourth side region EWB2 within the range of this embodiment.

[0218] Furthermore, by setting the inclination angle θ within the above-mentioned range, it becomes easy to set the relationship between the distance T0 from the first main surface TS1 to the second main surface TS2 at the center in the longitudinal direction L and the center in the width direction W of the exposed portion Ep of the laminate 10 described below, and the maximum distance T1 from the first main surface TS1 to the second main surface TS2 in the first covering portion C1 and the second covering portion C2 of the laminate 10 described below, within the range of this embodiment described below.

[0219] Furthermore, by setting the inclination angle θ3 within the above-mentioned range, it becomes easy to set the relationship between the distance T0 from the first main surface TS1 to the second main surface TS2 at the center in the longitudinal direction L and the center in the width direction W of the exposed portion Ep of the laminate 10 described later, and the maximum distance TW1 from the first main surface TS1 to the second main surface TS2 in the third covering portion CW1 and the fourth covering portion CW2 of the laminate 10 described later, within the range of this embodiment described later.

[0220] The thickness of the first inclined portion FA1 in the stacking direction T gradually decreases toward the first end face LS1 as shown in Figures 4A and 4B , and the thickness of the second inclined portion FA2 in the stacking direction T gradually decreases toward the second end face LS2 as shown in Figures 4A and 4B .

[0221] The thickness of the third inclined portion FB1 in the stacking direction T gradually decreases toward the first end face LS1 as shown in Figures 4A and 4B , and the thickness of the fourth inclined portion FB2 in the stacking direction T gradually decreases toward the second end face LS2 as shown in Figures 4A and 4B .

[0222] The thickness of the first side surface inclined portion FWA1 in the stacking direction T gradually decreases toward the first side surface WS1 as shown in Figures 5A to 5C. The thickness of the second side surface inclined portion FWA2 in the stacking direction T gradually decreases toward the second side surface WS2 as shown in Figures 5A to 5C.

[0223] The thickness of the third side surface inclined portion FWB1 in the stacking direction T gradually decreases toward the first side surface WS1 as shown in Figures 5A to 5C. The thickness of the fourth side surface inclined portion FWB2 in the stacking direction T gradually decreases toward the second side surface WS2 as shown in Figures 5A to 5C.

[0224] If there is a portion where the thickness of the internal electrode layers 30 changes suddenly, there is a possibility that a portion where the distance between the internal electrode layers 30 sandwiching the dielectric layer 20 is locally short will be formed. In this case, an electric field will be concentrated in that portion, which may reduce the reliability of the multilayer ceramic capacitor 1. With the above configuration, it is possible to prevent the formation of a portion where the distance between the internal electrode layers 30 is locally short near the inclined portion, and therefore it is possible to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1, while also preventing a reduction in the reliability of the multilayer ceramic capacitor 1 due to electric field concentration.

[0225] Furthermore, since stress concentration at the inclined portions can be prevented, the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1, and furthermore, the occurrence of cracks in the laminate can be suppressed.

[0226] 4B , a step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is larger than a thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is larger than a sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0227] More preferably, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0228] 4B , a step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 caused by the second inclined portion FA2 is larger than a thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 caused by the second inclined portion FA2 is larger than a sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0229] More preferably, the step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 caused by the second inclined portion FA2 is equal to or greater than twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 caused by the second inclined portion FA2 may be equal to or greater than three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0230] 4B , a step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is larger than a thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is larger than a sum Tt (=Te+Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0231] More preferably, the step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is equal to or greater than twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 may be equal to or greater than three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0232] 4B , a step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 caused by the fourth inclined portion FB2 is larger than a thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 caused by the fourth inclined portion FB2 is larger than a sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0233] More preferably, the step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 caused by the fourth inclined portion FB2 is equal to or greater than twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 caused by the fourth inclined portion FB2 may be equal to or greater than three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0234] 5C , the step distance lws1 in the stacking direction T between the first side region EWA1 and the first central region EA0, which is created by the first side inclined portion FWA1, is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance lws1 in the stacking direction T between the first side region EWA1 and the first central region EA0, which is created by the first side inclined portion FWA1, is larger than the sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0235] More preferably, the step distance lws1 in the stacking direction T between the first side surface region EWA1 and the first central region EA0 caused by the first side surface inclined portion FWA1 is equal to or greater than twice the sum Tt of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc in the stacking direction T of the dielectric layer 20. Furthermore, the step distance lws1 in the stacking direction T between the first side surface region EWA1 and the first central region EA0 caused by the first side surface inclined portion FWA1 may be equal to or greater than three times the sum Tt of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc in the stacking direction T of the dielectric layer 20.

[0236] 5C , the step distance lws2 in the stacking direction T between the second side surface region EWA2 and the first central region EA0, which is caused by the second side surface inclined portion FWA2, is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance lws2 in the stacking direction T between the second side surface region EWA2 and the first central region EA0, which is caused by the second side surface inclined portion FWA2, is larger than the sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0237] More preferably, the step distance lws2 in the stacking direction T between the second side surface region EWA2 and the first central region EA0 caused by the second side surface inclined portion FWA2 is equal to or greater than twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the step distance lws2 in the stacking direction T between the second side surface region EWA2 and the first central region EA0 caused by the second side surface inclined portion FWA2 may be equal to or greater than three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0238] 5C , a step distance lws3 in the stacking direction T between the third side surface region EWB1 and the second central region EB0, which is caused by the third side surface inclined portion FWB1, is larger than a thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance lws3 in the stacking direction T between the third side surface region EWB1 and the second central region EB0, which is caused by the third side surface inclined portion FWB1, is larger than a sum Tt (=Te+Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0239] More preferably, the step distance lws3 in the stacking direction T between the third side surface region EWB1 and the second central region EB0 caused by the third side surface inclined portion FWB1 is equal to or greater than twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the step distance lws3 in the stacking direction T between the third side surface region EWB1 and the second central region EB0 caused by the third side surface inclined portion FWB1 may be equal to or greater than three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0240] 5C , a step distance lws4 in the stacking direction T between the fourth side surface region EWB2 and the second central region EB0, which is caused by the fourth side surface inclined portion FWB2, is larger than a thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance lws4 in the stacking direction T between the fourth side surface region EWB2 and the second central region EB0, which is caused by the fourth side surface inclined portion FWB2, is larger than a sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0241] More preferably, the step distance lws4 in the stacking direction T between the fourth side surface region EWB2 and the second central region EB0 caused by the fourth side surface inclined portion FWB2 is equal to or greater than twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the step distance lws4 in the stacking direction T between the fourth side surface region EWB2 and the second central region EB0 caused by the fourth side surface inclined portion FWB2 may be equal to or greater than three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0242] The thickness Te of the internal electrode layer 30 in the stacking direction T is the thickness of the internal electrode layer 30 in the first central region EA0 and the second central region EB0 in the stacking direction T. The thickness Tc of the dielectric layer 20 in the stacking direction T is the thickness of the dielectric layer 20 arranged between the first central region EA0 and the second central region EB0 in the stacking direction T.

[0243] This allows the thickness of the internal electrode layer 30 in the first central region EA0 and the second central region EB0 to be increased by taking advantage of the steps created by the inclined portions, thereby sufficiently increasing the coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0244] The step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0, which is caused by the first inclined portion FA1, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less. The step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0, which is caused by the second inclined portion FA2, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less.

[0245] The step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0, which is caused by the third inclined portion FB1, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less. The step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0, which is caused by the fourth inclined portion FB2, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less.

[0246] The step distance lws1 in the stacking direction T between the first side surface region EWA1 and the first central region EA0, which is caused by the first side surface inclined portion FWA1, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less. The step distance lws2 in the stacking direction T between the second side surface region EWA2 and the first central region EA0, which is caused by the second side surface inclined portion FWA2, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less.

[0247] The step distance lws3 in the stacking direction T between the third side surface region EWB1 and the second central region EB0, which is caused by the third side surface inclined portion FWB1, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less. The step distance lws4 in the stacking direction T between the fourth side surface region EWB2 and the second central region EB0, which is caused by the fourth side surface inclined portion FWB2, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less.

[0248] The first internal electrode layer 31 further has a fifth inclined portion FA3 located in the first lead portion D1 and a sixth inclined portion FA4 located in the second lead portion D2. The second internal electrode layer 32 further has a fifth side surface inclined portion FWB3 located in the third lead portion D3 and a sixth side surface inclined portion FWB4 located in the fourth lead portion D4.

[0249] This ensures a long path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0250] Moisture such as plating solution may penetrate through the interface between the laminate 10 and the external electrode layers. By providing the fifth inclined portion FA3, the sixth inclined portion FA4, the fifth side surface inclined portion FWB3, and the sixth side surface inclined portion FWB4, it is possible to lengthen the distance of the penetration path through this interface to the end of the internal electrode layer 30. Therefore, it is possible to increase the capacitance and ensure moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0251] Furthermore, moisture such as plating solution may penetrate from the surface of the external electrode 40 through the thickness direction of the external electrode 40. By providing the fifth inclined portion FA3, the sixth inclined portion FA4, the fifth side surface inclined portion FWB3, and the sixth side surface inclined portion FWB4, the end of the internal electrode layer 30 can be positioned closer to the center in the height direction of the laminate 10, where the thickness of the external electrode 40 in the length direction L usually tends to be large. Therefore, it is possible to increase the capacitance and ensure moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0252] Furthermore, by providing the fifth inclined portion FA3, the sixth inclined portion FA4, the fifth side surface inclined portion FWB3, and the sixth side surface inclined portion FWB4, the distance from the end of the internal electrode layer 30 to the opposing portion of the internal electrode layer 30 can be increased. This increases the distance of the path for moisture penetration to reach the opposing portion of the internal electrode layer 30. Therefore, the capacitance can be increased and moisture resistance can be ensured without increasing the size of the multilayer ceramic capacitor 1.

[0253] The inclination angle θ of the first inclined portion FA1 and the second inclined portion FA2 is smaller than the inclination angle θ2 of the fifth inclined portion FA3. That is, the inclination angle θ2 of the fifth inclined portion FA3 is larger than the inclination angle θ of the first inclined portion FA1 and the second inclined portion FA2.

[0254] The inclination angle θ2 of the fifth inclined portion FA3 with respect to the first central area EA0, the first area EA1, or the second area EA2 may be, for example, 10° or more, or 15° or more.

[0255] The inclination angle θ of the first inclined portion FA1 and the second inclined portion FA2 is smaller than the inclination angle θ2 of the sixth inclined portion FA4. That is, the inclination angle θ2 of the sixth inclined portion FA4 is larger than the inclination angle θ of the first inclined portion FA1 and the second inclined portion FA2.

[0256] The inclination angle θ2 of the sixth inclined portion FA4 with respect to the first central area EA0, the first area EA1, or the second area EA2 may be, for example, 10° or more, or 15° or more.

[0257] The inclination angle θ3 of the third side surface inclined portion FWB1 and the fourth side surface inclined portion FWB2 is smaller than the inclination angle θ4 of the fifth side surface inclined portion FWB3. That is, the inclination angle θ4 of the fifth side surface inclined portion FWB3 is larger than the inclination angle θ3 of the third side surface inclined portion FWB1 and the fourth side surface inclined portion FWB2.

[0258] The inclination angle θ4 of the fifth side inclined portion FWB3 relative to the second central region EB0, the third side region EWB1, or the fourth side region EWB2 may be, for example, 10° or more, or 15° or more.

[0259] The inclination angle θ3 of the third side surface inclined portion FWB1 and the fourth side surface inclined portion FWB2 is smaller than the inclination angle θ4 of the sixth side surface inclined portion FWB4. That is, the inclination angle θ4 of the sixth side surface inclined portion FWB4 is larger than the inclination angle θ3 of the third side surface inclined portion FWB1 and the fourth side surface inclined portion FWB2.

[0260] The inclination angle θ4 of the sixth side inclined portion FWB4 relative to the second central region EB0, the third side region EWB1, or the fourth side region EWB2 may be, for example, 10° or more, or 15° or more.

[0261] In addition, FIG. 4B shows the inclination angle θ2 of the sixth inclined portion FA4 with respect to the first central region EA0, the first region EA1, and the second region EA2 in the first internal electrode layer 31 as a representative of the above-mentioned inclination angle θ2.

[0262] Figure 5B shows the inclination angle θ4 of the sixth side inclined portion FWB4 in the second internal electrode layer 32 relative to the second central region EB0, the third side region EWB1, and the fourth side region EWB2 as a representative of the above-mentioned inclination angle θ4.

[0263] This ensures a longer path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0264] As shown in Figures 4A to 5C, the laminate 10 also has exposed portions Ep exposed from the first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D, a first covering portion C1 covered by the first external electrode, a second covering portion C2 covered by the second external electrode 40B, a third covering portion CW1 covered by the third external electrode 40C, and a fourth covering portion CW2 covered by the fourth external electrode 40D.

[0265] The distance L1 in the longitudinal direction L of the exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B corresponds to the distance L1 between the first external electrode 40A and the second external electrode 40B.

[0266] In this embodiment, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is longer than the maximum distance T1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first covering portion C1. Also, in this embodiment, the distance T0 in the stacking direction T at the center of the length direction L of the exposed portion Ep is longer than the maximum distance T1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second covering portion C2.

[0267] The distance Lw1 in the width direction W of the exposed portion Ep exposed from the third external electrode 40C and the fourth external electrode 40D corresponds to the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D.

[0268] In this embodiment, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is longer than the maximum distance TW1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the third covering portion CW1. Also, in this embodiment, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is longer than the maximum distance TW1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the fourth covering portion CW2.

[0269] In this embodiment, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is the maximum distance in the stacking direction T at the exposed portion Ep of the laminate 10.

[0270] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0271] The distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is preferably 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first covering portion C1. For example, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first covering portion C1.

[0272] More preferably, the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1. Note that in this embodiment, the distance in the stacking direction T connecting the flat portion PA1 and the flat portion PB1 described below is the above-mentioned maximum distance T1.

[0273] The distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is preferably 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second covering portion C2. For example, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second covering portion C2.

[0274] More preferably, the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covering portion C2. Note that in this embodiment, the distance in the stacking direction T connecting the flat portion PA2 and the flat portion PB2 described below is the above-mentioned maximum distance T1.

[0275] The distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep is preferably 103% or less of the maximum distance TW1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the third covering portion CW1. For example, the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance TW1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the third covering portion CW1.

[0276] More preferably, the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance TW1 in the stacking direction T connecting the surface on the first main surface TS1 side and the surface on the second main surface TS2 side of the third covering portion CW1. Note that in this embodiment, the distance in the stacking direction T connecting the flat portion PWA1 and the flat portion PWB1 described below is the above-mentioned maximum distance TW1.

[0277] The distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep is preferably 103% or less of the maximum distance TW1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the fourth covering portion CW2. For example, the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep may be 101% or more and 103% or less of the maximum distance TW1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the fourth covering portion CW2.

[0278] More preferably, the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep may be 101% or more and 103% or more of the maximum distance TW1 in the stacking direction T connecting the surface on the first main surface TS1 side and the surface on the second main surface TS2 side of the fourth covering portion CW2. Note that in this embodiment, the distance in the stacking direction T connecting the flat portion PWA2 and the flat portion PWB2 described below is the above-mentioned maximum distance TW1.

[0279] The distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first external electrode 40A. Furthermore, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second external electrode 40B.

[0280] The distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is shorter than the maximum distance TW2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the third external electrode 40C. Furthermore, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is shorter than the maximum distance TW2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the fourth external electrode 40D.

[0281] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0282] The ratio of the thickness in the stacking direction T of the first central region EA0 of the first internal electrode layer 31 to the thickness in the stacking direction T of the first region EA1 may be set to be larger than the ratio of the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep of the laminate 10 to the maximum distance T1 in the stacking direction T of the first covered portion C1 of the laminate 10. The ratio of the thickness in the stacking direction T of the first central region EA0 of the first internal electrode layer 31 to the thickness of the second region EA2 may be set to be larger than the ratio of the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep of the laminate 10 to the maximum distance T1 in the stacking direction T of the second covered portion C2 of the laminate 10.

[0283] The ratio of the thickness in the stacking direction T of the second central region EB0 of the second internal electrode layer 32 to the thickness in the stacking direction T of the third side surface region EWB1 may be set to be larger than the ratio of the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep of the multilayer body 10 to the maximum distance TW1 in the stacking direction T of the third covered portion CW1 of the multilayer body 10. The ratio of the thickness in the stacking direction T of the second central region EB0 of the second internal electrode layer 32 to the thickness in the stacking direction T of the fourth side surface region EWB2 may be set to be larger than the ratio of the distance T0 in the stacking direction T at the center in the length direction L and the center in the width direction W of the exposed portion Ep of the multilayer body 10 to the maximum distance TW1 in the stacking direction T of the fourth covered portion CW2 of the multilayer body 10.

[0284] As shown in FIG. 4A , the first main surface TS1 has a first exposed surface EpsA exposed from the first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D, a first covered surface C1sA covered by the first external electrode 40A, and a second covered surface C2sA covered by the second external electrode 40B, and as shown in FIG. 5A , a first side covered surface CW1sA covered by the third external electrode 40C and a second side covered surface CW2sA covered by the fourth external electrode 40D.

[0285] As shown in Figures 1 and 4A, the first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first inclined surface FC1 connecting the first flat surface PA0 and the first covered surface C1sA, and a second inclined surface FC2 connecting the first flat surface PA0 and the second covered surface C2sA.

[0286] In this embodiment, a flat portion PA1 is formed on the first coated surface C1sA toward the center of the laminate, and a first inclined surface FC1 connects the first flat surface PA0 and the flat portion PA1. Also, a flat portion PA2 is formed on the second coated surface C2sA toward the center of the laminate, and a second inclined surface FC2 connects the first flat surface PA0 and the flat portion PA2.

[0287] That is, the first main surface TS1 of this embodiment has a planar portion PA1 on the first end face LS1 side, a planar portion PA2 on the second end face LS2 side, a first planar surface PA0 arranged between planar portions PA1 and PA2 and protruding from planar portions PA1 and PA2, a first inclined surface FC1 connecting the first planar surface PA0 and the planar portion PA1, and a second inclined surface FC2 connecting the first planar surface PA0 and the planar portion PA2.

[0288] As shown in Figures 1 and 5A, the first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first side surface inclined surface FWC1 connecting the first flat surface PA0 and the first side surface covering surface CW1sA, and a second side surface inclined surface FWC2 connecting the first flat surface PA0 and the second side surface covering surface CW2sA.

[0289] In this embodiment, a flat portion PWA1 is formed on the first side covering surface CW1sA toward the center of the laminate, and a first side inclined surface FWC1 connects the first flat surface PA0 to the flat portion PWA1. Also, a flat portion PWA2 is formed on the second side covering surface CW2sA toward the center of the laminate, and a second side inclined surface FWC2 connects the first flat surface PA0 to the flat portion PWA2.

[0290] That is, the first main surface TS1 of this embodiment has a planar portion PWA1 on the first end face LS1 side, a planar portion PWA2 on the second end face LS2 side, a first planar surface PA0 arranged between planar portions PWA1 and PWA2 and protruding from planar portions PWA1 and PWA2, a first side-side inclined surface FWC1 connecting the first planar surface PA0 and planar portion PWA1, and a second side-side inclined surface FWC2 connecting the first flat surface PA0 and planar portion PWA2.

[0291] As shown in FIG. 4A , the second main surface TS2 has a second exposed surface EpsB exposed from the first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D, a third covered surface C1sB covered by the first external electrode 40A, a fourth covered surface C2sB covered by the second external electrode 40B, a third side surface covered surface CW1sB covered by the third external electrode 40C, and a fourth side surface covered surface CW2sB covered by the fourth external electrode 40D.

[0292] The second exposed surface EpsB has a second flat surface PB0 parallel to the stacking direction T, a third inclined surface FC3 connecting the second flat surface PB0 and the third covered surface C1sB, and a fourth inclined surface FC4 connecting the second flat surface PB0 and the fourth covered surface C2sB.

[0293] In this embodiment, a flat portion PB1 is formed on the third coated surface C1sB toward the center of the stack, and a third inclined surface FC3 connects the second flat surface PB0 and the flat portion PB1. Also, a flat portion PB2 is formed on the fourth coated surface C2sB toward the center of the stack, and a fourth inclined surface FC4 connects the second flat surface PB0 and the flat portion PB2.

[0294] That is, the second main surface TS2 of this embodiment has a planar portion PB1 on the first end face LS1 side, a planar portion PB2 on the second end face LS2 side, a second planar surface PB0 arranged between the planar portions PB1 and PB2 and protruding from the planar portions PB1 and PB2, a third inclined surface FC3 connecting the second planar surface PB0 and the planar portion PB1, and a fourth inclined surface FC4 connecting the second planar surface PB0 and the planar portion PB2.

[0295] The second exposed surface EpsB has a second flat surface PB0 parallel to the stacking direction T, a third side surface inclined surface FWC3 connecting the second flat surface PB0 and the third side surface covering surface CW1sB, and a fourth side surface inclined surface FWC4 connecting the second flat surface PB0 and the fourth side surface covering surface CW2sB.

[0296] In this embodiment, a flat portion PWB1 is formed on the third side covering surface CW1sB toward the center of the laminate, and a third side inclined surface FWC3 connects the second flat surface PB0 and the flat portion PWB1. Also, a flat portion PWB2 is formed on the fourth side covering surface CW2sB toward the center of the laminate, and a fourth side inclined surface FWC4 connects the second flat surface PB0 and the flat portion PWB2.

[0297] That is, the second main surface TS2 of this embodiment has a planar portion PWB1 on the first end face LS1 side, a planar portion PWB2 on the second end face LS2 side, a second planar surface PB0 arranged between planar portions PWB1 and PWB2 and protruding from planar portions PWB1 and PWB2, a third side inclined surface FWC3 connecting the second planar surface PB0 and planar portion PWB1, and a fourth side inclined surface FWC4 connecting the second flat surface PB0 and planar portion PWB2.

[0298] This makes it easier to ensure the areas of the first central region EA0 and the second central region EB0 with high coverage corresponding to the first flat surface PA0 or the second flat surface PB0, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1. Furthermore, by forming the flat surfaces, it is possible to suppress poor suction during mounting.

[0299] 4B , in the longitudinal direction L of the LT cross section (a cross section parallel to the stacking direction T and the longitudinal direction L) at the center of the width direction W, the distance Lt1 in the longitudinal direction L of the first inclined surface FC1 and the distance Lt2 in the longitudinal direction L of the second inclined surface FC2 are shorter than the distance Lt0 in the longitudinal direction L of the first flat surface PA0. The distance Lt1 in the longitudinal direction L of the third inclined surface FC3 and the distance Lt2 in the longitudinal direction L of the fourth inclined surface FC4 are shorter than the distance Lt0 in the longitudinal direction L of the second flat surface PB0.

[0300] The distance Lwt1 in the width direction W of the first side inclined surface FWC1 and the distance Lwt2 in the width direction W of the second side inclined surface FWC2 are shorter than the distance Lwt0 in the width direction W of the first flat surface PA0. The distance Lwt1 in the width direction W of the third side inclined surface FWC3 and the distance Lwt2 in the width direction W of the fourth side inclined surface FWC4 are shorter than the distance Lt0 in the length direction L of the second flat surface PB0.

[0301] This makes it easier to ensure the areas of the first central region EA0 and the second central region EB0, which have high coverage, corresponding to the first flat surface PA0 or the second flat surface PB0, and thus makes it possible to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. Furthermore, by ensuring the areas of the flat surfaces, it is possible to suppress poor suction during mounting.

[0302] In this embodiment, the distance Lt0 of the first flat surface PA0 in the length direction L is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. Also, the distance Lt0 of the second flat surface PB0 in the length direction L is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B.

[0303] In this way, it is preferable that the distance Lt0 in the longitudinal direction L of the first flat surface PA0 and the second flat surface PB0 is arranged within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B.

[0304] The end 40AE of the first external electrode 40A may be located on the first inclined surface FC1 and the third inclined surface FC3, or may be located on the flat surface PA1 and the flat surface PB1 closer to the first end face LS1 than the first inclined surface FC1 and the third inclined surface FC3. The end 40BE of the second external electrode 40B may be located on the second inclined surface FC2 and the fourth inclined surface FC4, or may be located on the flat surface PA2 and the flat surface PB2 closer to the second end face LS2 than the second inclined surface FC2 and the fourth inclined surface FC4.

[0305] In this embodiment, the end 40AE of the first external electrode 40A is located near the boundary between the first inclined surface FC1 and the flat portion PA1 and near the boundary between the third inclined surface FC3 and the flat portion PB1. In this embodiment, the end 40BE of the second external electrode 40B is located near the boundary between the second inclined surface FC2 and the flat portion PA2 and near the boundary between the fourth inclined surface FC4 and the flat portion PB2.

[0306] In this embodiment, in the width direction W of the WT cross section (a cross section on a plane parallel to the stacking direction T and the width direction W) at the center of the length direction L, the distance Lwt0 of the first flat surface PA0 is shorter than the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D. Also, in the width direction W, the distance Lwt0 of the second flat surface PB0 is shorter than the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D.

[0307] In this way, it is preferable that the distance Lwt0 in the width direction W between the first flat surface PA0 and the second flat surface PB0 is arranged within the range of the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D.

[0308] The end 40CE of the third external electrode 40C may be located on the first side surface inclined surface FWC1 and the third side surface inclined surface FWC3, or on the flat surface portions PWA1 and PWB1 closer to the first end face LS1 than the first side surface inclined surface FWC1 and the third side surface inclined surface FWC3. The end 40DE of the fourth external electrode 40D may be located on the second side surface inclined surface FWC2 and the fourth side surface inclined surface FWC4, or on the flat surface portions PWA2 and PWB2 closer to the second end face LS2 than the second side surface inclined surface FWC2 and the fourth side surface inclined surface FWC4.

[0309] In this embodiment, the end 40CE of the third external electrode 40C is located near the boundary between the first side inclined surface FWC1 and the flat portion PWA1 and near the boundary between the third side inclined surface FWC3 and the flat portion PWB1, while the end 40DE of the fourth external electrode 40D is located near the boundary between the second side inclined surface FWC2 and the flat portion PWA2 and near the boundary between the fourth side inclined surface FWC4 and the flat portion PWB2.

[0310] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0311] The inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 may be 2° or more and 5° or less.

[0312] The inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 may be 2° or more and 5° or less.

[0313] The inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 may be 2° or more and 5° or less.

[0314] The inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 may be 2° or more and 5° or less.

[0315] The inclination angle φ2 of the first side inclined surface FWC1 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ2 of the first side inclined surface FWC1 with respect to the first flat surface PA0 may be 1° or more and 10° or less. More preferably, the inclination angle φ2 of the first side inclined surface FWC1 with respect to the first flat surface PA0 may be 2° or more and 5° or less.

[0316] The inclination angle φ2 of the second side surface inclined surface FWC2 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ2 of the second side surface inclined surface FWC2 with respect to the first flat surface PA0 may be 1° or more and 10° or less. More preferably, the inclination angle φ2 of the second side surface inclined surface FWC2 with respect to the first flat surface PA0 may be 2° or more and 5° or less.

[0317] The inclination angle φ2 of the third side surface inclined surface FWC3 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ2 of the third side surface inclined surface FWC3 with respect to the second flat surface PB0 may be 1° or more and 10° or less. More preferably, the inclination angle φ2 of the third side surface inclined surface FWC3 with respect to the second flat surface PB0 may be 2° or more and 5° or less.

[0318] The inclination angle φ2 of the fourth side surface inclined surface FWC4 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ2 of the fourth side surface inclined surface FWC4 with respect to the second flat surface PB0 may be 1° or more and 10° or less. More preferably, the inclination angle φ2 of the fourth side surface inclined surface FWC4 with respect to the second flat surface PB0 may be 2° or more and 5° or less.

[0319] FIG. 4A shows the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 on ​​the second main surface TS2 as a representative of the inclination angles φ described above.

[0320] FIG. 5C shows the inclination angle φ2 of the fourth side inclined surface FWC4 with respect to the second flat surface PB0 on ​​the second main surface TS2 as a representative of the inclination angle φ2 described above.

[0321] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0322] Specifically, by setting the inclination angle φ to 1° or more, preferably 2° or more, it is possible to ensure an area for increasing the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0. Furthermore, by setting the inclination angle φ to 10° or less, preferably 5° or less, it is possible to prevent the surface of the laminate 10 from expanding too much in the stacking direction T and protruding outward beyond the surfaces of the external electrodes 40.

[0323] Specifically, by setting the inclination angle φ2 to 1° or more, preferably 2° or more, it is possible to ensure an area for increasing the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0. Furthermore, by setting the inclination angle φ2 to 10° or less, preferably 5° or less, it is possible to prevent the surface of the laminate 10 from expanding too much in the stacking direction T and protruding outward beyond the surfaces of the external electrodes 40.

[0324] More specifically, by setting the inclination angle φ within the above-mentioned range, it becomes easy to set the relationship between the thickness of each of the first central region EA0 and the second central region and the thickness of each of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 within the range of this embodiment. Also, by setting the inclination angle φ within the above-mentioned range, it becomes easy to set the relationship between the distance T0 at the center of the exposed portion of the laminate 10 and the maximum distance T1 in the covered portion of the laminate within the range of this embodiment.

[0325] Furthermore, by setting the inclination angle φ2 within the above-mentioned range, it becomes easy to set the relationship between the thickness of each of the first central region EA0 and the second central region and the thickness of each of the first side region EWA1, the second side region EWA2, the third side region EWB1, and the fourth side region EWB2 within the range of this embodiment. Furthermore, by setting the inclination angle φ2 within the above-mentioned range, it becomes easy to set the relationship between the distance T0 at the center of the exposed portion of the laminate 10 and the maximum distance TW1 in the covered portion of the laminate within the range of this embodiment.

[0326] The first flat surface PA0 is preferably approximately parallel to a plane perpendicular to the stacking direction T. The first flat surface PA0 and the planar portions PA1 and PA2 are preferably approximately parallel to each other. More preferably, the first flat surface PA0 and the planar portions PA1 and PA2 are approximately parallel to a plane perpendicular to the stacking direction T. The first flat surface PA0 and the planar portions PWA1 and PWA2 are preferably approximately parallel to each other. More preferably, the first flat surface PA0 and the planar portions PWA1 and PWA2 are approximately parallel to a plane perpendicular to the stacking direction T.

[0327] The second flat surface PB0 is preferably approximately parallel to a plane perpendicular to the stacking direction T. The second flat surface PB0 and the planar portion PB1 and the planar portion PB2 are preferably approximately parallel to each other. More preferably, the second flat surface PB0 and the planar portion PB1 and the planar portion PB2 are approximately parallel to a plane perpendicular to the stacking direction T. The second flat surface PB0 and the planar portion PWB1 and the planar portion PWB2 are preferably approximately parallel to each other. More preferably, the second flat surface PB0 and the planar portion PWB1 and the planar portion PWB2 are approximately parallel to a plane perpendicular to the stacking direction T.

[0328] This makes it possible to prevent the formation of portions of the multilayer ceramic capacitor 1 that are locally large in size, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0329] As shown in Figure 4A, the step distance tf in the stacking direction T between the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 and the flat portion PA1 and the flat portion PA2, i.e., the protrusion height tf (one-side bulge dimension of the laminate) of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2, is preferably smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the first main surface TS1.

[0330] It is preferable that the step distance tf in the stacking direction T between the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 and the planar portion PB1 and the planar portion PB2, i.e., the protrusion height tf (one-side bulge dimension of the laminate) of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4, is smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the second main surface TS2.

[0331] As shown in Figure 4A, the step distance tf (see Figure 4A) in the stacking direction T between the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 and the flat portion PA1 and the flat portion PA2, i.e., the protrusion height tf (one-side bulge dimension of the laminate) of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2, is preferably smaller than the thickness twg (see Figure 5C) in the stacking direction T of the third external electrode 40C and the fourth external electrode 40D arranged on the first main surface TS1.

[0332] It is preferable that the step distance tf (see Figure 4A) in the stacking direction T between the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 and the flat portion PB1 and the flat portion PB2, i.e., the protrusion height tf (one-side bulge dimension of the laminate) of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4, is smaller than the thickness twg (see Figure 5C) in the stacking direction T of the third external electrode 40C and the fourth external electrode 40D arranged on the second main surface TS2.

[0333] As shown in Figure 5C, the step distance twf (see Figure 5C) in the stacking direction T between the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2 and the planar portion PWA1 and the planar portion PWA2, i.e., the protrusion height twf (one-sided bulge dimension of the laminate) of the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2, is preferably smaller than the thickness tg (see Figure 4A) in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the first main surface TS1.

[0334] It is preferable that the step distance twf (see Figure 5C) in the stacking direction T between the second flat surface PB0 formed by the third side inclined surface FWC3 and the fourth side inclined surface FWC4 and the planar portion PWB1 and the planar portion PWB2, i.e., the protrusion height twf (one-sided bulge dimension of the laminate) of the second flat surface PB0 formed by the third side inclined surface FWC3 and the fourth side inclined surface FWC4, is smaller than the thickness tg (see Figure 4A) in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the second main surface TS2.

[0335] As shown in Figure 5C, the step distance twf in the stacking direction T between the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2 and the planar portion PWA1 and the planar portion PWA2, i.e., the protrusion height twf (one-sided bulge dimension of the laminate) of the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2, is preferably smaller than the thickness twg in the stacking direction T of the third external electrode 40C and the fourth external electrode 40D arranged on the first main surface TS1.

[0336] It is preferable that the step distance twf in the stacking direction T between the second flat surface PB0 formed by the third side inclined surface FWC3 and the fourth side inclined surface FWC4 and the planar portion PWB1 and the planar portion PWB2, i.e., the protrusion height twf (one-sided bulge dimension of the laminate) of the second flat surface PB0 formed by the third side inclined surface FWC3 and the fourth side inclined surface FWC4, is smaller than the thickness twg in the stacking direction T of the third external electrode 40C and the fourth external electrode 40D arranged on the second main surface TS2.

[0337] This makes it possible to increase the capacitance while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0338] The first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 preferably has a protrusion height tf of 2.9 μm or more and 14.8 μm or less. The first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 may have a protrusion height tf of 2.9 μm or more and 12.6 μm or less.

[0339] The second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 preferably has a protrusion height tf of 2.9 μm or more and 14.8 μm or less. The second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 may also have a protrusion height tf of 2.9 μm or more and 12.6 μm or less.

[0340] The first flat surface PA0 formed by the first lateral inclined surface FWC1 and the second lateral inclined surface FWC2 preferably has a protrusion height twf of 2.9 μm or more and 14.8 μm or less. The first flat surface PA0 formed by the first lateral inclined surface FWC1 and the second lateral inclined surface FWC2 may have a protrusion height twf of 2.9 μm or more and 12.6 μm or less.

[0341] The second flat surface PB0 formed by the third lateral inclined surface FWC3 and the fourth lateral inclined surface FWC4 preferably has a protrusion height twf of 2.9 μm or more and 14.8 μm or less. The second flat surface PB0 formed by the third lateral inclined surface FWC3 and the fourth lateral inclined surface FWC4 may have a protrusion height twf of 2.9 μm or more and 12.6 μm or less.

[0342] The protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the internal electrode layers 30. More preferably, the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is larger than the sum Tt (=Te+Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0343] More preferably, the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0344] The protrusion height tf of the second flat surface PBO formed by the third inclined surface FC3 and the fourth inclined surface FC4 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the internal electrode layers 30. More preferably, the protrusion height tf of the second flat surface PBO formed by the third inclined surface FC3 and the fourth inclined surface FC4 is larger than the sum Tt (=Te+Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0345] More preferably, the protrusion height tf of the second flat surface PBO formed by the third inclined surface FC3 and the fourth inclined surface FC4 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height tf of the second flat surface PBO formed by the third inclined surface FC3 and the fourth inclined surface FC4 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0346] The protrusion height twf of the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the internal electrode layers 30. More preferably, the protrusion height twf of the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2 is larger than the sum Tt (=Te+Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0347] More preferably, the protrusion height twf of the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height twf of the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2 may be at least three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0348] The protrusion height twf of the second flat surface PBO formed by the third side surface inclined surface FWC3 and the fourth side surface inclined surface FWC4 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the internal electrode layers 30. More preferably, the protrusion height twf of the second flat surface PBO formed by the third side surface inclined surface FWC3 and the fourth side surface inclined surface FWC4 is larger than the sum Tt (=Te+Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0349] More preferably, the protrusion height twf of the second flat surface PBO formed by the third side surface inclined surface FWC3 and the fourth side surface inclined surface FWC4 is equal to or greater than twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Also, the protrusion height twf of the second flat surface PBO formed by the third side surface inclined surface FWC3 and the fourth side surface inclined surface FWC4 may be equal to or greater than three times the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0350] This makes it possible to take advantage of the steps created by the inclined surfaces to secure areas where the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 can be increased, thereby sufficiently increasing coverage, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0351] The thickness t01 in the stacking direction T in the first flat surface PA0 region of the first main surface side outer layer portion 12 is smaller than the thickness t11 in the stacking direction T in the first coated surface C1sA region of the first main surface side outer layer portion 12 and the thickness t21 in the stacking direction T in the second coated surface C2sA region of the first main surface side outer layer portion 12.

[0352] The thickness t02 in the stacking direction T in the second flat surface PB0 region of the second main surface side outer layer portion 13 is smaller than the thickness t12 in the stacking direction T in the third coating surface C1sB region of the second main surface side outer layer portion 13 and the thickness t22 in the stacking direction T in the fourth coating surface C2sB region of the second main surface side outer layer portion 13.

[0353] The thickness t01 in the stacking direction T in the first flat surface PA0 region of the first main surface side outer layer portion 12 is smaller than the thickness tw11 in the stacking direction T in the first side surface side covering surface CW1sA region of the first main surface side outer layer portion 12 and the thickness tw21 in the stacking direction T in the second side surface side covering surface CW2sA region of the first main surface side outer layer portion 12.

[0354] The thickness t02 in the stacking direction T in the second flat surface PB0 region of the second main surface side outer layer portion 13 is smaller than the thickness tw12 in the stacking direction T in the third side surface side covering surface CW1sB region of the second main surface side outer layer portion 13 and the thickness tw22 in the stacking direction T in the fourth side surface side covering surface CW2sB region of the second main surface side outer layer portion 13.

[0355] This increases the capacitance without increasing the size of the multilayer ceramic capacitor 1, while ensuring a longer distance between the external electrode 40 and the internal electrode layer 30, thereby suppressing the concentration of the electric field, thereby suppressing a decrease in the reliability of the multilayer ceramic capacitor 1 due to electric field concentration.

[0356] Furthermore, by ensuring that the distances between thicknesses t11, t21, t12, and t22 are longer, even if a crack occurs in the laminate 10 near the end of the external electrode 40, such as near the boundary between the exposed portion Ep of the laminate 10 and the first covering portion C1 or the second covering portion C2, the crack can be prevented from reaching the internal electrode.

[0357] Furthermore, by ensuring that the distances between the thicknesses tw11, tw21, tw12, and tw22 are longer, even if a crack occurs in the laminate 10 near the end of the external electrode 40, such as near the boundary between the exposed portion Ep of the laminate 10 and the third covering portion CW1 or the fourth covering portion CW2, the crack can be prevented from reaching the internal electrode.

[0358] In this embodiment, by having the above-mentioned inclined surfaces, flat surfaces as part of the surface of the laminate 10 are arranged in a raised manner on both the first main surface TS1 and the second main surface TS2, but a flat surface as part of the surface of the laminate 10 may also be arranged in a raised manner on either the first main surface TS1 or the second main surface TS2.

[0359] As shown in Figures 4A and 4B, the thickness in the longitudinal direction L at the center of the stacking direction T of the first external electrode 40A is thicker than the thickness in the longitudinal direction L on the first main surface TS1 side of the stacking direction T of the first external electrode 40A and the thickness in the longitudinal direction L on the second main surface TS2 side of the stacking direction T of the first external electrode 40A.

[0360] Also, as shown in Figures 6A and 6B, the thickness in the length direction L at the center in the width direction W of the first external electrode 40A is thicker than the thickness in the length direction L on the first side surface WS1 side in the width direction W of the first external electrode 40A and the thickness in the length direction L on the second side surface WS2 side in the width direction W of the first external electrode 40A.

[0361] As shown in Figures 4A and 4B, the thickness in the longitudinal direction L at the center of the stacking direction T of the second external electrode 40B is thicker than the thickness in the longitudinal direction L on the first main surface TS1 side of the stacking direction T of the second external electrode 40B and the thickness in the longitudinal direction L on the second main surface TS2 side of the stacking direction T of the second external electrode 40B.

[0362] Also, as shown in Figures 6A and 6B, the thickness in the length direction L at the center in the width direction W of the second external electrode 40B is thicker than the thickness in the length direction L on the first side surface WS1 side in the width direction W of the second external electrode 40B and the thickness in the length direction L on the second side surface WS2 side in the width direction W of the second external electrode 40B.

[0363] This ensures a longer path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0364] The first internal electrode layer 31 of this embodiment preferably has the above-mentioned first central region EA0 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, which has higher coverage and a greater thickness than the first region EA1 and the second region EA2.

[0365] However, the first internal electrode layer 31 may have the above-mentioned first central region EA0, which has a higher coverage and a greater thickness than the first region EA1 and the second region EA2, at least in either the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also has the effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0366] The second internal electrode layer 32 of this embodiment preferably has the above-mentioned second central region EB0 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, which has higher coverage and a greater thickness than the third region EB1 and the fourth region EB2.

[0367] However, the second internal electrode layer 32 may have the above-mentioned second central region EB0, which has higher coverage and is thicker than the third region EB1 and the fourth region EB2, at least in either the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also has the effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0368] The first internal electrode layer 31 of this embodiment preferably has the above-mentioned first central region EA0 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, which has higher coverage and a greater thickness than the first side surface side region EWA1 and the second side surface side region EWA2.

[0369] However, the first internal electrode layer 31 may have the above-mentioned first central region EA0, which has a higher coverage and a greater thickness than the first side surface region EWA1 and the second side surface region EWA2, at least in either the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also has the effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0370] The second internal electrode layer 32 of this embodiment preferably has the above-mentioned second central region EB0 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, which has higher coverage and a greater thickness than the third side surface side region EWB1 and the fourth side surface side region EWB2.

[0371] However, the second internal electrode layer 32 may have the above-mentioned second central region EB0, which has higher coverage and is thicker than the third side surface side region EWB1 and the fourth side surface side region EWB2, at least in either the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also has the effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0372] In this embodiment, the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, the fourth inclined portion FB2, the fifth inclined portion FA3, and the sixth inclined portion FA4 are arranged in the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113. However, the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, the fourth inclined portion FB2, the fifth inclined portion FA3, and the sixth inclined portion FA4 may be arranged in at least one portion of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113.

[0373] In this embodiment, the first side surface side inclined portion FWA1, the second side surface side inclined portion FWA2, the third side surface side inclined portion FWB1, the fourth side surface side inclined portion FWB2, the fifth side surface side inclined portion FWB3, and the sixth side surface side inclined portion FWB4 are arranged in the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113. However, the first side surface side inclined portion FWA1, the second side surface side inclined portion FWA2, the third side surface side inclined portion FWB1, the fourth side surface side inclined portion FWB2, the fifth side surface side inclined portion FWB3, and the sixth side surface side inclined portion FWB4 may be arranged in at least one portion of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113.

[0374] The first internal electrode layer 31 of this embodiment has, at least in the central opposing electrode portion 111E, the above-mentioned first central region EA0 which has higher coverage and a greater thickness than the first region EA1, the second region EA2, the first side region EWA1 and the second side region EWA2.

[0375] The second internal electrode layer 32 of this embodiment has, at least in the central opposing electrode portion 111E, the above-mentioned second central region EB0 which has higher coverage and a greater thickness than the third region EB1, the fourth region EB2, the third side region EWB1 and the fourth side region EWB2.

[0376] <Measurement of Various Parameters> Hereinafter, methods for measuring various parameters will be described. Various parameters can be measured by the following methods.

[0377] <Method of Measuring Thickness of Internal Electrode Layers and Dielectric Layers> Hereinafter, a method of measuring the thickness of the internal electrode layers 30 of the multilayer ceramic capacitor 1 in the lamination direction will be described.

[0378] First, the multilayer ceramic capacitor 1 is polished from the first side surface WS1 side or the second side surface WS2 side to expose the LT cross section exposing the opposing electrode portion 11E of the laminate 10. If necessary, the exposed cross section at the observation position is etched to remove the internal electrode layer 30 stretched by polishing.

[0379] The exposed cross section is observed using a scanning electron microscope (SEM) at measurement points M1 to M6, which will be described later. Note that, for example, if only the first main surface side inner layer portion 112 has the above-mentioned first central region EA0 and second central region EB0, which have high coverage and a large thickness, measurement points M1 to M3 are observed using the SEM.

[0380] Measurement points are set in areas with high coverage and high thickness, and areas with low coverage and low thickness. The measured values ​​are averaged over each area. The measurement points are preferably set according to the structure of the multilayer ceramic capacitor.

[0381] Measurement points M1 to M3 are set on the first main surface side inner layer portion 112.

[0382] The measurement point M1 is a portion including the first region EA1 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32. The measurement point M2 is a portion including the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. The measurement point M3 is a portion including the second region EA2 of the first internal electrode layer 31 and the fourth region EB2 of the second internal electrode layer 32.

[0383] Measurement points M4 to M6 are set on the second main surface side inner layer portion 113.

[0384] The measurement point M4 is a portion including the first region EA1 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32. The measurement point M5 is a portion including the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. The measurement point M6 is a portion including the second region EA2 of the first internal electrode layer 31 and the fourth region EB2 of the second internal electrode layer 32.

[0385] Measurement points M1 and M4 are set at the center of the distance Le1 shown in Fig. 4B in the length direction L. Measurement points M2 and M5 are set at the center of the distance Le0 shown in Fig. 4B in the length direction L. Measurement points M3 and M6 are set at the center of the distance Le2 shown in Fig. 4B in the length direction L.

[0386] Measurement points M2 and M5 are measurement points set in areas with high coverage and thick thickness, and measurement points M1, M3, M4, and M6 are measurement points set in areas with low coverage and thin thickness.

[0387] The observation magnification when observing each measurement point is set to a magnification at which the four dielectric layers 20 and the five internal electrode layers 30 can be observed and at which the dielectric layers 20 can be clearly distinguished from the internal electrode layers 30. Fig. 7 is a diagram illustrating an example of an enlarged image by SEM of the cross section of the exposed internal layer portion at the measurement point.

[0388] When measuring the thickness of the internal electrode layers 30 of the multilayer ceramic capacitor 1, first, as shown in Fig. 7, five straight lines La to Le extending in the lamination direction of the laminate 10 are drawn at equal intervals of a pitch S on an enlarged image of the cross section of the multilayer ceramic capacitor 1. The pitch S may be determined to be about 5 to 10 times the thickness of the internal electrode layers 30 to be measured, and for example, when measuring an internal electrode having a thickness of about 0.5 µm, the pitch S is set to 2.5 µm.

[0389] Next, the thickness of the internal electrode layer 30 is measured on each of the lines La to Le. However, if an internal electrode layer is missing on each of the lines La to Le and the dielectric layers 20 sandwiching the internal electrode layer 30 are connected to each other, or if the enlarged image of the measurement position is unclear, a new line is drawn and the thickness of the internal electrode layer 30 is measured.

[0390] For example, when measuring the thickness of the internal electrode layer 30, the thickness d1 on the line La, the thickness d2 on the line Lb, the thickness d3 on the line Lc, the thickness d4 on the line Ld, and the thickness d5 on the line Le are measured as shown in Fig. 7. Then, for each of the measurement points in the first main surface side internal layer portion 112 and the second main surface side internal layer portion 113, the thickness of each of the five internal electrode layers 30 is measured by the above method, and the average value thereof is set to the thickness of the internal electrode layer 30 of this embodiment.

[0391] For example, when measuring the thickness of the first central region EA0 and the second central region EB0, which are regions with high coverage and thick thickness, the thickness is measured at 25 points (5 locations x 5 layers) at each of measurement points M2 and M5, and the average value of the total 50 points is used as the thickness of the first central region EA0 and the second central region EB0 in this embodiment.

[0392] For example, when measuring the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, which are regions with low coverage and thin thickness, the thickness is measured at 25 points (5 locations x 5 layers) at each of measurement points M1, M3, M4, and M6, and the average value of a total of 100 points is used as the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 in this embodiment.

[0393] The thickness of the dielectric layer 20 is also measured in the same manner as the internal electrode layer 30. When measuring the thickness of the dielectric layer 20, as shown in Fig. 7, the thickness D1 on the line La, the thickness D2 on the line Lb, the thickness D3 on the line Lc, the thickness D4 on the line Ld, and the thickness D5 on the line Le are measured.

[0394] Then, the thickness of each of the four dielectric layers 20 is measured by the above-described method at each measurement point in the first main surface side inner layer portion 112 and each measurement point in the second main surface side inner layer portion 113, and the average value is taken as the thickness of the dielectric layer 20 of this embodiment. The thickness of the dielectric layer 20 can be measured for each of the regions corresponding to the first central region EA0 and the second central region EB0, the region corresponding to the first region EA1 and the third region EB1, and the region corresponding to the second region EA2 and the fourth region EB2.

[0395] By repeating polishing and measurement, measurements can be performed at six measurement points M1 to M6 at three positions: the center position in the width direction W of the first side surface side opposing electrode portion 112E, the center position in the width direction W of the central opposing electrode portion 111E, and the center position in the width direction W of the second side surface side opposing electrode portion 113E.

[0396] Note that measurement points are added depending on the measurement target locations to be measured. For example, if it is desired to measure the thickness of the internal electrode layers 30 in the stacking direction T in the first lead portion D1 and the second lead portion D2, the portions including the measurement target locations are added as measurement points. In this case, too, the measurement is performed in the same manner as described above.

[0397] Similarly, for the WT cross section, measurement points can be set in areas with high coverage and thick thickness, and areas with low coverage and thin thickness, and the thickness of each part of the internal electrode layer 30 can be measured.

[0398] <Coverage Measurement Method> A description will be given of a method for measuring coverage as the coverage rate of the internal electrode layer 30 relative to the dielectric layer 20. Note that the measurement of coverage in this measurement method is also called measurement of line coverage.

[0399] The line coverage of the exposed LT cross section is measured using an optical microscope. The measurement points for measuring the line coverage are the same as the measurement points M1 to M6 described above. However, the magnification for observing each measurement point is 1000x.

[0400] The internal electrode layer 30 has a region where a conductive component is present and a region where a conductive component is not present, such as a hollow portion. The line coverage is calculated as the ratio of the length in the length direction L of the region occupied by the conductive component that actually constitutes the internal electrode layer 30 to the length in the length direction L of the internal electrode layer 30 in an optical microscope image without taking into account the presence or absence of the conductive component, i.e., the ratio of the length in the length direction L of the internal electrode layer 30 excluding the region where the conductive component is not present to the length in the length direction L of the internal electrode layer 30 without taking into account the presence or absence of the conductive component.

[0401] Then, the coverage of the internal electrode layer 30 is measured for each measurement point in the first main surface side internal layer portion 112 and each measurement point in the second main surface side internal layer portion 113, and the average value is taken as the coverage of the internal electrode layer 30 in this embodiment.

[0402] For example, when measuring the coverage of the first central region EA0 and the second central region EB0, the coverage of the internal electrode layer 30 is measured for each of measurement points M2 and M5, and the average value is used as the coverage of the first central region EA0 and the second central region EB0 in this embodiment.

[0403] For example, when measuring the coverage of the first region EA1, the second region EA2, the third region EB1 and the fourth region EB2, the coverage of the internal electrode layer 30 is measured at each of the measurement points M1, M3, M4 and M6, and the average value is used as the coverage of the first region EA1, the second region EA2, the third region EB1 and the fourth region EB2 in this embodiment.

[0404] Note that measurement points are added depending on the measurement target locations to be measured. For example, if you want to measure the coverage of the first draw-out section D1 and the second draw-out section D2, you add the parts that include those measurement target locations as measurement points. In this case, too, the measurement is performed in the same manner as described above.

[0405] Similarly, for the WT cross section, measurement points can be set in areas with high coverage and thick thickness, and areas with low coverage and thin thickness, and the coverage of each part of the internal electrode layer 30 can be measured.

[0406] <Method of measuring distances and angles> Various distances and angles are measured using the exposed LT cross section described above. The distance and angle measurements are performed using a digital microscope.

[0407] <Manufacturing Method> Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The multilayer ceramic capacitor 1 of this embodiment may be manufactured by any method as long as it satisfies the above-described requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0408] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0409] On the dielectric sheet, the conductive paste for the internal electrode layer 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, or the like. In this way, a dielectric sheet on which the patterns of the first internal electrode layer 31 and the second internal electrode layer 32 are formed is prepared. Note that the printing method is not limited to screen printing or the like.

[0410] Here, a method for printing the conductive paste for the internal electrode layers 30 onto the dielectric sheets will be described with reference to FIGS.

[0411] 9, the dielectric sheet on which the pattern of the internal electrode layer 30 is printed is composed of a ceramic green sheet G and conductive pastes P1 and P2 arranged on the ceramic green sheet G. The conductive pastes P1 and P2 are formed in the hollow portions of the screens S1 and S2.

[0412] First, as shown in FIG. 8 , a conductive paste P1 is placed on a ceramic green sheet G using a screen S1 having a hollow portion formed in a pattern corresponding to the outer shapes of the first internal electrode layer 31 and the second internal electrode layer 32.

[0413] Next, as shown in Figure 9, a screen S2 having hollow portions formed in a pattern corresponding to the first central region EA0 and the second central region EB0 is used to screen-print a conductive paste P2 onto the conductive paste P1. As a result, the portions corresponding to the first central region EA0 and the second central region EB0 are thicker than the other regions. In this manner, a dielectric sheet is prepared.

[0414] Specifically, the portions corresponding to the first central region EA0 and the second central region EB0 are thicker than the portions corresponding to the first lead portion D1, the second lead portion D2, the third lead portion D3, the fourth lead portion D4, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, thereby making the first central region EA0 and the second central region EB0 high-coverage regions with higher coverage than the first lead portion D1, the second lead portion D2, the third lead portion D3, the fourth lead portion D4, the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Furthermore, the first lead-out portion D1, the second lead-out portion D2, the third lead-out portion D3 and the fourth lead-out portion D4, and the first region EA1, the second region EA2, the third region EB1 and the fourth region EB2 have substantially the same thickness and substantially the same coverage.

[0415] By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed, a portion P12 that becomes the first main surface side outer layer portion 12 on the first main surface TS1 side is formed.

[0416] Next, as shown in Fig. 10 , screen-printed dielectric sheets as shown in Fig. 9 are sequentially laminated on the surface of the portion P12 that will become the first main surface side outer layer portion 12, thereby forming the portion P11 that will become the inner layer portion 11. Focusing on the portion surrounded by C in Fig. 10 , a dielectric sheet G1 on which a conductive paste P31 that will become the first internal electrode layer 31 is arranged and a dielectric sheet G2 on which a conductive paste P32 that will become the second internal electrode layer 32 is arranged are sequentially laminated alternately. Note that the portion C in Fig. 10 is cut out in a subsequent process to form one laminated chip.

[0417] A predetermined number of dielectric sheets, on the surface of which the pattern of the internal electrode layer 30 is not printed, are laminated on the surface of the portion P11 that will become the inner layer portion 11, thereby forming a portion P13 that will become the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0418] The laminated sheets are pressed in the height direction by means of a hydrostatic press or the like to produce a laminated block.

[0419] The laminated block is cut to a predetermined size to obtain laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0420] The laminated chip is fired to produce the laminate 10. The firing temperature, which depends on the materials of the dielectric layers 20 and the internal electrode layers 30, is preferably 900°C or higher and 1400°C or lower. Here, by adjusting the thickness of the conductive paste for the internal electrode layers 30 according to the region and adjusting the pressing conditions and firing conditions, the laminate 10 having the structure of the internal electrode layers 30 and the surface shapes of the first main surface TS1 and the second main surface TS2 of this embodiment can be obtained. For example, by adjusting the application condition, including the thickness of the conductive paste for the internal electrode layers 30, and the pressing conditions, an inclined portion such as the first inclined portion FA1 whose thickness gradually decreases can be formed, thereby obtaining the internal electrode layers 30 of this embodiment.

[0421] A conductive paste that will become a base electrode layer is applied to both end surfaces and parts of both side surfaces of the laminate 10 .

[0422] In this embodiment, the conductive paste is also applied to the first and second main surfaces TS1 and TS2 and the first and second side surfaces WS1 and WS2 adjacent to both end surfaces of the laminate 10. At this time, the conductive paste is applied so that the distance L1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Le0 in the length direction L between the first central region EA0 and the second central region EB0.

[0423] In this embodiment, the conductive paste is also applied to the first main surface TS1 and the second main surface TS2 adjacent to portions of both side surfaces of the laminate 10. At this time, the conductive paste is applied so that the distance Lw1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Lwe0 in the width direction W between the first central region EA0 and the second central region EB0.

[0424] A more specific example of the manufacturing method will be described. The first main surface TS1 or the second main surface TS2 of the laminate 10 has a first flat surface PA0 and a second flat surface PB0 corresponding to the positions of the first central region EA0 and the second central region EB0. A first inclined surface FC1, a second inclined surface FC2, a third inclined surface FC3, and a fourth inclined surface FC4 are formed around the first flat surface PA0 and the second flat surface PB0. Furthermore, flat portions PA1, PA2, PB1, and PB2 are formed closer to the end faces than the inclined surfaces.

[0425] Therefore, for example, the conductive paste is applied to the flat portions PA1, PA2, PB1, and PB2 that are closer to the end faces than the inclined surfaces. By applying the conductive paste to the laminate 10 in this manner, the conductive paste is applied so that the distance L1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Lt0 in the longitudinal direction L between the first central region EA0 and the second central region EB0. Note that the conductive paste may be applied to portions of the end faces of the first inclined surface FC1, the second inclined surface FC2, the third inclined surface FC3, and the fourth inclined surface FC4.

[0426] The first main surface TS1 or the second main surface TS2 of the laminate 10 has a first flat surface PA0 and a second flat surface PB0 corresponding to the positions of the first central region EA0 and the second central region EB0. A first side inclined surface FWC1, a second side inclined surface FWC2, a third side inclined surface FWC3, and a fourth side inclined surface FWC4 are formed around the first flat surface PA0 and the second flat surface PB0. Furthermore, flat portions PWA1, PWA2, PWB1, and PWB2 are formed on the side surface side of each inclined surface.

[0427] Therefore, for example, the conductive paste is applied to the flat portions PWA1, PWA2, PWB1, and PWB2 that are located closer to the side faces than the inclined surfaces. By applying the conductive paste to the laminate 10 in this manner, the conductive paste is applied so that the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D is longer than the distance Lwe0 in the width direction W between the first central region EA0 and the second central region EB0. Note that the conductive paste may also be applied to portions of the end faces of the first side-side inclined surface FWC1, the second side-side inclined surface FWC2, the third side-side inclined surface FWC3, and the fourth side-side inclined surface FWC4.

[0428] The above is an example of the manufacturing method, and the method is not limited to this. The base electrode layer can also be removed after the baking treatment for adjustment.

[0429] In this embodiment, the base electrode layer is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0430] When the unfired laminated chip and the conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the ceramic material added. In this case, the conductive paste is applied to the unfired laminated chip, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously fired to form the laminate 10 with the fired layer formed thereon.

[0431] Thereafter, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. A second plating layer 60B is formed on the surface of the second base electrode layer 50B. A third plating layer 60C is formed on the surface of the third base electrode layer 50C. A fourth plating layer 60D is formed on the surface of the fourth base electrode layer 50D.

[0432] In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0433] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0434] Through these manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0435] Second Embodiment In the multilayer ceramic capacitor 1 according to the first embodiment, the first central region EA0 and the second central region EB0, which are regions with higher coverage than the surrounding areas, have a substantially H-shape when viewed in the stacking direction. In the second embodiment, the first central region EA0 and the second central region EB0, which are regions with higher coverage than the surrounding areas, have a substantially rectangular shape when viewed in the stacking direction. In addition, in the multilayer ceramic capacitor 1 according to the first embodiment, the third external electrode 40C and the fourth external electrode 40D are formed to extend over a portion of the first main surface TS1 and a portion of the second main surface TS2. In the second embodiment, as shown in FIG. 11 , the third external electrode 40C and the fourth external electrode 40D are not substantially disposed on the first main surface TS1 or the second main surface TS2.

[0436] The multilayer ceramic capacitor 1 according to the second embodiment will be described below with reference to FIGS. 11 to 13B. Note that in the following description, detailed description of the same configuration as in the first embodiment may be omitted. FIG. 11 is an external perspective view of the multilayer ceramic capacitor according to the second embodiment. FIG. 12 is a view corresponding to FIG. 5A of the multilayer ceramic capacitor according to the second embodiment. FIG. 13A is a view corresponding to FIG. 6A of the multilayer ceramic capacitor according to the second embodiment. FIG. 13B is a view corresponding to FIG. 6B of the multilayer ceramic capacitor according to the second embodiment. Note that the LT cross section of the multilayer ceramic capacitor 1 according to the second embodiment is basically the same as the cross section of FIGS. 4A to 4C of the first embodiment. However, the fourth external electrode 40D is not visible in the LT cross section of the second embodiment.

[0437] 11 to 13B, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, a second external electrode 40B arranged on the second end face LS2 side of the laminate 10, a third external electrode 40C arranged on the first side face WS1 side of the laminate 10, and a fourth external electrode 40D arranged on the second side face WS2 side of the laminate 10. The layer structure of the external electrode 40 is the same as in the first embodiment.

[0438] The third external electrode 40C is disposed on the first side surface WS1. The fourth external electrode 40D is disposed on the second side surface WS2. The third external electrode 40C and the fourth external electrode 40D according to the second embodiment are not substantially disposed on the first main surface TS1 side or the second main surface TS2 side. The third external electrode 40C and the fourth external electrode 40D may extend to the chamfered region of the ridge of the laminate 10. The extension range of the third external electrode 40C and the fourth external electrode 40D is preferably at least closer to the side surface than the boundary between the counter electrode portion 11E and the side gap when viewed in the stacking direction. That is, the third external electrode 40C and the fourth external electrode 40D preferably remain as far as the side gap region when viewed in the stacking direction, and do not extend to the counter electrode portion 11E.

[0439] 12 , in a WT cross section (a cross section on a plane parallel to the stacking direction T and the width direction W) at the center of the length direction L, the distance between the opposing electrode portions 11E (first opposing portion EA, second opposing portion EB) in the width direction W is preferably shorter than the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D. Note that, in the width direction W, the opposing electrode portions 11E (first opposing portion EA, second opposing portion EB) are preferably arranged within the range of the distance Lw1 between the third external electrode 40C and the fourth external electrode 40D.

[0440] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0441] Next, the internal electrode layer 30 according to the second embodiment will be described in detail with reference to FIGS. 11 to 13B.

[0442] As shown in FIG. 13A , the first internal electrode layer 31 has a first opposing portion EA, a first lead portion D1, and a second lead portion D2. The first opposing portion EA has a first region EA1 on the first end face LS1 side, a second region EA2 on the second end face LS2 side, and a first central region EA0 located between the first region EA1 and the second region EA2 and having higher coverage than the first region EA1 and the second region EA2. This embodiment does not have the first side region EWA1 and second side region EWA2 shown in the first embodiment. Therefore, in the LW cross section viewed in the stacking direction shown in FIG. 13A , the shape of the first central region EA0, which is a high-coverage region, is substantially rectangular. The length in the width direction W of the first central area EA0 as the first high coverage area may be approximately the same as the length in the width direction W of the first facing portion EA.

[0443] As shown in FIG. 13B , the second internal electrode layer 32 has a second opposing portion EB, a third lead portion D3, and a fourth lead portion D4. The second opposing portion EB has a third region EB1 on the first end face LS1 side, a fourth region EB2 on the second end face LS2 side, and a second central region EB0 located between the third region EB1 and the fourth region EB2 and having higher coverage than the third region EB1 and the fourth region EB2. This embodiment does not have the third side region EWB1 and the fourth side region EWB2 shown in the first embodiment. Therefore, in the LW cross section viewed in the stacking direction shown in FIG. 13B , the shape of the second central region EB0, which is a high-coverage region, is substantially rectangular. The length in the width direction W of the second central region EB0 as the second high coverage region may be approximately the same as the length in the width direction W of the second facing portion EB.

[0444] This allows the thickness of the internal electrode layers 30 to be increased over a wider range, thereby sufficiently increasing coverage, and therefore the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1.

[0445] As in the first embodiment, the first facing portion EA may have a first inclined portion FA1 connecting the first region EA1 and the first central region EA0 and a second inclined portion FA2 connecting the second region EA2 and the first central region EA0. The second facing portion EB may have a third inclined portion FB1 connecting the third region EB1 and the second central region EB0 and a fourth inclined portion FB2 connecting the fourth region EB2 and the second central region EB0.

[0446] In the second embodiment, the thickness in the stacking direction T of the second central region EB0 of the second internal electrode layer 32 may be the same as the thickness of the third lead portion D3 and the thickness of the fourth lead portion D4. The coverage of the second central region EB0 of the second internal electrode layer 32 may be the same as the coverage of the third lead portion D3 and the fourth lead portion D5.

[0447] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T may be greater than the thickness of the third lead portion D3 and the thickness of the fourth lead portion D4. The coverage of the second central region EB0 of the second internal electrode layer 32 may be greater than the coverage of the third lead portion D3 and the fourth lead portion D5.

[0448] For example, the thickness of the second central region EB0 may be 101% to 111% of the thickness of the third lead portion D3 and the fourth lead portion D4. For example, the thickness of the second central region EB0 may be 101% to 110% or 102% to 110% of the thickness of the third lead portion D3 and the fourth lead portion D4. For example, the thickness of the second central region EB0 may be 103% to 110% of the thickness of the third lead portion D3 and the fourth lead portion D4.

[0449] This allows the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0450] The thickness of the first lead portion D1 and the second lead portion D2 may be thinner than the thickness of the first high coverage area EA0 and thinner than the thickness of the second high coverage area EB0. Furthermore, the thickness of the first lead portion D1 and the second lead portion D2 may be thinner than the thickness of the third lead portion D3 and the thickness of the third lead portion D4.

[0451] The coverage of the first lead-out portion D1 and the second lead-out portion D2 may be lower than that of the first high coverage area EA0 and lower than that of the second high coverage area EB0. Furthermore, the coverage of the first lead-out portion D1 and the second lead-out portion D2 may be lower than the coverage of the third lead-out portion D3 and the coverage of the fourth lead-out portion D4.

[0452] 4A and 12, the first main surface TS1 has a first exposed surface EpsA that is exposed from the first external electrode 40A and the second external electrode 40B, a first covered surface C1sA that is covered by the first external electrode 40A, and a second covered surface C2sA that is covered by the second external electrode 40B. Unlike the first embodiment, the first main surface TS1 according to the second embodiment does not have a first side covered surface CW1sA that is covered by the third external electrode 40C or a second side covered surface CW2sA that is covered by the fourth external electrode 40D.

[0453] 4A and 12, the second principal surface TS2 has a second exposed surface EpsB exposed from the first external electrode 40A and the second external electrode 40B, a third covered surface C1sB covered by the first external electrode 40A, and a fourth covered surface C2sB covered by the second external electrode 40B. Unlike the first embodiment, the second principal surface TS2 according to the second embodiment does not have a third side surface covered surface CW1sB covered by the third external electrode 40C or a fourth side surface covered surface CW2sB covered by the fourth external electrode 40D.

[0454] This makes it easier to ensure the areas of the first central region EA0 and the second central region EB0 with high coverage corresponding to the first flat surface PA0 or the second flat surface PB0, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1. Furthermore, by forming the flat surfaces, it is possible to suppress poor suction during mounting.

[0455] The first internal electrode layer 31 of this embodiment preferably has the above-mentioned first central region EA0 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, which has higher coverage and a greater thickness than the first region EA1 and the second region EA2.

[0456] However, the first internal electrode layer 31 may have the above-mentioned first central region EA0, which has a higher coverage and a greater thickness than the first region EA1 and the second region EA2, at least in either the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also has the effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0457] The second internal electrode layer 32 of this embodiment preferably has the above-mentioned second central region EB0 in the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and the central inner layer portion 111, which has higher coverage and a greater thickness than the third region EB1 and the fourth region EB2.

[0458] However, the second internal electrode layer 32 may have the above-mentioned second central region EB0, which has higher coverage and is thicker than the third region EB1 and the fourth region EB2, at least in either the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also has the effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0459] The multilayer ceramic capacitor 1 according to each of the above-described embodiments has the following advantages. In a typical multilayer ceramic capacitor, a space exists between the surface of the laminate and an imaginary plane connecting the surfaces of the first and second external electrodes. This space exists as long as the external electrodes have a side thickness, but it does not contribute to capacitance density.

[0460] One method for improving capacitance is to increase the coverage of the internal electrode layers to increase the net effective surface area. Here, since there is a positive correlation between the coverage of the internal electrode layers and the thickness of the internal electrode layers, the thickness of the internal electrode layers must be increased in order to improve the coverage. Therefore, in order to design a laminate with the same dimensions in the stacking direction T, it was necessary to reduce the number of internal electrode layers by the amount of the increased thickness of the internal electrode layers. Therefore, the effect of increasing capacitance by increasing the thickness of the internal electrode layers is negated by the reduction in the number of internal electrode layers.

[0461] According to the present disclosure, it is possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor 1, even in a multi-terminal type multilayer ceramic capacitor, by effectively utilizing the space that exists between the virtual plane that connects the surfaces of the first external electrode and the second external electrode and the surface of the laminate.

[0462] (1) The multilayer ceramic capacitor 1 of the present disclosure is a multilayer ceramic capacitor having a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30 stacked on the dielectric layers 20, the multilayer ceramic capacitor having a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first end face LS1 and a second end face LS2 facing in a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T and the length direction L, and three or more external electrodes 40. 1, the plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32, the first internal electrode layer 31 has a first opposing portion EA facing the second internal electrode layer 32 via the dielectric layer 20, a first lead portion D1 extending from the first opposing portion EA and drawn to a first end surface LS1 of the laminate 10, and a second lead portion D2 extending from the first opposing portion EA and drawn to a second end surface LS2 of the laminate 10, and the second internal electrode layer 32 has a first opposing portion EA facing the second internal electrode layer 32 via the dielectric layer 20, a first lead portion D1 extending from the first opposing portion EA and drawn to a first end surface LS1 of the laminate 10, and a second lead portion D2 extending from the first opposing portion EA and drawn to a second end surface LS2 of the laminate 10 and a third lead portion D3 extending from the second facing portion EB and led out to the first side surface WS1 of the laminate 10. The three or more external electrodes 40 include a first external electrode 40A connected to the first lead portion D1, a second external electrode 40B connected to the second lead portion D2, and a third external electrode 40C connected to the third lead portion D3. The first facing portion EA includes a first region EA1 which is a region on the first end face LS1 side, a second region EA2 which is a region on the second end face LS2 side, and a first The second opposing portion EB has a first central region EA0 which is located between the region EA1 and the second region EA2 and has a higher coverage than the coverage of the first region EA1 and the second region EA2, and the second opposing portion EB has a third region EB1 which is a region on the first end face LS1 side, a fourth region EB2 which is a region on the second end face LS2 side, and a second central region EB0 which is located between the third region EB1 and the fourth region EB2 and has a higher coverage than the coverage of the third region EB1 and the fourth region EB2.

[0463] This makes it possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0464] (2) Furthermore, in the multilayer ceramic capacitor 1 of the present disclosure, in the length direction L, the distance Lt0 of the first central region EA0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B, and in the length direction L, the distance Lt0 of the second central region EB0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B.

[0465] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0466] (3) Furthermore, in the multilayer ceramic capacitor 1 of the present disclosure, the laminate 10 has a first covering portion C1 covered by the first external electrode 40A, a second covering portion C2 covered by the second external electrode 40B, and exposed portions Ep exposed from three or more external electrodes 40, and the maximum distance in the stacking direction T of the exposed portions Ep is longer than the maximum distance T1 in the stacking direction T connecting the surfaces of the first covering portion C1 and the second covering portion C2 on the first main surface TS1 side and the second main surface TS2 side, and shorter than the maximum distance T2 in the stacking direction T connecting the surfaces of the first external electrode 40A and the second external electrode 40B on the first main surface TS1 side and the second main surface TS2 side.

[0467] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0468] (4) In the multilayer ceramic capacitor 1 of the present disclosure, the laminate 10 further has a third covering portion CW1 covered by the third external electrode 40C, and the maximum distance in the stacking direction T of the exposed portion Ep is longer than the maximum distance TW1 in the stacking direction T connecting the surface of the third covering portion CW1 on the first main surface TS1 side and the surface of the third external electrode 40C on the second main surface TS2 side, and shorter than the maximum distance TW1 in the stacking direction T connecting the surface of the third external electrode 40C on the first main surface TS1 side and the surface of the third external electrode 40C on the second main surface TS2 side.

[0469] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0470] (5) In the multilayer ceramic capacitor 1 of the present disclosure, the first opposing portion EA has a first side surface region EWA1 on the first side surface WS1 side of the first central region EA0, the first side surface region EWA1 having a lower coverage than the coverage of the first central region EA0.

[0471] This allows the multi-terminal multilayer ceramic capacitor to have a configuration that allows for increased freedom in arranging the external electrodes, without increasing the size of the multilayer ceramic capacitor 1, and that facilitates increased capacitance.

[0472] (6) In the multilayer ceramic capacitor of the present disclosure, the second opposing portion EB has a third side surface region EWB1 on the first side surface WS1 side of the second central region EB0, the third side surface region EWB1 having a lower coverage than the coverage of the second central region EB0.

[0473] This allows the multi-terminal multilayer ceramic capacitor to have a configuration that allows for increased freedom in arranging the external electrodes, without increasing the size of the multilayer ceramic capacitor 1, and that facilitates increased capacitance.

[0474] (7) In the multilayer ceramic capacitor 1 of the present disclosure, the second internal electrode layer 32 further has a fourth lead portion D4 extending from the second opposing portion EB and drawn out to the second side surface WS2 of the laminate 10, and the three or more external electrodes 40 further have a fourth external electrode 40D connected to the fourth lead portion D4.

[0475] Even in such a multi-terminal type multilayer ceramic capacitor, it is possible to provide a multilayer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0476] (8) In the multilayer ceramic capacitor 1 of the present disclosure, the distance of the first central region EA0 in the width direction W is shorter than the distance between the third external electrode 40C and the fourth external electrode 40D, and the distance of the second central region EB0 in the width direction W is shorter than the distance between the third external electrode 40C and the fourth external electrode 40D.

[0477] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0478] (9) In the multilayer ceramic capacitor 1 of the present disclosure, the thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is thicker than the thickness of the first extension portion D1, and the thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is thicker than the thickness of the second extension portion D2.

[0479] This allows the multi-terminal multilayer ceramic capacitor to have a configuration that increases the degree of freedom in arranging the external electrodes and makes it easy to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0480] (10) In the multilayer ceramic capacitor 1 of the present disclosure, the thickness in the stacking direction T of the second central region EB0 of the second internal electrode layer 32 is thicker than the thickness of the third lead portion D3, and the thickness in the stacking direction T of the second central region EB0 of the second internal electrode layer 32 is thicker than the thickness of the fourth lead portion D4.

[0481] This allows the multi-terminal multilayer ceramic capacitor to have a configuration that increases the degree of freedom in arranging the external electrodes and makes it easy to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0482] (11) In the multilayer ceramic capacitor 1 of the present disclosure, in the stacking direction T, the surface of the exposed portion Ep is located farther from the center of the laminate 10 than the surface of the third covering portion CW1 on the first main surface TS1 side and the surface of the third covering portion CW1 on the second main surface TS2 side, and in the stacking direction T, the surface of the exposed portion Ep is located closer to the center of the laminate 10 than the surface of the third external electrode 40C on the first main surface TS1 side and the surface of the third external electrode 40C on the second main surface TS2 side.

[0483] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0484] (12) In the multilayer ceramic capacitor 1 of the present disclosure, in the stacking direction T, the surface of the exposed portion Ep is located farther from the center of the laminate 10 than the surfaces of the first covering portion C1 and the second covering portion C2 on the first main surface TS1 side and the surfaces of the second main surface TS2 side, and in the stacking direction T, the surface of the exposed portion Ep is located closer to the center of the laminate 10 than the surfaces of the first external electrode 40A, the second external electrode 40B, and the third external electrode 40C on the first main surface TS1 side and the surfaces of the second main surface TS2 side.

[0485] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0486] (13) In the multilayer ceramic capacitor 1 of the present disclosure, the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first external electrode 40A, and the distance in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second external electrode 40B.

[0487] (14) In the multilayer ceramic capacitor 1 of the present disclosure, the laminate 10 has a counter electrode portion 1E in which a first counter portion EA and a second counter portion EB oppose each other, and a first side surface side outer layer portion WG1 and a second side surface side outer layer portion WG2 arranged to sandwich the counter electrode portion 11E in the width direction W. The distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Ep is longer than a maximum distance TW1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first side surface side outer layer portion WG1, and the distance T0 in the stacking direction T at the center of the length direction L and the center of the width direction W of the exposed portion Tp is longer than a maximum distance TW1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second side surface side outer layer portion WG2.

[0488] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0489] (15) In the multilayer ceramic capacitor 1 of the present disclosure, the first main surface TS1 includes a first exposed surface EpsA exposed from the first external electrode 40A, the second external electrode 40B, the third external electrode 40C, and the fourth external electrode 40D, a first covered surface C1sA covered by the first external electrode 40A, a second covered surface C2sA covered by the second external electrode 40B, a first side surface covered surface CW1sA covered by the third external electrode 40C, and a second side surface CW2sA covered by the fourth external electrode 40D. The first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first inclined surface FC1 connecting the first flat surface PA0 and the first covered surface C1sA, a second inclined surface FC2 connecting the first flat surface PA0 and the second covered surface C2sA, a first side surface inclined surface FWC1 connecting the first flat surface PA0 and the first side surface inclined surface CW1sA, and a second side surface inclined surface FWC2 connecting the first flat surface PA0 and the second side surface inclined surface CW2sA.

[0490] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0491] (16) In the multilayer ceramic capacitor 1 of the present disclosure, the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the first main surface TS1, and the protrusion height twf of the first flat surface PA0 formed by the first side surface inclined surface FWC1 and the second side surface inclined surface FWC2 is smaller than the thickness twg in the stacking direction T of the third external electrode 40C and the fourth external electrode 40D arranged on the first main surface TS.

[0492] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0493] (17) In the multilayer ceramic capacitor 1 of the present disclosure, the first opposing portion EA has, on the first side surface WS1 side of the first central region EA0, a first side surface region EWA1 having lower coverage than the coverage of the first central region EA0, and the second opposing portion EB has, on the first side surface WS1 side of the second central region EB0, a third side surface region EWB1 having lower coverage than the coverage of the second central region EB0, the first internal electrode layer 31 further has a first side surface side inclined portion FWA1 connecting the first side surface region EWA1 and the first central region EA0, and the second internal electrode layer 32 further has a third side surface side inclined portion FWB1 connecting the third side surface region EWB1 and the second central region EB0.

[0494] This allows the multi-terminal multilayer ceramic capacitor to have a configuration that increases the degree of freedom in arranging the external electrodes and makes it easy to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0495] (18) In the multilayer ceramic capacitor 1 of the present disclosure, the first opposing portion EA has, on the second side surface WS2 side of the first central region EA0, a second side surface region EWA2 having a lower coverage than the coverage of the first central region EA0, and the second opposing portion EB has, on the second side surface WS2 side of the second central region EB0, a fourth side surface region EWB2 having a lower coverage than the coverage of the second central region EB0, the first internal electrode layer 31 further has a second side surface side inclined portion FWA2 connecting the second side surface region EWA2 and the first central region EA0, and the second internal electrode layer 32 further has a fourth side surface side inclined portion FWB2 connecting the fourth side surface region EWB2 and the second central region EB0.

[0496] This allows the multi-terminal multilayer ceramic capacitor to have a configuration that increases the degree of freedom in arranging the external electrodes and makes it easy to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0497] (19) In the multilayer ceramic capacitor 1 of the present disclosure, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T, and the thickness t01 in the stacking direction T in the region of the first flat surface PA0 of the first main surface side outer layer portion 12 is smaller than the thickness t11 in the stacking direction T in the region of the first covered surface C1sA of the first main surface side outer layer portion 12 and the thickness t21 in the stacking direction T in the region of the second covered surface C2sA of the first main surface side outer layer portion 12.

[0498] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0499] (20) In the multilayer ceramic capacitor 1 of the present disclosure, the thickness t01 in the stacking direction T in the region of the first flat surface PA0 of the first main surface side outer layer portion 12 is smaller than the thickness tw11 in the stacking direction T in the region of the first side surface side covering surface CW1sA of the first main surface side outer layer portion 12 and the thickness tw21 in the stacking direction T in the region of the second side surface side covering surface CW2sA of the first main surface side outer layer portion 12.

[0500] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to improve coverage and thereby make it easier to increase capacitance, even in a multi-terminal type multilayer ceramic capacitor, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0501] Further, the multilayer ceramic capacitor 1 of the present disclosure is a multilayer ceramic capacitor 1 having a laminate 10 and three or more external electrodes 40, in which the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32, the first internal electrode layers 31 have a first opposing portion EA facing the second internal electrode layers 32 via a dielectric layer 20, a first lead portion D1 extending from the first opposing portion EA and drawn to a first end face LS1 of the laminate 10, and a second lead portion D2 extending from the first opposing portion EA and drawn to a second end face LS2 of the laminate 10, and the second internal electrode layers 32 have a second opposing portion E B, and a third lead portion D3 extending from the second opposing portion EB and drawn out to the first side surface WS1 of the laminate 10, and the three or more external electrodes 40 include a first external electrode 40A connected to the first lead portion D1, a second external electrode 40B connected to the second lead portion D2, and a third external electrode 40C connected to the third lead portion D3, and the first opposing portion EA has a first region EA1 which is a region on the first end face LS1 side, a second region EA2 which is a region on the second end face LS2 side, and a first central region EA0 which is a region located between the first region EA1 and the second region EA2 and has a higher coverage than the coverage of the first region EA1 and the second region EA2.

[0502] This also makes it possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0503] The multilayer ceramic capacitor 1 of the present disclosure has a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and has a first main surface TS1 and a second main surface TS2 facing in a lamination direction T, a first end face LS1 and a second end face LS2 facing in a length direction L perpendicular to the lamination direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the lamination direction T and the length direction L. The laminated ceramic capacitor 1 has a laminate 10 and three or more external electrodes 40, and the internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32, and the first internal electrode layers 31 have a first opposing portion EA that faces the second internal electrode layers 32 via a dielectric layer 20, a first lead portion D1 that extends from the first opposing portion EA and is led to a first end face LS1 of the laminate 10, and The second internal electrode layer 32 has a second opposing portion EB that faces the first internal electrode layer 31 via the dielectric layer 20, and a third opposing portion D3 that extends from the second opposing portion EB and is led to the first side surface WS1 of the laminate 10. The three or more external electrodes 40 include a first external electrode 40A connected to the first opposing portion D1 and a third external electrode 40B connected to the second opposing portion D2. The first opposing portion EA has a first region EA1 which is a region on the first end face LS1 side, a second region EA2 which is a region on the second end face LS2 side, and a first central region EA0 which is a region located between the first region EA1 and the second region EA2 and has a higher coverage than the coverage of the first region EA1 and the second region EA2.

[0504] With this configuration, it is possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0505] The multilayer ceramic capacitor 1 of the present disclosure has a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and has a first main surface TS1 and a second main surface TS2 facing in a lamination direction T, a first end face LS1 and a second end face LS2 facing in a length direction L perpendicular to the lamination direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the lamination direction T and the length direction L. The laminated ceramic capacitor 1 has a laminate 10 and three or more external electrodes 40, and the internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32, and the first internal electrode layers 31 have a first opposing portion EA that faces the second internal electrode layers 32 via a dielectric layer 20, a first lead portion D1 that extends from the first opposing portion EA and is led to a first end face LS1 of the laminate 10, and The second internal electrode layer 32 has a second opposing portion EB that faces the first internal electrode layer 31 via the dielectric layer 20, and a third opposing portion D3 that extends from the second opposing portion EB and is led to the first side surface WS1 of the laminate 10. The three or more external electrodes 40 include a first external electrode 40A connected to the first opposing portion D1 and a third external electrode 40B connected to the second opposing portion D2. The second opposing portion EB has a third region EB1 which is a region on the first end face LS1 side, a fourth region EB2 which is a region on the second end face LS2 side, and a second central region EB0 which is a region located between the third region EB1 and the fourth region EB2 and has a higher coverage than the coverage of the third region EB1 and the fourth region EB2.

[0506] With this configuration, it is possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0507] The multilayer ceramic capacitor 1 of the present disclosure is a multilayer ceramic capacitor 1 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, the multilayer ceramic capacitor 1 having a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first end face LS1 and a second end face LS2 facing in a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T and the length direction L, and three or more external electrodes 40, wherein the plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32, and the first internal electrode layer 31 has a first opposing portion EA facing the second internal electrode layer 32 via the dielectric layer 20, and a first external electrode 40 extending from the first opposing portion EA to form a first external electrode 40 of the multilayer ceramic capacitor 10. The laminate 10 has a first lead portion D1 that is led out to the end surface LS1, and a second lead portion D2 that extends from the first opposing portion EA and is led out to a second end surface LS2 of the laminate 10, the second internal electrode layer 32 has a second opposing portion EB that faces the first internal electrode layer 31 via the dielectric layer 20, and a third lead portion D3 that extends from the second opposing portion EB and is led out to the first side surface WS1 of the laminate 10, the three or more external electrodes 40 have a first external electrode 40A that is connected to the first lead portion D1, a second external electrode 40B that is connected to the second lead portion D2, and a third external electrode 40C that is connected to the third lead portion D3, and the first opposing portion EA has a first high coverage area EA0 that is an area with higher coverage than the coverage of the first lead portion D1 and the second lead portion D2.

[0508] With this configuration, it is possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0509] Furthermore, in the multilayer ceramic capacitor 1 of the present disclosure, the first opposing portion EA may be positioned biased toward the outside of the laminate 10 in the stacking direction T relative to the first lead portion D1 and the second lead portion D2, and may have a first high coverage area EA0 which is an area with higher coverage than the coverage of the first lead portion D1 and the second lead portion D2.

[0510] With this configuration, it is possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0511] Furthermore, in the multilayer ceramic capacitor 1 of the present disclosure, the coverage of the first lead portion D1 and the second lead portion D2 may be lower than the coverage of the first high coverage area EA0, and the coverage of the third lead portion D3 and the fourth lead portion D4 may be lower than the coverage of the second high coverage area EB0.

[0512] With this configuration, it is possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0513] In the multilayer ceramic capacitor 1 of the present disclosure, the coverage of the first lead portion D1 and the second lead portion D2 may be lower than the coverage of the first high coverage region EA0 and lower than the coverage of the second high coverage region EB0. Furthermore, the coverage of the first lead portion D1 and the second lead portion D2 may be lower than the coverage of the third lead portion D3. Furthermore, when the second internal electrode layer 32 has a fourth lead portion D4, the coverage of the first lead portion D1 and the second lead portion D2 may be lower than the coverage of the fourth lead portion D4.

[0514] With this configuration, it is possible to provide a multi-terminal multi-layer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multi-layer ceramic capacitor.

[0515] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0516] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 40 External electrode 40A First external electrode 40B Second external electrode 40C Third external electrode D1 First lead portion D2 Second lead portion D3 Third lead portion EA First opposing portion EA0 First central region EA1 First region EA2 Second region EB Second opposing portion EB0 Second central region EB1 Third region EB2 Fourth region L Length direction LS1 First end face LS2 Second end face T Stacking direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface

Claims

1. A multilayer ceramic capacitor having a laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having first and second main surfaces opposing each other in the lamination direction, first end faces and second end faces opposing each other in a length direction perpendicular to the lamination direction, and first and second side faces opposing each other in a width direction perpendicular to the lamination direction and the length direction; and three or more external electrodes, wherein the plurality of internal electrode layers comprise a plurality of first internal electrode layers and a plurality of second internal electrode layers, and the first internal electrode layer has a first opposing portion opposing the second internal electrode layer via the dielectric layer, a first lead portion extending from the first opposing portion and drawn to a first end face of the laminate, and a second lead portion extending from the first opposing portion and drawn to a second end face of the laminate, the second internal electrode layer has a second opposing portion opposing the first internal electrode layer via the dielectric layer, and a third lead portion extending from the second opposing portion and led out to a first side surface of the laminate; the three or more external electrodes have a first external electrode connected to the first lead portion, a second external electrode connected to the second lead portion, and a third external electrode connected to the third lead portion; the first opposing portion has: a first region which is a region on the first end face side; a second region which is a region on the second end face side; and a first central region which is a region located between the first region and the second region and has a higher coverage than the coverage of the first region and the second region; and the second opposing portion has: a third region which is a region on the first end face side; and a fourth region which is a region on the second end face side. a second central region located between the third region and the fourth region, the second central region having a higher coverage than the third region and the fourth region.

2. The multilayer ceramic capacitor according to claim 1, wherein the distance in the length direction of the first central region is shorter than the distance between the first external electrode and the second external electrode, and the distance in the length direction of the second central region is shorter than the distance between the first external electrode and the second external electrode.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein the laminate has a first covering portion covered by the first external electrode, a second covering portion covered by the second external electrode, and exposed portions exposed from the three or more external electrodes, and the maximum distance in the stacking direction of the exposed portions is longer than the maximum distance in the stacking direction connecting the surfaces on the first principal surface side and the surfaces on the second principal surface side of the first covering portion and the second covering portion, and shorter than the maximum distance in the stacking direction connecting the surfaces on the first principal surface side and the surfaces on the second principal surface side of the first external electrode and the second external electrode.

4. The multilayer ceramic capacitor according to claim 3, wherein the laminate further has a third covering portion covered by the third external electrode, and the maximum distance in the lamination direction of the exposed portion is longer than the maximum distance in the lamination direction connecting the surface of the third covering portion on the first principal surface side and the surface of the second principal surface side, and shorter than the maximum distance in the lamination direction connecting the surface of the third external electrode on the first principal surface side and the surface of the second principal surface side.

5. The multilayer ceramic capacitor according to claim 4, wherein the first opposing portion has a first side surface region on a first side surface side of the first central region, the first side surface region having a lower coverage than the coverage of the first central region.

6. A multilayer ceramic capacitor according to claim 4 or 5, wherein the second opposing portion has a third side surface region on the first side surface side of the second central region, the third side surface region having a lower coverage than the coverage of the second central region.

7. A multilayer ceramic capacitor according to any one of claims 4 to 6, wherein the second internal electrode layer further has a fourth lead portion extending from the second opposing portion and led out to a second side surface of the laminate, and the three or more external electrodes further have a fourth external electrode connected to the fourth lead portion.

8. The multilayer ceramic capacitor according to claim 7, wherein the distance in the width direction of the first central region is shorter than the distance between the third external electrode and the fourth external electrode, and the distance in the width direction of the second central region is shorter than the distance between the third external electrode and the fourth external electrode.

9. A multilayer ceramic capacitor according to claim 7 or 8, wherein the thickness of the first central region of the first internal electrode layer in the stacking direction is greater than the thickness of the first lead portion, and the thickness of the first central region of the first internal electrode layer in the stacking direction is greater than the thickness of the second lead portion.

10. A multilayer ceramic capacitor according to any one of claims 7 to 9, wherein the thickness of the second central region of the second internal electrode layer in the stacking direction is greater than the thickness of the third lead portion, and the thickness of the second central region of the second internal electrode layer in the stacking direction is greater than the thickness of the fourth lead portion.

11. A multilayer ceramic capacitor according to any one of claims 7 to 10, wherein, in the stacking direction, the surface of the exposed portion is located on a side farther away from the center of the laminate than the surface of the third cover on the first principal surface side and the surface of the second principal surface side, and the surface of the exposed portion is located on a side closer to the center of the laminate than the surface of the third external electrode on the first principal surface side and the surface of the second principal surface side.

12. A multilayer ceramic capacitor according to any one of claims 7 to 11, wherein, in the stacking direction, the surface of the exposed portion is located farther from the center of the laminate than the surfaces of the first and second main surfaces of the first and second covering portions, and the surface of the exposed portion is located closer to the center of the laminate than the surfaces of the first, second, and third external electrodes on the first and second main surfaces.

13. A multilayer ceramic capacitor according to any one of claims 7 to 12, wherein the distance in the stacking direction at the center of the length and the center of the width of the exposed portion is shorter than a maximum distance that is the maximum value of the distance in the stacking direction connecting the first main surface side surface and the second main surface side surface of the first external electrode, and the distance in the stacking direction at the center of the length and the center of the width of the exposed portion is shorter than a maximum distance that is the maximum value of the distance in the stacking direction connecting the first main surface side surface and the second main surface side surface of the second external electrode.

14. The multilayer ceramic capacitor according to any one of claims 7 to 13, wherein the laminate has an opposing electrode portion in which the first opposing portion and the second opposing portion are opposed, and a first side surface outer layer portion and a second side surface outer layer portion arranged to sandwich the opposing electrode portion in the width direction, wherein the distance in the stacking direction at the center of the length direction and the center of the width direction of the exposed portion is longer than a maximum distance which is the maximum value of the distance in the stacking direction T connecting the first main surface side surface and the second main surface side surface of the first side surface outer layer portion, and wherein the distance in the stacking direction at the center of the length direction and the center of the width direction of the exposed portion is longer than a maximum distance which is the maximum value of the distance in the stacking direction connecting the first main surface side surface and the second main surface side surface of the second side surface outer layer portion.

15. The multilayer ceramic capacitor according to any one of claims 7 to 14, wherein the first main surface has a first exposed surface exposed from the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode, a first covered surface covered by the first external electrode, a second covered surface covered by the second external electrode, a first side surface covered by the third external electrode, and a second side surface covered by the fourth external electrode, and the first exposed surface has a first flat surface parallel to the stacking direction, a first inclined surface connecting the first flat surface and the first covered surface, a second inclined surface connecting the first flat surface and the second covered surface, a first side surface inclined surface connecting the first flat surface and the first side surface covered surface, and a second side surface inclined surface connecting the first flat surface and the second side surface covered surface.

16. The multilayer ceramic capacitor according to claim 15, wherein the height of the first flat surface formed by the first inclined surface and the second inclined surface is smaller than the thickness in the stacking direction of the first external electrode and the second external electrode arranged on the first main surface, and the height of the first flat surface formed by the first side inclined surface and the second side inclined surface is smaller than the thickness in the stacking direction of the third external electrode and the fourth external electrode arranged on the first main surface.

17. The multilayer ceramic capacitor according to claim 15 or 16, wherein the first opposing portion has, on the first side surface side of the first central region, a first side surface region having lower coverage than the coverage of the first central region; the second opposing portion has, on the first side surface side of the second central region, a third side surface region having lower coverage than the coverage of the second central region; the first internal electrode layer further has a first side surface inclined portion connecting the first side surface region and the first central region; and the second internal electrode layer further has a third side surface inclined portion connecting the third side surface region and the second central region.

18. The multilayer ceramic capacitor according to claim 17, wherein the first opposing portion has, on the second side surface side of the first central region, a second side surface region having lower coverage than the coverage of the first central region, the second opposing portion has, on the second side surface side of the second central region, a fourth side surface region having lower coverage than the coverage of the second central region, the first internal electrode layer further has a second side surface inclined portion connecting the third side surface region and the first central region, and the second internal electrode layer further has a fourth side surface inclined portion connecting the fourth side surface region and the second central region.

19. A multilayer ceramic capacitor according to any one of claims 15 to 18, wherein the laminate has an inner layer portion, and a first main surface side outer layer portion and a second main surface side outer layer portion arranged to sandwich the inner layer portion in the stacking direction, and the thickness of the first main surface side outer layer portion in the stacking direction in the region of the first flat surface is smaller than the thickness of the first main surface side outer layer portion in the stacking direction in the region of the first covered surface and the thickness of the first main surface side outer layer portion in the stacking direction in the region of the second covered surface.

20. A multilayer ceramic capacitor as described in claim 19, wherein the thickness in the stacking direction in the region of the first flat surface of the first main surface side outer layer portion is smaller than the thickness in the stacking direction in the region of the first side surface side covering surface of the first main surface side outer layer portion and the thickness in the stacking direction in the region of the second side surface side covering surface of the first main surface side outer layer portion.

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