Circuit board and power device

Abstract

This circuit board comprises: a ceramic substrate made of a material containing silicon nitride as a main component; a bonding layer formed on one main surface of the ceramic substrate; and a conductor layer bonded to the ceramic substrate via the bonding layer, wherein the maximum circle equivalent diameter of Kirkendall voids present in the conductor layer within a distance of 10 μm from the interface between the ceramic substrate and the bonding layer is 2 μm or less.

Description

Circuit Boards and Power Devices

[0001] The present invention relates to a circuit board made of a ceramic substrate containing silicon nitride as a main component, and a power device using the same.

[0002] Silicon nitride, with its high thermal conductivity and strength, has traditionally attracted attention as an insulating heat dissipation substrate for inverter power modules installed in electric vehicles (EVs) and hybrid vehicles (HVs). Aluminum nitride has often been used as a material for such insulating heat dissipation substrates. However, in the case of high-current power modules, such as those used in EVs, temperatures reach approximately 250°C, and the difference in thermal expansion between the substrate and the bonded metal, such as copper, generates significant thermal stress, which can lead to cracks and fractures in aluminum nitride, which has low strength. Therefore, silicon nitride, which has a higher thermal conductivity and higher strength than other common insulating ceramics, is increasingly being adopted, although its thermal conductivity is inferior to that of aluminum nitride. The bonding of silicon nitride heat dissipation substrates to conductor layers is typically performed by brazing using a brazing filler metal.

[0003] Patent Document 1 discloses a ceramic circuit board having high bonding strength and excellent heat cycle resistance, and which aims to improve the operational reliability of electronic devices and to provide excellent heat dissipation. This ceramic circuit board is a ceramic circuit board in which both main surfaces of the ceramic substrate and a metal plate are bonded via a silver-copper based brazing filler metal layer, and the silver-copper based brazing filler metal layer is composed of 75 to 98 parts by mass of silver powder and 2 to 25 parts by mass of copper powder, for a total of 100 parts by mass, and contains 0.1 to 5.0 parts by mass of graphite powder and 0.5 to 10 parts by mass of at least one active metal selected from titanium, zirconium, hafnium, niobium, tantalum, vanadium, and tin, and the specific surface area of ​​the graphite powder is 5 to 100 m ２ / g.

[0004] JP 2014-118310 A

[0005] In recent years, as power modules have become hotter, there has been a demand for improved heat dissipation characteristics, improved bonding strength, and improved resistance to thermal cycling. Circuit boards for power modules include a substrate (e.g., a ceramic substrate) and a conductor layer, which are bonded to each other by a bonding layer. During the manufacture of such circuit boards, voids may occur within the circuit board. For example, increasing the bonding temperature or maintaining the temperature for a long period of time to improve the bonding strength between the substrate and the conductor layer promotes interdiffusion of metal components between the conductor layer (Cu) and the bonding layer (e.g., brazing material or a thin metal film such as Ti). This can lead to the formation of "Kirkendall voids" due to differences in the diffusion rates between the metals. The formation of numerous voids and the presence of interconnected portions can lead to reduced heat dissipation from the power semiconductor, cracks that originate from the voids, and potential degradation of thermal cycling durability.

[0006] The present invention has been made in view of the above circumstances, and has an object to provide a circuit board having high thermal conductivity and excellent heat cycle resistance, and a power device using the same.

[0007] (1) In order to achieve the above object, the present invention provides the following means: That is, a circuit board according to one aspect of the present invention includes a ceramic substrate made of a material containing silicon nitride as a main component, a bonding layer formed on one main surface of the ceramic substrate, and a conductor layer bonded to the ceramic substrate via the bonding layer, wherein the distance from the interface between the ceramic substrate and the bonding layer is 10 μm or less, and the maximum value of the circle-equivalent diameter of voids present in the conductor layer is 2 μm or less.

[0008] With this configuration, even if voids are present, a decrease in thermal conductivity and the development of cracks are avoided, making it possible to maintain high thermal conductivity and heat cycle resistance.

[0009] (2) In a circuit board according to one aspect of the present invention, the voids are Kirkendall voids.

[0010] Kirkendall voids can be formed near the bonding layer of the conductor layer due to the difference in diffusion rate in the interdiffusion of metal components between the conductor layer (Cu) and the metal thin film that serves as the bonding layer. Therefore, with this configuration, it is possible to easily achieve a state in which the distance from the interface between the ceramic substrate and the bonding layer is 10 μm or less and the maximum circle-equivalent diameter of voids present in the conductor layer is 2 μm or less.

[0011] (3) Furthermore, a circuit board according to one embodiment of the present invention is characterized in that the distance from the interface is within 10 μm, and the area occupied by Kirkendall voids in the conductor layer in a cross section perpendicular to the surface direction is 10% or less.

[0012] With this configuration, even if Kirkendall voids are present, a decrease in thermal conductivity and the development of cracks can be avoided, and high thermal conductivity and heat cycle resistance can be maintained.

[0013] (4) In the circuit board according to one aspect of the present invention, the thickness of the bonding layer is 3 μm or less.

[0014] By thinning the bonding layer in this way, the amount of material used in the bonding layer can be reduced, heat dissipation can be improved, and the overall size can be made more compact.

[0015] (5) In a circuit board according to one aspect of the present invention, the conductor layer is mainly composed of Cu, and the bonding layer contains at least Ti.

[0016] With this configuration, even if voids occur during bonding due to differences in the diffusion rates of Cu and Ti, a decrease in thermal conductivity and the progression of cracks are avoided, making it possible to maintain high thermal conductivity and heat cycle resistance.

[0017] (6) Furthermore, a power device according to one aspect of the present invention is characterized by comprising the circuit board described in (1) or (2) above and a power semiconductor mounted on the conductor layer.

[0018] With this configuration, even if voids exist in the conductor layer of the circuit board, a decrease in thermal conductivity and the progression of cracks are avoided, making it possible to maintain high thermal conductivity and heat cycle resistance.

[0019] According to the present invention, it is possible to realize a circuit board having high thermal conductivity and excellent heat cycle resistance, and a power device using the same.

[0020] Fig. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention. Fig. 2 is a flowchart showing a manufacturing procedure for a circuit board according to this embodiment. Fig. 3 is a flowchart showing a manufacturing procedure for a silicon nitride sintered body. Fig. 4 is a diagram showing the results of a thermal cycle test. Fig. 5 is a cross-sectional view showing an example of a power device according to an embodiment of the present invention.

[0021] The inventors noticed that due to the difference in diffusion rates between Cu and Ti, voids (Kirkendall voids) are generated depending on the joining conditions, and discovered that by controlling the size and content of the voids when they are generated, it is possible to avoid the reduction in thermal conductivity, crack progression, and reduced thermal cycle resistance caused by the voids, which led to the present invention.

[0022] That is, a circuit board according to one embodiment of the present invention comprises a ceramic substrate made of a material primarily composed of silicon nitride, a bonding layer formed on one main surface of the ceramic substrate, and a conductor layer bonded to the ceramic substrate via the bonding layer, characterized in that the distance from the interface between the ceramic substrate and the bonding layer is 10 μm or less, and the maximum value of the circular equivalent diameter of voids present in the conductor layer is 2 μm or less.

[0023] With this configuration, the inventors have been able to avoid a decrease in thermal conductivity and the development of cracks, even when voids are present, and maintain high thermal conductivity and heat cycle resistance. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, Kirkendall voids are shown as the voids. However, the voids are not limited to Kirkendall voids.

[0024] 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention. ３ N ４ ) and a conductor layer (Cu) are bonded by a bonding layer (containing Ti). As indicated by the arrows on one side of Figure 1, Kirkendall voids are generated in the conductor layer due to the difference in diffusion rates between Cu and Ti. The bonding strength between the ceramic substrate and the conductor layer increases as the temperature during bonding increases and the heating time increases, but more Kirkendall voids are generated. On the other hand, the lower the bonding temperature and the shorter the heating time, the less likely Kirkendall voids are to be generated, but the bonding strength decreases. Therefore, it is possible to control the generation of Kirkendall voids depending on the temperature and time during bonding, and to realize a circuit board with high thermal conductivity and excellent heat cycle resistance.

[0025] In this embodiment, the distance from the interface between the ceramic substrate and the bonding layer is 10 μm or less, and the maximum value of the circle-equivalent diameter of Kirkendall voids present in the conductor layer is 2 μm or less, as shown by the arrows on both sides of Fig. 1. Since the shape of the interface is not a flat surface as shown in Fig. 1, the distance from the interface can be determined using the average value of the height for a certain width, etc.

[0026] In this way, by setting the maximum circle-equivalent diameter of Kirkendall voids present in a region 10 μm or less away from the interface between the ceramic substrate and the bonding layer to 2 μm or less, even if Kirkendall voids are present, dielectric breakdown and crack propagation can be avoided, and high thermal conductivity and heat cycle resistance can be maintained. The maximum circle-equivalent diameter of Kirkendall voids is preferably 1.5 μm or less, and more preferably 1 μm or less.

[0027] In this embodiment, the area ratio of Kirkendall voids present in the conductor layer in a cross section perpendicular to the surface direction at a distance of 10 μm or less from the interface is 10% or less. The area ratio of Kirkendall voids is preferably 5% or less, and more preferably 3% or less. By keeping the area ratio of Kirkendall voids at 10% or less, even if Kirkendall voids are present, dielectric breakdown and crack propagation can be avoided, and high thermal conductivity and heat cycle resistance can be maintained.

[0028] In this embodiment, the thickness of the bonding layer is 3 μm or less. By thinning the bonding layer in this way, the material used for the bonding layer can be reduced, and the overall size can be made more compact.

[0029] [Method for Manufacturing Circuit Board] The circuit board according to this embodiment is manufactured by the following manufacturing method. FIG. 2 is a flowchart showing the manufacturing procedure for the circuit board according to this embodiment, and FIG. 3 is a flowchart showing the manufacturing procedure for a silicon nitride sintered body. In FIG. 2, first, a ceramic substrate is created (step S11). A general silicon nitride sintered body can be used for the ceramic substrate. The silicon nitride sintered body can be manufactured, for example, by the following method. In FIG. 3, first, raw material powder for the silicon nitride sintered body is weighed (step S21). The raw material powder for the silicon nitride sintered body may be an oxide, carbonate, hydroxide, nitride, or the like of each element contained in the silicon nitride sintered body. In addition to silicon nitride, examples of raw material powder for the silicon nitride sintered body include magnesium carbonate, calcium carbonate, and yttrium oxide.

[0030] Ethanol is added to these raw material powders, and the mixture is wet mixed and pulverized in a ball mill at, for example, 40 to 100 rpm for 6 to 60 hours to obtain a slurry. The slurry is dried in a hot water bath or a spray dryer to obtain a mixed powder (step S22).

[0031] Next, the mixed powder is filled into a mold and uniaxially pressed at a pressure of, for example, 30 MPa to form the desired shape. After that, a CIP (cold isostatic pressing) process is performed at a pressure of, for example, 100 to 150 MPa to obtain a compact (CIP pressed body) (Step S23). The obtained compact is placed in a silicon carbide mold with the inside coated with BN, and sintered at a maximum temperature of 1800 to 1900°C for 5 to 30 hours in a nitrogen atmosphere at 9 atmospheres to obtain a silicon nitride sintered body (Step S24).

[0032] 2, the resulting silicon nitride sintered body is processed to a predetermined shape and thickness (step S25) to produce a ceramic substrate. Processing can be performed by, for example, cutting, grinding, polishing, etc. The main surface of the ceramic substrate on the side to which the conductor layer or second conductor layer is bonded is preferably polished to a surface roughness Ra of 0.5 μm or less.

[0033] Separately from the manufacture of the ceramic substrate, a plate material of a predetermined thickness is prepared to serve as the conductor layer or second conductor layer. The plate material is preferably made of a metal containing copper, more preferably a metal primarily composed of copper, and even more preferably oxygen-free copper. Next, a metal film primarily composed of Ti to serve as a bonding layer is formed on one main surface of the plate material or ceramic substrate (step S12). The metal film can be formed by sputtering, vapor deposition, plating, or the like. The thickness of the metal film is preferably 3 μm or less. A metal film to serve as a second bonding layer may be formed on the other main surface. If a metal foil of a similar thickness can be prepared, forming a metal film is not necessary. Furthermore, prior to forming the metal film, it is preferable to include a step of removing organic matter, such as oil, from the surface of the ceramic substrate and plate material. Sufficient removal of organic matter from the surface is believed to suppress gas generation during heat treatment and contribute to copper diffusion. The organic matter removal step can be performed using various methods, such as degreasing, water washing, and acetone washing. These methods may be combined, or a drying step may be included.

[0034] Next, the plate material with the metal film formed thereon and the ceramic substrate are stacked so that the metal film is sandwiched between them (step S13). If no metal film is formed, the plate material, metal foil, and ceramic substrate are stacked in this order. Then, the plate material and the ceramic substrate can be bonded by HP treatment (hot pressing) or HIP treatment (hot isostatic pressing) (step S14). The HP treatment conditions can be, for example, a pressure of 5 MPa to 30 MPa, a maximum temperature of 850°C to 1050°C, and a maximum temperature holding time of 10 minutes to 2 hours.

[0035] The occurrence of Kirkendall voids varies depending on the maximum temperature and the time it is held at the maximum temperature during HP or HIP treatment. For example, if the maximum temperature is low or the time it is held at the maximum temperature is short, the interdiffusion of Cu in the conductor layer and Ti in the bonding layer does not progress, and Kirkendall voids do not occur near the interface between the conductor layer and the bonding layer. However, unbonded areas occur at the interface between the ceramic substrate and the bonding layer, and voids remain, resulting in a decrease in thermal conductivity (W / mK) and a decrease in heat cycle resistance.

[0036] Furthermore, if the maximum temperature is too high or the holding time at the maximum temperature is too long, the difference in the interdiffusion rate between the Cu in the conductor layer and the Ti in the bonding layer will cause a large number of Kirkendall voids to form near the interface between the conductor layer and the bonding layer, and in the worst case, these voids may join together to form cracks while the bonding is still in progress. Therefore, the present invention was achieved by adjusting the bonding temperature, holding time, and pressure.

[0037] This manufacturing method makes it possible to manufacture a circuit board that has high thermal cycle resistance and improved reliability while maintaining heat conductivity between the ceramic substrate and the conductor layer.

[0038] [Cold-Heat Cycle Test] The circuit boards of the examples and comparative examples were placed in a cold-heat cycle tester, and a maximum of 2,000 cold-heat cycle tests were performed, with one cycle consisting of "-40°C for 5 minutes," "220°C for 5 minutes," and "cooling to -40°C." An SAT test (ultrasonic flaw detection test) was then performed every 100 cycles to check for the presence or absence of cracks at the edge of the bonding layer. If a crack occurred, its length was measured, and if it was 1 mm or more, it was determined that a crack preventing continued use had occurred. A test board that developed a crack preventing continued use after less than 500 cycles was deemed to have failed (×), while a test board that developed a crack preventing continued use after 500 cycles or more was deemed to have passed. Among the passed tests, a test board that completed fewer than 1,000 cycles was deemed to have been good (◯), and a test board that completed 1,000 cycles or more was deemed to have been excellent (◎).

[0039] The measurement method was as follows. Specifically, the "Kirkendall void distance" was the maximum distance from the "cera substrate / bonding interface" to the "Kirkendall void." The "circle equivalent diameter of the Kirkendall void" was calculated by image analysis of a cross-sectional SEM photograph. The "area ratio of the Kirkendall void" was calculated by image analysis of a cross-sectional SEM photograph. That is, it was calculated from the region up to 10 μm from the "cera substrate / bonding interface." The "bonding layer thickness" was calculated from a cross-sectional SEM photograph. That is, a perpendicular line was drawn from the "cera substrate / bonding layer" interface on the cross-sectional photograph, and the average value of 10 measurements was used.

[0040] The results of this thermal cycling test are shown in Figure 4. As described above, according to the present invention, a circuit board having high thermal conductivity and high thermal cycling resistance can be obtained.

[0041] [Configuration of Power Device] Fig. 5 is a schematic cross-sectional view showing an example of a power device according to an embodiment of the present invention. In Fig. 5, the power device 100 includes a circuit board 50 and a power semiconductor 60. The circuit board 50 is the circuit board 50 described above. The circuit board 50 has a conductor layer 30 formed on at least one main surface of a ceramic substrate 10. The circuit board 50 may have a second conductor layer 32 formed on the other main surface opposite to the one main surface.

[0042] A power semiconductor 60 is mounted on the upper side of the conductor layer 30 of the circuit board 50. The power semiconductor 60 and the conductor layer 30 may be joined using solder 52 or the like. The power semiconductor 60 may be, for example, a semiconductor for use in an EV that flows a large current and is prone to high temperatures. The circuit board 50 of the present invention has increased bonding strength while maintaining heat dissipation properties, and therefore has high resistance to thermal cycles. Therefore, even if a large thermal stress is generated in the ceramic substrate 10 due to the difference in thermal expansion between the ceramic substrate 10 and the joined metal due to high temperatures, cracks or breakage are unlikely to occur.

[0043] When the circuit board 50 includes the second conductor layer 32, the heat sink 70 may be joined to the underside of the second conductor layer 32. The heat sink 70 and the second conductor layer 32 may be joined using solder 52 or the like.

[0044] The surface of the heat sink 70 opposite to the surface bonded to the second conductor layer 32 may be in contact with the heat dissipation member 80 via grease 72 or the like. The heat sink 70 is preferably made of metal, more preferably made of a metal containing copper as a main component, and even more preferably made of oxygen-free copper. The heat dissipation member 80 preferably has heat dissipation fins formed thereon. The heat dissipation member 80 is preferably made of metal, more preferably made of a metal containing copper or aluminum as a main component.

[0045] As described above, according to this embodiment, it is possible to realize a circuit board having high thermal conductivity and excellent heat cycle resistance, and a power device using the same.

[0046] Although Kirkendall voids are shown as voids in the above-described embodiments and examples, the voids are not necessarily limited to Kirkendall voids. For example, a porous plate having a predetermined pore size can be used as the conductive layer, and the ceramic substrate and the porous plate are bonded to each other through a thin metal film that serves as a bonding layer, and then heated and pressurized until the voids reach the desired pore size. In this case, the voids are distributed throughout the conductive layer. Therefore, if it is desired to have voids only near the bonding layer, a flat, dense plate on which particles of the same material are deposited can be prepared, and the particle-deposited side of the plate and the ceramic substrate are bonded to each other through a thin metal film that serves as a bonding layer, and then heated and pressurized until voids with the desired pore size are formed in the particle-deposited area.

[0047] REFERENCE SIGNS LIST 10 ceramic substrate 30 conductor layer 32 second conductor layer 50 circuit board 52 solder 60 power semiconductor 70 heat sink 72 grease 80 heat dissipation member 100 power device

Claims

1. A circuit board comprising: a ceramic substrate made of a material primarily composed of silicon nitride; a bonding layer formed on one main surface of said ceramic substrate; and a conductor layer bonded to said ceramic substrate via said bonding layer, wherein the distance from the interface between said ceramic substrate and said bonding layer is 10 μm or less, and the maximum value of the circle-equivalent diameter of voids present in said conductor layer is 2 μm or less.

2. The circuit board according to claim 1, wherein said voids are Kirkendall voids.

3. The circuit board according to claim 2, characterized in that the Kirkendall voids present in the conductor layer at a distance of 10 μm or less from the interface and in a cross section perpendicular to the surface direction have an area ratio of 10% or less.

4. The circuit board according to any one of claims 1 to 3, wherein the thickness of the bonding layer is 3 μm or less.

5. The circuit board according to any one of claims 1 to 3, wherein the conductor layer is mainly composed of Cu, and the bonding layer contains at least Ti.

6. A power device comprising: a circuit board according to any one of claims 1 to 3; and a power semiconductor mounted on the conductor layer.

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