Display device

Abstract

The present invention provides a display device capable of achieving improved display characteristics. This display device comprises: a plurality of display elements; a plurality of pixel ICs that are connected to at least one of the plurality of display elements; and a driver IC that supplies a clock signal and image data to the plurality of pixel ICs connected in a daisy chain. Each of the plurality of daisy-chained pixel ICs includes a clock shaping circuit that performs waveform shaping on the input clock signal. At least one of the plurality of clock shaping circuits is either a first circuit that generates, as a clock signal to be output to a subsequent-stage pixel IC, a signal obtained by exchanging a high-potential period and a low-potential period of the input clock signal, or a second circuit that generates, as the clock signal to be output to the subsequent-stage pixel IC, a signal having a high potential for a predetermined period from the rising edge of the input clock signal.

Description

display device

[0001] The present invention relates to a display device.

[0002] Patent Documents 1 and 2 disclose techniques in which a pixel IC (referred to as a pixel controller or controller in Patent Documents 1 and 2) is connected to one or more pixels.

[0003] US Patent No. 10,832,609 JP 2014-63845 A

[0004] In Patent Document 1, pixel ICs arranged in a matrix are controlled by a row controller and a column controller so as to synchronize with each other in the row and column directions. In Patent Document 1, it is necessary to ensure synchronization in the row and column directions, and there is a possibility that good display characteristics cannot be obtained in a display device with a large number of pixels, for example.

[0005] In Patent Document 2, brightness data and a clock signal are branched and supplied in parallel to each controller connected to a plurality of LEDs. Therefore, when a large number of LEDs are connected, data transmission may become difficult. Furthermore, Patent Document 2 is a technology related to an LED lighting device, and does not take into consideration a display device in which a large number of pixels are arranged.

[0006] An object of the present disclosure is to provide a display device capable of improving display characteristics.

[0007] A display device according to one aspect of the present disclosure comprises a plurality of display elements, a plurality of pixel ICs connected to at least one of the plurality of display elements, and a driver IC that supplies a clock signal and image data to the plurality of pixel ICs connected in a daisy chain, wherein the plurality of pixel ICs connected in a daisy chain each comprise a clock shaping circuit that shapes the waveform of an input clock signal, and at least one of the plurality of clock shaping circuits is either a first circuit that generates a signal in which the high potential period and the low potential period of the input clock signal are swapped as a clock signal to be output to a subsequent pixel IC, or a second circuit that generates a signal that becomes a high potential for a predetermined period from the rising edge of the input clock signal as a clock signal to be output to a subsequent pixel IC.

[0008] A display device according to one aspect of the present disclosure comprises a plurality of display elements, a plurality of pixel ICs connected to at least one of the plurality of display elements, and a driver IC that supplies a clock signal and image data to the plurality of pixel ICs connected in a daisy chain, wherein the plurality of pixel ICs connected in a daisy chain each comprise a clock shaping circuit that performs waveform shaping of an input clock signal, and the clock shaping circuit is configured to be able to select either a first function of generating a signal in which the high potential period and the low potential period of the input clock signal are swapped as a clock signal to be output to a subsequent pixel IC, or a second function of generating a signal that becomes a high potential for a predetermined period from the rising edge of the input clock signal as a clock signal to be output to a subsequent pixel IC.

[0009] FIG. 1 is a plan view schematically showing a display device according to a first embodiment. FIG. 2 is a plan view showing pixels of the display device according to the first embodiment. FIG. 3 is a circuit diagram showing a driver IC, a plurality of pixel ICs, and a plurality of light-emitting elements. FIG. 4 is a block diagram showing an example of the configuration of a pixel IC. FIG. 5 is a timing chart showing clock signals and image data in the pixel IC. FIG. 6 is a timing chart schematically showing a display operation for one frame. FIG. 7 is an explanatory diagram for explaining an example of the configuration of image data transmitted and received by the pixel IC. FIG. 8 is an explanatory diagram for explaining a method of rewriting identification information. FIG. 9 is a schematic connection diagram of a clock shaping circuit between pixel ICs according to the first embodiment. FIG. 10 is a conceptual diagram showing an example of a clock signal waveform between pixel ICs according to the first embodiment. FIG. 11 is a block diagram showing an example of the configuration of pixel ICs according to the first embodiment. FIG. 12 is a schematic connection diagram of a clock shaping circuit between pixel ICs according to the first embodiment. FIG. 13 is a conceptual diagram showing an example of a clock signal waveform between pixel ICs according to the first embodiment. FIG. 14 is a block diagram showing an example of the configuration of a pixel IC according to a second embodiment. FIG. 15 is a block diagram showing an example of the configuration of a clock shaping circuit according to the second embodiment. FIG. 16 is a conceptual diagram showing waveforms of each part of a clock signal in a clock shaping circuit according to embodiment 2. FIG. 17 is a block diagram showing a configuration example of a clock shaping circuit according to a modification of embodiment 2. FIG. 18 is a conceptual diagram showing waveforms of each part of a clock signal in a clock shaping circuit according to a modification of embodiment 2. FIG. 19 is a schematic connection diagram of a clock shaping circuit between pixel ICs according to embodiment 3. FIG. 20 is a conceptual diagram showing an example of a clock signal waveform between pixel ICs according to embodiment 3. FIG. 21 is a schematic connection diagram of a clock shaping circuit between pixel ICs according to a modification of embodiment 3. FIG. 22 is a conceptual diagram showing an example of a clock signal waveform between pixel ICs according to a modification of embodiment 3. FIG. 23 is a block diagram showing a configuration example of a pixel IC according to embodiment 4.

[0010] Modes (embodiments) for carrying out the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Furthermore, the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this specification and each figure, elements similar to those described above with reference to the previous figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] 1 is a plan view schematically showing a display device according to embodiment 1. As shown in Fig. 1, the display device 1 includes a substrate 21, a plurality of pixels PX, driver ICs (Integrated Circuits) 11A and 11B, clock signal supply wiring 12, image data supply wiring 13, and a host 101. The host 101 is a host IC, a host CPU, or the like.

[0012] The substrate 21 is an insulating substrate made of glass, a film-like resin, etc. The substrate 21 is a substrate on which the pixel ICs 50 for driving the pixels PX and the plurality of light-emitting elements 3 (see FIG. 2) are mounted.

[0013] In the following description, the first direction Dx and the second direction Dy are directions parallel to the surface of the substrate 21. The first direction Dx is perpendicular to the second direction Dy. However, the first direction Dx may intersect with the second direction Dy without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy. The third direction Dz corresponds to, for example, the normal direction of the substrate 21. Note that hereinafter, a planar view refers to the positional relationship when viewed from the third direction Dz.

[0014] 1, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area that is arranged to overlap with a plurality of pixels PX and displays an image. The peripheral area GA is an area that does not overlap with the plurality of pixels PX and is arranged outside the display area AA.

[0015] The plurality of pixels PX are arranged in a matrix in the display area AA of the substrate 21. That is, the plurality of pixels PX are arranged in a first direction Dx and in a second direction Dy. The plurality of pixels PX arranged in the second direction Dy are connected in series via clock signal supply wiring 12 and image data supply wiring 13. In the following description, the plurality of pixels PX connected in series may be referred to as a pixel group PX-G.

[0016] The pixel group PX-G (plurality of pixels PX connected in series) is arranged in the second direction Dy in the order of pixel PX-1, pixel PX-2, pixel PX-3, ..., pixel PX-(N-2), pixel PX-(N-1), and pixel PX-N. Of the (pixel group PX-G) (plurality of pixels PX connected in series), pixel PX-1 located at one end in the second direction Dy is connected to driver ICs 11A and 11B. Furthermore, clock signal supply wiring 12 and image data supply wiring 13 are not provided between the plurality of pixels PX adjacent to each other in the first direction Dx, and therefore transmission and reception of various signals is not performed.

[0017] The driver ICs 11A and 11B are circuits that control the display of the display device 1. The driver ICs 11A and 11B are provided in the peripheral area GA of the substrate 21. The driver ICs 11A and 11B supply a clock signal CK and image data DT (see FIG. 3) to each of the pixel groups PX-G. The driver ICs 11A and 11B also supply the clock signal CK and image data DT in synchronization with each other to the plurality of pixel groups PX-G arranged in the first direction Dx. Note that a detailed connection configuration of the driver ICs 11A and 11B and the plurality of pixels PX will be described later with reference to FIG. 3.

[0018] The driver ICs 11A and 11B are arranged adjacent to each other in the first direction Dx. The driver IC 11A controls the display of a plurality of pixels PX located on the left side of the center of the display area AA in the first direction Dx, among the plurality of pixels PX. The driver IC 11B controls the display of a plurality of pixels PX located on the right side of the center of the display area AA in the first direction Dx, among the plurality of pixels PX. The driver IC 11A and the driver IC 11B control the pixel group PX-G in synchronization with each other. However, this is not limited to this, and the display device 1 may have one driver IC 11 or three or more driver ICs 11.

[0019] FIG. 2 is a plan view showing pixels of the display device according to the first embodiment. As shown in FIG. 2, one pixel PX includes a plurality of pixels SPX and a pixel IC 50. For example, the pixel PX includes a pixel SPX-R, a pixel SPX-G, and a pixel SPX-B. The pixel SPX-R displays a primary color of red as a first color. The pixel SPX-G displays a primary color of green as a second color. The pixel SPX-B displays a primary color of blue as a third color. As shown in FIG. 2, in one pixel PX, the pixels SPX-R, SPX-G, and SPX-B are aligned in the first direction Dx. Note that the first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color, such as a complementary color, can be selected. Hereinafter, when there is no need to distinguish between the pixels SPX-R, SPX-G, and SPX-B, they will be simply referred to as pixel SPX.

[0020] Each pixel SPX has a light-emitting element 3, a cathode electrode 31, and an anode electrode 32. The display device 1 displays an image by emitting different light from each of the light-emitting elements 3R, 3G, and 3B in the pixels SPX-R, SPX-G, and SPX-B. That is, the light-emitting elements 3R, 3G, and 3B are display elements of the display device 1, and are self-emitting elements that emit red light, green light, and blue light, respectively.

[0021] The light-emitting element 3 is an inorganic light-emitting diode (LED) chip having a size of approximately 3 μm or more and 300 μm or less in plan view, and is called a micro LED. A display device 1 having a micro LED in each pixel is also called a micro LED display device. Note that the "micro" in micro LED does not limit the size of the light-emitting element 3.

[0022] The plurality of light-emitting elements 3 may emit light of four or more different colors. The arrangement of the plurality of pixels SPX is not limited to the configuration shown in Fig. 2. For example, one pixel SPX among the plurality of pixels SPX may be adjacent to another pixel SPX in the second direction Dy. The plurality of pixels SPX may also be arranged in a triangular lattice pattern.

[0023] The pixel IC 50 is formed of, for example, a micro IC, and is provided for each pixel PX. In the example shown in FIG. 2 , one pixel IC 50 is provided for three pixels SPX. The pixel IC 50 is connected to the cathode electrode 31 (cathode of the light-emitting element 3) of each pixel SPX via wiring 14. The pixel IC 50 is also connected to the anode electrode 32 (anode of the light-emitting element 3) of each pixel SPX via wiring 15. The pixel IC 50 controls the flow of a predetermined current through each light-emitting element 3 based on control signals (clock signal CK and image data DT) from the driver ICs 11A and 11B, causing the light-emitting element 3 to emit light.

[0024] 2 shows a configuration in which one pixel IC 50 is connected to three light-emitting elements 3, but this is not limiting, and one pixel IC 50 may be connected to at least one light-emitting element 3. Alternatively, one pixel IC 50 may be connected to four or more light-emitting elements 3. Furthermore, the pixel IC 50 is not limited to a configuration in which it is provided for each pixel PX, and one pixel IC 50 may be provided for a plurality of pixels PX (for example, two adjacent pixels PX).

[0025] 2, the plurality of light-emitting elements 3 are mounted on a common substrate 21 together with the pixel ICs 50. However, the present invention is not limited to this, and the plurality of light-emitting elements 3 may be mounted on a mounting substrate different from the substrate 21. In this case, the plurality of light-emitting elements 3 are mounted on the substrate 21 together with the mounting substrate, and the pixel ICs 50 are electrically connected to the plurality of light-emitting elements 3 through the mounting substrate.

[0026] 3 is a circuit diagram showing a driver IC, a plurality of pixel ICs, and a plurality of light-emitting elements. As shown in FIG. 3, the display device 1 has a plurality of light-emitting elements 3 (display elements), a plurality of pixel ICs 50, and a driver IC 11. The plurality of pixel ICs 50 include a first pixel IC 50-1, a second pixel IC 50-2, and a third pixel IC 50-3 connected in series. The first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 are provided corresponding to the pixels PX-1, PX-2, and PX-3 (see FIG. 1), respectively.

[0027] For ease of understanding, FIG. 3 shows three rows and two columns of pixel ICs (pixels PX) among the multiple pixel ICs (pixels PX). In the following description, when there is no need to distinguish between the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3, they will simply be referred to as pixel ICs 50. When there is no need to distinguish between the driver ICs 11A and 11B, they will simply be referred to as driver ICs 11. When there is no need to distinguish between the clock signal supply wirings 12-1, 12-2, 12-3, and 12-4, they will simply be referred to as clock signal supply wiring 12. When there is no need to distinguish between the image data supply wirings 13-1, 13-2, 13-3, and 13-4, they will simply be referred to as image data supply wiring 13.

[0028] Each of the pixel ICs 50 has a clock signal input terminal 51, an image data input terminal 52, a clock signal output terminal 53, and an image data output terminal 54. A clock signal CK is input to the clock signal input terminal 51. Image data DT is input to the image data input terminal 52. The clock signal output terminal 53 outputs the clock signal CK. The image data output terminal 54 outputs the image data DT.

[0029] The plurality of clock signal supply wirings 12-1, 12-2, 12-3, and 12-4 are provided independently between two pixel ICs 50 adjacent to each other in the second direction Dy. Similarly, the plurality of image data supply wirings 13-1, 13-2, 13-3, and 13-4 are provided independently between two pixel ICs 50 adjacent to each other in the second direction Dy.

[0030] The pixel ICs 50 arranged in the second direction Dy are connected in a so-called daisy chain manner via the clock signal supply wiring 12 and the image data supply wiring 13. Hereinafter, the daisy chain connection manner will also be simply referred to as a "daisy chain connection." Multiple sets of circuits in which the pixel ICs 50 are daisy chain connected are connected in parallel to the driver ICs 11A and 11B.

[0031] Specifically, the clock signal input terminal 51 of the first pixel IC 50-1 is connected to the driver IC 11 via the clock signal supply wiring 12-1, and the image data input terminal 52 of the first pixel IC 50-1 is connected to the driver IC 11 via the image data supply wiring 13-1.

[0032] The clock signal output terminal 53 of the first pixel IC 50-1 is connected to the clock signal input terminal 51 of the second pixel IC 50-2 via the clock signal supply wiring 12-2. The image data output terminal 54 of the first pixel IC 50-1 is connected to the image data input terminal 52 of the second pixel IC 50-2 via the image data supply wiring 13-2.

[0033] The clock signal output terminal 53 of the second pixel IC 50-2 is connected to the clock signal input terminal 51 of the third pixel IC 50-3 via the clock signal supply wiring 12-3. The image data output terminal 54 of the second pixel IC 50-2 is connected to the image data input terminal 52 of the third pixel IC 50-3 via the image data supply wiring 13-3.

[0034] In other words, the multiple clock signal supply wirings 12 are provided between two pixel ICs 50 adjacent to each other in the second direction Dy, and are spaced apart from each other for each pixel IC 50. Similarly, the multiple image data supply wirings 13 are provided between two pixel ICs 50 adjacent to each other in the second direction Dy, and are spaced apart from each other for each pixel IC 50. As a result, the first pixel IC 50-1, second pixel IC 50-2, and third pixel IC 50-3 arranged in the second direction Dy are connected in series.

[0035] The clock signal CK output from the driver IC 11 is sequentially transmitted in series to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 via the clock signal supply wiring 12. Furthermore, the image data DT output from the driver IC 11 is sequentially transmitted in series to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 via the image data supply wiring 13.

[0036] As a result, the display device 1 of this embodiment can increase the bandwidth (frequency) of the transmitted clock signal CK and image data DT compared to when multiple pixel ICs 50 are connected in parallel to a common clock signal supply wiring 12 and a common image data supply wiring 13. In other words, the display device 1 can suppress voltage fluctuations and delays in the clock signal CK and image data DT due to the wiring resistance of the clock signal supply wiring 12 and the image data supply wiring 13. This also allows the phase relationship between the clock signal CK and the image data DT to be maintained. Therefore, the display device 1 of this embodiment can achieve good display characteristics even when the number of daisy-chained pixels PX is increased. For example, the display device 1 can be applied to full HD displays, 4K displays, and displays with even greater pixel counts.

[0037] Note that the clock signal supply wiring 12 and the image data supply wiring 13 are not provided between the pixel ICs 50 adjacent to each other in the first direction Dx, and therefore the clock signal CK and the image data DT are not transmitted or received between the pixel ICs 50. The driver IC 11 outputs the clock signal CK and the image data DT in synchronization with each other among the plurality of pixel ICs 50 (the plurality of pixel groups PX-G) arranged in the first direction Dx.

[0038] The plurality of pixel ICs 50 further include a power supply terminal 55, a reference potential terminal 56, and connection terminals 57, 58, and 59 (see FIG. 4 ). The power supply terminal 55 is connected to the driver IC 11 via a power supply potential supply wiring 17. As a result, the driver IC 11 supplies a power supply potential PVDD to the plurality of pixel ICs 50 through the power supply terminal 55 and the power supply potential supply wiring 17. The power supply potential supply wiring 17 is also connected to the anodes of the light-emitting elements 3 (3R, 3G, and 3B). The driver IC 11 supplies the power supply potential PVDD to the anodes of the light-emitting elements 3 (3R, 3G, and 3B) through the power supply potential supply wiring 17.

[0039] The pixel ICs 50 and the light-emitting elements 3 are connected in parallel to the power supply potential supply wiring 17. In other words, the power supply potential supply wiring 17 is provided in common to the pixel ICs 50 and the light-emitting elements 3 arranged in the second direction Dy. In addition, in Fig. 3, the power supply potential supply wiring 17 is provided in common to two columns of the pixel ICs 50 and the light-emitting elements 3 aligned in the first direction Dx. However, the present invention is not limited to this, and the power supply potential supply wiring 17 may be provided in common to one column or three or more columns of the pixel ICs 50 and the light-emitting elements 3.

[0040] The reference potential terminal 56 is connected to the driver IC 11 via the reference potential supply wiring 18. As a result, the driver IC 11 supplies a reference potential GND to the plurality of pixel ICs 50 via the reference potential terminal 56 and the reference potential supply wiring 18. The reference potential GND is, for example, a ground potential. However, the reference potential GND is not limited to this, and may be a predetermined fixed potential different from the ground potential.

[0041] The reference potential supply wiring 18 is provided in common to the plurality of pixel ICs 50 arranged in the second direction Dy. In other words, the plurality of pixel ICs 50 are connected in parallel to the reference potential supply wiring 18. In Fig. 3, the reference potential supply wiring 18 is provided in common to the plurality of pixel ICs 50 in two columns aligned in the first direction Dx. However, the present invention is not limited to this, and the reference potential supply wiring 18 may be provided in common to one column or three or more columns of the plurality of pixel ICs 50.

[0042] The connection terminals 57, 58, and 59 are connected to the cathodes of the light-emitting elements 3R, 3G, and 3B, respectively. The cathodes of the light-emitting elements 3R, 3G, and 3B are connected to the reference potential GND via the drive transistors inside the light-emitting element drive circuit 68 (see FIG. 4) by operation of the light-emitting element drive circuit 68 of the pixel IC 50. As a result, the light-emitting elements 3R, 3G, and 3B are each forward-bias driven and emit light.

[0043] Fig. 4 is a block diagram showing an example of the configuration of a pixel IC. As shown in Fig. 4, the pixel IC 50 includes a clock shaping circuit 610, a buffer circuit 62, flip-flop circuits 63 and 64, a control circuit 65, a PWM control circuit 66, a memory circuit 67, and a light-emitting element drive circuit 68 (display element drive circuit). In the configuration of the pixel IC 50 shown in Fig. 4, the clock shaping circuit 610 is a buffer circuit.

[0044] The clock shaping circuit 610 is connected between the clock signal input terminal 51 and the clock signal output terminal 53. As a result, the clock signal CK input to the clock signal input terminal 51 of the pixel IC 50 is output from the clock signal output terminal 53 via the clock shaping circuit 610. The buffer circuit constituting the clock shaping circuit 610 corrects for voltage fluctuations in the clock signal CK caused by resistance of the clock signal supply wiring 12, wiring within the pixel IC 50, and the like, and outputs the clock signal CK. As a result, in a configuration in which multiple pixel ICs 50 are daisy-chain connected, the clock signal CK reaches the pixel IC 50 in the final stage (the Nth pixel IC 50-N).

[0045] The flip-flop circuit 63 is connected between the clock signal input terminal 51 and the image data input terminal 52 and the control circuit 65. The buffer circuit 62 and the flip-flop circuit 64 are connected in series between the control circuit 65 and the image data output terminal 54.

[0046] The flip-flop circuit 63 receives the clock signal CK from the clock signal input terminal 51 and the image data DT from the image data input terminal 52, and outputs the image data DT to the control circuit 65 at a timing according to the clock signal CK.

[0047] The control circuit 65 controls the lighting of the light-emitting elements 3 connected to the pixel ICs 50 based on the image data DT input through the image data input terminals 52 and the flip-flop circuits 63. The control circuit 65 performs predetermined processing on the input image data DT and outputs the result to the buffer circuit 62. The predetermined processing of the image data DT by the control circuit 65 and the detailed operations of the PWM control circuit 66, the memory circuit 67, and the light-emitting element drive circuit 68 will be described later with reference to FIG. 6 and subsequent figures.

[0048] The buffer circuit 62 corrects and outputs the image data DT for voltage fluctuations and delay time caused by resistance of the image data supply wiring 13 and wiring within the pixel IC 50. The delay time is corrected by adjusting the delay time so that the delay time of the data obtained by performing predetermined processing on the image data DT is not shorter than the delay time caused by the clock shaping circuit 610 provided for the clock signal CK.

[0049] The flip-flop circuit 64 receives a clock signal CK supplied from the clock signal input terminal 51 through the clock shaping circuit 610, and image data DT from the image data input terminal 52 via the flip-flop circuit 63, the control circuit 65, and the buffer circuit 62. The flip-flop circuit 64 outputs the image data DT to the image data output terminal 54 at a timing according to the clock signal CK.

[0050] 5 is a timing chart showing clock signals and image data in a pixel IC, which shows a clock signal CK (IN) input to a clock signal input terminal 51, image data DT (IN) input to an image data input terminal 52, a clock signal CK (OUT) output from a clock signal output terminal 53, and image data DT (OUT) output from an image data output terminal 54.

[0051] 5, the clock signal CK(OUT) output from the clock signal output terminal 53 is slightly delayed relative to the clock signal CK(IN) due to the operation of the buffer circuit that constitutes the clock shaping circuit 610. For example, the delay of the clock signal CK(OUT) is the difference between time t2 and time t1 shown in FIG.

[0052] The flip-flop circuits 63 and 64 output the image data DT at the rising (or falling) timing of the clock signal CK. That is, the image data DT is output from each of the flip-flop circuits 63 and 64 with a delay of one bit relative to the clock signal CK.

[0053] Specifically, as shown in Fig. 5, the image data DT includes multiple image data DT(a), DT(b), DT(c), and DT(d). Note that the image data DT(a), DT(b), DT(c), and DT(d) are shown schematically for ease of understanding. The structure of the image data DT will be described later with reference to Fig. 7.

[0054] Focusing on image data DT(a) of the image data DT, the image data DT(a) is input to image data input terminal 52 a predetermined time after time t1 when clock signal CK(IN) is input to clock signal input terminal 51. In first-stage flip-flop circuit 63, image data DT(a) is output at the rising edge of clock signal CK(IN) (time t3). In other words, image data DT(a) is delayed by one bit relative to clock signal CK(IN).

[0055] In the second-stage flip-flop circuit 64, the image data DT(a) is output at the rising edge of the clock signal CK(OUT) (time t8). As a result, compared with the timing relationship between the input clock signal CK(IN) and the image data DT(IN), the image data DT(OUT) is output with a delay of a total of two bits relative to the clock signal CK(OUT).

[0056] As described above, in the pixel ICs 50, the clock shaping circuit 610, the buffer circuit 62, and the flip-flop circuits 63 and 64 cause the image data DT(OUT) output from the image data output terminal 54 to be delayed by a predetermined number of bits (for example, 2 bits) relative to the clock signal CK(OUT) output from the clock signal output terminal 53. However, the timing relationship (delay time) between the clock signal CK(OUT) and the image data DT(OUT) is substantially the same for each of the multiple pixel ICs 50. This allows the display device 1 to display images satisfactorily even in a configuration where horizontal synchronization is not achieved (for example, where there is no gate drive signal in an active matrix system).

[0057] Next, a method for processing the image data DT by the control circuit 65 and PWM driving of the plurality of light-emitting elements 3 will be described with reference to FIGS. 4 and 6 to 8. FIG.

[0058] FIG. 6 is a timing chart schematically illustrating the display operation of one frame. The light-emitting elements 3 connected to the pixel ICs 50 are controlled by PWM (Pulse Width Modulation) driving. As shown in FIG. 6, the daisy-chained pixel ICs 50 (the first pixel IC 50-1 to the Nth pixel IC 50-N) sequentially acquire image data DT. Each of the pixel ICs 50 (the first pixel IC 50-1 to the Nth pixel IC 50-N) PWM-drives the light-emitting elements 3 based on the acquired image data DT. Furthermore, the light-emitting elements 3 of the pixel ICs 50 arranged in parallel in the first direction Dx are PWM-driven in synchronization with one another by a clock signal CK supplied from the driver IC 11. This displays an image for one frame (1F).

[0059] 6, the light-emitting element PWM drive period is arranged in a time-division manner in which the light-emitting element 3 is turned on and off depending on the gradation. The light-emitting element 3 may be controlled in any manner. For example, the light-emitting element 3 may be turned on and off in a plurality of periods as needed.

[0060] 4 performs predetermined processing on the input image data DT and outputs the processed data to a storage circuit 67, and also controls a PWM control circuit 66 and a light-emitting element drive circuit 68 based on the input image data DT. The storage circuit 67 stores the image data DT input from the control circuit 65. The PWM control circuit 66 determines the lighting periods of the plurality of light-emitting elements 3 corresponding to the gradation based on the image data DT acquired from the control circuit 65, and generates a PWM control signal.

[0061] The light-emitting element drive circuit 68 drives the plurality of light-emitting elements 3 connected to the connection terminals 57, 58, and 59 of the pixel IC 50 based on the PWM control signal acquired from the PWM control circuit 66. Specifically, the light-emitting element drive circuit 68 may be configured to include, for example, a plurality of switch elements that switch the connection state between the cathodes of the light-emitting elements 3 and the reference potential terminal 56. For example, the light-emitting element drive circuit 68 may be configured to include a plurality of switch elements that switch the connection (on) and disconnection (off) between the cathodes of the light-emitting elements 3 and the reference potential GND based on the PWM control signal. During a predetermined period when the cathodes of the light-emitting elements 3 are connected to the reference potential GND, a current flows through the light-emitting elements 3, causing them to light up. Furthermore, during a period when the cathodes of the light-emitting elements 3 are not connected to the reference potential GND, the light-emitting elements 3 are turned off. By varying the on and off periods based on the PWM control signal, the light-emitting elements 3 can express gradations corresponding to the image data DT. As described above, the plurality of light-emitting elements 3 are driven by PWM (Pulse Width Modulation) based on the image data DT acquired by the control circuit 65 .

[0062] FIG. 7 is an explanatory diagram schematically illustrating an example of the configuration of image data transmitted and received by a pixel IC. As shown in FIG. 7, the image data DT includes multiple pixel data DTp corresponding to multiple serially connected pixels PX (pixels SPX). That is, the image data DT includes multiple pixel data DTp (e.g., (N×3) pixel data DTp) corresponding to multiple serially connected pixels PX (e.g., N pixels PX). For ease of understanding, FIG. 7 shows three pixel data DTp corresponding to one pixel PX (pixel IC 50). The three pixel data DTp correspond to multiple light-emitting elements 3R, 3G, and 3B (pixels SPX-R, SPX-G, and SPX-B) connected to the pixel IC 50, respectively. The light-emitting elements 3 connected to each of the multiple pixel ICs 50 are driven based on the pixel data DTp corresponding to the light-emitting element 3, out of the image data DT.

[0063] In each pixel data DTp, the data start signal Start is set to "0" and the data end signal Stop is set to "1." The period T between adjacent pixel data DTp is a period that does not include pixel data, and is all set to "1."

[0064] Here, the period T between adjacent pixel data DTp can be set arbitrarily so that the driver IC 11 (see FIG. 3) that transmits the image data DT matches the video data input from the external host 101 (see FIG. 1).

[0065] 3, the driver IC 11 receives video data and stores it in the line memory 16. When one row of image data DT (image data DT corresponding to a plurality of pixels PX-1 arranged in the first direction Dx) is accumulated, the driver IC 11 transmits the image data DT to the first pixel IC 50-1 in the first row. At this time, the clock signal CK is set to a sufficiently high frequency so that the driver IC 11 finishes transmitting the image data DT for one row before the image data DT for the next row is accumulated.

[0066] The driver IC 11 can synchronize the reception of video data with the transmission of image data DT by setting the period T between adjacent pixel data DTp shown in FIG. 7 to any period. Furthermore, because the driver IC 11 can set the period T to any period, it does not need to provide a frame memory for storing image data DT for an entire frame (F), and only needs to provide a line memory 16 for storing at least one row of image data DT. The driver IC 11 can reduce the memory capacity compared to when a frame memory is provided, thereby enabling a smaller circuit size. Furthermore, if it is not necessary to output one row of image data DT at the same time, the line memory 16 may be omitted.

[0067] 7, the pixel data DTp includes multiple pieces of lighting information L that respectively light up multiple light-emitting elements 3, and identification information V corresponding to the lighting information L. For example, the pixel data DTp is 17 bits long, and includes 16 bits of lighting information L and 1 bit of identification information V. The lighting information L is, for example, a 16-bit PWM value, and is set for each of the multiple pieces of pixel data DTp according to the gradation of each pixel PX. Note that the PWM value is not limited to 16 bits, and can be changed as appropriate according to the gradation of the pixel PX.

[0068] The control circuit 65 acquires lighting information L corresponding to each light-emitting element 3 connected to the pixel IC 50 from among the plurality of lighting information L corresponding to the plurality of serially connected pixels PX, based on the identification information V. More specifically, the image data DT includes pixel data DTp (identification information V and lighting information L) corresponding to each light-emitting element 3 of the plurality of serially connected pixel ICs 50 (first pixel IC50-1 to Nth pixel IC50-N).

[0069] The control circuit 65 included in the first pixel IC 50-1 acquires, from the plurality of pieces of lighting information L, lighting information L that corresponds to each of the light-emitting elements 3R, 3G, 3B connected to the first pixel IC 50-1, based on the identification information V. The control circuit 65 included in the second pixel IC 50-2 acquires, from the plurality of pieces of lighting information L, lighting information L that corresponds to each of the light-emitting elements 3R, 3G, 3B connected to the second pixel IC 50-2, based on the identification information V. The control circuit 65 included in the Nth pixel IC 50-N in the final stage acquires, from the plurality of pieces of lighting information L, lighting information L that corresponds to each of the light-emitting elements 3R, 3G, 3B connected to the Nth pixel IC 50-N, based on the identification information V.

[0070] Next, a method for processing image data DT by the control circuit 65 will be described with reference to FIG. 8. FIG. 8 is an explanatory diagram for explaining a method for rewriting identification information. Note that, for ease of understanding, FIG. 8 shows only the identification information V of the image data DT. However, as shown in FIG. 7, the image data DT includes lighting information L corresponding to each of the identification information V. Also, FIG. 8 describes a configuration in which the image data DT includes N pieces of identification information V(1), V(2), V(3), ..., V(N-1), V(N) corresponding to N pixels PX connected in series.

[0071] As shown in Figure 8, in the image data DT input to the first pixel IC50-1 in the first row, all of the identification information V(1), V(2), V(3), ..., V(N-1), V(N) is set to "1" in advance.

[0072] The control circuit 65 of the first pixel IC 50-1 first retrieves pixel data DTp (lighting information L) whose identification information V is "1" from the input image data DT. Then, the control circuit 65 of the first pixel IC 50-1 transmits the retrieved pixel data DTp (lighting information L) based on the initial identification information V(1) to the memory circuit 67.

[0073] The control circuit 65 of the first pixel IC 50-1 rewrites the identification information V(1) corresponding to the acquired lighting information L from "1" to "0." Then, the control circuit 65 of the first pixel IC 50-1 outputs the image data DT having the rewritten identification information V from the image data output terminal 54.

[0074] The control circuit 65 of the second pixel IC 50-2 in the next stage retrieves pixel data DTp (lighting information L) corresponding to the identification information V(2) whose identification information V is "1" first among the input image data DT. In other words, the control circuit 65 of the second pixel IC 50-2 does not retrieve pixel data DTp corresponding to the identification information V(1) whose identification information V is "0". The control circuit 65 of the second pixel IC 50-2 transmits the pixel data DTp (lighting information L) retrieved based on the second identification information V(2) to the memory circuit 67.

[0075] The control circuit 65 of the second pixel IC 50-2 rewrites the identification information V(2) corresponding to the acquired lighting information L from "1" to "0." Then, the control circuit 65 of the second pixel IC 50-2 outputs the image data DT having the rewritten identification information V from the image data output terminal 54.

[0076] The third pixel IC50-3 to the Nth pixel IC50-N sequentially acquire pixel data DTp (lighting information L) based on the identification information V and rewrite the identification information V. The Nth pixel IC50-N in the final stage acquires pixel data DTp (lighting information L) corresponding to the identification information V(N) whose identification information V is "1" first among the input image data DT.

[0077] The control circuit 65 of the Nth pixel IC 50-N rewrites the identification information V(N) corresponding to the acquired lighting information L from "1" to "0", and the capture of the image data DT for one frame (1F) is completed.

[0078] As described above, image data DT including multiple pieces of pixel data DTp is serially transmitted between multiple serially connected pixels PX (multiple pixel ICs 50 connected in a daisy chain), and the pixel IC 50 of each pixel PX retrieves the pixel data DTp corresponding to that pixel PX from the image data DT. At this time, the pixel IC 50 performs a process of rewriting only the identification information V, and transmits the remaining information, such as the lighting information L, the data start signal Start, and the data end signal Stop, to the next pixel PX (pixel IC 50) without modification.

[0079] The identification information V may be provided for each of the pixel data DTp(R), DTp(G), and DTp(B) corresponding to RGB, or the identification information V may be provided for the pixel data DTp(R) arranged first, and the pixel data DTp(G) and DTp(B) may be acquired based on the identification information V of the pixel data DTp(R). In this case, one bit corresponding to the identification information V of each of the pixel data DTp(G) and DTp(B) may be used for another purpose.

[0080] As described above, even if the display device 1 is configured without horizontal synchronization (for example, without a gate drive signal in an active matrix system), it can import pixel data DTp corresponding to pixel PX from the image data DT based on the identification information V, and can display an image well.

[0081] The display device 1 is an inorganic EL display that uses inorganic light-emitting diodes (micro LEDs) as display elements. However, the display device 1 is not limited to this, and may be, for example, a liquid crystal display device that uses liquid crystals as display elements. The display device 1 may also be an organic EL display that uses organic light-emitting diodes (OLEDs) as display elements. The display device 1 may also be an electrophoretic display (EPD), or may even be a transparent display that displays an image on a transparent display surface.

[0082] As described above, the clock signal CK(OUT) output from the clock signal output terminal 53 is delayed by the operation of the buffer circuit that constitutes the clock shaping circuit 610. Specifically, the rising edge of the clock signal CK(OUT) is delayed relative to the rising edge of the clock signal CK(IN), and the falling edge of the clock signal CK(OUT) is delayed relative to the falling edge of the clock signal CK(IN).

[0083] Fig. 9 is a schematic connection diagram of clock shaping circuits between pixel ICs according to embodiment 1. Fig. 10 is a conceptual diagram showing an example of clock signal waveforms between pixel ICs according to embodiment 1. Figs. 9 and 10 illustrate connection modes and clock signal waveforms of the clock shaping circuits 610 from the first pixel IC 50-1 to the nth pixel IC 50-n (n<N).

[0084] The frequency of the clock signal CK is set to 10 MHz, and the ideal values ​​of the high potential period and low potential period of the clock signal CK are each set to 50 ns.

[0085] The buffer circuit constituting the clock shaping circuit 610 is configured, for example, as a CMOS (complementary metal-oxide semiconductor) circuit combining PMOS and NMOS transistors. Generally, the on-resistance of the NMOS transistor is smaller than that of the PMOS transistor. Therefore, the delay Rdl relative to the rising edge of the clock signal CK(IN) is greater than the delay Fdl relative to the falling edge of the clock signal CK(IN) (Rdl>Fdl).

[0086] 10, the difference between the rise delay and fall delay of the clock signal CK accumulates, reducing the high potential period (pulse width HP) of the clock signal CK, and depending on the number of pixel ICs 50 connected in a daisy chain, there is a possibility that the clock signal CK will disappear before reaching the Nth pixel IC 50-N. In other words, the resolution of the display device according to the first embodiment is limited by the number of reachable clock signals CK. A configuration that enables even higher resolution will be described below.

[0087] Fig. 11 is a block diagram showing an example of the configuration of a pixel IC according to embodiment 1. Fig. 12 is a schematic connection diagram of clock shaping circuits between pixel ICs according to embodiment 1. Fig. 13 is a conceptual diagram showing an example of a clock signal waveform between pixel ICs according to embodiment 1. Figs. 12 and 13 illustrate examples of connection modes and clock signal waveforms of the clock shaping circuits 610 from the first pixel IC 50-1 to the nth pixel IC 50-n (n<N).

[0088] In the configuration of the pixel IC 50a according to the first embodiment shown in FIG. 11, the clock shaping circuit 610a (first circuit) generates a signal in which the high potential period and the low potential period of the clock signal CK(IN) are swapped, as the clock signal CK(OUT) to be output to the pixel IC 50 in the subsequent stage.

[0089] More specifically, the clock shaping circuit 610a is, for example, an inverting buffer circuit. In the configuration of the pixel IC 50a according to the first embodiment, the inverting buffer circuit constituting the clock shaping circuit 610a (first circuit) cancels out the difference between the delay Rdl with respect to the rising edge of the clock signal CK(IN) and the delay Fdl with respect to the falling edge of the clock signal CK(IN). This reduces the limitations imposed by the number of reachable edges of the clock signal CK, enabling even higher resolution.

[0090] (Embodiment 2) Fig. 14 is a block diagram showing a configuration example of a pixel IC according to embodiment 2. Fig. 15 is a block diagram showing a configuration example of a clock shaping circuit according to embodiment 2. Fig. 16 is a conceptual diagram showing waveforms of various parts of a clock signal in the clock shaping circuit according to embodiment 2.

[0091] In the configuration of the pixel IC 50b according to the second embodiment shown in FIG. 14, the clock shaping circuit 610b (second circuit) generates a signal that remains at a high potential for a predetermined period from the rising edge of the clock signal CK(IN), as the clock signal CK(OUT) to be output to the pixel IC in the subsequent stage.

[0092] More specifically, the clock shaping circuit 610 b includes an edge detection circuit 611 and a pulse width adjustment circuit 612 .

[0093] In the configuration of the clock shaping circuit 610b according to the second embodiment shown in FIG. 15, the edge detection circuit 611 includes an inverting buffer circuit INV, a delay circuit DL1, and a logical product operation circuit AND.

[0094] The inverting buffer circuit INV inverts the low and high potentials of the clock signal CK (IN). The delay circuit DL1 delays the output signal of the inverting buffer circuit INV. The delay time dl1 by the delay circuit DL1 is set to, for example, 4 ns. The delay time dl1 by the delay circuit DL1 varies due to process variations and temperature characteristics and is set to, for example, ±2 ns. The waveform CKM1 shown in FIG. 16 represents the output waveform of the delay circuit DL1.

[0095] The AND circuit AND performs a logical AND operation on the clock signal CK(IN) and the output signal of the delay circuit DL1. This generates a signal with a pulse width of 4 ns±2 ns (=dl1) synchronized with the rising edge of the clock signal CK(IN). The waveform CKM2 shown in Figure 16 represents the output waveform of the AND circuit AND.

[0096] 15 , the pulse width adjustment circuit 612 includes a plurality of delay circuits DL2 connected in series and a logical OR circuit OR. The delay time dl2 of the delay circuit DL2 is set to, for example, 2 ns. The delay time dl2 of the delay circuit DL2 varies due to process variations and temperature characteristics and is set to, for example, ±1 ns.

[0097] The number p of serially connected delay circuits DL2 is, for example, 18. In this case, as shown in Fig. 16, a clock signal CK(OUT) is generated that has a pulse width HP (= 4 ns ± 2 ns (= dl1) + 40 ns ± 20 ns (= p × dl2)) synchronized with the rising edge of the clock signal CK(IN). This reduces the limitations imposed by the reachable number of the clock signal CK, enabling even higher resolution.

[0098] 17 is a block diagram showing a configuration example of a clock shaping circuit according to a modification of embodiment 2. Fig. 18 is a conceptual diagram showing waveforms of various parts of a clock signal in a clock shaping circuit according to a modification of embodiment 2.

[0099] As shown in FIG. 17, a clock shaping circuit 610b according to a modification of the second embodiment may have a configuration including a delay circuit DL1, a delay circuit DL3, and a D flip-flop circuit D-FF.

[0100] In the configuration of the clock shaping circuit 610b according to the modified example of the second embodiment shown in FIG. 17, the limitations imposed by the reachable number of the clock signal CK are suppressed, as in the configuration of the second embodiment, thereby enabling even higher resolution.

[0101] 11, an imbalance between a high potential period and a low potential period may occur due to, for example, the regularity of a displayed image. Also, in the configuration of the pixel IC 50b according to the second embodiment shown in FIG. 14, power consumption increases as the number of transistors constituting the logic circuit increases.

[0102] Fig. 19 is a schematic connection diagram of a clock shaping circuit between pixel ICs according to embodiment 3. Fig. 20 is a conceptual diagram showing an example of a clock signal waveform between pixel ICs according to embodiment 3.

[0103] As shown in Fig. 19 , in the third embodiment, the pixel IC 50a according to the first embodiment shown in Fig. 11 and the pixel IC 50b according to the second embodiment shown in Fig. 14 are mixed together. Specifically, in Fig. 19 , one of the q (q<N) pixel ICs is a pixel IC 50b equipped with a clock shaping circuit 610b (second circuit), and the remaining q pixel ICs are pixel ICs 50a equipped with a clock shaping circuit 610a (first circuit).

[0104] More specifically, the q-1th pixel IC 50b-q equipped with a clock shaping circuit 610b (second circuit) is provided downstream of the series-connected first pixel IC 50a-1 to the q-1th pixel IC 50a-q-1, each equipped with a clock shaping circuit 610a (first circuit). Furthermore, the q+1th pixel IC 50a-q+1 to the 2q-1th pixel IC 50a-2q-1, each equipped with a clock shaping circuit 610a (first circuit), are connected in series downstream of the q-1th pixel IC 50b-q equipped with the clock shaping circuit 610a (second circuit), and the 2q-2th pixel IC 50b-2q equipped with the clock shaping circuit 610b (second circuit) is provided downstream of the q-1th pixel IC 50b-q equipped with the clock shaping circuit 610b (second circuit).

[0105] This makes it possible to eliminate the imbalance between the high potential period and the low potential period that occurs when the pixel ICs 50a are connected in series, while suppressing an increase in power consumption due to an increase in the number of transistors.

[0106] 21 is a schematic connection diagram of a clock shaping circuit between pixel ICs according to a modification of embodiment 3. Fig. 22 is a conceptual diagram showing an example of a clock signal waveform between pixel ICs according to a modification of embodiment 3.

[0107] As shown in Fig. 21 , the modification of the third embodiment mixes the pixel IC 50 shown in Fig. 4 with the pixel IC 50b according to the second embodiment shown in Fig. 14. Specifically, in Fig. 21 , one of the r pixel ICs is a pixel IC 50b equipped with a clock shaping circuit 610b (second circuit), and the remaining r (r<N) pixel ICs are pixel ICs 50 equipped with a clock shaping circuit 610b (buffer circuit).

[0108] More specifically, the qth pixel IC 50b-q equipped with a clock shaping circuit 610b (second circuit) is provided downstream of the series-connected first pixel IC 50-1 to the r−1th pixel IC 50-r-1, each equipped with a clock shaping circuit 610 (buffer circuit). Furthermore, the r+1th pixel IC 50-r+1 to the 2r−1th pixel IC 50-2r-1, each equipped with a clock shaping circuit 610 (buffer circuit), are connected in series downstream of the qth pixel IC 50b-q equipped with the clock shaping circuit 610b (second circuit), and the 2rth pixel IC 50b-2r equipped with a clock shaping circuit 610b (second circuit) is provided downstream of the qth pixel IC 50b-q equipped with the clock shaping circuit 610b (second circuit).

[0109] As a result, similar to the configuration of the third embodiment, it is possible to suppress an increase in power consumption due to an increase in the number of transistors.

[0110] 23 is a block diagram showing an example of the configuration of a pixel IC according to embodiment 4. In the above-described embodiments, a pixel IC 50a including a clock shaping circuit 610a (first circuit) and a pixel IC 50b including a clock shaping circuit 610b (second circuit) have been described, but in the configuration of a pixel IC 50c according to embodiment 4 shown in Fig. 23, the clock shaping circuit 610c is configured to be able to select either a first function of generating, as a clock signal CK(OUT), a signal that remains at a high potential for a predetermined period from the rising edge of a clock signal CK(IN) to be output to a subsequent pixel IC 50c, or a second function of generating, as a clock signal CK(OUT), a signal that remains at a high potential for a predetermined period from the rising edge of the clock signal CK(IN) to be output to a subsequent pixel IC 50c.

[0111] The clock shaping circuit 610c may select between the first function and the second function, for example, by inputting a setting value from the driver ICs 11A and 11B. Specifically, the clock shaping circuit 610c selects either the first function or the second function based on the setting value input from the driver ICs 11A and 11B.

[0112] Furthermore, the method of selecting between the first function and the second function in the clock shaping circuit 610c may be, for example, a mode in which the function is set in advance as a register value in the storage circuit 67. Specifically, for example, the clock shaping circuit 610c selects either the first function or the second function based on the register value set in advance in the storage circuit 67.

[0113] Alternatively, the clock shaping circuit 610c may select between the first and second functions by switching between the first and second functions depending on the pulse width HP of the clock signal CK(IN). Specifically, the clock shaping circuit 610c may be preset to the first function as a default setting, autonomously monitor the pulse width HP of the clock signal CK(IN), and switch to the second function when the pulse width HP of the clock signal CK(IN) falls below a predetermined value.

[0114] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure naturally fall within the technical scope of the present disclosure. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-described embodiments and modifications.

[0115] 1 Display device 3, 3R, 3G, 3B Light-emitting element 11, 11A, 11B Driver IC 12 Clock signal supply wiring 13 Image data supply wiring 21 Substrate 50 Pixel IC 50-1 First pixel IC 50-2 Second pixel IC 50-3 Third pixel IC 51 Clock signal input terminal 52 Image data input terminal 53 Clock signal output terminal 54 Image data output terminal 55 Power supply terminal 56 Reference potential terminal 57, 58, 59 Connection terminal 62 Buffer circuit 63, 64 Flip-flop circuit 65 Control circuit 66 PWM control circuit 67 Memory circuit 68 Light-emitting element drive circuit 610, 610a, 610b, 610c Clock shaping circuit 611 Edge detection circuit 612 Pulse width adjustment circuit DT, DT(a), DT(b), DT(c), DT(d) Image data DTp Pixel data L Lighting information PX, PX-1, PX-2, PX-3 Pixel V, V(1), V(2), V(3), V(N) Identification information

Claims

1. A display device comprising: a plurality of display elements; a plurality of pixel ICs connected to at least one of the plurality of display elements; and a driver IC that supplies a clock signal and image data to the plurality of daisy-chained pixel ICs, wherein the plurality of daisy-chained pixel ICs each have a clock shaping circuit that shapes the waveform of an input clock signal, and at least one of the plurality of clock shaping circuits is either: a first circuit that generates a signal in which the high potential period and low potential period of the input clock signal are swapped, as a clock signal to be output to a subsequent pixel IC; or a second circuit that generates a signal that remains high potential for a predetermined period from the rising edge of the input clock signal, as a clock signal to be output to a subsequent pixel IC.

2. The display device according to claim 1, wherein all of said clock shaping circuits are said first circuits.

3. The display device according to claim 1, wherein all of said clock shaping circuits are said second circuits.

4. The display device according to claim 1, wherein one of the clock shaping circuits, which is q less than the total number of daisy-chained pixel ICs, is the second circuit and the rest are the first circuit.

5. The display device according to claim 1, wherein at least one of the plurality of clock shaping circuits is a buffer circuit, and one of the clock shaping circuits, which is r circuits less than the total number of pixel ICs connected in a daisy chain, is the second circuit, and the rest are buffer circuits.

6. A display device comprising: a plurality of display elements; a plurality of pixel ICs connected to at least one of the plurality of display elements; and a driver IC that supplies a clock signal and image data to the plurality of pixel ICs connected in a daisy chain; wherein the plurality of pixel ICs connected in a daisy chain each have a clock shaping circuit that shapes the waveform of an input clock signal, and the clock shaping circuit is configured to be able to select either a first function of generating a signal in which the high potential period and low potential period of the input clock signal are swapped, as a clock signal to be output to a pixel IC in a subsequent stage, or a second function of generating a signal that remains at a high potential for a predetermined period from the rising edge of the input clock signal, as a clock signal to be output to a pixel IC in a subsequent stage.

7. The display device according to any one of claims 1 to 6, wherein the plurality of display elements are self-luminous elements that emit red light, green light, and blue light.

8. The display device according to claim 7, wherein the self-luminous elements are controlled by PWM (Pulse Width Modulation) driving.

9. A display device according to any one of claims 1 to 6, wherein the image data includes a plurality of pixel data corresponding to the plurality of pixel ICs connected in series and at least one of the display elements connected to the pixel ICs, and the plurality of pixel ICs drive the display elements to which they are respectively connected based on the pixel data corresponding to the display elements.

10. A display device as claimed in any one of claims 1 to 6, wherein the image data includes a plurality of pieces of lighting information for lighting a plurality of the display elements and identification information corresponding to each of the plurality of pieces of lighting information, and the plurality of pixel ICs acquire lighting information corresponding to the display elements to which they are respectively connected based on the identification information.

11. The display device according to claim 10, wherein each of the plurality of pixel ICs acquires lighting information corresponding to the display element connected thereto, and then outputs image data in which identification information has been rewritten to a subsequent pixel IC.

12. The display device according to any one of claims 1 to 6, wherein the pixel ICs have a plurality of sets of circuits daisy-chained together, and the plurality of sets of circuits are connected in parallel to the driver IC.

Images