Multilayer substrate, multilayer substrate module, and electronic device

Abstract

The present invention reduces disturbance of impedance. In a multilayer substrate (100), a conductor pattern part (3) has a signal line and a first pad electrode (5). A connection conductor part (7) connects the first pad electrode (5) and a second pad electrode (6). The first pad electrode (5) has a third main surface (51) that touches the connection conductor part (7), and a fourth main surface (52) that faces a ground electrode (8). A multilayer substrate (1) has space (9) where the entirety of the fourth main surface (52) of the first pad electrode (5) is exposed within the multilayer substrate (1). In the multilayer substrate (1), the entirety of the space (9) overlaps with the ground electrode (8) in plan view from the thickness direction (D1) of the multilayer substrate (1). In the multilayer substrate (1), at least one insulating layer (11) among a plurality of insulating layers (11-14) is positioned between the space (9) and the ground electrode (8) in the thickness direction (D1) of the multilayer substrate (1).

Description

Multilayer substrate, multilayer substrate module and electronic device

[0001] The present invention generally relates to a multilayer substrate, a multilayer substrate module, and an electronic device, and more particularly to a multilayer substrate having a signal line, a multilayer substrate module having a multilayer substrate, and an electronic device having a multilayer substrate module.

[0002] Patent Document 1 discloses a multilayer board. The multilayer board disclosed in Patent Document 1 includes a first line-including layer, a second line-including layer, an adjacent insulating layer, a ground-including layer, and a signal via. The first line-including layer has a first transmission line that transmits a signal and a first land to which the first transmission line is connected. The second line-including layer has a second transmission line that transmits the signal and a second land to which the second transmission line is connected. The adjacent insulating layer is adjacent to one side of the first line-including layer in the thickness direction of the multilayer board. The ground-including layer is stacked on the first line-including layer with the adjacent insulating layer sandwiched therebetween and has a planar ground pattern. The signal via is arranged between the first land and the second land and connects the first land and the second land.

[0003] In the multilayer board disclosed in Patent Document 1, the first land and the ground pattern generate parasitic capacitance due to capacitive coupling across the adjacent insulating layer.

[0004] JP 2017-117890 A

[0005] In a multilayer board, impedance is prone to disturbance at an extraction portion connecting a signal line arranged in a laminate board having multiple insulating layers stacked together and a pad electrode arranged on an insulating layer different from the insulating layer on which the signal line is arranged. In the multilayer board disclosed in Patent Document 1, the parasitic capacitance is a predetermined capacitance that suppresses changes in the impedance of the via portion caused by changes in the impedance component of the via portion that includes the signal via, the first land, and the second land.

[0006] An object of the present invention is to provide a multilayer board, a multilayer board module, and an electronic device that can reduce impedance disturbances.

[0007] A multilayer substrate according to one aspect of the present invention includes a laminated substrate, a conductor pattern portion having a signal line and a first pad electrode, a second pad electrode, a connection conductor portion, and a ground electrode. The laminated substrate is formed by stacking multiple insulating layers. The laminated substrate has a first main surface and a second main surface. The conductor pattern portion is disposed within the laminated substrate. The second pad electrode is disposed on the first main surface of the laminated substrate. The second pad electrode is separated from the first pad electrode in the thickness direction of the laminated substrate and overlaps the first pad electrode in a plan view from the thickness direction of the laminated substrate. At least a portion of the connection conductor portion is disposed within the laminated substrate. The connection conductor portion connects the first pad electrode and the second pad electrode. The ground electrode is disposed on the second main surface of the laminated substrate. The ground electrode faces the first pad electrode and the signal line in the thickness direction of the laminated substrate. The first pad electrode has a third main surface in contact with the connection conductor and a fourth main surface facing the ground electrode. The width of the first pad electrode in the width direction of the signal line is larger than the width of the signal line. In a plan view from the thickness direction of the laminated substrate, the connection conductor is smaller than the first pad electrode. The laminated substrate has a space exposing the entire fourth main surface of the first pad electrode within the laminated substrate. In the laminated substrate, the entire space overlaps the ground electrode in a plan view from the thickness direction of the laminated substrate. In the laminated substrate, at least one insulating layer of the multiple insulating layers is located between the space and the ground electrode in the thickness direction of the laminated substrate.

[0008] A multilayer substrate module according to one aspect of the present disclosure includes the multilayer substrate according to the above aspect and a connector connected to the second pad electrode of the multilayer substrate.

[0009] An electronic device according to one aspect of the present disclosure includes the multilayer substrate module according to the above aspect and a housing that houses the multilayer substrate module.

[0010] The multilayer substrate, multilayer substrate module, and electronic device according to the above aspects of the present invention can reduce impedance disturbances.

[0011] FIG. 1 is a plan view of a multilayer substrate according to a first embodiment. FIG. 2 is a bottom view of the same. FIG. 3 is a cross-sectional view of the same multilayer substrate taken along line III-III in FIG. 1. FIG. 4 is a cross-sectional view of the same multilayer substrate taken along line IV-IV in FIG. 3. FIG. 5 is a plan view of a multilayer substrate module including the same multilayer substrate. FIG. 6 is a cross-sectional view of the same multilayer substrate module taken along line VI-VI in FIG. 5. FIG. 7 is a schematic configuration diagram of an electronic device including the same multilayer substrate. FIG. 8 is a cross-sectional view of a multilayer substrate according to a second embodiment. FIG. 9 is a cross-sectional view of the same multilayer substrate taken along line IX-IX in FIG. 8. FIG. 10 is a cross-sectional view of a multilayer substrate according to a third embodiment. FIG. 11 is a cross-sectional view of a multilayer substrate according to a modified example of the third embodiment. FIG. 12 is a plan view of a multilayer substrate according to a fourth embodiment. FIG. 13 is a bottom view of the same multilayer substrate. FIG. 14 is a cross-sectional view of the same multilayer substrate taken along line XIV-XIV in FIG. 12. FIG. 15 is a cross-sectional view of the multilayer substrate of the same embodiment, taken along line XV-XV in FIG. 14 . FIG. 16 is a cross-sectional view of a multilayer substrate according to a fifth embodiment. FIG. 17 is a plan view of a multilayer substrate according to a sixth embodiment. FIG. 18 is a cross-sectional view of the multilayer substrate of the same embodiment, taken along line XVIII-XVIII in FIG. 17 . FIG. 19 is a cross-sectional view of the multilayer substrate of the same embodiment, taken along line XIX-XIX in FIG. 17 . FIG. 20 is a cross-sectional view of the multilayer substrate of the same embodiment, taken along line XX-XX in FIG. 18 . FIG. 21 is a plan view of a multilayer substrate module including a multilayer substrate according to a seventh embodiment. FIG. 22 is a cross-sectional view of the multilayer substrate module of the same embodiment, taken along line XXII-XXII in FIG. 21 . FIG. 23 is a cross-sectional view of a multilayer substrate according to an eighth embodiment. FIG. 24 is a plan view of a multilayer substrate according to a ninth embodiment. FIG. 25 is a cross-sectional view of the multilayer substrate of the same embodiment, taken along line XXV-XXV in FIG. 24 .

[0012] Hereinafter, embodiments 1 to 9 will be described with reference to the drawings. The drawings referred to in the following embodiments 1 to 9 are schematic diagrams, and the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensions, and the size ratios and thickness ratios between the components do not necessarily reflect the actual dimensional ratios.

[0013] First Embodiment A multilayer substrate 100, a multilayer substrate module 400, and an electronic device 500 according to a first embodiment will be described with reference to FIGS.

[0014] (1) Multilayer Substrate As shown in FIGS. 1 to 4 , the multilayer substrate 100 according to the first embodiment includes a laminated substrate 1, a conductor pattern portion 3 having a signal line 4 and two first pad electrodes 5, two second pad electrodes 6, two connection conductor portions 7 (hereinafter also referred to as first connection conductor portions 7), and a ground electrode 8 (hereinafter also referred to as first ground electrode 8). The multilayer substrate 100 further includes a second ground electrode 82 and a third ground electrode 83. The multilayer substrate 100 further includes a fourth ground electrode 84 and a fifth ground electrode 85. The multilayer substrate 100 further includes two third pad electrodes 122 and two fourth pad electrodes 123. The multilayer substrate 100 further includes a plurality of second connection conductor portions 72 and a plurality of third connection conductor portions 73. In this embodiment, the first pad electrode 5 and the connection conductor 7 overlapping in the thickness direction D1 of the laminated substrate 1 form an extraction portion 10 connecting the signal line 4 and the second pad electrode 6.

[0015] 1 to 6, a Cartesian coordinate system is defined having three mutually orthogonal axes, the X-axis, the Y-axis, and the Z-axis, which is the axis along the thickness direction D1 of the multilayer substrate 1 (see FIG. 3), is indicated as the Z-axis. The X-axis, the Y-axis, and the Z-axis are all imaginary axes, and the arrows indicating "X," "Y," and "Z" in the drawings are merely indicated for the purpose of explanation and do not have any physical substance. The multilayer substrate 100 is, for example, a flexible substrate. The thickness direction D1 of the multilayer substrate 100 is the direction along the Z-axis in the example of FIG. 3, but if the multilayer substrate 100 is bent, this direction may differ depending on the position on the multilayer substrate 100.

[0016] The multilayer substrate 100 is housed in a housing 501 of an electronic device 500, for example, as shown in Fig. 7. The electronic device 500 is, for example, a communication device. The communication device is, for example, a mobile phone (e.g., a smartphone), but is not limited to a mobile phone and may be, for example, a notebook personal computer, a wearable device (e.g., a smart watch), etc.

[0017] (1.1) Laminated Substrate As shown in Fig. 3, the laminated substrate 1 has a plurality of (four in the example of Fig. 3) insulating layers 11, 12, 13, and 14, and the insulating layers 11, 12, 13, and 14 are stacked. A thickness direction D1 of the laminated substrate 1 is the stacking direction of the insulating layers 11, 12, 13, and 14. In the laminated substrate 1, the insulating layer 11, the insulating layer 12, the insulating layer 13, and the insulating layer 14 are stacked in this order.

[0018] In this embodiment, the conductor pattern portion 3 is arranged on a main surface 131 of the insulating layer 13 that faces the ground electrode 8. In this embodiment, the insulating layer 13 constitutes a first insulating layer 13 on which the conductor pattern portion 3 is arranged on the main surface 131 that faces the ground electrode 8. In addition, in this embodiment, the insulating layer 12 constitutes a second insulating layer 12 that faces the main surface 131 of the first insulating layer 13.

[0019] The material of each of the insulating layers 11, 12, 13, and 14 is, for example, polyimide (PI). The material of each of the insulating layers 11, 12, 13, and 14 is not limited to polyimide, and may be, for example, modified polyimide (Modified-PI).

[0020] The thickness of each of the insulating layers 11, 12, 13, and 14 is, for example, not less than 10 μm and not more than 120 μm.

[0021] In this embodiment, the laminate substrate 1 further includes an adhesive layer 21 interposed between the insulating layer 11 and the insulating layer 12. The laminate substrate 1 also includes an adhesive layer 22 interposed between the insulating layer 12 (second insulating layer 12) and the insulating layer 13 (first insulating layer 13). The laminate substrate 1 also includes an adhesive layer 23 interposed between the insulating layer 13 and the insulating layer 14. The material of each of the adhesive layers 21, 22, and 23 is, for example, thermoplastic polyimide. The material of each of the adhesive layers 21, 22, and 23 is not limited to thermoplastic polyimide, and may be, for example, a polyolefin resin, an epoxy resin, or an acrylic resin.

[0022] The thickness of each of the adhesive layers 21, 22, and 23 is, for example, not less than 10 μm and not more than 120 μm.

[0023] In this embodiment, the laminated substrate 1 has an elongated shape in which the length along the Y axis is longer than the length along the X axis when viewed from above in the thickness direction D1 of the laminated substrate 1. When viewed from above in the thickness direction D1 of the laminated substrate 1, the shape of the laminated substrate 1 may be a shape other than an elongated shape.

[0024] (1.2) Conductive Pattern Portion The conductor pattern portion 3 is disposed within the laminated substrate 1, as shown in FIGS. 1, 3, and 4. The conductor pattern portion 3 is conductive. The material of the conductor pattern portion 3 is, for example, copper. The conductor pattern portion 3 is formed in a predetermined pattern. The conductor pattern portion 3 has a signal line 4 and two first pad electrodes 5. In the conductor pattern portion 3, the two first pad electrodes 5 and the signal line 4 are seamlessly connected. The conductor pattern portion 3 is formed by patterning copper foil (hereinafter also referred to as first copper foil) attached to the first insulating layer 13.

[0025] The signal line 4 is a line through which a high-frequency signal is transmitted. The frequency of the high-frequency signal is, for example, 1 GHz or higher, but is not limited to 1 GHz or higher and may be less than 1 GHz. The multilayer substrate 100 of this embodiment is designed so that the impedance of the signal line 4 is 50Ω.

[0026] In a plan view from the thickness direction D1 of the laminated substrate 1, the signal line 4 is linear. The length of the signal line 4 along the Y axis is longer than the length along the X axis. In this embodiment, the signal line 4 has a line width in the X axis direction. In the X axis direction, the line width of the signal line 4 is narrower than the width of the laminated substrate 1. In the Y axis direction, the length of the signal line 4 is shorter than the length of the laminated substrate 1. In a plan view from the thickness direction D1 of the laminated substrate 1, the signal line 4 may have a shape other than linear, for example, a curved shape or a bent shape.

[0027] In the conductor pattern portion 3, the signal line 4 is located between two first pad electrodes 5. In the conductor pattern portion 3, one of the two first pad electrodes 5 is connected to a first end 41 of the signal line 4, and the remaining first pad electrode 5 is connected to a second end 42 of the signal line 4.

[0028] In a plan view from the thickness direction D1 of the laminated substrate 1, each of the two first pad electrodes 5 has a rectangular shape, but the shape is not limited to a rectangular shape and may also be a circular shape. As shown in Fig. 4, the width W5 of each first pad electrode 5 in the width direction of the signal line 4 (in this embodiment, the direction parallel to the X-axis) is larger than the width W4 of the signal line 4. Note that the width W5 of each first pad electrode 5 is the maximum width of each first pad electrode 5 in the width direction of the signal line 4, and when each first pad electrode 5 is circular, the width W5 of each first pad electrode 5 means the diameter of each first pad electrode 5.

[0029] As shown in Figure 3, each of the two first pad electrodes 5 has a third main surface 51 that is in contact with the connecting conductor portion 7 of the two connecting conductor portions 7 that corresponds to the first pad electrode 5, and a fourth main surface 52 that faces the ground electrode 8.

[0030] (1.3) Second Pad Electrodes As shown in Figures 1 and 3, the two second pad electrodes 6 are arranged on the first main surface 101 of the laminated substrate 1. In this embodiment, each second pad electrode 6 is arranged on the first main surface 101 of the laminated substrate 1 via an electrode 62.

[0031] The two second pad electrodes 6 correspond one-to-one to the two first pad electrodes 5. In a plan view from the thickness direction D1 of the laminated substrate 1 (see FIG. 3 ), each of the two second pad electrodes 6 overlaps a corresponding one of the two first pad electrodes 5. The first pad electrode 5 and the second pad electrode 6 that overlap in the thickness direction D1 of the laminated substrate 1 are spaced apart in the thickness direction D1 of the laminated substrate 1. The material of the two second pad electrodes 6 is, for example, copper.

[0032] In a plan view from the thickness direction D1 of the laminated substrate 1, each of the two second pad electrodes 6 has a circular shape, but the shape is not limited to a circular shape and may be a rectangular shape. In the X-axis direction, the width of each second pad electrode 6 is wider than the width of the signal line 4. Note that the width of each second pad electrode 6 is the maximum width of each second pad electrode 6 in the width direction of the signal line 4, and when each second pad electrode 6 has a circular shape, the width of each second pad electrode 6 means the diameter of each second pad electrode 6.

[0033] (1.4) Connection Conductor As shown in Fig. 1 , the two connection conductors 7 are in one-to-one correspondence with the two first pad electrodes 5. Furthermore, the two connection conductors 7 are in one-to-one correspondence with the two second pad electrodes 6. At least a portion of each connection conductor 7 is disposed within the laminated substrate 1. Each of the two connection conductors 7 connects a corresponding one of the two first pad electrodes 5 to a corresponding one of the two second pad electrodes 6. In short, each connection conductor 7 connects a first pad electrode 5 and a second pad electrode 6 that overlap in the thickness direction D1 of the laminated substrate 1, as shown in Fig. 3 .

[0034] Each of the two connection conductors 7 is cylindrical. In plan view from the thickness direction D1 of the laminated substrate 1, each of the two connection conductors 7 is smaller than the corresponding one of the two first pad electrodes 5. Also, in plan view from the thickness direction D1 of the laminated substrate 1, each of the two connection conductors 7 is smaller than the corresponding one of the two second pad electrodes 6. Each of the two connection conductors 7 is formed by through-hole plating. The through-hole plating is made of, for example, copper.

[0035] 2 and 3 , the first ground electrode 8 is disposed on the second main surface 102 of the laminated substrate 1. The ground electrode 8 faces the two first pad electrodes 5 and the signal line 4 in the thickness direction D1 of the laminated substrate 1.

[0036] The first ground electrode 8 is conductive. The material of the first ground electrode 8 is, for example, copper. The first ground electrode 8 is formed in a predetermined pattern. In a plan view of the laminated substrate 1 in the thickness direction D1, the first ground electrode 8 has, for example, an elongated shape in which the length along the Y-axis is longer than the length along the X-axis. The first ground electrode 8 is formed, for example, by patterning copper foil (hereinafter also referred to as second copper foil) attached to the insulating layer 11. The first ground electrode 8 is disposed on the second main surface 102 of the laminated substrate 1 so as to cover most of the second main surface 102 of the laminated substrate 1. In a plan view of the laminated substrate 1 in the thickness direction D1, the first ground electrode 8 overlaps the conductor pattern portion 3, the second ground electrode 82, and the third ground electrode 83.

[0037] (1.6) Second Ground Electrode and Third Ground Electrode As shown in FIGS. 3 and 4 , the second ground electrode 82 and the third ground electrode 83 are disposed within the laminated substrate 1. The second ground electrode 82 and the third ground electrode 83 are electrically conductive. The second ground electrode 82 and the third ground electrode 83 are made of, for example, copper. Each of the second ground electrode 82 and the third ground electrode 83 is formed in a predetermined pattern. When viewed in a plan view from the thickness direction D1 of the laminated substrate 1, each of the second ground electrode 82 and the third ground electrode 83 has an elongated shape such that the length along the Y-axis is longer than the length along the X-axis.

[0038] The second ground electrode 82 and the third ground electrode 83 are adjacent to the first pad electrode 5. "The second ground electrode 82 and the third ground electrode 83 are adjacent to the first pad electrode 5" means that the second ground electrode 82 and the third ground electrode 83 are arranged at a distance from the first pad electrode 5, without any other conductor being arranged between the second ground electrode 82 and the third ground electrode 83 and the first pad electrode 5 in the width direction of the first pad electrode 5 (in the X-axis direction in this embodiment).

[0039] In a plan view of the laminated substrate 1 in the thickness direction D1 , the first pad electrode 5 is located between the second ground electrode 82 and the third ground electrode 83 .

[0040] The second ground electrode 82 and the third ground electrode 83 are disposed on the main surface 131 of the first insulating layer 13. Therefore, in this embodiment, the second ground electrode 82, the third ground electrode 83, the two first pad electrodes 5, and the signal line 4 are disposed on the main surface 131 of the first insulating layer 13. The second ground electrode 82 and the third ground electrode 83, like the two first pad electrodes 5 and the signal line 4, are formed by patterning a first copper foil attached to the first insulating layer 13.

[0041] (1.7) Fourth Ground Electrode and Fifth Ground Electrode As shown in FIGS. 1 and 3 , the fourth ground electrode 84 and the fifth ground electrode 85 are disposed on the laminated substrate 1. The fourth ground electrode 84 and the fifth ground electrode 85 are electrically conductive. The fourth ground electrode 84 and the fifth ground electrode 85 are made of, for example, copper. Each of the fourth ground electrode 84 and the fifth ground electrode 85 is formed in a predetermined pattern. When viewed in a plan view from the thickness direction D1 of the laminated substrate 1, each of the fourth ground electrode 84 and the fifth ground electrode 85 has an elongated shape, for example, such that the length along the Y-axis is longer than the length along the X-axis. Each of the fourth ground electrode 84 and the fifth ground electrode 85 may have a shape other than an elongated shape.

[0042] The fourth ground electrode 84 and the fifth ground electrode 85 are disposed on the main surface 141 of the insulating layer 14. Therefore, in the present embodiment, the fourth ground electrode 84, the fifth ground electrode 85, and the two electrodes 62 are disposed on the main surface 141 of the insulating layer 14. The fourth ground electrode 84, the fifth ground electrode 85, and the two electrodes 62 are formed by patterning a third copper foil attached to the insulating layer 14.

[0043] 1 and 3, two third pad electrodes 122 and two fourth pad electrodes 123 are arranged on the first main surface 101 of the laminated substrate 1. In this embodiment, each third pad electrode 122 is arranged on the first main surface 101 of the laminated substrate 1 via a fourth ground electrode 84. Furthermore, each fourth pad electrode 123 is arranged on the first main surface 101 of the laminated substrate 1 via a fifth ground electrode 85.

[0044] In the thickness direction D1 of the laminated substrate 1, the two third pad electrodes 122 overlap the second ground electrode 82 and the first ground electrode 8. In the thickness direction D1 of the laminated substrate 1, each third pad electrode 122 is spaced apart from the second ground electrode 82 and the first ground electrode 8, respectively. The material of the two third pad electrodes 122 is, for example, copper.

[0045] In the thickness direction D1 of the laminated substrate 1, the two fourth pad electrodes 123 overlap the third ground electrode 83 and the first ground electrode 8. In the thickness direction D1 of the laminated substrate 1, each fourth pad electrode 123 is spaced apart from the third ground electrode 83 and the first ground electrode 8, respectively. The material of the two fourth pad electrodes 123 is, for example, copper.

[0046] When viewed in a plane from the thickness direction D1 of the laminated substrate 1, each of the two third pad electrodes 122 and the two fourth pad electrodes 123 is circular, but is not limited to a circular shape and may be, for example, a rectangular shape.

[0047] (1.9) Second Connection Conductors and Third Connection Conductors The plurality of second connection conductors 72 (see FIG. 1 ) and the plurality of third connection conductors 73 (see FIG. 1 ) penetrate the laminated substrate 1 in the thickness direction D1 of the laminated substrate 1 (see FIG. 3 ). Each second connection conductor 72 also penetrates the first ground electrode 8, the second ground electrode 82, and the fourth ground electrode 84. Furthermore, each third connection conductor 73 also penetrates the first ground electrode 8, the third ground electrode 83, and the fifth ground electrode 85.

[0048] Each second connecting conductor 72 connects the first ground electrode 8, the second ground electrode 82, and the fourth ground electrode 84. Each third connecting conductor 73 connects the first ground electrode 8, the third ground electrode 83, and the fifth ground electrode 85.

[0049] In this embodiment, the first ground electrode 8, the second ground electrode 82, and the fourth ground electrode 84 are electrically connected by a plurality of second connecting conductors 72. The plurality of second connecting conductors 72 are spaced apart in the longitudinal direction of the second ground electrode 82. The longitudinal direction of the second ground electrode 82 is along the longitudinal direction of the signal line 4 and is perpendicular to the width direction (line width direction) of the signal line 4. The longitudinal direction of the signal line 4 is the direction in which a high-frequency signal is transmitted. In this embodiment, the first ground electrode 8, the third ground electrode 83, and the fifth ground electrode 85 are electrically connected by a plurality of third connecting conductors 73. The plurality of third connecting conductors 73 are spaced apart in the longitudinal direction of the third ground electrode 83. The longitudinal direction of the third ground electrode 83 is along the longitudinal direction of the signal line 4.

[0050] Each of the second connection conductors 72 and the third connection conductors 73 is formed by through-hole plating, which may be made of copper, for example.

[0051] (1.10) Space in the Laminated Substrate As shown in FIG. 3 , the first pad electrode 5 has a third main surface 51 in contact with the connection conductor 7 and a fourth main surface 52 facing the ground electrode 8. The laminated substrate 1 has a space 9 that exposes the entire fourth main surface 52 of the first pad electrode 5 within the laminated substrate 1. The space 9 is a closed space that does not communicate with the outside of the laminated substrate 1. In the laminated substrate 1, the entire space 9 overlaps with the first ground electrode 8 in a planar view from the thickness direction D1 of the laminated substrate 1. In other words, in the laminated substrate 1, there is no area of ​​the space 9 that does not overlap with the first ground electrode 8 in a planar view from the thickness direction D1 of the laminated substrate 1. In the laminated substrate 1, at least one insulating layer 11 of the multiple insulating layers 11 to 14 is located between the space 9 and the first ground electrode 8 in the thickness direction D1 of the laminated substrate 1. In the laminated substrate 1 of this embodiment, two insulating layers 12, 11 of the multiple insulating layers 11 to 14 are located between the space 9 and the first ground electrode 8 in the thickness direction D1 of the laminated substrate 1. Furthermore, in the laminated substrate 1 of this embodiment, two insulating layers 12, 11 of the multiple insulating layers 11 to 14 are located between the signal line 4 (see FIGS. 1 and 4 ) and the first ground electrode 8 in the thickness direction D1 of the laminated substrate 1. More specifically, in the laminated substrate 1 of this embodiment, a laminate of an adhesive layer 22, an insulating layer 12, an adhesive layer 21, and an insulating layer 11 is located between the signal line 4 and the first ground electrode 8 in the thickness direction D1 of the laminated substrate 1.

[0052] 3 and 4 , the space 9 includes an opening 220 in the adhesive layer 22. The opening 220 in the adhesive layer 22 is a through-hole that penetrates the adhesive layer 22 in the thickness direction D1 of the laminated substrate 1. In a plan view from the thickness direction D1 of the laminated substrate 1, the opening 220 is larger than the first pad electrode 5. In a plan view from the thickness direction D1 of the laminated substrate 1, the opening shape of the opening 220 is a rectangle that is long in the width direction of the first pad electrode 5 (a direction parallel to the X-axis), but may be a shape other than a rectangle.

[0053] In the width direction of the first pad electrode 5 , the opening width of the opening 220 is smaller than the distance between the second ground electrode 82 and the third ground electrode 83 .

[0054] In this embodiment, a thickness T222 of a portion 222 of the adhesive layer 22 that is interposed between the second ground electrode 82 and the second insulating layer 12 is thinner than a thickness T221 of a portion 221 of the adhesive layer 22 that is interposed between the first insulating layer 13 and the second insulating layer 12. Also, in this embodiment, a thickness T223 of a portion 223 of the adhesive layer 22 that is interposed between the third ground electrode 83 and the second insulating layer 12 is thinner than a thickness T221 of a portion 221 of the adhesive layer 22 that is interposed between the first insulating layer 13 and the second insulating layer 12.

[0055] (2) Multilayer Substrate Module As shown in FIGS. 5 and 6 , the multilayer substrate module 400 includes a multilayer substrate 100 and a plurality of connectors 410 (two in the example of FIG. 5 ). The two connectors 410 correspond one-to-one to the two second pad electrodes 6. Each of the two connectors 410 is connected to a corresponding one of the two second pad electrodes 6. The two connectors 410 also correspond one-to-one to the two third pad electrodes 122. Each of the two connectors 410 is connected to a corresponding one of the two third pad electrodes 122. The two connectors 410 also correspond one-to-one to the two fourth pad electrodes 123. Each of the two connectors 410 is connected to a corresponding one of the two fourth pad electrodes 123.

[0056] Each of the two connectors 410 has a signal terminal 421 connected to the second pad electrode 6, a first ground terminal 422 connected to the third pad electrode 122, a second ground terminal 423 connected to the fourth pad electrode 123, and a connector body 411. The connector body 411 holds the signal terminal 421, the first ground terminal 422, and the second ground terminal 423. The connector body 411 is electrically insulating.

[0057] In the multilayer substrate module 400, two connectors 410 are mounted on the multilayer substrate 100. The multilayer substrate module 400 further includes a solder portion 431 connecting the signal terminal 421 and the second pad electrode 6. The multilayer substrate module 400 also includes a solder portion 432 connecting the first ground terminal 422 and the third pad electrode 122. The multilayer substrate module 400 also includes a solder portion 433 connecting the second ground terminal 423 and the fourth pad electrode 123.

[0058] (3) Electronic Device As shown in FIG. 7, the electronic device 500 according to the first embodiment includes the multilayer substrate module 400 and a housing 501 that houses the multilayer substrate module 400 .

[0059] Electronic device 500 further includes a first printed wiring board 504, a second printed wiring board 505, a connector 514 mounted on first printed wiring board 504, and a connector 515 mounted on second printed wiring board 505. A battery 503 serving as a power source for electronic device 500 is housed within housing 501 of electronic device 500.

[0060] In electronic device 500, one of two connectors 410 of multilayer substrate module 400 is connected to connector 514, and the other connector 410 is connected to connector 515. As a result, in electronic device 500, first printed wiring board 504 and second printed wiring board 505 are connected via multilayer substrate module 400. In electronic device 500, multilayer substrate 100 of multilayer substrate module 400 is accommodated in housing 501 in a bent state.

[0061] At least one of the first printed wiring board 504 and the second printed wiring board 505 is provided with, for example, a signal processing circuit for processing high frequency signals.

[0062] (4) Effects In the multilayer substrate 100 according to the first embodiment, in the conductor pattern portion 3 having the signal line 4 and the first pad electrode 5, the first pad electrode 5 has a third main surface 51 in contact with the connection conductor 7 and a fourth main surface 52 facing the ground electrode 8. The width W5 of the first pad electrode 5 in the width direction of the signal line 4 is greater than the width W4 of the signal line 4. In a plan view from the thickness direction D1 of the laminated substrate 1, the connection conductor 7 is smaller than the first pad electrode 5. The laminated substrate 1 has a space 9 that exposes the entire fourth main surface 52 of the first pad electrode 5 within the laminated substrate 1. In the laminated substrate 1, the entire space 9 overlaps with the ground electrode 8 in a plan view from the thickness direction D1 of the laminated substrate 1. In the laminated substrate 1, at least one insulating layer 11 of the multiple insulating layers 11 to 14 is located between the space 9 and the ground electrode 8 in the thickness direction D1 of the laminated substrate 1.

[0063] According to the above configuration, it is possible to reduce impedance disturbances while making the width W5 of the first pad electrode 5 larger than the width W4 of the signal line 4. More specifically, according to the above configuration, by making the width W5 of the first pad electrode 5 larger than the width W4 of the signal line 4, it is possible to improve the connection reliability between the connection conductor 7 and the first pad electrode 5 and reduce the connection resistance between the connection conductor 7 and the first pad electrode 5. Furthermore, according to the above configuration, the laminated substrate 1 has the space 9 that exposes the entire fourth main surface 52 of the first pad electrode 5 within the laminated substrate 1, thereby reducing the dielectric constant compared to a case where the space 9 is not provided. This reduces the parasitic capacitance formed between the ground electrode 8 and the first pad electrode 5, which is larger than the connection conductor 7 in a plan view from the thickness direction D1 of the laminated substrate 1, and thereby reduces impedance disturbances in the lead-out portion 10 including the first pad electrode 5 and the connection conductor 7. Furthermore, according to the above configuration, in the laminated substrate 1, at least one insulating layer 11 of the plurality of insulating layers 11 to 14 is located between the space 9 and the ground electrode 8 in the thickness direction D1 of the laminated substrate 1. As a result, even if the laminated substrate 1 has the space 9, the multilayer substrate 100 can suppress changes in the shape of the first pad electrode 5 due to the influence of stress or the like at the connection portion between the first pad electrode 5 and the connection conductor 7, thereby reducing impedance disturbance and preventing a short circuit between the first pad electrode 5 and the ground electrode 8.

[0064] The multilayer substrate 100 according to the first embodiment further includes a second ground electrode 82 and a third ground electrode 83 disposed within the laminated substrate 1 and adjacent to the first pad electrode 5. In the multilayer substrate 100, the first pad electrode 5 is located between the second ground electrode 82 and the third ground electrode 83 in a plan view in the thickness direction D1 of the laminated substrate 1.

[0065] According to the above configuration, it is possible to suppress noise leakage in the width direction of the first pad electrode 5 .

[0066] Furthermore, in the multilayer substrate 100 according to the first embodiment, the multiple insulating layers 11 to 14 include a first insulating layer 13 having a conductor pattern portion 3 arranged on a main surface 131 facing the ground electrode 8, and a second insulating layer 12 facing the main surface 131 of the first insulating layer 13. The multilayer substrate 1 further includes an adhesive layer 22 located between the first insulating layer 13 and the second insulating layer 12. A thickness T222 of a portion 222 of the adhesive layer 22 located between the second ground electrode 82 and the second insulating layer 12 and a thickness T223 of a portion 223 of the adhesive layer 22 located between the third ground electrode 83 and the second insulating layer 12 are each thinner than a thickness T221 of a portion 221 of the portion 221 located between the first insulating layer 13 and the second insulating layer 12.

[0067] According to the above configuration, it is possible to form a space 9 between the first pad electrode 5 and the second insulating layer 12 .

[0068] The multilayer substrate module 400 according to the first embodiment also includes the multilayer substrate 100 and a connector 410 connected to the second pad electrodes 6 of the multilayer substrate 100 .

[0069] According to the above configuration, it is possible to reduce impedance disturbance.

[0070] The electronic device 500 according to the first embodiment includes the multilayer substrate module 400 and a housing 501 that houses the multilayer substrate module 400 .

[0071] According to the above configuration, it is possible to reduce impedance disturbance.

[0072] (Embodiment 2) A multilayer substrate 100A according to embodiment 2 will be described with reference to Figures 8 and 9. With regard to the multilayer substrate 100A according to embodiment 2, components that are the same as those in the multilayer substrate 100 according to embodiment 1 (see Figures 1 to 6) are denoted by the same reference numerals, and description thereof will be omitted. In Figures 8 and 9, as in Figures 1 to 6, Cartesian coordinates having three mutually orthogonal axes, namely, the X-axis, the Y-axis, and the Z-axis, are defined and expressed.

[0073] (1) Configuration The multilayer substrate 100A of the second embodiment differs from the multilayer substrate 100 of the first embodiment in that the space 9 of the multilayer substrate 1 is formed so as to span a part of the second ground electrode 82, the first ground electrode 8, and a part of the third ground electrode 83.

[0074] In this embodiment, each of the two spaces 9 in the laminated substrate 1 includes a first space 91, a second space 92, and a third space 93. The first space 91 overlaps the first pad electrode 5 in the thickness direction D1 of the laminated substrate 1. The second space 92 is interposed between the first pad electrode 5 and the second ground electrode 82. The third space 93 is interposed between the first pad electrode 5 and the third ground electrode 83. The second ground electrode 82 faces the first pad electrode 5 across the second space 92. The third ground electrode 83 faces the first pad electrode 5 across the third space 93. The second space 92 and the third space 93 communicate with the first space 91.

[0075] In the multilayer substrate 100A of this embodiment, the adhesive layer 22 is not interposed between the second ground electrode 82 and the first pad electrode 5. In addition, the adhesive layer 22 is not interposed between the third ground electrode 83 and the first pad electrode 5.

[0076] (2) Effects The multilayer substrate 100A according to the second embodiment has the same effects as the multilayer substrate 100 according to the first embodiment.

[0077] In addition, in the multilayer substrate 100A of embodiment 2, the second ground electrode 82 faces the first pad electrode 5 through the second space 92, and the third ground electrode 83 faces the first pad electrode 5 through the third space 93.

[0078] According to the above configuration, it is possible to reduce the parasitic capacitance formed between the first pad electrode 5 and the second ground electrode 82, and also to reduce the parasitic capacitance formed between the first pad electrode 5 and the third ground electrode 83, thereby making it possible to further reduce the impedance disturbance in the lead-out portion 10 including the first pad electrode 5 and the connection conductor 7. Furthermore, according to the above configuration, it is possible to reduce the variation in the parasitic capacitance formed between the first pad electrode 5 and the second ground electrode 82, and also to reduce the variation in the parasitic capacitance formed between the first pad electrode 5 and the third ground electrode 83.

[0079] (Embodiment 3) A multilayer substrate 100B according to embodiment 3 will be described with reference to Fig. 10. With regard to the multilayer substrate 100B according to embodiment 3, components that are the same as those of the multilayer substrate 100A according to embodiment 2 (see Figs. 8 and 9) are denoted by the same reference numerals, and description thereof will be omitted. In Fig. 10, as in Figs. 8 and 9, Cartesian coordinates having three mutually orthogonal axes, i.e., an X-axis, a Y-axis, and a Z-axis, are defined and expressed.

[0080] (1) Configuration In this embodiment, in the thickness direction D1 of the multilayer substrate 1, the thickness T5 of the first pad electrode 5 is thinner than the thickness T82 of the second ground electrode 82 and thinner than the thickness T83 of the third ground electrode 83. That is, in this embodiment, the thicknesses T5, T82, and T83 of the first pad electrode 5, the second ground electrode 82, and the third ground electrode 83 are determined so as to satisfy the conditions T5<T82 and T5<T83. In this embodiment, for example, during the manufacture of the multilayer substrate 100B, only the second ground electrode 82 and the third ground electrode 83 out of the first pad electrode 5, the second ground electrode 82, and the third ground electrode 83 are thickened by plating, thereby satisfying the conditions T5<T82 and T5<T83. In the multilayer substrate 100B, for example, when manufacturing the multilayer substrate 100B, the conditions T5<T82 and T5<T83 may be satisfied by thinning only the first pad electrode 5 among the first pad electrode 5, the second ground electrode 82, and the third ground electrode 83 by etching or polishing, etc.

[0081] (2) Effects The multilayer substrate 100B according to the third embodiment has the same effects as the multilayer substrate 100A according to the second embodiment.

[0082] Furthermore, in the multilayer substrate 100B of embodiment 3, in the thickness direction D1 of the multilayer substrate 1, the thickness T5 of the first pad electrode 5 is thinner than the thicknesses T82 and T83 of the second ground electrode 82 and the third ground electrode 83, respectively.

[0083] According to the above configuration, the parasitic capacitance between the first pad electrode 5 and the first ground electrode 8 can be further reduced, and the impedance disturbance in the extraction portion 10 including the first pad electrode 5 and the connection conductor portion 7 can be further reduced.

[0084] (3) Modification A multilayer substrate 100C according to a modification of embodiment 3 differs from the multilayer substrate 100B according to embodiment 3 in that a space 9 is interposed between the first pad electrode 5 and the insulating layer 11, as shown in FIG. 11 .

[0085] The multilayer substrate 100C according to the modified example of the third embodiment has the same effects as the multilayer substrate 100B according to the third embodiment.

[0086] (Embodiment 4) A multilayer substrate 100D according to embodiment 4 will be described with reference to Figures 12 to 15. With regard to the multilayer substrate 100D according to embodiment 4, components that are the same as those in the multilayer substrate 100 according to embodiment 1 (see Figures 1 to 6) are denoted by the same reference numerals, and description thereof will be omitted. In Figures 12 to 15, as in Figures 1 to 6, Cartesian coordinates having three mutually orthogonal axes, i.e., an X-axis, a Y-axis, and a Z-axis, are defined and expressed.

[0087] (1) Configuration The multilayer substrate 100D of this embodiment includes a laminated substrate 1D, a conductor pattern portion 3 having a signal line 4 and two first pad electrodes 5, two second pad electrodes 6D, two connecting conductor portions 7D (hereinafter also referred to as first connecting conductor portions 7D), and a first ground electrode 8. In this embodiment, the first pad electrode 5 and the connecting conductor portion 7D overlapping in the thickness direction D1 of the laminated substrate 1D form an extension portion 10D connecting the signal line 4 and the second pad electrode 6D. The multilayer substrate 100D also includes a second ground electrode 82, a third ground electrode 83, a fourth ground electrode 84D having two third pad electrodes 122D, a fifth ground electrode 85D having two fourth pad electrodes 123D, a sixth ground electrode 86D, and a seventh ground electrode 87D. The multilayer substrate 100D further includes a plurality of second connection conductors 72D connecting the second ground electrode 82 and the fourth ground electrode 84D, and a plurality of third connection conductors 73D connecting the third ground electrode 83 and the fifth ground electrode 85D. Each of the second connection conductors 72D includes a ground connection conductor V32 and a ground connection conductor V42. Each of the third connection conductors 73D includes a ground connection conductor V33 and a ground connection conductor V43. The multilayer substrate 100D further includes a plurality of ground connection conductors V22 connecting the second ground electrode 82 and the sixth ground electrode 86D, and a plurality of ground connection conductors V12 connecting the sixth ground electrode 86D and the first ground electrode 86D. In addition, the multilayer substrate 100D further includes a plurality of ground connection conductors V23 connecting the third ground electrode 83 and the seventh ground electrode 87D, and a plurality of ground connection conductors V13 connecting the seventh ground electrode 87D and the first ground electrode 8.

[0088] (1.1) Laminated Substrate As shown in Fig. 14 , the laminated substrate 1D has a plurality of insulating layers 11D, 12D, 13D, and 14D (four in the example of Fig. 13 ), and the insulating layers 11D, 12D, 13D, and 14D are stacked. The thickness direction D11 of the laminated substrate 1D is the stacking direction of the insulating layers 11D, 12D, 13D, and 14D. In the laminated substrate 1D, the insulating layer 11D, the insulating layer 12D, the insulating layer 13D, and the insulating layer 14D are stacked in this order.

[0089] In this embodiment, the conductor pattern portion 3 is arranged on a main surface 131D of the insulating layer 13D that faces the ground electrode 8.

[0090] The material of each of the insulating layers 11D, 12D, 13D, and 14D includes, for example, a thermoplastic resin. The thermoplastic resin is, for example, a liquid crystal polymer. The thermoplastic resin is not limited to a liquid crystal polymer, but may be, for example, PTFE (polytetrafluoroethylene). In this embodiment, the insulating layer 11D and the insulating layer 12D are self-adhesive, and no adhesive layer is interposed between the insulating layer 11D and the insulating layer 12D. Also, in this embodiment, the insulating layer 12D and the insulating layer 13D are self-adhesive, and no adhesive layer is interposed between the insulating layer 12D and the insulating layer 13D. This allows the multilayer substrate 100D to improve the controllability of the shape of the space 9 in the multilayer substrate 1D, making it easier to adjust the impedance of the lead portion 10D, including the first pad electrode 5 and the connection conductor 7D, to the desired impedance. Furthermore, from the perspective of reducing water absorption, it is preferable to use a liquid crystal polymer as the thermoplastic resin material.

[0091] The thickness of each of the insulating layers 11D, 12D, 13D, and 14D is, for example, not less than 10 μm and not more than 120 μm.

[0092] In the present embodiment, when viewed from above in the thickness direction D11 of the laminated substrate 1D, the laminated substrate 1D has an elongated shape in which the length along the Y axis is longer than the length along the X axis. When viewed from above in the thickness direction D11 of the laminated substrate 1D, the shape of the laminated substrate 1D may be a shape other than an elongated shape.

[0093] 12 and 14, the conductor pattern portion 3 is disposed within the laminated substrate 1D. The conductor pattern portion 3 has a signal line 4 and two first pad electrodes 5. The conductor pattern portion 3 is formed by patterning a copper foil (hereinafter also referred to as a first copper foil) attached to the insulating layer 13D.

[0094] The signal line 4 is a line through which a high-frequency signal is transmitted. The frequency of the high-frequency signal is, for example, 1 GHz or higher, but is not limited to 1 GHz or higher and may be less than 1 GHz. The signal line 4 is designed so that the impedance of the signal line 4 is 50Ω.

[0095] The signal line 4 has a linear shape when viewed from above in the thickness direction D11 of the laminated substrate 1D. When viewed from above in the thickness direction D11 of the laminated substrate 1D, the signal line 4 may have a shape other than a linear shape.

[0096] In a plan view from the thickness direction D11 of the laminated substrate 1D, each of the two first pad electrodes 5 has a quadrangular shape, but the shape is not limited to a quadrangular shape and may also be a circular shape.

[0097] Each of the two first pad electrodes 5 has a third main surface 51 in contact with the connecting conductor portion 7D corresponding to the first pad electrode 5 out of the two connecting conductor portions 7D, and a fourth main surface 52 facing the ground electrode 8.

[0098] (1.3) Second Pad Electrodes As shown in FIG. 12, two second pad electrodes 6D are disposed on the first main surface 101D of the multilayer substrate 1D.

[0099] The two second pad electrodes 6D correspond one-to-one to the two first pad electrodes 5. In a plan view from the thickness direction D11 of the laminated substrate 1D (see FIG. 14 ), each of the two second pad electrodes 6D overlaps a corresponding one of the two first pad electrodes 5. The first pad electrode 5 and the second pad electrode 6D that overlap in the thickness direction D11 of the laminated substrate 1D are spaced apart in the thickness direction D11 of the laminated substrate 1D. The material of the two second pad electrodes 6D is, for example, copper.

[0100] In a plan view in the thickness direction D11 of the laminated substrate 1D, each of the two second pad electrodes 6D has a rectangular shape, but the shape is not limited to a rectangular shape and may be a circular shape. In the X-axis direction, the width of each second pad electrode 6D is wider than the width of the signal line 4.

[0101] (1.4) Connection Conductor As shown in Fig. 12, the two connection conductors 7D are in one-to-one correspondence with the two first pad electrodes 5. Furthermore, the two connection conductors 7D are in one-to-one correspondence with the two second pad electrodes 6D. The two connection conductors 7D are arranged within the laminated substrate 1. Each of the two connection conductors 7D connects a corresponding one of the two first pad electrodes 5 to a corresponding one of the two second pad electrodes 6D. In short, each connection conductor 7D connects a first pad electrode 5 and a second pad electrode 6D that overlap in the thickness direction D11 of the laminated substrate 1D.

[0102] As shown in FIG. 4 , each of the two connection conductor portions 7D includes a connection conductor V31 and a connection conductor V41 that overlap in the thickness direction D11 of the laminated substrate 1D. The connection conductors V31 and V41 are electrically conductive. The connection conductors V31 and V41 each include, for example, copper, a copper-tin alloy, and a resin. The two connection conductors V31 are formed, for example, by filling two via holes formed in the insulating layer 13 with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and then heating the two via holes, each of which is blocked by a portion of copper foil (the first pad electrode 5). The two connection conductors V41 are formed, for example, by filling two via holes formed in the insulating layer 14 with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and then heating the two via holes, each of which is blocked by a portion of copper foil (the second pad electrode 6D).

[0103] 13 and 14 , the first ground electrode 8 is disposed on the second main surface 102D of the laminated substrate 1D. The ground electrode 8 faces the two first pad electrodes 5 and the signal line 4 in the thickness direction D11 of the laminated substrate 1D.

[0104] The first ground electrode 8 is conductive. The material of the first ground electrode 8 is, for example, copper. The first ground electrode 8 is formed in a predetermined pattern. In a plan view of the laminated substrate 1D in the thickness direction D11, the first ground electrode 8 has, for example, an elongated shape in which the length along the Y axis is longer than the length along the X axis. The first ground electrode 8 is formed, for example, by patterning copper foil attached to the insulating layer 11D. The first ground electrode 8 is disposed on the second main surface 102D of the laminated substrate 1D so as to cover most of the second main surface 102D of the laminated substrate 1D. In a plan view of the laminated substrate 1D in the thickness direction D11, the first ground electrode 8 overlaps the conductor pattern portion 3, the sixth ground electrode 86D, and the seventh ground electrode 87D.

[0105] 14, the second ground electrode 82 and the third ground electrode 83 are disposed in the multilayer substrate 1D. The second ground electrode 82 and the third ground electrode 83 are adjacent to the first pad electrode 5.

[0106] In a plan view of the laminated substrate 1D in the thickness direction D11, the first pad electrode 5 is located between the second ground electrode 82 and the third ground electrode 83.

[0107] The second ground electrode 82 and the third ground electrode 83 are disposed on the main surface 131D of the insulating layer 13D. Therefore, in this embodiment, the second ground electrode 82, the third ground electrode 83, the two first pad electrodes 5, and the signal line 4 (see FIG. 12 ) are disposed on the main surface 131D of the insulating layer 13D. Like the two first pad electrodes 5, the second ground electrode 82 and the third ground electrode 83 are formed by patterning copper foil attached to the insulating layer 13D.

[0108] (1.7) Fourth Ground Electrode and Fifth Ground Electrode When viewed in a plan view from the thickness direction D11 of the laminated substrate 1D, each of the fourth ground electrode 84D and the fifth ground electrode 85D has an elongated shape in which the length along the Y-axis is longer than the length along the X-axis, as shown in FIG. 12 , for example.

[0109] 14 , the fourth ground electrode 84D and the fifth ground electrode 85D are disposed on the main surface 141D of the insulating layer 14D. Therefore, in this embodiment, the fourth ground electrode 84D, the fifth ground electrode 85D, and two second pad electrodes 6D are disposed on the main surface 141D of the insulating layer 14D. The fourth ground electrode 84D has two third pad electrodes 122D. The fifth ground electrode 85D has two fourth pad electrodes 123D. The fourth ground electrode 84D, the fifth ground electrode 85D, and the two second pad electrodes 6D are formed by patterning copper foil attached to the insulating layer 14D.

[0110] In the thickness direction D11 of the laminated substrate 1D, the two third pad electrodes 122D overlap the second ground electrode 82 and the first ground electrode 8. In the thickness direction D11 of the laminated substrate 1D, each third pad electrode 122D is spaced apart from the second ground electrode 82 and the first ground electrode 8, respectively.

[0111] As shown in FIG. 12, each of the two third pad electrodes 122D has a quadrangular shape when viewed from above in the thickness direction D11 of the laminated substrate 1D, but the shape is not limited to a quadrangular shape and may be, for example, a circular shape.

[0112] In the thickness direction D11 of the laminated substrate 1D, the two fourth pad electrodes 123D overlap the third ground electrode 83 and the first ground electrode 8. In the thickness direction D11 of the laminated substrate 1D, each fourth pad electrode 123D is spaced apart from the third ground electrode 83 and the first ground electrode 8, respectively.

[0113] In a plan view in the thickness direction D11 of the laminated substrate 1D, each of the two fourth pad electrodes 123D has a quadrangular shape, but the shape is not limited to a quadrangular shape and may be, for example, a circular shape.

[0114] (1.8) Second Connection Conductor and Third Connection Conductor As shown in FIG. 14 , each of the second connection conductors 72D has a ground connection conductor V32 and a ground connection conductor V42 that overlap in the thickness direction D11 of the laminated substrate 1D. Each of the third connection conductors 73D has a ground connection conductor V33 and a ground connection conductor V43 that overlap in the thickness direction D11 of the laminated substrate 1D. Each of the ground connection conductors V32, V42, V33, and V43 is conductive. Each of the ground connection conductors V32, V42, V33, and V43 contains, for example, copper, a copper-tin alloy, and a resin. The ground connection conductors V32 are formed, for example, by filling a plurality of via holes formed in the insulating layer 13D with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and heating the paste, with each via hole being blocked by a portion of copper foil (the second ground electrode 82). The ground connection conductors V42 are formed, for example, by filling a plurality of via holes formed in the insulating layer 14D with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and heating the paste, with each via hole being blocked by a portion of copper foil (the fourth ground electrode 84D). The ground connection conductors V33 are formed, for example, by filling a plurality of via holes formed in the insulating layer 13D with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and heating the paste, with each via hole being blocked by a portion of copper foil (the third ground electrode 83). The plurality of ground connection conductors V43 are formed, for example, by filling a plurality of via holes formed in the insulating layer 14D with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and heating the paste, with each via hole being blocked by a portion of copper foil (fifth ground electrode 85D).

[0115] (1.9) Other Ground Connection Conductors The ground connection conductors V22, V12, V23, and V13 are each electrically conductive. The ground connection conductors V22, V12, V23, and V13 each contain, for example, copper, a copper-tin alloy, and resin. The ground connection conductors V22 are formed, for example, by filling a conductive paste containing copper, a low-melting-point metal (e.g., tin), and resin into a plurality of via holes formed in the insulating layer 12D, each of which is blocked by a portion of copper foil (the sixth ground electrode 86D), and then heating the via holes. The ground connection conductors V23 are formed, for example, by filling a conductive paste containing copper, a low-melting-point metal (e.g., tin), and resin into a plurality of via holes formed in the insulating layer 12D, each of which is blocked by a portion of copper foil (the seventh ground electrode 87D), and then heating the via holes. The ground connection conductors V12 are formed, for example, by filling a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin into a plurality of via holes formed in the insulating layer 11D, each of which is blocked with a portion of the copper foil (first ground electrode 8), and then heating the via holes. The ground connection conductors V13 are formed, for example, by filling a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin into a plurality of via holes formed in the insulating layer 11D, each of which is blocked with a portion of the copper foil (first ground electrode 8), and then heating the via holes.

[0116] In this embodiment, the ground connection conductors V22 and the ground connection conductors V12 correspond one-to-one to each other, and corresponding ground connection conductors V22 and V12 overlap in the thickness direction D11 of the multilayer substrate 1D. In the multilayer substrate 100D, the ground connection conductors V22 and V12 may be arranged so as to be shifted from each other in the longitudinal direction of the second ground electrode 82. Furthermore, the number of ground connection conductors V22 and V12 may differ from each other.

[0117] In this embodiment, the ground connection conductors V23 and the ground connection conductors V13 correspond one-to-one to each other, and corresponding ground connection conductors V23 and V13 overlap in the thickness direction D11 of the multilayer substrate 1D. In the multilayer substrate 100D, the ground connection conductors V23 and V13 may be arranged so as to be shifted from each other in the longitudinal direction of the third ground electrode 83. Furthermore, the number of ground connection conductors V23 and V13 may differ from each other.

[0118] (1.10) Space in the Laminated Substrate As shown in FIG. 14 , the first pad electrode 5 has a third main surface 51 in contact with the connection conductor 7D and a fourth main surface 52 facing the ground electrode 8. The laminated substrate 1D has a space 9 that exposes the entire fourth main surface 52 of the first pad electrode 5 within the laminated substrate 1D. The space 9 is a closed space and does not communicate with the outside of the laminated substrate 1D. In the laminated substrate 1D, the entire space 9 overlaps with the first ground electrode 8 in a plan view from the thickness direction D11 of the laminated substrate 1D. In the laminated substrate 1D, at least one insulating layer 11D of the multiple insulating layers 11D to 14D is located between the space 9 and the first ground electrode 8 in the thickness direction D11 of the laminated substrate 1D. In the laminated substrate 1D of this embodiment, one insulating layer 11D of the multiple insulating layers 11D to 14D is located between the space 9 and the first ground electrode 8 in the thickness direction D11 of the laminated substrate 1D. Furthermore, in the laminated substrate 1D of this embodiment, two insulating layers 12D and 11D among the insulating layers 11D to 14D are located between the signal line 4 and the first ground electrode 8 in the thickness direction D11 of the laminated substrate 1D.

[0119] 14 and 15 , the space 9 includes an opening 120D in the insulating layer 12D. The opening 120D in the insulating layer 12D is a through-hole that penetrates the insulating layer 12D in the thickness direction D11 of the laminated substrate 1D. In a plan view from the thickness direction D11 of the laminated substrate 1D, the opening 120D is larger than the first pad electrode 5. In a plan view from the thickness direction D11 of the laminated substrate 1D, the opening shape of the opening 120D is a rectangle that is long in the width direction of the first pad electrode 5 (a direction parallel to the X-axis), but it may be a shape other than a rectangle.

[0120] In the width direction of the first pad electrode 5 , the opening width of the opening 120D is smaller than the distance between the second ground electrode 82 and the third ground electrode 83 .

[0121] (2) Effects In the multilayer substrate 100D according to the fourth embodiment, in the conductor pattern portion 3 having the signal line 4 and the first pad electrode 5, the first pad electrode 5 has a third main surface 51 in contact with the connection conductor portion 7D and a fourth main surface 52 facing the ground electrode 8. The width W5 of the first pad electrode 5 in the width direction of the signal line 4 is greater than the width W4 of the signal line 4. In a plan view from the thickness direction D11 of the laminated substrate 1D, the connection conductor portion 7D is smaller than the first pad electrode 5. The laminated substrate 1D has a space 9 that exposes the entire fourth main surface 52 of the first pad electrode 5 within the laminated substrate 1D. In the laminated substrate 1D, the entire space 9 overlaps with the ground electrode 8 in a plan view from the thickness direction D11 of the laminated substrate 1D. In the laminated substrate 1D, at least one insulating layer 11D among the multiple insulating layers 11D to 14D is located between the space 9 and the ground electrode 8 in the thickness direction D11 of the laminated substrate 1D.

[0122] The above configuration reduces impedance disturbances. More specifically, the above configuration allows the laminated substrate 1D to have the space 9 that exposes the entire fourth main surface 52 of the first pad electrode 5 within the laminated substrate 1D, thereby reducing the dielectric constant compared to a case where the space 9 is not provided. This reduces the parasitic capacitance formed between the ground electrode 8 and the first pad electrode 5, which is larger than the connection conductor 7D in a plan view from the thickness direction D11 of the laminated substrate 1D, and reduces impedance disturbances in the extension portion 10D that includes the first pad electrode 5 and the connection conductor 7D. Furthermore, the above configuration allows at least one insulating layer 11D of the multiple insulating layers 11D to 14D to be located between the space 9 and the ground electrode 8 in the thickness direction D11 of the laminated substrate 1D. As a result, even if the multilayer substrate 100D has a space 9, the multilayer substrate 100D can suppress changes in the shape of the first pad electrode 5 due to the influence of stress, etc. at the connection between the first pad electrode 5 and the connection conductor portion 7D, thereby reducing impedance disturbances and preventing short circuits between the first pad electrode 5 and the ground electrode 8.

[0123] The multilayer substrate 100D according to the fourth embodiment further includes a second ground electrode 82 and a third ground electrode 83 disposed within the laminated substrate 1D and adjacent to the first pad electrode 5. In the multilayer substrate 100D, the first pad electrode 5 is located between the second ground electrode 82 and the third ground electrode 83 in a plan view in the thickness direction D11 of the laminated substrate 1D.

[0124] According to the above configuration, it is possible to suppress noise leakage in the width direction of the first pad electrode 5 .

[0125] Fifth Embodiment A multilayer substrate 100E according to a fifth embodiment will be described with reference to Fig. 16. Regarding the multilayer substrate 100E according to the fifth embodiment, the same components as those of the multilayer substrate 100 according to the first embodiment (see Figs. 1 to 6) are denoted by the same reference numerals, and description thereof will be omitted. In Fig. 16, as in Figs. 1 to 6, an orthogonal coordinate system having three mutually orthogonal axes, the X-axis, the Y-axis, and the Z-axis, is defined, and the axis along the thickness direction D1 of the multilayer substrate 1 is indicated as the Z-axis.

[0126] (1) Configuration In the multilayer substrate 100E according to the fifth embodiment, the space 9 contains the first pad electrode 5 in a plan view in the thickness direction D1 of the laminated substrate 1. In this embodiment, the insulating layer 13 on which the first pad electrode 5 is arranged, among the multiple insulating layers 11 to 14, has a recess 133 surrounding the first pad electrode 5 in a plan view in the thickness direction D1 of the laminated substrate 1. The recess 133 is formed in the main surface 131 of the insulating layer 13. In this embodiment, the internal space of the recess 133 also serves as part of the space 9.

[0127] In this embodiment, a space 9 is formed between the first pad electrode 5 and the adhesive layer 21 .

[0128] (2) Effects The multilayer substrate 100E according to the fifth embodiment has the same effects as the multilayer substrate 100 according to the first embodiment.

[0129] Sixth Embodiment A multilayer substrate 100F according to a sixth embodiment will be described with reference to Figures 17 to 20. Regarding the multilayer substrate 100F according to the sixth embodiment, the same components as those of the multilayer substrate 100 according to the first embodiment (see Figures 1 to 6) are denoted by the same reference numerals, and description thereof will be omitted. In Figures 17 to 20, as in Figures 1 to 6, an orthogonal coordinate system having three mutually orthogonal axes, the X-axis, the Y-axis, and the Z-axis, is defined, and the axis along the thickness direction D1 of the multilayer substrate 1 is represented as the Z-axis.

[0130] (1) Configuration In the multilayer substrate 100F according to the sixth embodiment, as shown in FIG. 19 , the laminated substrate 1 further includes a space 19 that exposes at least a portion of the main surface 43 (see FIG. 19 ) of the signal line 4 that faces the ground electrode 8 within the laminated substrate 1.

[0131] 19 and 20 , in a plan view of the laminated substrate 1 in the thickness direction D1, the space 19 overlaps the entire area of ​​the signal line 4. In addition, in the plan view of the laminated substrate 1 in the thickness direction D1, the width of the space 19 is wider than the width of the signal line 4. In the present embodiment, the space 19 overlapping the signal line 4 communicates with the two spaces 9 overlapping the two first pad electrodes 5, respectively. The space 19 need only expose at least a portion of the main surface 43 of the signal line 4 within the laminated substrate 1, and does not have to communicate with the two spaces 9. In addition, multiple spaces 19 may be positioned spaced apart from each other in the signal transmission direction of the signal line 4.

[0132] (2) Effects The multilayer substrate 100F according to the sixth embodiment has the same effects as the multilayer substrate 100 according to the first embodiment.

[0133] In addition, in the multilayer substrate 100F of embodiment 6, the laminated substrate 1 further has a space 19 that exposes at least a portion of the main surface 43 (see Figure 19) of the signal line 4 that faces the ground electrode 8 within the laminated substrate 1.

[0134] According to the above configuration, it is possible to improve the insertion loss characteristics.

[0135] Seventh Embodiment A multilayer substrate 100G and a multilayer substrate module 400G according to a seventh embodiment will be described with reference to Figures 21 and 22. Regarding the multilayer substrate 100G according to the seventh embodiment, components that are the same as those in the multilayer substrate 100 according to the first embodiment (see Figures 1 to 6) are denoted by the same reference numerals, and descriptions thereof will be omitted. In Figures 21 and 22, as in Figures 1 to 6, an orthogonal coordinate system having three mutually orthogonal axes, the X-axis, the Y-axis, and the Z-axis, is defined, and the axis along the thickness direction D1 of the multilayer substrate 1 is indicated as the Z-axis.

[0136] (1) Configuration The multilayer substrate 100G according to the seventh embodiment differs from the multilayer substrate 100 according to the first embodiment in that it includes a first resist layer 150 and a second resist layer 160. The first resist layer 150 has an opening 151 that exposes the second pad electrode 6. In this embodiment, the opening 151 is smaller than the second pad electrode 6 in a plan view from the thickness direction D1 of the laminated substrate 1. The first resist layer 150 also has an opening 152 that exposes the third pad electrode 122 and an opening 153 that exposes the fourth pad electrode 123. In this embodiment, the opening 152 is smaller than the third pad electrode 122, and the opening 153 is smaller than the fourth pad electrode 123 in a plan view from the thickness direction D1 of the laminated substrate 1. The first resist layer 150 covers the first main surface 101 of the laminated substrate 1. The second resist layer 160 covers the second main surface 102 of the multilayer substrate 1 and the ground electrode 8 .

[0137] Each of the first resist layer 150 and the second resist layer 160 includes, for example, a polyimide film and an adhesive layer. The material of the adhesive layer includes, for example, an acrylic resin, a silicone resin, an epoxy resin, or a urethane resin. Each of the first resist layer 150 and the second resist layer 160 is not limited to a configuration including a polyimide film and an adhesive layer, and may be a resist layer formed using, for example, spin coating technology and photolithography technology.

[0138] (2) Multilayer Substrate Module The multilayer substrate module 400G differs from the multilayer substrate module 400 according to the first embodiment (see FIGS. 5 and 6) in that it includes a multilayer substrate 100G instead of the multilayer substrate 100 of the multilayer substrate module 400.

[0139] (3) Effects The multilayer substrate 100G according to the seventh embodiment has the same effects as the multilayer substrate 100 according to the first embodiment.

[0140] Moreover, the multilayer substrate 100G according to the seventh embodiment includes a first resist layer 150 and a second resist layer 160.

[0141] According to the above configuration, the first resist layer 150 and the second resist layer 160 can reinforce the laminated substrate 1, and deformation of the laminated substrate 1 around the space 9 can be suppressed.

[0142] The multilayer substrate module 400G also includes a multilayer substrate 100G and a connector 410 connected to the second pad electrodes 6 of the multilayer substrate 100G.

[0143] According to the above configuration, it is possible to reduce impedance disturbance.

[0144] Eighth Embodiment A multilayer substrate 100H according to an eighth embodiment will be described with reference to Fig. 23. With respect to the multilayer substrate 100H according to the eighth embodiment, components that are the same as those of the multilayer substrate 100D according to the fourth embodiment (see Figs. 12 to 15) are denoted by the same reference numerals, and description thereof will be omitted. In Fig. 23, as in Figs. 12 to 15, Cartesian coordinates having three mutually orthogonal axes, i.e., an X-axis, a Y-axis, and a Z-axis, are defined and expressed.

[0145] (1) Configuration The multilayer substrate 100H according to the eighth embodiment differs from the multilayer substrate 100D according to the fourth embodiment in that the multilayer substrate 1D further includes an insulating layer 15D. The insulating layer 15D covers the first main surface 101D, the second pad electrode 6D, the fourth ground electrode 84D, and the fifth ground electrode 85D of the multilayer substrate 1D. The multilayer substrate 100H also includes a fifth pad electrode 18D, an eighth ground electrode 88D, and a ninth ground electrode 89D, which are arranged on the main surface 151D of the insulating layer 15D. In this embodiment, the main surface 151D of the insulating layer 15D constitutes the third main surface of the multilayer substrate 1D.

[0146] The fifth pad electrode 18D overlaps the second pad electrode 6D in the thickness direction D11 of the laminated substrate 1D. The fifth pad electrode 18D is separated from the second pad electrode 6D in the thickness direction D11 of the laminated substrate 1D. The fifth pad electrode 18D, the eighth ground electrode 88D, and the ninth ground electrode 89D are made of, for example, copper. The fifth pad electrode 18D, the eighth ground electrode 88D, and the ninth ground electrode 89D are formed by patterning copper foil attached to the insulating layer 15D. The insulating layer 15D is made of, like the materials of the insulating layers 11D, 12D, 13D, and 14D, a thermoplastic resin. The thermoplastic resin is, for example, a liquid crystal polymer. The thermoplastic resin is not limited to a liquid crystal polymer, and may be, for example, PTFE. In this embodiment, the insulating layer 14D and the insulating layer 15D are self-adhesive, and no adhesive layer is interposed between the insulating layer 14D and the insulating layer 15D. The thickness of the insulating layer 15D is, for example, not less than 10 μm and not more than 120 μm.

[0147] The multilayer substrate 100H further includes a connecting conductor V51 connecting the second pad electrode 6D and the fifth pad electrode 18D, a ground connecting conductor V52 connecting the fourth ground electrode 84D and the eighth ground electrode 88D, and a ground connecting conductor V53 connecting the fifth ground electrode 85D and the ninth ground electrode 89D.

[0148] The connecting conductor V51 is formed, for example, by filling a via hole formed in the insulating layer 15D with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and heating the via hole, while the via hole is blocked with a portion of copper foil (the fifth pad electrode 18D). The ground connecting conductor V52 is formed, for example, by filling a via hole formed in the insulating layer 15D with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and heating the via hole, while the via hole is blocked with a portion of copper foil (the eighth ground electrode 88D). The ground connecting conductor V53 is formed, for example, by filling a via hole formed in the insulating layer 15D with a conductive paste containing copper, a low-melting-point metal (e.g., tin), and a resin, and heating the via hole, while the via hole is blocked with a portion of copper foil (the ninth ground electrode 89D).

[0149] (2) Effects The multilayer substrate 100H according to the eighth embodiment can reduce impedance disturbances, similar to the multilayer substrate 100D according to the fourth embodiment.

[0150] Ninth Embodiment A multilayer substrate 100I according to a ninth embodiment will be described with reference to Figures 24 and 25. With respect to the multilayer substrate 100I according to the ninth embodiment, components that are the same as those in the multilayer substrate 100 according to the first embodiment (see Figures 1 to 6) are denoted by the same reference numerals, and description thereof will be omitted. In Figures 24 and 25, as in Figures 1 to 6, Cartesian coordinates having three mutually orthogonal axes, namely, the X-axis, the Y-axis, and the Z-axis, are defined and expressed.

[0151] (1) Configuration The multilayer substrate 100I of embodiment 9 differs from the multilayer substrate 100 of embodiment 1 in that one of the two second pad electrodes 6 is larger than the remaining second pad electrode 6 and constitutes the radiation electrode 170 of the antenna 17.

[0152] When viewed from above in the thickness direction D1 of the laminated substrate 1, the radiation electrode 170 has, for example, a square shape, but is not limited to a square shape and may have, for example, a rectangular shape.

[0153] In this embodiment, the antenna 17 includes a radiating electrode 170, a portion of the laminated substrate 1 that overlaps with the radiating electrode 170 in the thickness direction D1 of the laminated substrate 1, and a portion of the ground electrode 8 that overlaps with the radiating electrode 170 in the thickness direction D1 of the laminated substrate 1.

[0154] In this embodiment, one of the two connection conductors 7 is connected to the radiation electrode 170. The connection conductor 7 connected to the radiation electrode 170 functions as a feeding point of the antenna 17.

[0155] (2) Effects The multilayer substrate 100I according to the ninth embodiment can reduce impedance disturbances, similar to the multilayer substrate 100 according to the first embodiment. Furthermore, the multilayer substrate 100I according to the ninth embodiment can reduce impedance disturbances in the lead-out portion 10 connected to the antenna 17, thereby improving antenna performance.

[0156] (Modifications) The above-described first to ninth embodiments are merely examples of various embodiments of the present invention. The above-described first to ninth embodiments can be modified in various ways depending on the design and the like, and may be combined as appropriate, as long as the object of the present invention can be achieved.

[0157] For example, the multilayer substrates 100, 100A to 100C, and 100E to 100G each include two first pad electrodes 5, two second pad electrodes 6, and two connecting conductors 7, but may instead include one first pad electrode 5, one second pad electrode 6, and one connecting conductor 7. The multilayer substrates 100D and 100H each include two first pad electrodes 5, two second pad electrodes 6D, and two connecting conductors 7D, but may instead include one first pad electrode 5, one second pad electrode 6D, and one connecting conductor 7D.

[0158] Furthermore, in the multilayer substrates 100, 100A to 100C, and 100E to 100G, one of the two second pad electrodes 6 may be a radiation electrode of an antenna, similar to the multilayer substrate 100I. Furthermore, in the multilayer substrates 100D and 100H, one of the two second pad electrodes 6D may be a radiation electrode of an antenna, similar to the multilayer substrate 100I.

[0159] Furthermore, the multilayer substrates 100, 100A to 100C, 100E to 100G, and 100I may be configured without the third pad electrodes 122 and the fourth pad electrodes 123. Furthermore, the multilayer substrates 100D and 100H may be configured without the third pad electrodes 122D and the fourth pad electrodes 123D.

[0160] Furthermore, multilayer substrates 100A-100I may be curved, similar to multilayer substrate 100 in Fig. 7. Multilayer substrate 100D can maintain its shape by itself if it is bent by plastically deforming thermoplastic resin. This makes it easier to place multilayer substrate 100D within housing 501 of electronic device 500 (see Fig. 7), for example, when the storage space for multilayer substrate 100D in housing 501 of electronic device 500 is a curved space.

[0161] Moreover, the multilayer substrate module 400 according to the first embodiment may include any one of the multilayer substrates 100A to 100F, 100H, and 100I in place of the multilayer substrate 100.

[0162] Furthermore, the electronic device 500 may include multilayer substrates 100A to 100I instead of the multilayer substrate 100 of the multilayer substrate module 400. The multilayer substrates 100 to 100I may be curved.

[0163] Furthermore, the multilayer substrates 100 to 100F, 100H, and 100I may have the same configuration as the first resist layer 150 and the second resist layer 160 of the multilayer substrate 100G.

[0164] Similarly to the multilayer substrate 100H, the multilayer substrates 100 to 100C and 100E to 100G may have an insulating layer disposed on the first main surface 101 of the laminate substrate 1. In the multilayer substrates 100 to 100C, 100E to 100G, and 100I, the multiple insulating layers of the laminate substrate 1 may include an insulating layer that covers the second main surface 102 of the laminate substrate 1 and the ground electrode 8, in addition to the insulating layers 11 to 14. In the multilayer substrates 100D and 100H, the multiple insulating layers of the laminate substrate 1 may include an insulating layer that covers the second main surface 102D of the laminate substrate 1D and the ground electrode 8, in addition to the insulating layers 11D to 11D and 11D to 15D.

[0165] For example, in the case of multilayer substrates 100, 100A to 100I, when the second ground electrode 82 and the third ground electrode 83 are adjacent to the first pad electrode 5, the first pad electrode 5 is surrounded by multiple ground electrodes including the first ground electrode 8, the second ground electrode 82, and the third ground electrode 83, and therefore the first pad electrode 5 and the multiple ground electrodes are close to each other, which can easily cause impedance disturbances.

[0166] To address this issue, in each of the multilayer substrates 100, 100A to 100I, the multilayer substrates 1, 1D have a space 9, which makes it possible to reduce impedance disturbances regardless of the size of the first pad electrode 5.

[0167] (Aspects) The present specification discloses the following aspects.

[0168] A multilayer substrate (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H; 100I) according to a first aspect includes a laminated substrate (1; 1D), a conductor pattern portion (3) having a signal line (4) and a first pad electrode (5), a second pad electrode (6; 6D), a connection conductor portion (7; 7D), and a ground electrode (8). The laminated substrate (1; 1D) has a plurality of insulating layers (11-14; 11D-14D; 11D-15D) stacked one on top of the other. The laminated substrate (1; 1D) has a first main surface (101; 101D) and a second main surface (102; 102D). The conductor pattern portion (3) is disposed within the laminated substrate (1; 1D). The second pad electrode (6; 6D) is arranged on the first main surface (101; 101D) of the laminated substrate (1; 1D). The second pad electrode (6; 6D) is spaced apart from the first pad electrode (5) in the thickness direction (D1; D11) of the laminated substrate (1; 1D) and overlaps the first pad electrode (5) in a plan view from the thickness direction (D1; D11) of the laminated substrate (1; 1D). At least a portion of the connection conductor portion (7; 7D) is arranged within the laminated substrate (1; 1D). The connection conductor portion (7; 7D) connects the first pad electrode (5) and the second pad electrode (6; 6D). The ground electrode (8) is arranged on the second main surface (102; 102D) of the laminated substrate (1; 1D). The ground electrode (8) faces the first pad electrode (5) and the signal line (4) in the thickness direction (D1; D11) of the laminated substrate (1; 1D). The first pad electrode (5) has a third main surface (51) in contact with the connection conductor portion (7; 7D) and a fourth main surface (52) facing the ground electrode (8). In the width direction of the signal line (4), the width (W5) of the first pad electrode (5) is larger than the width (W4) of the signal line (4). In a plan view from the thickness direction (D1; D11) of the laminated substrate (1; 1D), the connection conductor portion (7; 7D) is smaller than the first pad electrode (5). The laminated substrate (1; 1D) has a space (9) that exposes the entire fourth main surface (52) of the first pad electrode (5) within the laminated substrate (1; 1D). In the laminated substrate (1; 1D), the entire space (9) overlaps with the ground electrode (8) when viewed from above in the thickness direction (D1; D11) of the laminated substrate (1; 1D).In the laminated substrate (1; 1D), at least one insulating layer (11; 11D) of a plurality of insulating layers (11-14; 11D-14D; 11D-15D) is located between the space (9) and the ground electrode (8) in the thickness direction (D1; D11) of the laminated substrate (1; 1D).

[0169] According to this aspect, it is possible to reduce the disturbance of the impedance.

[0170] The multilayer substrate (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H; 100I) according to the second aspect further includes a second ground electrode (82) and a third ground electrode (83) in the first aspect. The second ground electrode (82) and the third ground electrode (83) are different from the first ground electrode (8), which is the ground electrode (8). The second ground electrode (82) and the third ground electrode (83) are disposed within the multilayer substrate (1; 1D) and adjacent to the first pad electrode (5). In a plan view from the thickness direction (D1; D11) of the multilayer substrate (1; 1D), the first pad electrode (5) is located between the second ground electrode (82) and the third ground electrode (83).

[0171] According to this aspect, it is possible to suppress noise leakage in the width direction of the first pad electrode (5).

[0172] In a multilayer substrate (100A; 100B; 100C) according to a third aspect, in the second aspect, the space (9) of the laminated substrate (1) includes a first space (91), a second space (92), and a third space (93). The first space (91) overlaps the first pad electrode (5) in the thickness direction (D1) of the laminated substrate (1). The second space (92) is interposed between the first pad electrode (5) and the second ground electrode (82). The third space (93) is interposed between the first pad electrode (5) and the third ground electrode (83). The second ground electrode (82) faces the first pad electrode (5) across the second space (92). The third ground electrode (83) faces the first pad electrode (5) across the third space (93).

[0173] According to this aspect, it is possible to reduce the parasitic capacitance formed between the first pad electrode (5) and the second ground electrode (82), and also to reduce the parasitic capacitance formed between the first pad electrode (5) and the third ground electrode (83), thereby making it possible to further reduce impedance disturbance. Furthermore, according to the above configuration, it is possible to reduce the variation in the parasitic capacitance formed between the first pad electrode (5) and the second ground electrode (82), and also to reduce the variation in the parasitic capacitance formed between the first pad electrode (5) and the third ground electrode (83).

[0174] A multilayer substrate (100B) according to a fourth aspect is based on the second or third aspect. In a thickness direction (D1) of the multilayer substrate (1), a thickness (T5) of the first pad electrode (5) is thinner than thicknesses (T82, T83) of the second ground electrode (82) and the third ground electrode (83), respectively.

[0175] According to this aspect, the parasitic capacitance formed between the first pad electrode (5) and the first ground electrode (8) can be further reduced, and the disturbance of the impedance can be further reduced.

[0176] In a multilayer substrate (100E) according to a fifth aspect, in any one of the first to fourth aspects, the space (9) contains the first pad electrode (5) in a plan view from the thickness direction (D1) of the laminated substrate (1). Of the multiple insulating layers (11 to 14), the insulating layer (13) on which the first pad electrode (5) is arranged has a recess (133) surrounding the first pad electrode (5) in a plan view from the thickness direction (D1) of the laminated substrate (1). The internal space of the recess (133) also serves as part of the space (9).

[0177] In a multilayer substrate (100D; 100H) according to a sixth aspect, in any one of the first to fifth aspects, the material of each of the plurality of insulating layers (11D to 14D; 11D to 15D) includes a thermoplastic resin.

[0178] According to this aspect, it is possible to improve the bendability of the multilayer substrate (100D; 100H).

[0179] In a multilayer substrate (100) according to a seventh aspect, in any one of the second to fourth aspects, the plurality of insulating layers (11 to 14) include a first insulating layer (13) having a conductor pattern portion (3) disposed on a main surface (131) facing the ground electrode (8), and a second insulating layer (12) facing the main surface (131) of the first insulating layer (13). The laminated substrate (1) further has an adhesive layer (22) located between the first insulating layer (13) and the second insulating layer (12). The adhesive layer (22) has a thickness (T222) of a portion (222) interposed between the second ground electrode (82) and the second insulating layer (12) and a thickness (T223) of a portion (223) interposed between the third ground electrode (83) and the second insulating layer (12), each of which is thinner than the thickness (T221) of the portion (221) interposed between the first insulating layer (13) and the second insulating layer (12).

[0180] According to this aspect, it is possible to form a space (9) between the first pad electrode (5) and the second insulating layer (12).

[0181] In the multilayer substrate (100F) according to the eighth aspect, in any one of the first to seventh aspects, the laminated substrate (1) further has a space (19) that exposes within the laminated substrate (1) at least a portion of the main surface (43) of the signal line (4) that faces the ground electrode (8).

[0182] According to this aspect, it is possible to improve the insertion loss characteristics.

[0183] A multilayer substrate (100F) according to a ninth aspect is the same as any one of the first to eighth aspects, further comprising a first resist layer (150) and a second resist layer (160). The first resist layer (150) has an opening (151) that exposes the second pad electrode (6). The first resist layer (150) covers the first main surface (101) of the multilayer substrate (1). The second resist layer covers the second main surface (102) of the multilayer substrate (1) and the ground electrode (8).

[0184] According to this aspect, the first resist layer (150) and the second resist layer (160) can reinforce the laminated substrate (1), making it possible to suppress deformation of the laminated substrate (1) around the space (9).

[0185] In a multilayer substrate (100H) according to a tenth aspect, in any one of the first to ninth aspects, the plurality of insulating layers (11D to 15D) includes an insulating layer (15D) covering the first main surface (101D) of the multilayer substrate (1D) and the second pad electrode (6D).

[0186] The multilayer substrate (100I) according to an eleventh aspect is any one of the first to ninth aspects, and includes two second pad electrodes (6). One of the two second pad electrodes (6) is a radiation electrode (170) of the antenna (17).

[0187] According to this aspect, it is possible to reduce impedance disturbances and improve antenna performance.

[0188] A multilayer substrate module (400; 400G) according to a twelfth aspect comprises a multilayer substrate (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H; 100I) according to any one of the first to eleventh aspects, and a connector (410) connected to a second pad electrode (6; 6D) of the multilayer substrate (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H; 100I).

[0189] According to this aspect, it is possible to reduce the disturbance of the impedance.

[0190] An electronic device (500) according to a thirteenth aspect includes the multilayer substrate module (400; 400G) according to the twelfth aspect, and a housing (501) that houses the multilayer substrate module (400; 400G).

[0191] According to this aspect, it is possible to reduce the disturbance of the impedance.

[0192] A multilayer substrate (100; 100A; 100B; 100C; 100D; 100E; 100F; 100G; 100H; 100I) according to a fourteenth aspect includes a laminated substrate (1; 1D), a conductor pattern portion (3) having a signal line (4) and a first pad electrode (5), a second pad electrode (6; 6D), a connecting conductor portion (7; 7D), a first ground electrode (8), a second ground electrode (82), and a third ground electrode (83). The laminated substrate (1; 1D) is formed by stacking a plurality of insulating layers (11-14; 11D-14D; 11D-15D). The laminated substrate (1; 1D) has a first main surface (101; 101D) and a second main surface (102; 102D). The conductor pattern portion (3) is arranged within the laminated substrate (1; 1D). The second pad electrode (6; 6D) is arranged on the first main surface (101; 101D) of the laminated substrate (1; 1D). The second pad electrode (6; 6D) is separated from the first pad electrode (5) in the thickness direction (D1; D11) of the laminated substrate (1; 1D) and overlaps the first pad electrode (5) in a plan view from the thickness direction (D1; D11) of the laminated substrate (1; 1D). At least a portion of the connection conductor portion (7; 7D) is arranged within the laminated substrate (1; 1D). The connection conductor portion (7; 7D) connects the first pad electrode (5) and the second pad electrode (6; 6D). The first ground electrode (8) is arranged on the second main surface (102; 102D) of the laminated substrate (1; 1D). The first ground electrode (8) faces the first pad electrode (5) and the signal line (4) in the thickness direction (D1; D11) of the laminated substrate (1; 1D). The first pad electrode (5) has a third main surface (51) in contact with the connection conductor (7; 7D) and a fourth main surface (52) facing the first ground electrode (8). The second ground electrode (82) and the third ground electrode (83) are disposed within the laminated substrate (1; 1D) and adjacent to the first pad electrode (5). In a plan view from the thickness direction (D1; D11) of the laminated substrate (1), the first pad electrode (5) is located between the second ground electrode (82) and the third ground electrode (83). The laminated substrate (1; 1D) has a space (9) that exposes the entire fourth main surface (52) of the first pad electrode (5) within the laminated substrate (1; 1D).In the laminated substrate (1; 1D), the entire space (9) overlaps the ground electrode (8) in a plan view in the thickness direction (D1; D11) of the laminated substrate (1; 1D). In the laminated substrate (1; 1D), at least one insulating layer (11; 11D) of the plurality of insulating layers (11-14; 11D-14D; 11D-15D) is located between the space (9) and the ground electrode (8) in the thickness direction (D1; D11) of the laminated substrate (1; 1D).

[0193] According to this aspect, it is possible to reduce the disturbance of the impedance.

[0194] DESCRIPTION OF SYMBOLS 1, 1D Laminated substrate 101, 101D First main surface 102, 102D Second main surface 11 Insulating layer 11D Insulating layer 12 Insulating layer (second insulating layer) 12D Insulating layer 13 Insulating layer (first insulating layer) 131 Main surface 13D Insulating layer 14 Insulating layer 14D Insulating layer 15D Insulating layer 21 Adhesive layer 22 Adhesive layer 23 Adhesive layer 3 Conductive pattern portion 4 Signal line 43 Main surface 5 First pad electrode 51 Third main surface 52 Fourth main surface 6, 6D Second pad electrode 7, 7D Connection conductor portion 8 Ground electrode (first ground electrode) 82 Second ground electrode 83 Third ground electrode 9 Space 91 First space 92 Second space 93 Third space 10, 10D Lead portion 17 Antenna 170 Radiation electrode 19 Space 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I Multilayer substrate 150 First resist layer 151 Opening 160 Second resist layer 400, 400G Multilayer substrate module 500 Electronic device 501 Housing D1, D11 Thickness direction T5 Thickness T82 Thickness T83 Thickness T221 Thickness T222 Thickness T223 Thickness W4 Width W5 Width

Claims

1. A laminated substrate comprising a plurality of insulating layers stacked one on top of the other, the laminated substrate having a first main surface and a second main surface; a conductor pattern portion disposed within the laminated substrate and having a signal line and a first pad electrode; a second pad electrode disposed on the first main surface of the laminated substrate, spaced apart from the first pad electrode in the thickness direction of the laminated substrate, and overlapping the first pad electrode in a plan view from the thickness direction of the laminated substrate; a connection conductor portion at least a portion of which is disposed within the laminated substrate and connecting the first pad electrode and the second pad electrode; and a ground electrode disposed on the second main surface of the laminated substrate and facing the first pad electrode and the signal line in the thickness direction of the laminated substrate, the first pad electrode having a third main surface in contact with the connection conductor portion and a fourth main surface facing the ground electrode, the width of the first pad electrode in the width direction of the signal line being larger than the width of the signal line, and the connection conductor portion being smaller than the first pad electrode in a plan view from the thickness direction of the laminated substrate, the laminated substrate has a space that exposes the entire fourth main surface of the first pad electrode within the laminated substrate, the entire space overlaps the ground electrode in a plan view in the thickness direction of the laminated substrate, and at least one insulating layer of the plurality of insulating layers is located between the space and the ground electrode in the thickness direction of the laminated substrate.

2. The multilayer substrate according to claim 1, further comprising a second ground electrode and a third ground electrode that are different from the first ground electrode and are disposed within the laminated substrate and adjacent to the first pad electrode, and the first pad electrode is located between the second ground electrode and the third ground electrode when viewed in a plan view in the thickness direction of the laminated substrate.

3. The multilayer substrate according to claim 2, wherein the spaces in the laminated substrate include a first space overlapping the first pad electrode in the thickness direction of the laminated substrate, a second space interposed between the first pad electrode and the second ground electrode, and a third space interposed between the first pad electrode and the third ground electrode, wherein the second ground electrode faces the first pad electrode across the second space, and the third ground electrode faces the first pad electrode across the third space.

4. The multilayer substrate according to claim 2 or 3, wherein the thickness of the first pad electrode is thinner than the thickness of each of the second ground electrode and the third ground electrode in the thickness direction of the multilayer substrate.

5. A multilayer substrate as claimed in any one of claims 1 to 4, wherein, in a plan view from the thickness direction of the laminated substrate, the space contains the first pad electrode, and an insulating layer among the plurality of insulating layers on which the first pad electrode is arranged has a recess surrounding the first pad electrode in a plan view from the thickness direction of the laminated substrate, and the internal space of the recess doubles as part of the space.

6. The multilayer board according to any one of claims 1 to 5, wherein the material of each of the plurality of insulating layers includes a thermoplastic resin.

7. A multilayer substrate as claimed in any one of claims 2 to 4, wherein the plurality of insulating layers include a first insulating layer having the conductor pattern portion disposed on a main surface facing the ground electrode, and a second insulating layer facing the main surface of the first insulating layer, and the laminated substrate further has an adhesive layer located between the first insulating layer and the second insulating layer, and the thickness of a portion of the adhesive layer interposed between the second ground electrode and the second insulating layer and the thickness of a portion of the adhesive layer interposed between the third ground electrode and the second insulating layer are each thinner than the thickness of a portion interposed between the first insulating layer and the second insulating layer.

8. The multilayer substrate according to any one of claims 1 to 7, further comprising a space that exposes within the laminate substrate at least a portion of a main surface of the signal line that faces the ground electrode.

9. A multilayer substrate according to any one of claims 1 to 8, further comprising: a first resist layer having an opening for exposing the second pad electrode and covering the first main surface of the laminated substrate; and a second resist layer covering the second main surface of the laminated substrate and the ground electrode.

10. The multilayer substrate according to any one of claims 1 to 9, wherein the plurality of insulating layers includes an insulating layer that covers the first main surface of the multilayer substrate and the second pad electrode.

11. The multilayer substrate according to any one of claims 1 to 9, comprising two second pad electrodes, one of which is a radiation electrode of an antenna.

12. A multilayer substrate module comprising: a multilayer substrate according to any one of claims 1 to 11; and a connector connected to the second pad electrode of the multilayer substrate.

13. An electronic device comprising: the multilayer substrate module according to claim 12; and a housing that houses the multilayer substrate module.

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