Semiconductor device and power conversion device

Abstract

The present invention suppresses breakdown voltage lowering in a semiconductor device. Provided is a semiconductor device comprising a drift layer, a diffusion region, a top electrode, and a bottom electrode. In an element region, a source region of a first conductivity type, an element region trench, an element region gate electrode, and an element unit sidewall base region are provided. In a boundary region, a boundary region trench and a boundary region gate electrode are provided. In a termination region, at least one termination region trench is provided to surround the boundary region in a plan view while also reaching into the interior of the drift layer from the top of the diffusion region.

Description

Semiconductor device and power conversion device

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] A semiconductor device using a silicon carbide (SiC) substrate (hereinafter referred to as an "SiC semiconductor device") has superior voltage resistance and heat resistance compared to a semiconductor device using a silicon (Si) substrate (hereinafter referred to as an "Si semiconductor device").

[0003] In order to enable semiconductor devices to have high breakdown voltage, low loss, or be used in high-temperature environments, SiC semiconductor devices have conventionally been applied to power semiconductor devices such as metal-oxide-semiconductor field-effect transistors (in other words, MOSFETs) or insulated gate bipolar transistors (in other words, IGBTs).

[0004] SiC has a higher breakdown field strength than Si. Therefore, the SiC semiconductor device can have a thinner breakdown voltage layer (drift layer) than a Si semiconductor device to achieve the same breakdown voltage. Furthermore, the SiC semiconductor device can have a higher impurity doping amount in the breakdown voltage layer than a Si semiconductor device.

[0005] For these reasons, SiC semiconductor devices have a significantly smaller on-resistance than Si semiconductor devices. For example, the on-resistance of a SiC-MOSFET with a breakdown voltage of 1 kV or more and 1.2 kV or less is 5 mΩcm. ２ This is less than half the value of a Si-MOSFET or Si-IGBT with the same breakdown voltage.

[0006] It is expected that the majority of Si-IGBTs used as inverter components will be replaced by SiC semiconductor devices in the future, due to reductions in manufacturing costs, improvements in process technology, and other performance improvements.Currently, trench-gate SiC-MOSFETs or SiC-IGBTs are being developed to reduce losses during current flow in SiC semiconductor devices.

[0007] A power semiconductor device is divided into an element region that conducts current and a termination region that maintains the breakdown voltage. The termination region has the function of maintaining the breakdown voltage in the depth direction of the semiconductor device's substrate and in the direction along the main surface of the substrate.

[0008] However, in trench gate SiC-MOSFETs or SiC-IGBTs, the depletion layer in the termination region does not expand quickly, which can cause an electric field to concentrate between the element region and the termination region, resulting in a decrease in breakdown voltage.

[0009] In contrast to this, for example, in Patent Document 1, a p-type diffusion layer is formed in the termination region so as to surround the trench, thereby increasing the rate at which the termination region is depleted and distributing the potential evenly throughout the termination region, thereby improving the breakdown voltage.

[0010] JP 2015-126086 A

[0011] In trench-gate SiC-MOSFETs or SiC-IGBTs, current flows in the element region and the breakdown voltage is maintained in the termination region. In the element region, the potential along the main surface is constant, while in the termination region, the potential along the main surface is gradually reduced toward the chip edge.

[0012] An electric field tends to concentrate at the boundary between the element region and the termination region where the potential in the direction along the main surface begins to decrease, causing a decrease in breakdown voltage.

[0013] Furthermore, as shown in Patent Document 1, when the element region and termination region, which are the current path, are adjacent to each other, the area with a high impact ionization rate and the area where the current is concentrated are adjacent to each other. The greater the number of electron or hole current carriers and the stronger the electric field, the more likely avalanche breakdown occurs, and the lower the breakdown voltage. Therefore, when the element region and termination region are adjacent to each other, there is a problem of a lower breakdown voltage.

[0014] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for suppressing a decrease in the breakdown voltage of a semiconductor device.

[0015] A semiconductor device according to a first aspect of the technology disclosed in the present specification includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on an upper surface of the semiconductor substrate, a diffusion region of a second conductivity type formed in a surface layer of the drift layer, an upper surface electrode formed on the upper surface of the drift layer, and a lower surface electrode formed on a lower surface of the semiconductor substrate, wherein a region in which a switching element that switches between the upper surface electrode and the lower surface electrode is formed is defined as an element region, a region surrounding the element region in a planar view is defined as a boundary region, and a region surrounding the boundary region in a planar view is defined as a termination region, the upper surface electrode overlaps only the element region and the boundary region in a planar view, and a source of the first conductivity type partially formed in a surface layer of the diffusion region in the element region, the source region includes a source / drain region, at least one element region trench extending from an upper surface of the source region to the interior of the drift layer, an element region gate electrode surrounded by a gate insulating film inside the element region trench, and an element portion sidewall base region of a second conductivity type formed on a sidewall of the element region trench; in the boundary region, at least one boundary region trench extending from an upper surface of the diffusion region to the interior of the drift layer while surrounding the element region in a planar view, and a boundary region gate electrode surrounded by the gate insulating film inside the boundary region trench; and in the termination region, at least one termination region trench extending from the upper surface of the diffusion region to the interior of the drift layer while surrounding the boundary region in a planar view.

[0016] According to at least the first aspect of the technology disclosed in the present specification, the element region where current flows easily and the termination region where electric field is concentrated are separated by a boundary region, thereby increasing the distance between the current concentration point and the electric field concentration point, thereby increasing the breakdown voltage of the semiconductor device.

[0017] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below.

[0018] FIG. 1 is a plan view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing an example of the configuration of the A-B cross section shown in FIG. 1. FIG. 3 is a plan view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing an example of the configuration of a cross section different from the A-B cross section shown in FIG. 1. FIG. 5 is a diagram showing an example of the spread of a potential difference in the structure shown in FIG. 2. FIG. 6 is a diagram showing an example of a current flow region and its direction, and a location where electric field concentration or impact ionization rate is high in the structure shown in FIG. 2. FIG. 7 is a flowchart showing an example of a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 8 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 9 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 10 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 11 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 12 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 13 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 14 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 15 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 16 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 17 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 18 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 19 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 20 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 21 is a plan view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 22 is a cross-sectional view illustrating an example of the configuration of the CD cross section shown in FIG. 21. FIG. 23 is a cross-sectional view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 24 is a cross-sectional view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 25 is a cross-sectional view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment.FIG. 26 is a diagram showing an example of a current flow region and its direction, and a location where electric field concentration or impact ionization rate is increased in the structure shown in FIG. 25 . FIG. 27 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 28 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 29 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 30 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 31 is a diagram showing an example of a current flow region and its direction, and a location where electric field concentration or impact ionization rate is increased in the structure shown in FIG. 29 . FIG. 32 is a cross-sectional view showing a modified example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 33 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 34 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 35 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 36 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 37 is a plan view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 38 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 39 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 40 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 41 is a cross-sectional view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 42 is a cross-sectional view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 43 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 44 is a plan view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 45 is a cross-sectional view illustrating an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 46 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 47 is a cross-sectional view illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 48 is a cross-sectional view illustrating a modified configuration of a SiC semiconductor device according to an embodiment. FIG. 49 is a cross-sectional view illustrating a modified configuration of a SiC semiconductor device according to an embodiment.FIG. 50 is a conceptual diagram showing an example of the configuration of a power conversion system including a power conversion apparatus according to an embodiment. FIG. 51 is a diagram showing an example of the spread of a potential difference when the impurity concentration of the p-type boundary portion sidewall base region is the same as that of the p-type element portion sidewall base region. FIG. 52 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 53 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 54 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 55 is a cross-sectional view showing a modified example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 56 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 57 is a cross-sectional view for illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 58 is a cross-sectional view for illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 59 is a cross-sectional view for illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 60 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 61 is a cross-sectional view for illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 62 is a cross-sectional view for illustrating a manufacturing flow of a SiC semiconductor device according to an embodiment. FIG. 63 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 64 is a cross-sectional view showing a modified example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 65 is a diagram showing an example of the spread of the potential difference in the structure shown in FIG.

[0019] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0020] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0021] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0022] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0023] Furthermore, in the description of this specification, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to make it easier to understand the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0024] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0025] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude the interposition of another component "C" between A and B.

[0026] First Embodiment A semiconductor device according to the present embodiment and a semiconductor device therefor will be described below.

[0027] 1 is a plan view showing an example of the configuration of a SiC semiconductor device according to this embodiment. Shown in FIG. 1 is an example of a SiC-n-type MOSFET with a trench gate structure, which shows an element region gate electrode 2, a boundary region gate electrode 3, and a termination region gate electrode 4 of the main part of the SiC semiconductor device.

[0028] Although a SiC-n type MOSFET will be described below, the present invention is also applicable to a SiC-p type MOSFET or a SiC-IGBT.

[0029] Fig. 2 is a cross-sectional view showing an example of the configuration of the A-B cross section shown in Fig. 1. As shown in the example in Fig. 2, an n-type drift layer 24 is formed on the upper surface of an n-type SiC substrate 1. Then, a p-type base region 8 is formed in the surface layer of the n-type drift layer 24.

[0030] An n-type source region 7 is formed in a part of the surface layer of the p-type base region 8. Furthermore, a p-type surface base region 18 is formed in a part of the surface layer of the p-type base region 8.

[0031] In the element region 14 where the switching element is formed, a trench 1000 is formed from the upper surface of the n-type source region 7 to the inside of the n-type drift layer 24, and in the boundary region 15 and the termination region 16, a trench 1000 is formed from the upper surface of the p-type surface base region 18 to the inside of the n-type drift layer 24. A p-type bottom base region 10 is formed at the bottom of the trench 1000. The boundary region 15 is a region that surrounds the element region 14 in a planar view. The termination region 16 is a region that surrounds the boundary region 15 in a planar view.

[0032] In the element region 14, a p-type element sidewall base region 9 is formed on the sidewall of the trench 1000. In the boundary region 15, a p-type boundary sidewall base region 22 is formed on the sidewall of the trench 1000. In the termination region 16, a p-type termination sidewall base region 12 is formed on the sidewall of the trench 1000.

[0033] In the element region 14, an element region gate electrode 2 is formed within the trench 1000 and surrounded by the gate insulating film 11. In the boundary region 15, a boundary region gate electrode 3 is formed within the trench 1000 and surrounded by the gate insulating film 11. In the termination region 16, a termination region gate electrode 4 is formed within the trench 1000 and surrounded by the gate insulating film 11.

[0034] An interlayer insulating film 17 is formed to cover the element region gate electrode 2, the boundary region gate electrode 3 and the termination region gate electrode 4, respectively.

[0035] In the element region 14 and the boundary region 15 , the source electrode 5 is formed so as to cover the interlayer insulating film 17 .

[0036] Here, the element region 14 is a region extending from the sidewall of the boundary region gate electrode 3 to the boundary of the p-type element portion sidewall base region 9 on the element region 14 side. The boundary region 15 is a region between the element region 14 and the termination region 16, and extends to the center line of the termination region gate electrode 4 on the boundary region 15 side. The termination region 16 is also a region extending to the edge of the chip.

[0037] On the other hand, a drain electrode 13 is formed on the lower surface of the n-type SiC substrate 1. The drain electrode 13 covers the entire lower surface of the n-type SiC substrate 1. The drain electrode 13 is in ohmic contact with the lower surface of the n-type SiC substrate 1.

[0038] 1, all electrodes of the element region gate electrode 2 are made of continuous electrodes and are electrically at the same potential. All electrodes of the boundary region gate electrode 3 are also made of continuous electrodes and are electrically at the same potential. On the other hand, each electrode of the termination region gate electrode 4 is independent and electrically insulated.

[0039] In the element region 14, an n-type source region 7, a p-type surface base region 18, a p-type base region 8, a p-type element sidewall base region 9, and a p-type bottom base region 10 are formed.

[0040] The n-type source region 7 is an n-type region containing a high concentration of n-type impurities and is partially formed in an upper layer of the n-type drift layer 24. The n-type source region 7 is ohmically connected to the source electrode 5.

[0041] The p-type surface base region 18 is a p-type region containing a high concentration of p-type impurities. The p-type surface base region 18 is formed in an upper layer of the n-type drift layer 24 at a position in the element region 14 where the n-type source region 7 is not formed. The p-type surface base region 18 is ohmically connected to the source electrode 5 in the element region 14. The p-type surface base region 18 is formed in an upper layer of the n-type drift layer 24 in the termination region 16. The upper surface of the p-type surface base region 18 in the termination region 16 is covered with the interlayer insulating film 17.

[0042] The p-type base region 8 is a p-type region containing a low concentration of p-type semiconductor impurities. The p-type impurity concentration of the p-type base region 8 is lower than the p-type impurity concentration of the p-type surface base region 18. The p-type base region 8 is formed on the underside of the n-type source region 7 and the p-type surface base region 18, and is in contact with these regions.

[0043] 3 is a plan view showing an example of the configuration of a SiC semiconductor device according to this embodiment, in which only an n-type SiC substrate 1, an element region trench 19, a boundary region trench 20, and a termination region trench 21 are shown, and other components are omitted as appropriate.

[0044] As shown in the example of Fig. 3, n-type SiC substrate 1 is surrounded by termination region trenches 21. Therefore, the p-type base regions 8 in termination region 16 shown in Fig. 2 are all separated by termination region trenches 21, and the p-type base regions 8 between termination region trenches 21 are not connected to each other and exist independently.

[0045] The p-type bottom base region 10 is a p-type region containing a high concentration of p-type impurities. The impurity concentration of the p-type bottom base region 10 is higher than the p-type impurity concentration of the p-type base region 8. The p-type bottom base region 10 is formed below the trench bottoms of the gate insulating film 11 present in the element region trench 19, the boundary region trench 20, and the termination region trench 21, and is in contact with these trench bottoms.

[0046] The p-type element sidewall base region 9 is a p-type region. The impurity concentration of the p-type element sidewall base region 9 is higher than the p-type impurity concentration of the p-type base region 8.

[0047] P-type bottom base region 10 at the bottom of the trench prevents an excessive electric field from being applied to gate insulating film 11, thereby improving the breakdown voltage of the gate oxide film. Furthermore, the formation of p-type bottom base region 10 at the bottom of termination region trench 21 in termination region 16 produces an effect similar to that of a guard ring, which reduces the electric field in the surface direction of termination region trench 21, thereby improving the breakdown voltage of the chip.

[0048] Fig. 4 is a cross-sectional view showing an example of a cross-sectional configuration different from the A-B cross-section shown in Fig. 1. As shown in the example in Fig. 4, in a part of the chip, there may be an area on the side wall of the element region trench 19 in the element region 14 where the p-type element portion sidewall base region 9 does not exist.

[0049] The p-type boundary sidewall base regions 22 are p-type regions. The p-type boundary sidewall base regions 22 are formed on both sidewalls of all boundary region trenches 20 in the boundary region 15. The boundary region gate electrode 3 is short-circuited to the source electrode 5 and has the same potential as the source electrode 5.

[0050] The p-type termination sidewall base region 12 is a p-type region. The p-type termination sidewall base region 12 is formed on both sidewalls of all termination region trenches 21 in the termination region 16. The impurity concentration of the p-type termination sidewall base region 12 is lower than the p-type impurity concentration of the p-type base region 8. In other words, the impurity concentration of the p-type termination sidewall base region 12 is lower than the impurity concentration of the p-type element portion sidewall base region 9.

[0051] 2 shows three element region trenches 19, four boundary region trenches 20, and seven termination region trenches 21. However, the number of each trench may be different from the number shown in FIG. 2 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0052] The planar shape of the trench at the chip corner has a curvature that increases toward the chip periphery, as shown in Figure 1. By increasing the curvature of the chip corner of the trench in the termination region, electric field concentration can be suppressed and the breakdown voltage can be improved.

[0053] <Method for Manufacturing a Semiconductor Device> Next, a method for manufacturing a SiC semiconductor device according to this embodiment will be described. Fig. 7 is a flowchart showing an example of a manufacturing flow of a SiC semiconductor device according to this embodiment. The SiC semiconductor device according to this embodiment is manufactured according to the procedure shown in Fig. 7. Figs. 8 to 20 are cross-sectional views for explaining the manufacturing flow of a SiC semiconductor device according to this embodiment.

[0054] First, as shown in an example in FIG. 8 , an n-type drift layer 24 made of n-type SiC is formed as an epitaxial film on a first main surface (hereinafter referred to as the upper surface) of an n-type SiC substrate 1 (step ST1 shown in FIG. 7 ).

[0055] 9, impurities are ion-implanted into the upper surface of n-type drift layer 24 to form p-type base regions 8 in the surface layer of n-type drift layer 24 (step ST2 shown in FIG. 7). If there are areas on the semiconductor chip (hereinafter sometimes simply referred to as chip) where ion implantation is not desired, a mask (not shown) made of resist or the like may be formed, and then impurities may be ion-implanted into the upper surface of n-type drift layer 24 to form p-type base regions 8. Examples of p-type impurities include boron (B) and aluminum (Al).

[0056] Next, as shown in an example in Figure 10, impurities are ion-implanted into the surface layer of the p-type base region 8 to partially form the n-type source region 7 (step ST3 shown in Figure 7). If there are areas on the chip where the ion implantation is not desired, the ion implantation may be performed after forming a mask (not shown) made of resist or the like. Examples of n-type impurities include phosphorus (P) and nitrogen (N).

[0057] Next, as shown in an example in FIG. 10, a mask (not shown here) made of resist or the like is formed, and then ions are implanted into the surface layer of the p-type base region 8 to partially form a p-type surface base region 18 in order to reduce the surface resistance.

[0058] 11, a mask is formed using trench resist 25, and then trenches 1000 are formed by dry etching using plasma or the like (step ST4 shown in FIG. 7). Here, trench 1000 in element region 14 corresponds to element region trench 19, trench 1000 in boundary region 15 corresponds to boundary region trench 20, and trench 1000 in termination region 16 corresponds to termination region trench 21.

[0059] If it is not possible to form a resist mask sufficient for forming trench 1000, a deeper trench can be formed by depositing an oxide film using, for example, TEOS as a raw material on the upper surface of n-type source region 7 and the upper surface of p-type surface base region 18 shown in FIG. 11 and then dry-etching the oxide film using a resist mask.

[0060] 12, using the trench resist 25 as it is, impurities such as boron (B) or aluminum (Al) are implanted into the bottom of the trench 1000. Then, a p-type bottom base region 10 is formed at the bottom of the trench 1000 to relieve the electric field applied to that location.

[0061] 13, a diffusion layer is formed on the sidewall of trench 1000 by ion implantation (step ST5 shown in FIG. 7). After forming a mask using resist 26 for the element portion sidewall base region, ions are implanted obliquely into the sidewall of trench 1000 to form p-type element portion sidewall base region 9.

[0062] 14, a mask pattern may be used that covers the entire element region 14 within the chip. In this case, the device structure shown in FIG. 4 is finally completed.

[0063] Furthermore, as shown in FIG. 15, ions may be implanted into the sidewalls on both sides of a trench 1000 in a part of the chip, and p-type element portion sidewall base regions 9 may be formed on both sides of the trench 1000.

[0064] Next, as shown in an example in Figure 16, after forming a mask using resist 27 for the boundary sidewall base region, ions are implanted obliquely into the sidewall of the trench 1000 to form a p-type boundary sidewall base region 22.

[0065] This ion implantation process results in boundary trench 20 being surrounded by p-type base region 8 , p-type boundary sidewall base region 22 , p-type bottom base region 10 and p-type surface base region 18 .

[0066] Next, as shown in an example in Figure 17, a mask is formed using resist 28 for the termination sidewall base region, and then ions are implanted obliquely into the sidewall of the trench 1000 to form a p-type termination sidewall base region 12.

[0067] This ion implantation process results in termination region trench 21 being surrounded by p-type base region 8 , p-type termination sidewall base region 12 , p-type bottom base region 10 , and p-type surface base region 18 .

[0068] Next, in order to activate the ions implanted up to this point, the semiconductor chip is heat-treated at high temperature using a heat treatment device (not shown), which electrically activates the p-type or n-type ions implanted into the p-type base region 8, the n-type source region 7, the p-type element portion sidewall base region 9, the p-type bottom base region 10, the p-type surface base region 18, the p-type boundary portion sidewall base region 22, and the p-type termination portion sidewall base region 12.

[0069] Next, as shown in FIG. 18 , a gate insulating film 11 is formed on the surface of the n-type drift layer 24 (including the upper surfaces of the n-type source regions 7, the upper surfaces of the p-type surface base regions 18, and the inside of the trenches 1000) by a deposition method such as thermal oxidation or chemical vapor deposition (step ST6 shown in FIG. 7 ).

[0070] Before forming the gate insulating film 11, oxidation may be performed by thermal oxidation to remove plasma damage that occurs when the trench 1000 is formed.

[0071] Next, a gate electrode is formed so as to fill the trench 1000 surrounded by the gate insulating film 11 (step ST7 shown in FIG. 7). Then, after forming a mask (not shown) made of resist or the like, the gate electrode is patterned by removing excess portions of the gate electrode, as shown in the example of FIG. 19. An element region gate electrode 2 is formed in the element region, a boundary region gate electrode 3 is formed in the boundary region, and a termination region gate electrode 4 is formed in the termination region.

[0072] As shown in the example of Figure 1, all of the element region gate electrodes 2 are connected continuously on the upper surface of the chip. Similarly, the boundary region gate electrodes 3 are also connected continuously on the upper surface of the chip. On the other hand, as shown in the example of Figure 1, the termination region gate electrodes 4 are each separated and exist independently on the circumference.

[0073] The gate electrode is etched by a highly anisotropic etching method such as dry etching using plasma. By performing the highly anisotropic etching, the gate electrode is formed only in the opening of the resist in the trench 1000.

[0074] 20, an interlayer insulating film 17 is formed by chemical vapor deposition (CVD), and then patterned by photolithography and etching to remove the remaining portions mainly in the element region 14 and boundary region 15 (step ST8 shown in FIG. 7). By patterning, the n-type source region 7 and a part of the p-type surface base region 18 in the element region 14 and boundary region 15 are exposed.

[0075] The corners of the interlayer insulating film 17 can be rounded by introducing impurities such as B (boron) or P (phosphorus). The interlayer insulating film 17 is formed by deposition and patterning, and the deposited material is, for example, silicon nitride (SixNy) or silicon oxide (SiO ２ ) and the thickness of the interlayer insulating film 17 is preferably 0.5 μm or more and 2.0 μm or less.

[0076] Next, a source electrode 5 is formed using a barrier metal made of aluminum or an aluminum alloy made of aluminum and silicon, an aluminum alloy made of aluminum and copper, or nickel, etc., and a titanium compound such as titanium or titanium nitride (TiN) as appropriate (step ST9 shown in FIG. 7).

[0077] 2, the source electrode 5 is not only in contact with the upper surface of the n-type SiC substrate 1, but is also patterned using a mask (not shown) made of resist or the like so as to be in contact with the upper surface of the boundary region gate electrode 3. Here, the boundary region gate electrode 3 and the source electrode 5 are in ohmic contact.

[0078] 21 is a plan view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which is an example of a SiC-n-type MOSFET with a trench gate structure, and shows an element region gate electrode 2, a boundary region gate electrode 3, and a termination region gate electrode 4 of the main part of the SiC semiconductor device.

[0079] Fig. 22 is a cross-sectional view showing an example of the configuration of the CD cross section shown in Fig. 21. As shown in the example in Fig. 22, the boundary region gate electrode 3 and the source electrode 5 are connected on the upper surface.

[0080] As a result, the potential of the source electrode 5 becomes equal to the potential of the boundary region gate electrode 3. When the potential of the boundary region gate electrode 3 becomes equal to the potential of the source electrode 5, the charge on the upper surface of the boundary region 15 is more likely to escape from the source electrode 5 due to capacitive coupling, and the potential of the upper surface of the boundary region 15 is less likely to deviate from the source potential even during switching operations, thereby suppressing a decrease in breakdown voltage during switching operations.

[0081] Next, as necessary, a second main surface (hereinafter referred to as the lower surface) of the n-type SiC substrate 1 of the SiC semiconductor device, which is opposite to the first main surface, is machined using a grinding wheel to thin the n-type SiC substrate 1 (step ST10 shown in FIG. 7 ).

[0082] Next, a nickel film of about 600 nm is formed on the lower surface of the n-type SiC substrate 1 by appropriately using a sputtering method or the like, thereby forming the drain electrode 13 (step ST11 shown in FIG. 7).

[0083] In this way, a SiC semiconductor device such as the one shown in Fig. 2 is completed. Regarding the nickel surface, oxidation of the outermost surface reduces the wettability of the solder alloy with nickel, resulting in poor bonding during chip bonding. Therefore, a metal with poor reactivity with the outside, such as gold or silver, can be used as a protective film on the nickel surface, and a laminated film consisting of nickel and gold or silver can be used as the drain electrode 13.

[0084] <Operation of the Semiconductor Device> Next, the operation of the semiconductor device according to this embodiment will be described. When the semiconductor device is operated, a voltage is applied between the drain electrode 13 and the source electrode 5 so that the drain electrode 13 is positive. Furthermore, a gate-on voltage is applied to the element region gate electrode 2, turning on the MOSFET in the element region 14. That is, a channel is formed at the interface between the gate insulating film 11 and the p-type base region 8 at a position facing the element region gate electrode 2, and electrons flow from the source electrode 5 through the n-type source region 7, the channel, the n-type drift layer 24, and the n-type SiC substrate 1 toward the drain electrode 13.

[0085] 2 , when a p-type element portion sidewall base region 9 is formed on the side wall of the element region gate electrode 2 in the element region 14, no channel is formed on the side where the p-type element portion sidewall base region 9 is present. Therefore, a channel is formed only on the side where the p-type element portion sidewall base region 9 is not present, and electron current flows only on one side of the element region trench 19.

[0086] As shown in the example in Figure 4, when there is no p-type element portion sidewall base region 9 on either sidewall of the element region gate electrode 2, a channel is formed on both sidewalls of the element region gate electrode 2, and electron current flows on both sides of the element region trench 19.

[0087] When the application of the gate-on voltage to the element region gate electrode 2 is stopped, the channel disappears and the MOSFET is turned off. When the MOSFET is turned off, a depletion layer spreads from the pn junction at the boundary between the p-type base region 8 and the n-type drift layer 24 in the range covered by the source electrode 5 toward the drain electrode 13. In addition, a potential difference occurs in the depletion layer according to the potential difference between the drain electrode 13 and the source electrode 5.

[0088] Figure 5 is a diagram illustrating an example of the potential difference spreading in the structure shown in Figure 2. In the example of Figure 5, an example of equipotential lines 1002 is shown, with the source electrode 5 at a low potential (e.g., 0 V) ​​and the drain electrode 13 at a high potential.

[0089] 5 , the equipotential lines pass through the gate insulating film 11 in the termination region 16, where the source electrode 5 is not present, and penetrate into the interlayer insulating film 17. Because the source electrode 5 is present in the element region 14 and the boundary region 15, the top surface of the n-type SiC substrate 1 in the element region 14 and the boundary region 15 has the same potential as the source potential. Therefore, a potential difference in the direction perpendicular to the direction connecting the source electrode 5 and the drain electrode 13 (in other words, a potential difference in the direction connecting the element region 14 and the termination region 16) is generated in the termination region 16.

[0090] Fig. 6 is a diagram showing examples of current flow regions and their directions, and locations where the electric field concentration or impact ionization rate is increased in the structure shown in Fig. 2. In the example of Fig. 6, examples of equipotential lines 1002 and current flow directions 1004 are shown.

[0091] 6 , when a gate-on voltage is applied, a current flows through the element region 14 (see current flow direction 1004). In contrast, the impact ionization rate increases at the boundary between the boundary region 15, where electric field concentration is likely to occur, and the termination region 16. This boundary region is referred to as a high-impact ionization region 23.

[0092] As can be seen from the density of the equipotential lines 1002 shown in Figure 6, electric field concentration is likely to occur and the impact ionization rate is likely to become high at the boundary portion (high impact ionization region 23) between the boundary region 15 and the termination region 16 where a potential difference begins to occur in a direction perpendicular to the direction connecting the source electrode 5 and the drain electrode 13 (in other words, a potential difference in the direction connecting the element region 14 and the termination region 16).

[0093] According to this embodiment, a boundary region 15 is provided between an element region 14 through which current flows when a gate-on voltage is applied and a termination region 16 that reduces the potential difference in a direction perpendicular to the direction connecting the source electrode 5 and the drain electrode 13.

[0094] Therefore, it is possible to separate the current concentration area from the area where the impact ionization rate is high, and it is possible to maintain a higher breakdown voltage than conventional power devices.

[0095] In the first embodiment described above, when the impurity concentration of p-type boundary sidewall base region 22 is the same as that of p-type element portion sidewall base region 9, equipotential lines do not escape at the end of boundary region 15, and the electric field in boundary region 15 can be alleviated accordingly, thereby increasing the breakdown voltage of the semiconductor device.

[0096] On the other hand, if the impurity concentration of the p-type boundary sidewall base region 22 is the same as that of the p-type termination sidewall base region 12, the equipotential lines are eliminated at the end of the boundary region 15, thereby shortening the distance of the termination region 16 and enabling the chip size to be reduced.

[0097] 51 is a diagram showing an example of the spread of the potential difference when the impurity concentration of the p-type boundary sidewall base region 22 is the same as that of the p-type element portion sidewall base region 9. Unlike the case shown in FIG. 5 , the equipotential line 1002 does not disappear even at the boundary between the boundary region 15 and the termination region 16.

[0098] Second Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0099] <Regarding the Configuration of the Semiconductor Device> In the present embodiment, compared to the first embodiment, a structure is shown in which the spacing between trenches 1000 in boundary region 15 and termination region 16 is narrower than the spacing between trenches 1000 in element region 14. This structure can improve the breakdown voltage of the SiC semiconductor device.

[0100] 23 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0101] In the structure shown in FIG. 23, if the distance between adjacent trenches 1000 in the element region 14 is W1 and the distance between adjacent trenches 1000 in the boundary region 15 and the termination region 16 is W2, then W2 < W1.

[0102] 23, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and 14 termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in FIG. 23 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more the number of element region trenches 19 is increased, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 is increased, the more the breakdown voltage of the chip can be improved.

[0103] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, and ST3 shown in FIG. 7 are the same in this embodiment.

[0104] In step ST4 shown in FIG. 7, a different mask from that shown in the first embodiment is used to form trench 1000 so that W2<W1.

[0105] The steps from step ST5 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 23 is completed.

[0106] In the SiC semiconductor device according to this embodiment, the distance (W2) between the element region trench 19 and the boundary region 20 located at the boundary between the element region 14 and the boundary region 15 is narrower than the distance (W1) between the element region trenches 19 in the element region 14. In addition, the distance (W2) between the boundary region trench 20 and the termination region trench 21 located at the boundary between the boundary region 15 and the termination region 16 is narrower than the distance (W1) between the element region trenches 19 in the element region 14.

[0107] As described above, the trench pitch at the boundaries of each region where electric fields are likely to concentrate (the boundary between the element region 14 and the boundary region 15, and the boundary between the boundary region 15 and the termination region 16) is shorter than W1, so that the concentration of electric fields in the SiC semiconductor device can be alleviated while increasing its breakdown voltage.

[0108] Third Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0109] <Regarding the Configuration of the Semiconductor Device> In the present embodiment, compared to the first embodiment, a structure is shown in which the spacing between trenches 1000 in termination region 16 gradually increases toward the outside of termination region 16. This structure allows the electric field to be alleviated over a short distance, and the overall width of termination region 16 can be reduced. Therefore, the chip size can be reduced while maintaining the breakdown voltage of the SiC semiconductor device, thereby reducing the manufacturing cost of the semiconductor device.

[0110] 24 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0111] 24 , if the distance between adjacent trenches 1000 in element region 14 and boundary region 15 is W1, and the distances between adjacent trenches 1000 in termination region 16 are Wt1, Wt2, Wt3, and Wt4, then W1≦Wt1≦Wt2≦Wt3≦Wt4 holds. Here, Wt1, Wt2, Wt3, and Wt4 are set in this order toward the outside of termination region 16 (in other words, toward the side of termination region 16 farther from element region 14).

[0112] 24, there are three element region trenches 19 in element region 14, four boundary region trenches 20 in boundary region 15, and four termination region trenches 21 in termination region 16. However, the number of each trench may be different from the number shown in FIG. 24 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0113] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, and ST3 shown in FIG. 7 are the same in this embodiment.

[0114] In step ST4 shown in FIG. 7, a different mask from that shown in the first embodiment is used to form trench 1000 so that W1≦Wt1≦Wt2≦Wt3≦Wt4.

[0115] The steps from step ST5 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 24 is completed.

[0116] In the SiC semiconductor device according to this embodiment, the distance between termination region trenches 21 increases toward the outside of termination region 16 (in other words, toward the side of termination region 16 farther from element region 14).

[0117] According to the above structure, the electric field can be made large even in termination region trench 21, which is located away from element region 14 and where the generated electric field is small and where a potential difference is unlikely to occur. Therefore, the breakdown voltage of the SiC semiconductor device can be maintained with termination region 16 having a small width.

[0118] As described above, the chip size can be reduced while maintaining the breakdown voltage of the SiC semiconductor device, thereby reducing the manufacturing cost of the semiconductor device.

[0119] Fourth Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0120] <Regarding the Configuration of the Semiconductor Device> In the present embodiment, a structure is shown in which the width of the p-type bottom base region is longer in boundary region 15 and termination region 16 than in the first embodiment. This structure can improve the breakdown voltage of the SiC semiconductor device.

[0121] 25 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0122] 25 , when the width of p-type bottom base region 10 in element region 14 is L1 and the width of p-type bottom base region 10A in boundary region 15 and termination region 16 is L2, L1<L2. Alternatively, the width of p-type bottom base region 10 in boundary region 15 may be L1, and only the width of p-type bottom base region 10A in termination region 16 may be L2, resulting in a structure that suppresses the electric field only in termination region 16 (not shown here).

[0123] 25, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and five termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in FIG. 23 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0124] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, and ST3 shown in FIG. 7 are the same in this embodiment.

[0125] In step ST4 shown in FIG. 7, a different mask from that shown in the first embodiment is used to form trench 1000 (corresponding to L1) and trench 1000A (corresponding to L2) so that L1<L2.

[0126] 7 and subsequent steps are the same in this embodiment, except that p-type bottom base region 10A is formed corresponding to trench 1000A, and boundary region gate electrode 3A and termination region gate electrode 4A corresponding to the width of trench 1000A are formed. In this way, a SiC semiconductor device such as the one shown in FIG. 25 is completed.

[0127] In the SiC semiconductor device according to this embodiment, L1<L2 holds true. In such a structure, in p-type bottom base region 10A in boundary region 15 and termination region 16, equipotential lines 1002 maintain the same potential over a width of L2 along p-type bottom base region 10A in a direction perpendicular to the direction connecting source electrode 5 and drain electrode 13 (in other words, the direction connecting element region 14 and termination region 16), as shown in the example of FIG.

[0128] This makes it possible to alleviate the concentration of the electric field in boundary region 15 and termination region 16, thereby increasing the breakdown voltage of the SiC semiconductor device. Fig. 26 is a diagram showing an example of a current flow region and its direction, and a location where the electric field concentration or impact ionization rate is increased in the structure shown in Fig. 25. In the example of Fig. 26, an example of equipotential lines 1002 is shown.

[0129] Fifth Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0130] <Regarding the Configuration of the Semiconductor Device> In this embodiment, compared to the fourth embodiment, a structure is shown in which the width of the p-type bottom base region in termination region 16 gradually decreases toward the outside of termination region 16. This structure allows the electric field to be alleviated over a short distance, and the width of the termination region to be shortened. Therefore, the chip size can be reduced while maintaining the breakdown voltage, thereby reducing the manufacturing cost of the SiC semiconductor device.

[0131] 27 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0132] In the structure shown in the example of Figure 27, if the width of the p-type bottom base region 10 in the element region 14 is L1, the width of the p-type bottom base region 10A in the boundary region 15 is L2, and the widths of the p-type bottom base region 10B in the termination region 16 are Lt1 to Lt6, then L2 ≧ Lt1 ≧ Lt2 ≧ Lt3 ≧ Lt4 ≧ Lt5 ≧ Lt6 ≧ L1.

[0133] 27, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and six termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in FIG. 27 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0134] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, and ST3 shown in FIG. 7 are the same in this embodiment.

[0135] In step ST4 shown in FIG. 7, a different mask from that shown in the first embodiment is used to form trench 1000 (corresponding to L1), trench 1000A (corresponding to L2), and trench 1000B (corresponding to Lt1, Lt2, Lt3, Lt4, and Lt5) so that L2≧Lt1≧Lt2≧Lt3≧Lt4≧Lt5≧Lt6≧L1.

[0136] 7 and subsequent steps are the same in this embodiment, except that p-type bottom base region 10A and boundary region gate electrode 3A are formed corresponding to trench 1000A, and p-type bottom base region 10B and termination region gate electrode 4B are formed corresponding to trench 1000B. In this way, a SiC semiconductor device such as the one shown in FIG. 27 is completed.

[0137] In the SiC semiconductor device according to this embodiment, L2 ≥ Lt1 ≥ Lt2 ≥ Lt3 ≥ Lt4 ≥ Lt5 ≥ Lt6 ≥ L1 is satisfied. In such a structure, in p-type bottom base region 10A in boundary region 15, equipotential lines 1002 maintain the same potential over a width of L2 along p-type bottom base region 10A in a direction perpendicular to the direction connecting source electrode 5 and drain electrode 13 (in other words, in the direction connecting element region 14 and termination region 16), as shown in the example of FIG.

[0138] As can be seen from the density of the equipotential lines 1002 shown in Figure 6, electric field concentration is likely to occur and the impact ionization rate is likely to become high at the boundary portion (high impact ionization region 23) between the boundary region 15 and the termination region 16 where a potential difference begins to occur in a direction perpendicular to the direction connecting the source electrode 5 and the drain electrode 13 (in other words, a potential difference in the direction connecting the element region 14 and the termination region 16).

[0139] According to this embodiment, the electric field is alleviated by setting the width of p-type bottom base region 10B near the boundary between boundary region 15 and termination region 16 to Lt1. On the other hand, since the electric field is lower outside termination region 16 (in other words, on the side of termination region 16 farther from element region 14), the width of p-type bottom base region 10B is set to Lt6, which is shorter than Lt1.

[0140] This makes it possible to maintain the breakdown voltage of the SiC semiconductor device while shortening the width of termination region 16. This allows the chip size to be reduced, and the manufacturing cost of the semiconductor device to be reduced.

[0141] Sixth Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0142] <Regarding the Configuration of the Semiconductor Device> In comparison with the first embodiment, the present embodiment shows a structure in which p-type termination sidewall base region 12 is not formed in termination region 16. By adopting such a shape, the SiC semiconductor device can be manufactured with fewer manufacturing steps, thereby reducing the manufacturing cost of the SiC semiconductor device.

[0143] 28 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0144] In the structure exemplified in FIG. 28, the p-type termination sidewall base region 12 in the termination region 16 is not formed.

[0145] 28, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and seven termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in Fig. 28 as long as the current capacity or withstand voltage of the designed chip is satisfied. The more the number of element region trenches 19 is increased, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 is increased, the more the withstand voltage of the chip can be improved.

[0146] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, ST3, and ST4 shown in FIG. 7 are the same in this embodiment.

[0147] In step ST5 shown in FIG. 7, unlike the first embodiment, p-type termination sidewall base region 12 is not formed.

[0148] The steps from step ST6 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 28 is completed.

[0149] According to this embodiment, the number of process steps is reduced, and therefore the manufacturing cost of the SiC semiconductor device can be reduced.

[0150] Since the sidewalls of termination region trench 21 in termination region 16 are n-type, an electric field is more likely to concentrate on the trench sidewall in termination region 16 than when p-type termination sidewall base region 12 is formed. For this reason, this embodiment may be combined with the structure shown in the second or fourth embodiment that alleviates the electric field and improves the breakdown voltage (changing the spacing between trenches, changing the trench width).

[0151] Seventh Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0152] <Regarding the Configuration of the Semiconductor Device> In comparison with the first embodiment, the present embodiment shows a structure in which a p-type termination sidewall one-side base region 29 is formed only on one sidewall of termination region trench 21 in termination region 16. This structure can improve the breakdown voltage of the SiC semiconductor device.

[0153] 29 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0154] In the structure exemplified in FIG. 29, a p-type termination sidewall one-side base region 29 is formed only on one side of termination region trench 21 in termination region 16 (in other words, a portion of termination region trench 21).

[0155] 29, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and seven termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in FIG. 29 as long as the current capacity or withstand voltage of the designed chip is satisfied. The more the number of element region trenches 19 is increased, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 is increased, the more the withstand voltage of the chip can be improved.

[0156] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, ST3, and ST4 shown in FIG. 7 are the same in this embodiment.

[0157] 7, unlike the case shown in the first embodiment, p-type termination portion sidewall one-side base region 29 is formed by ion implantation in only one direction, as shown in the example of Fig. 30. Here, Fig. 30 is a cross-sectional view for explaining the manufacturing flow of the SiC semiconductor device according to this embodiment.

[0158] The steps from step ST6 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 29 is completed.

[0159] Here, the p-type termination sidewall one-side base region 29 is a p-type region containing a high concentration of p-type impurities. The impurity concentration of the p-type termination sidewall one-side base region 29 is higher than the p-type impurity concentration of the p-type base region 8. The impurity concentration of the p-type termination sidewall one-side base region 29 may be the same as the p-type impurity concentration of the element portion sidewall base region 9.

[0160] According to this embodiment, one of the sidewalls and bottom of termination region trench 21 in termination region 16 can be surrounded by p-type termination sidewall one-side base region 29, which is a high-concentration p-type impurity region, and p-type bottom base region 10. Therefore, as shown in FIG. 31 , equipotential lines 1002 can extend only from the trench sidewall on the side where the p-type region is not formed. As a result, the spacing between equipotential lines 1002 is increased, suppressing electric field concentration and increasing the breakdown voltage of the SiC semiconductor device. FIG. 31 illustrates equipotential lines in the structure shown in FIG. 29 . This structure suppresses the concentration of equipotential lines at the bottom of the trench at the boundary between boundary region 15 and termination region 16 compared to FIG. 5 (in other words, suppressing the electric field at the bottom of the trench).

[0161] Furthermore, the formation direction of p-type termination sidewall one-side base region 29A may be on the high potential side (outside termination region 16) as shown in Fig. 32. Here, Fig. 32 is a cross-sectional view showing a modified example of the configuration of the SiC semiconductor device according to the present embodiment.

[0162] Eighth Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0163] <Regarding the Configuration of the Semiconductor Device> In comparison with the first embodiment, the present embodiment shows a structure in which an n-type impurity concentration layer is formed at the chip end of termination region 16. This structure can improve the breakdown voltage of the SiC semiconductor device.

[0164] 33 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0165] 33 , an n-type electric-field prevention region 30 is formed at the chip end (outer edge) of termination region 16. In other words, n-type electric-field prevention region 30 is formed in the surface layer of drift layer 24, surrounding all termination region trenches 21 in plan view. The n-type concentration in n-type electric-field prevention region 30 is equal to the n-type concentration in source region 7.

[0166] 33, there are three element region trenches 19 in element region 14, four boundary region trenches 20 in boundary region 15, and seven termination region trenches 21 in termination region 16. However, the number of each trench may be different from the number shown in FIG. 33 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0167] <Method of Manufacturing a Semiconductor Device> The steps up to step ST1 shown in FIG. 7 are the same in this embodiment.

[0168] 7, unlike the case shown in the first embodiment, a mask (not shown here) made of resist or the like is formed, and then impurity ions are implanted to form p-type base region 8 in the region excluding the chip end portion, as shown in the example of Fig. 34. Here, Fig. 34 is a cross-sectional view for explaining the manufacturing flow of the SiC semiconductor device according to this embodiment.

[0169] 7, unlike the case shown in the first embodiment, a mask (not shown here) made of resist or the like is formed, and then impurity ions are implanted to form n-type source regions 7 also at the chip end portions, as shown in the example of Fig. 35. Here, Fig. 35 is a cross-sectional view for explaining the manufacturing flow of the SiC semiconductor device according to this embodiment.

[0170] Next, as shown in an example in Fig. 36, a mask (not shown here) made of resist or the like is formed, and then ion implantation is performed to form a p-type surface base region 18 in order to reduce the surface resistance. At this time, the p-type surface base region 18 is not formed at the chip end. Here, Fig. 36 is a cross-sectional view for explaining the manufacturing flow of the SiC semiconductor device according to this embodiment.

[0171] The steps from step ST4 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 33 is completed.

[0172] According to this embodiment, the end (outer edge) of termination region 16 is surrounded by electric-field spread prevention region 30. Fig. 37 is a plan view showing an example of the configuration of a SiC semiconductor device according to this embodiment. As shown in the example in Fig. 37, electric-field spread prevention region 30 is formed so as to surround the end of the chip.

[0173] When a voltage is applied between the source electrode 5 and the drain electrode 13 with the drain electrode 13 at a higher potential, equipotential lines 1002 are formed as shown in Fig. 5. As the potential difference increases, the electric field expands accordingly.

[0174] 2, if the potential difference is too high, the electric field spreads to the chip edge. If the electric field spreads to the chip edge, the electric field concentrates at the pn junction at the boundary between the p-type base region 8 and the n-type drift layer 24 at the chip edge, which is the edge of the termination region 16, causing a decrease in the breakdown voltage of the SiC semiconductor device.

[0175] 33 , even if the potential difference increases and the electric field spreads to the chip edge, the electric field stops spreading at the pn junction between the n-type electric-field spread prevention region 30 and the p-type surface base region 18, and the high-voltage potential difference is borne by the entire termination region 16 on the device region 14 side of the electric-field spread prevention region 30. In other words, the electric field does not concentrate at the chip edge, but increases throughout the entire termination region 16, preventing localized electric field concentration. This allows the breakdown voltage of the SiC semiconductor device to be increased.

[0176] Ninth Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0177] <Regarding the Configuration of the Semiconductor Device> In comparison with the first embodiment, the present embodiment shows a structure in which n-type electric-field spread prevention sidewall regions 31 are formed on the sidewalls of termination region trench 21 at the chip end of termination region 16. This structure can improve the breakdown voltage of the SiC semiconductor device.

[0178] 38 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0179] 38 , n-type electric-field spread prevention sidewall regions 31 are formed on the sidewalls of termination region trenches 21 at the chip end of termination region 16. In other words, n-type electric-field spread prevention sidewall regions 31 are formed on the sidewalls of termination region trenches 21 located furthest from element region 14, instead of p-type termination sidewall base regions 12.

[0180] 38 , there are three element region trenches 19 in element region 14, four boundary region trenches 20 in boundary region 15, and seven termination region trenches 21 in termination region 16. However, the number of each trench may be different from the number shown in FIG. 38 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0181] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, ST3, and ST4 shown in FIG. 7 are the same in this embodiment.

[0182] 7, a mask is formed using resist 26 for the device sidewall base region, and then oblique ion implantation is performed to form p-type device sidewall base regions 9 on the sidewalls of trench 1000. A mask pattern that covers the entire device region 14 within the chip may also be used. Furthermore, as shown in an example in FIG. 15, ions may be implanted into both sidewalls of trench 1000 in a portion of the chip, so that p-type device sidewall base regions 9 are formed on both sidewalls of trench 1000.

[0183] Next, a mask is formed using a boundary sidewall base region resist 27, and then oblique ion implantation is performed to form the p-type boundary sidewall base region 22. By this ion implantation process, the boundary region trench 20 is surrounded by the p-type base region 8, the p-type boundary sidewall base region 22, the p-type bottom base region 10, and the p-type surface base region 18.

[0184] Next, unlike the first embodiment, a mask is formed using termination sidewall base region resist 28A as shown in an example in Figure 39, and then impurity ions are implanted. As shown in an example in Figure 39, termination sidewall base region resist 28A covers the chip end of termination region 16, so that p-type termination sidewall base region 12 is not formed in trench 1000 at that location. Here, Figure 39 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to this embodiment.

[0185] Next, as shown in an example in Figure 40, a mask 28B made of resist or the like is formed, and then impurity ions are implanted. In this embodiment, n-type electric field spread prevention sidewall region 31, which is an n-type impurity diffusion layer, is formed. Examples of n-type impurities include phosphorus (P) and nitrogen (N). Here, Figure 40 is a cross-sectional view for explaining the manufacturing flow of the SiC semiconductor device according to this embodiment.

[0186] Thereafter, the SiC wafer is heat-treated at a high temperature in a heat treatment device (not shown) to activate the previously implanted ions, thereby electrically activating the previously implanted p-type and n-type ions.

[0187] The steps from step ST6 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 38 is completed.

[0188] In the SiC semiconductor device according to this embodiment, the end of termination region 16 is surrounded by n-type electric field spread prevention sidewall region 31 formed on the sidewall of trench 1000. When a voltage is applied between source electrode 5 and drain electrode 13 with drain electrode 13 at a high potential, equipotential lines 1002 are formed as shown in Fig. 5. As the potential difference increases, the electric field spreads accordingly.

[0189] 2, if the potential difference is too high, the electric field spreads to the chip edge. If the electric field spreads to the chip edge, the electric field concentrates at the pn junction at the boundary between the p-type base region 8 and the n-type drift layer 24, causing a decrease in the breakdown voltage of the SiC semiconductor device.

[0190] 38 , even if the potential difference becomes large and the electric field spreads to the chip edge, the electric field stops spreading at the interface between n-type electric-field spread prevention sidewall region 31 and gate insulating film 11, and the high-voltage potential difference is borne by the entire termination region 16, which is closer to device region 14 than n-type electric-field spread prevention sidewall region 31. In other words, the electric field does not concentrate at the chip edge, but increases throughout termination region 16, preventing local electric field concentration. This allows the SiC semiconductor device to have an increased breakdown voltage.

[0191] Tenth Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0192] <Configuration of the Semiconductor Device> In this embodiment, compared to the first embodiment, the chip surface in boundary region 15 and termination region 16 is made n-type, which makes it easier for surface charges to follow voltage changes when the voltage changes rapidly. This structure can improve the breakdown voltage of the SiC semiconductor device.

[0193] 41 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0194] In the structure shown in FIG. 41, n-type source regions 7 are formed on the entire chip surface in boundary region 15 and termination region 16 .

[0195] 41 , there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and seven termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in FIG. 41 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0196] <Method of Manufacturing a Semiconductor Device> Steps ST1 and ST2 shown in FIG. 7 are the same in this embodiment.

[0197] 7, unlike the case shown in the first embodiment, a mask (not shown here) made of resist or the like is formed, and then impurity ions are implanted to form n-type source regions 7 over the entire chip surface in boundary region 15 and termination region 16, as shown in the example of Fig. 41. Then, a mask (not shown here) made of resist or the like is formed, and then ions are implanted into the surface layer of p-type base region 8 to partially form p-type surface base regions 18 in order to reduce the surface resistance.

[0198] The steps from step ST4 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 41 is completed.

[0199] According to this embodiment, by converting the chip surface (the surface layer of the p-type base region 8) in the boundary region 15 and the termination region 16 to n-type, the surface charge can more easily follow the voltage change when the voltage changes rapidly.

[0200] For example, when the SiC semiconductor device performs a switching operation by applying or stopping a gate-on voltage to the element region gate electrode 2, if the charge present on the chip surface in boundary region 15 and termination region 16 cannot keep up with the fast rate at which the voltage changes, the potential difference between adjacent trenches in termination region 16 increases, causing electric field concentration. In particular, the vicinity of high-impact ionization region 23 shown in Figure 6 is a region where a potential difference begins to occur, so the electric field is likely to concentrate, causing a decrease in the breakdown voltage of the SiC semiconductor device.

[0201] 2, the chip surface (surface layer of p-type base region 8) of boundary region 15 and termination region 16 is made p-type (forming p-type surface base region 18). On the other hand, in this embodiment, the chip surface of boundary region 15 and termination region 16 is made n-type (forming n-type source region 7).

[0202] 2, holes exist as majority carriers on the chip surface, whereas in this embodiment, electrons exist as majority carriers.

[0203] Electrons have higher mobility than holes. Therefore, when a potential difference occurs due to switching operation or the like, carriers tend to move in response to the potential difference. This makes it difficult for a high potential difference to occur between trenches, and localized electric field concentration is unlikely to occur, thereby increasing the breakdown voltage of the SiC semiconductor device.

[0204] Eleventh Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0205] <Regarding the Configuration of the Semiconductor Device> In the present embodiment, compared to the first embodiment, a structure is shown in which interlayer insulating film 17 is formed continuously from termination region 16 to boundary region 15 (a structure in which p-type surface base region 18 in boundary region 15 is not exposed). This structure can improve the discharge breakdown voltage of the SiC semiconductor device.

[0206] 42 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0207] 42, the interlayer insulating film 17 is formed continuously from the termination region 16 to the boundary region 15. In other words, the source electrode 5 overlaps only the element region 14 in plan view.

[0208] 42, there are three element region trenches 19 in element region 14, four boundary region trenches 20 in boundary region 15, and seven termination region trenches 21 in termination region 16. However, the number of each trench may be different from the number shown in Fig. 42 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0209] <Method of Manufacturing Semiconductor Device> Steps ST1, ST2, ST3, ST4, ST5, ST6 and ST7 shown in FIG. 7 are the same in this embodiment.

[0210] 7, an interlayer insulating film 17 similar to that in the first embodiment is formed by chemical vapor deposition (CVD), and then patterned by photolithography and etching to remove the remaining portion mainly in the element region 14. By patterning, the n-type source region 7 and a portion of the p-type surface base region 18 in the element region 14 are exposed, as shown in an example in FIG. 43. Here, FIG. 43 is a cross-sectional view for explaining the manufacturing flow of the SiC semiconductor device according to this embodiment.

[0211] The steps from step ST9 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 42 is completed.

[0212] According to this embodiment, the interlayer insulating film 17 is formed continuously from the termination region 16 to the boundary region 15, so that the distance D1 between the source electrode 5 and the chip end can be made longer than in the case shown in FIG. 2, as shown in an example in FIG. 42.

[0213] When a voltage is applied to the source electrode 5 and the drain electrode 13, if D1 is short, a discharge may occur between the source electrode 5 and the tip end, and the tip may be destroyed by the discharge.

[0214] On the other hand, according to this embodiment, the interlayer insulating film 17 is formed continuously from the termination region 16 to the boundary region 15, so that the occurrence of the above-mentioned discharge can be suppressed.

[0215] In this embodiment, as shown in Fig. 44, boundary region 15 of the entire chip is covered with interlayer insulating film 17, and there is no pattern connecting annular boundary region gate electrodes 3 to each other as shown in Fig. 1. Here, Fig. 44 is a plan view showing an example of the configuration of a SiC semiconductor device according to this embodiment.

[0216] Therefore, the chip surface in the boundary region 15 and the boundary region gate electrode 3 are isolated from the source potential. Therefore, the p-type boundary sidewall base region 22 in the boundary region 15 must be a p-type region containing a higher concentration of p-type impurities than the p-type termination sidewall base region 12. The impurity concentration of the p-type boundary sidewall base region 22 must be higher than the p-type impurity concentration of the p-type base region 8. If the impurity concentration of the p-type boundary sidewall base region 22 were the same as that of the p-type base region 8, even in the boundary region 15, a change in the equipotential lines 1002 similar to that in the termination region 16, such as the high-impact ionization region 23 ( FIG. 6 ), would occur, resulting in electric field concentration. As a result, the breakdown voltage of the SiC semiconductor device would decrease. Therefore, the p-type impurity concentration of the p-type boundary sidewall base region 22 must be higher than the p-type impurity concentration of the p-type base region 8.

[0217] Twelfth Embodiment A semiconductor device according to this embodiment and a semiconductor device according to the present invention will be described. In the following description, components similar to those described in the above embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0218] <Regarding the Configuration of the Semiconductor Device> In this embodiment, compared to the first embodiment, a structure is shown in which the thickness of the thick gate insulating film 34 in the boundary region 15 and the termination region 16 is thicker than the thickness of the gate insulating film 11 in the element region 14. This structure can improve the breakdown voltage of the gate insulating film.

[0219] 45 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment, which corresponds to a modified example of the configuration of the AB cross section shown in FIG.

[0220] In the structure exemplified in FIG. 45, the thickness of the thick gate insulating film 34 which is the gate insulating film in the boundary region 15 and the termination region 16 is thicker than the thickness of the gate insulating film 11 in the element region 14 .

[0221] 45, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and seven termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in Fig. 45 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0222] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, ST3, ST4, and ST5 shown in FIG. 7 are the same in this embodiment.

[0223] In step ST6 shown in FIG. 7 , a gate insulating film is formed by a deposition method such as thermal oxidation or chemical vapor deposition. Before forming the gate insulating film, oxidation may be performed using thermal oxidation to remove plasma damage that may have occurred during the formation of the trench gate. Thereafter, a mask (not shown) made of resist or the like is formed, followed by etching. As shown in FIG. 46 , the gate insulating film is removed only in the element region 14, leaving a gate insulating film 34A in the boundary region 15 and the termination region 16. Here, FIG. 46 is a cross-sectional view for explaining the manufacturing flow of a SiC semiconductor device according to this embodiment.

[0224] Thereafter, after removing the mask such as resist, a gate insulating film is formed again by a deposition method such as thermal oxidation or chemical vapor deposition. As a result, as shown in an example in Figure 47, a structure can be formed in which the thickness of thick gate insulating film 34, which is the gate insulating film formed in boundary region 15 and termination region 16, is thicker than the thickness of gate insulating film 11 formed in element region 14. Here, Figure 47 is a cross-sectional view for explaining the manufacturing flow of the SiC semiconductor device according to this embodiment.

[0225] The steps from step ST7 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 45 is completed.

[0226] Note that, by using a similar manufacturing method, the thick gate insulating film 34 may be formed from a trench 1000 midway through the boundary region 15, as shown in the example of Fig. 48. In other words, the thick gate insulating film 34 may be formed in a portion of the trench 1000 in the boundary region 15. Here, Fig. 48 is a cross-sectional view showing a modified example of the configuration of the SiC semiconductor device according to the present embodiment.

[0227] Furthermore, trench 1000 in boundary region 15 and termination region 16 may be filled with gate insulating film 34B as shown in Fig. 49. Here, Fig. 49 is a cross-sectional view showing a modified example of the configuration of the SiC semiconductor device according to the present embodiment.

[0228] 55, trench 1000 in termination region 16 may be filled with gate insulating film 34B. Also, boundary region gate electrode 3 in the boundary region is shorted (same potential) to source electrode 5. Here, FIG. 55 is a cross-sectional view showing a modified example of the configuration of the SiC semiconductor device according to the present embodiment.

[0229] According to this embodiment, the thickness of the thick gate insulating film 34 in the boundary region 15 and the termination region 16 is greater than the thickness of the gate insulating film 11 in the element region 14 .

[0230] When a voltage is applied to the source electrode 5 and the drain electrode 13, as shown in the high-impact ionization region 23 ( FIG. 6 ), equipotential lines 1002 pass through the gate insulating film 11 at the outer edge of the boundary region 15 and the gate insulating film 11 in the termination region 16. For this reason, an electric field is likely to concentrate on the gate insulating film 11 at the outer edge of the boundary region 15 and the gate insulating film 11 in the termination region 16. This may result in the electric field concentrating on the gate insulating film 11 and causing breakdown of the gate insulating film 11 before the withstand voltage is reached in the n-type SiC substrate 1.

[0231] On the other hand, in this embodiment, in order to keep the resistance in the channel low, the gate insulating film 11 in the element region 14 is not thickened, and a thick gate insulating film 34 is formed only in the boundary region 15 and the termination region 16 where the electric field is likely to concentrate, thereby achieving both low channel resistance and high gate insulating film breakdown voltage.

[0232] 52 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment. Fig. 52 corresponds to a modified example of the configuration of the AB cross section shown in Fig. 1.

[0233] In the structure exemplified in FIG. 52, p-type boundary sidewall base region 22 in boundary region 15 and p-type termination sidewall base region 12 in termination region 16 are not formed.

[0234] 52, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and seven termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in Fig. 52 as long as the current capacity or withstand voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the withstand voltage of the chip can be improved.

[0235] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, ST3, and ST4 shown in FIG. 7 are the same in this embodiment.

[0236] In step ST5 shown in FIG. 7, unlike the first embodiment, p-type boundary sidewall base region 22 and p-type termination sidewall base region 12 are not formed.

[0237] The steps from step ST6 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 52 is completed.

[0238] According to this embodiment, the number of process steps is reduced, and therefore the manufacturing cost of the SiC semiconductor device can be reduced.

[0239] The above-described configuration improves the breakdown voltage of the semiconductor device. Furthermore, because the pn junction between the base region 8 and the drift layer 24 is located on the sidewall of the gate insulating film 11 in the termination region 16, the equipotential lines tend to escape, electric field concentration tends to occur, and the breakdown voltage of the semiconductor device is lower than in a structure in which a p-type layer is formed on the sidewall (for example, the structure shown in the first embodiment). The way in which the equipotential lines escape is the same as in the case shown in FIG. 5 .

[0240] <Fourteenth Embodiment> Fig. 53 is a cross-sectional view showing an example of the configuration of an SiC semiconductor device according to this embodiment. Fig. 53 corresponds to a modified example of the configuration of the AB cross section shown in Fig. 1.

[0241] 53, the interlayer insulating film 17 is formed continuously from the termination region 16 to the boundary region 15. In other words, the source electrode 5 overlaps only the element region 14 in plan view.

[0242] 53, there are three element region trenches 19 in element region 14, four boundary region trenches 20 in boundary region 15, and seven termination region trenches 21 in termination region 16. However, the number of each trench may be different from the number shown in Fig. 53 as long as the current capacity or withstand voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the numbers of boundary region trenches 20 and termination region trenches 21 are formed, the more the withstand voltage of the chip can be improved.

[0243] <Method of Manufacturing Semiconductor Device> Steps ST1, ST2, ST3, ST4, ST5, ST6 and ST7 shown in FIG. 7 are the same in this embodiment.

[0244] 7, the interlayer insulating film 17 similar to that in the first embodiment is formed by chemical vapor deposition (CVD), and then patterned by photolithography and etching to remove the remaining portions mainly in the element region 14. By patterning, the n-type source region 7 and a part of the p-type surface base region 18 in the element region 14 are exposed.

[0245] 7 and subsequent steps are similar to those in the present embodiment, except that the boundary region gate electrode 3 in the boundary region is shorted (has the same potential) to the source electrode 5. In this way, a SiC semiconductor device such as the one shown in FIG.

[0246] With the above-described configuration, the potential of the boundary region 15 can be stably fixed at 0 V. This improves the breakdown voltage of the semiconductor device. Furthermore, even in a structure in which the boundary sidewall base region 22 is not present in the boundary region 15 or in which an n-type layer is formed on the trench sidewall of the boundary region 15, the potential of the boundary region 15 can be fixed at 0 V, so the step of implanting a p-type sidewall base region can be omitted. The equipotential lines are drawn in the same manner as in the case shown in FIG. 5 .

[0247] 54 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment. Fig. 54 corresponds to a modified example of the configuration of the AB cross section shown in Fig. 1.

[0248] In the structure exemplified in FIG. 54, n-type boundary sidewall base regions 122 are formed on the sidewalls of boundary region trench 20, and n-type termination sidewall base regions 112 are formed on the sidewalls of termination region trench 21.

[0249] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, ST3, and ST4 shown in FIG. 7 are the same in this embodiment.

[0250] 7 , a mask is formed using resist 26 for the device sidewall base region, and then oblique ion implantation is performed to form p-type device sidewall base regions 9 on the sidewalls of trench 1000. A mask pattern that covers the entire device region 14 within the chip may also be used. Furthermore, ions may be implanted into both sidewalls of trench 1000 in part of the chip, so that p-type device sidewall base regions 9 are formed on both sidewalls of trench 1000.

[0251] Next, a mask is formed using resist 27 for the boundary sidewall base region, and then ions are implanted obliquely into the sidewall of trench 1000 to form n-type boundary sidewall base region 122. Examples of n-type impurities include phosphorus (P) and nitrogen (N).

[0252] Next, a mask is formed using resist 28 for the termination sidewall base region, and then ions are implanted obliquely into the sidewall of trench 1000 to form n-type termination sidewall base region 112. Examples of n-type impurities include phosphorus (P) or nitrogen (N).

[0253] Thereafter, the SiC wafer is heat-treated at a high temperature in a heat treatment device (not shown) to activate the previously implanted ions, thereby electrically activating the previously implanted p-type and n-type ions.

[0254] The steps from step ST6 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 54 is completed.

[0255] The above-described configuration improves the breakdown voltage of the semiconductor device. Furthermore, since the pn junction between the base region 8 and the n-type termination sidewall base region 112 is located on the sidewall of the gate insulating film 11 in the termination region 16, the equipotential lines are easily eliminated. Furthermore, since the distance of the termination region 16 can be shortened, the chip size can be reduced.

[0256] Sixteenth Embodiment In this embodiment, compared to the first embodiment, a structure is shown in which the source electrode 5 does not contact the surface of the SiC substrate 1 in the boundary region 15. According to this structure, the distance w2 between the boundary region trenches 20 in the boundary region 15 can be narrowed. This allows the chip size to be reduced, and the chip cost to be reduced.

[0257] 56 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment. Fig. 56 corresponds to a modified example of the configuration of the AB cross section shown in Fig. 1.

[0258] In the structure exemplified in FIG. 56 , the boundary region gate electrode 3B is formed so as to extend not only within the trench 1000 but also to the upper surface of the p-type surface base region 18, thereby preventing contact between the surface of the SiC substrate 1 and the source electrode 5 in the boundary region 15. Therefore, there is no need to form contact holes between the boundary region trenches 20 for contacting the source electrode 5 and the surface of the SiC substrate 1, as shown in FIG. 2 of the first embodiment. Therefore, the distance w2 between the boundary region trenches 20 can be made narrower than in the first embodiment. This allows the width of the boundary region 15 to be shortened, thereby reducing the chip size.

[0259] 56, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and seven termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in Fig. 56 as long as the current capacity or breakdown voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 are formed, the more the breakdown voltage of the chip can be improved.

[0260] <Method of Manufacturing a Semiconductor Device> Steps ST1, ST2, ST3, ST4, ST5, and ST6 shown in FIG. 7 are the same in this embodiment.

[0261] 7, a gate electrode is formed to fill the trench 1000 surrounded by the gate insulating film 11. Then, after forming a mask (not shown) made of resist or the like, the gate electrode is patterned by removing excess portions of the gate electrode, as shown in the example of Fig. 57. An element region gate electrode 2 is formed in the element region, a boundary region gate electrode 3B is formed in the boundary region, and a termination region gate electrode 4 is formed in the termination region.

[0262] Next, as shown in FIG. 58, an interlayer insulating film 17 is formed by chemical vapor deposition (CVD), followed by patterning by photolithography and etching to remove the remaining portions mainly in the element region 14 and boundary region 15 (step ST8 shown in FIG. 7). By patterning, the n-type source region 7 and a portion of the p-type surface base region 18 in the element region 14 and boundary region 15 are exposed. The corners of the interlayer insulating film 17 can also be rounded by doping with impurities such as boron (B) or phosphorus (P). The interlayer insulating film 17 is formed by deposition and patterning, and the deposited material can be, for example, silicon nitride (Si x N y ) or silicon oxide (SiO ２ ) and the thickness of the interlayer insulating film 17 is preferably 0.5 μm or more and 2.0 μm or less.

[0263] Next, a source electrode 5 is formed using a barrier metal made of aluminum or an aluminum alloy made of aluminum and silicon, an aluminum alloy made of aluminum and copper, or nickel, or the like, and a titanium compound such as titanium or titanium nitride (TiN) as appropriate (step ST9 shown in FIG. 7).

[0264] 59, the source electrode 5 is in contact with the surface of the n-type SiC substrate 1 in the element region 14, but is not in contact with the surface of the SiC substrate 1 in the boundary region 15 and the termination region 16. A pattern is formed using a mask (not shown here) made of resist or the like so that the source electrode 5 is also in contact with the surface of the boundary region gate electrode 3. Here, the boundary region gate electrode 3B and the source electrode 5 are in ohmic contact.

[0265] The steps from step ST10 onwards shown in Fig. 7 are the same in this embodiment as well. In this way, a SiC semiconductor device such as the one shown in Fig. 56 is completed.

[0266] According to this embodiment, the distance w2 between the boundary region trenches 20 in the boundary region 15 can be narrowed, the chip size can be reduced, and the chip cost can be reduced.

[0267] In this embodiment, in boundary region 15, the surface of SiC substrate 1 is not in contact with source electrode 5, but source electrode 5 is in ohmic contact with boundary region gate electrode 3B. Capacitive coupling via boundary region gate electrode 3B and gate insulating film 11 keeps the surface of boundary region 15 at the same potential as the source potential. Therefore, relaxation of the electric field in the creeping direction (the direction along the substrate in a plan view) occurs in the termination region, and the breakdown voltage can be kept high, as in the first embodiment.

[0268] Seventeenth Embodiment In comparison with the first embodiment, this embodiment shows a structure in which a diffusion layer is not formed near the surface in termination region 16. According to this structure, the electric field can be alleviated over a short distance in termination region 16, which makes it possible to reduce the chip size and chip costs.

[0269] 60 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment. Fig. 60 corresponds to a modified example of the configuration of the AB cross section shown in Fig. 1.

[0270] 60 , no diffusion layers such as source region 7, base region 8, or surface base region 18 are formed in the surface layer of n-type drift layer 24 in termination region 16. Therefore, as shown in FIG. 65 , equipotential lines are eliminated in the n-type region on the surface of SiC substrate 1 between termination region trenches 21, and the electric field is relaxed. Compared to the first embodiment, the electric field can be relaxed over a shorter distance in the termination region. This allows the width of termination region 16 to be shortened, thereby reducing the chip size.

[0271] 60, there are three element region trenches 19 in the element region 14, four boundary region trenches 20 in the boundary region 15, and seven termination region trenches 21 in the termination region 16. However, the number of each trench may be different from the number shown in Fig. 60 as long as the current capacity or withstand voltage of the designed chip is satisfied. The more element region trenches 19 are formed, the more the current capacity of the chip can be improved, and the more the number of boundary region trenches 20 and termination region trenches 21 are formed, the more the withstand voltage of the chip can be improved.

[0272] <Method of Manufacturing a Semiconductor Device> Step ST1 shown in FIG. 7 is the same in this embodiment.

[0273] 7, a mask (not shown) made of resist or the like is formed, and p-type base region 8 is not formed in termination region 16. Similarly, in step ST3, p-type base region 8 is not formed in termination region 16. In step ST4, trench 1000 is formed in the same manner as in the first embodiment. Then, p-type bottom base region 10 is formed in the same manner as in the first embodiment. FIG. 61 is a cross-sectional view after completion of step ST4. Ion implantation in step ST4 may be scattered in the air or performed at an angle, and a structure as shown in the cross-sectional view of FIG. 62 may be formed when step ST5 is completed.

[0274] Steps from step ST5 onwards are the same as those in the first embodiment. In this way, a SiC semiconductor device such as the one shown in FIG.

[0275] If the termination sidewall base region 12 is not formed in step ST4, a semiconductor device as shown in FIG. 63 is completed. Alternatively, as shown in FIG. 45 or 49 of the twelfth embodiment, the gate oxide film in the termination region 16 may be thickened or the trench may be filled with an insulating film. This improves the breakdown voltage of the gate oxide film. In this case, a semiconductor device as shown in FIG. 64 is completed.

[0276] According to this embodiment, since no diffusion layer is formed in the surface layer of n-type drift layer 24 in termination region 16, the equipotential lines extend from sources other than gate insulating film 11, as shown in Fig. 65. Therefore, the electric field can be alleviated with a shorter width of termination region 16, which allows the chip size to be reduced and chip costs to be reduced.

[0277] Eighteenth Embodiment A power conversion device and a method for manufacturing the power conversion device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0278] <Configuration of the Power Conversion Device> In this embodiment, the semiconductor device (SiC semiconductor device) according to the above-described embodiment is applied to a power conversion device. The power conversion device to which the present invention is applied is not limited to a specific application, but the following describes a case where the present invention is applied to a three-phase inverter.

[0279] FIG. 50 is a diagram conceptually illustrating an example of the configuration of a power conversion system including the power conversion device of this embodiment.

[0280] As shown in the example of FIG. 50 , the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery. The power supply 2100 can also be configured from a rectifier circuit connected to an AC system or an AC-DC converter. The power supply 2100 can also be configured from a DC-DC converter that converts DC power output from a DC system into a predetermined power.

[0281] The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.

[0282] Moreover, as shown in an example in FIG. 50 , the power conversion device 2200 includes a conversion circuit 2201 that converts DC power into AC power and outputs it, a drive circuit 2202 that outputs drive signals for driving each switching element of the conversion circuit 2201, and a control circuit 2203 that outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202.

[0283] The load 2300 is a three-phase electric motor driven by AC power supplied from the power conversion device 2200. The load 2300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, such as a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0284] The power conversion device 2200 will be described in detail below. The conversion circuit 2201 includes a switching element and a freewheeling diode (not shown). The switching element performs a switching operation to convert DC power supplied from the power supply 2100 into AC power, which is then supplied to the load 2300.

[0285] There are various specific circuit configurations for the conversion circuit 2201, but the conversion circuit 2201 according to this embodiment is a two-level three-phase full-bridge circuit, and includes six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements.

[0286] The semiconductor device according to any of the above-described embodiments is applied to at least one of the switching elements and freewheeling diodes in the conversion circuit 2201. Six switching elements are connected in series in groups of two to form upper and lower arms, each of which constitutes a phase (i.e., U phase, V phase, and W phase) of a full-bridge circuit. The output terminals of each of the upper and lower arms (i.e., the three output terminals of the conversion circuit 2201) are connected to the load 2300.

[0287] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201, and further supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on control signals output from a control circuit 2203 (described later), the drive circuit 2202 outputs drive signals for turning the switching elements on and off to the control electrodes of the respective switching elements.

[0288] When the switching element is maintained in the on state, the drive signal is a voltage signal (i.e., an on signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (i.e., an off signal) that is equal to or less than the threshold voltage of the switching element.

[0289] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that a desired power is supplied to the load 2300. Specifically, the control circuit 2203 calculates the time (i.e., on-time) that each switching element of the conversion circuit 2201 should be in the on-state based on the power to be supplied to the load 2300. For example, the conversion circuit 2201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.

[0290] Then, the control circuit 2203 outputs a control command (i.e., a control signal) to the drive circuit 2202 so that an ON signal is output to a switching element that should be in an ON state at each point in time, and an OFF signal is output to a switching element that should be in an OFF state at each point in time. Based on the control signal, the drive circuit 2202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0291] In the power conversion device 2200 according to this embodiment, a semiconductor device according to any of the embodiments described above is applied as the switching element of the conversion circuit 2201, and therefore the on-resistance can be stabilized after a current cycle.

[0292] In this embodiment, an example has been described in which the semiconductor device in any of the above-described embodiments is applied to a two-level three-phase inverter, but the application example is not limited to this, and the semiconductor device in any of the above-described embodiments can be applied to various power conversion devices.

[0293] Although the present embodiment has been described with respect to a two-level power conversion device, the semiconductor device according to any of the above-described embodiments may be applied to a three-level or multilevel power conversion device. When power is supplied to a single-phase load, the semiconductor device according to any of the above-described embodiments may be applied to a single-phase inverter.

[0294] Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any of the above-described embodiments can be applied to a DC-DC converter or an AC-DC converter.

[0295] Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied is not limited to a case in which the load is an electric motor, and can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, for example. Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0296] <Method for Manufacturing Power Converter> Next, a method for manufacturing the power converter according to this embodiment will be described.

[0297] First, a semiconductor device is manufactured by the manufacturing method described in the above-described embodiment. Then, a conversion circuit 2201 including the semiconductor device is provided as a component of a power conversion device. The conversion circuit 2201 is a circuit for converting input power and outputting it.

[0298] The power conversion device further includes a driver circuit 2202. The driver circuit 2202 is a circuit for outputting a driver signal to the semiconductor device for driving the semiconductor device. The power conversion device further includes a control circuit 2203. The control circuit 2203 is a circuit for outputting a control signal to the driver circuit 2202 for controlling the driver circuit 2202.

[0299] The semiconductor switching elements used in the embodiments described above are not limited to switching elements made of silicon (Si) semiconductors, and for example, the semiconductor switching elements may be made of non-Si semiconductor materials having a wider band gap than Si semiconductors.

[0300] Examples of wide band gap semiconductors that are non-Si semiconductor materials include silicon carbide, gallium nitride-based materials, and diamond.

[0301] Switching elements made of wide bandgap semiconductors can be used in high voltage regions where unipolar operation is difficult with Si semiconductors, and can significantly reduce the switching loss that occurs during switching operation, thereby enabling a significant reduction in power loss.

[0302] Furthermore, switching elements made of wide bandgap semiconductors have low power loss and high heat resistance, which means that when configuring a power module with a cooling unit, it is possible to reduce the size of the heat dissipation fins of the heat sink, thereby enabling further miniaturization of the semiconductor module.

[0303] Furthermore, switching elements made of wide bandgap semiconductors are suitable for high-frequency switching operations. Therefore, when applied to converter circuits that require higher frequencies, increasing the switching frequency also enables the size of reactors or capacitors connected to the converter circuit to be reduced.

[0304] Therefore, the same effect can be obtained even when the semiconductor switching elements in the above-described embodiments are made of a wide-gap semiconductor such as silicon carbide.

[0305] <Regarding the Effects Produced by the Multiple Embodiments Described Above> Next, examples of the effects produced by the multiple embodiments described above will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the multiple embodiments described above, but these may be replaced with other specific configurations exemplified in the present specification to the extent that similar effects are produced. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0306] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0307] According to the embodiment described above, the semiconductor device includes a semiconductor substrate of a first conductivity type (n-type), an n-type drift layer 24, a diffusion region of a second conductivity type (p-type), an upper electrode, and a lower electrode. Here, the semiconductor substrate corresponds to, for example, a SiC substrate 1. The diffusion region corresponds to, for example, a base region 8. The upper electrode corresponds to, for example, a source electrode 5. The lower electrode corresponds to, for example, a drain electrode 13. The drift layer 24 is formed on the upper surface of the SiC substrate 1. The base region 8 is formed in a surface layer of the drift layer 24. The source electrode 5 is formed on the upper surface of the drift layer 24. The drain electrode 13 is formed on the lower surface of the SiC substrate 1. Here, a region where a switching element that switches between the source electrode 5 and the drain electrode 13 is formed is referred to as an element region 14. A region surrounding the element region 14 in a plan view is referred to as a boundary region 15. The region surrounding the boundary region 15 in plan view is defined as a termination region 16. The source electrode 5 overlaps the device region 14 and the boundary region 15 in plan view. The device region 14 includes an n-type source region 7 partially formed in the surface layer of the base region 8, at least one device region trench 19 extending from the upper surface of the source region 7 to the inside of the drift layer 24, a device region gate electrode 2 surrounded by a gate insulating film within the device region trench 19, and a p-type device sidewall base region 9 formed on the sidewall of the device region trench 19. Here, the gate insulating film corresponds to, for example, the gate insulating film 11 or the thick gate insulating film 34. The boundary region 15 also includes at least one boundary region trench 20 extending from the upper surface of the base region 8 to the inside of the drift layer 24 while surrounding the device region 14 in plan view, a boundary region gate electrode 3 surrounded by the gate insulating film 11 within the boundary region trench 20, and a p-type boundary sidewall base region 22 formed on the sidewall of the boundary region trench 20. Furthermore, the termination region 16 includes at least one termination region trench 21 that surrounds the boundary region 15 in a plan view and reaches from the upper surface of the base region 8 to the inside of the drift layer 24 .

[0308] With this configuration, the element region 14, where current easily flows when a high voltage is applied, and the termination region 16, where the impact ionization rate is high, are separated by the boundary region 15. This increases the distance between the current concentration point and the point with a high ionization rate, making avalanche breakdown less likely to occur and increasing the breakdown voltage of the semiconductor device. Furthermore, because there is no need to form a base region in the termination region trench 21, the breakdown voltage structure can be formed with fewer steps, reducing manufacturing costs.

[0309] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0310] Furthermore, according to the embodiment described above, the semiconductor device includes a p-type termination sidewall base region formed on a portion of the sidewall of termination region trench 21. Here, the termination sidewall base region corresponds to, for example, termination sidewall one-side base region 29 or termination sidewall one-side base region 29A. The p-type concentration of termination sidewall one-side base region 29 or termination sidewall one-side base region 29A is equal to the p-type concentration of device portion sidewall base region 9. With this configuration, equipotential lines 1002 can extend only from the trench sidewall on the side where the p-type region is not formed. As a result, the spacing between equipotential lines 1002 is increased, suppressing electric field concentration and increasing the breakdown voltage of the SiC semiconductor device.

[0311] Furthermore, according to the embodiment described above, the semiconductor device includes a p-type termination sidewall base region formed on the sidewall of termination region trench 21. Here, termination sidewall base region corresponds to termination sidewall base region 12, for example. The p-type concentration of element sidewall base region 9 is higher than the p-type concentration of termination sidewall base region 12. With this configuration, it is possible to suppress electric field concentration on the sidewall of termination region trench 21.

[0312] Moreover, according to the embodiment described above, a plurality of boundary region trenches 20 are provided. The boundary region gate electrodes 3 in the plurality of boundary region trenches 20 are electrically connected to each other. With this configuration, all of the boundary region gate electrodes 3 have the same potential.

[0313] Furthermore, according to the embodiment described above, the boundary region gate electrode 3 and the source electrode 5 are ohmically connected. With this configuration, the boundary region gate electrode 3 and the source electrode 5 have the same potential, which makes it easier for the charge on the upper surface of the boundary region 15 to escape from the source electrode 5 due to capacitive coupling. Therefore, the potential of the upper surface of the boundary region 15 is less likely to deviate from the potential of the source electrode 5 even during switching operations.

[0314] Furthermore, according to the embodiment described above, the SiC substrate 1 is made of SiC. With such a configuration, the breakdown voltage of the semiconductor device can be increased.

[0315] Furthermore, according to the embodiment described above, a plurality of element region trenches 19 are provided. A plurality of boundary region trenches 20 are provided, and a plurality of termination region trenches 21 are provided. The spacing between the boundary region trenches 20 (e.g., W2 in FIG. 23 ) and the spacing between the termination region trenches 21 (e.g., W2 in FIG. 23 ) are narrower than the spacing between the element region trenches 19 (e.g., W1 in FIG. 23 ). With this configuration, electric field concentration between the boundary region 15 and the element region 14 or between the boundary region 15 and the termination region 16 can be suppressed, thereby improving the breakdown voltage of the semiconductor device.

[0316] Furthermore, according to the embodiment described above, a plurality of termination region trenches 21 are provided. The spacing between termination region trenches 21 (for example, Wt in FIG. 24 ) increases with increasing distance from device region 14. With this configuration, the electric field can be increased even in termination region trenches 21 located away from device region 14, where the generated electric field is small and potential difference is unlikely to occur. Therefore, the breakdown voltage of the SiC semiconductor device can be maintained with a termination region 16 having a small width.

[0317] Furthermore, according to the embodiment described above, the semiconductor device includes a p-type first bottom base region formed on the lower surface of the element region trench 19 and a p-type second bottom base region formed on the lower surface of the boundary region trench 20. Here, the first bottom base region corresponds to, for example, the bottom base region 10. The second bottom base region corresponds to, for example, the bottom base region 10A. The width of the bottom base region 10A (e.g., L2 in FIG. 25 ) is wider than the width of the bottom base region 10 (e.g., L1 in FIG. 25 ). With this configuration, electric field concentration below the trench 1000 in the boundary region 15 can be suppressed, thereby improving the breakdown voltage of the semiconductor device.

[0318] Furthermore, according to the embodiment described above, the semiconductor device includes p-type bottom base region 10 formed on the lower surface of element region trench 19 and a p-type third bottom base region formed on the lower surface of termination region trench 21. Here, the third bottom base region corresponds to, for example, bottom base region 10A. The width of bottom base region 10A (e.g., L2 in FIG. 25 ) is wider than the width of bottom base region 10 (e.g., L1 in FIG. 25 ). With this configuration, electric field concentration at the bottom of trench 1000 in termination region 16 can be suppressed, thereby improving the breakdown voltage of the semiconductor device.

[0319] Furthermore, according to the embodiment described above, the semiconductor device includes a plurality of p-type fourth bottom base regions formed on the lower surface of termination region trench 21. Here, the fourth bottom base regions correspond to, for example, bottom base region 10B. The width of bottom base region 10B (e.g., Lt in FIG. 25 ) narrows with increasing distance from element region 14. This configuration allows the width of termination region 16 to be shortened while maintaining the breakdown voltage of the SiC semiconductor device. This allows the chip size to be reduced, thereby reducing the manufacturing cost of the semiconductor device.

[0320] Furthermore, according to the embodiment described above, the semiconductor device includes an n-type field-spread prevention region 30 formed in the surface layer of the drift layer 24, surrounding all of the termination region trenches 21 in a plan view. The n-type concentration in the field-spread prevention region 30 is equal to the n-type concentration in the source region 7. With this configuration, even if the potential difference increases and the electric field spreads to the chip edge, the electric field stops spreading at the pn junction between the n-type field-spread prevention region 30 and the p-type surface base region 18, and the entire termination region 16 on the device region 14 side of the field-spread prevention region 30 bears the high-voltage potential difference. In other words, the electric field does not concentrate at the chip edge, but increases throughout the termination region 16, preventing localized electric field concentration. This increases the breakdown voltage of the SiC semiconductor device.

[0321] Furthermore, according to the embodiment described above, the semiconductor device includes n-type field-spread prevention sidewall region 31 formed in place of termination sidewall base region 12 on the sidewall of termination region trench 21 located farthest from device region 14. With this configuration, even if the potential difference becomes high and the electric field spreads to the chip edge, the development of the electric field stops at the interface between n-type field-spread prevention sidewall region 31 and gate insulating film 11, and the entire termination region 16 closer to device region 14 than n-type field-spread prevention sidewall region 31 bears the high-voltage potential difference. In other words, the electric field does not concentrate at the chip edge, but rather increases throughout termination region 16, preventing localized field concentration. This increases the breakdown voltage of the SiC semiconductor device.

[0322] Furthermore, according to the embodiment described above, the source region 7 is formed in the surface layer of the base region 8 in the boundary region 15 and the termination region 16. With this configuration, by converting the chip surface of the boundary region 15 and the termination region 16 (the surface layer of the p-type base region 8) into n-type, the surface charge can more easily follow the voltage change when the voltage changes rapidly. Therefore, a high potential difference is less likely to occur between the trenches, and local electric field concentration is less likely to occur, thereby increasing the breakdown voltage of the SiC semiconductor device.

[0323] Furthermore, according to the embodiment described above, the thickness of the thick gate insulating film 34 inside the boundary region trench 20 is thicker than the thickness of the gate insulating film 11 inside the element region trench 19. With this configuration, the gate insulating film 11 in the element region 14 is not thickened in order to keep the resistance in the channel low, and the thick gate insulating film 34 is formed only in the boundary region 15 and the termination region 16 where an electric field is likely to concentrate, thereby achieving both low channel resistance and high gate insulating film breakdown voltage.

[0324] Furthermore, according to the embodiment described above, the thickness of the thick gate insulating film 34 inside the termination region trench 21 is thicker than the thickness of the gate insulating film 11 inside the element region trench 19. With this configuration, the gate insulating film 11 in the element region 14 is not thickened in order to keep the resistance in the channel low, and the thick gate insulating film 34 is formed only in the boundary region 15 and the termination region 16 where an electric field is likely to concentrate, thereby achieving both low channel resistance and high gate insulating film breakdown voltage.

[0325] Furthermore, according to the embodiment described above, the semiconductor device includes termination region gate electrode 4 surrounded by gate insulating film 11 inside termination region trench 21. With this configuration, element region 14 and termination region 16 are separated by boundary region 15. This allows the breakdown voltage of the semiconductor device to be increased.

[0326] Furthermore, according to the embodiment described above, the semiconductor device includes a first insulating film filled inside termination region trench 21. Here, the first insulating film corresponds to, for example, gate insulating film 34B. With this configuration, gate insulating film 34B filled in termination region trench 21 has a large thickness, which can improve the breakdown voltage of termination region 16.

[0327] Moreover, according to the embodiment described above, a plurality of boundary region trenches 20 are provided. The semiconductor device also includes a second insulating film filled inside some of the boundary region trenches 20. Here, the second insulating film corresponds to, for example, the gate insulating film 34B. With this configuration, the gate insulating film 34B filled in the boundary region trench 20 has a large thickness, which can improve the breakdown voltage of the semiconductor device.

[0328] According to the embodiment described above, the semiconductor device includes an n-type SiC substrate 1, an n-type drift layer 24, a p-type base region 8, a source electrode 5, and a drain electrode 13. The n-type drift layer 24 is formed on the upper surface of the SiC substrate 1. The p-type base region 8 is formed in a surface layer of the drift layer 24. The source electrode 5 is formed on the upper surface of the drift layer 24. The drain electrode 13 is formed on the lower surface of the SiC substrate 1. Here, a region in which a switching element that switches between the source electrode 5 and the drain electrode 13 is formed is defined as an element region 14. A region surrounding the element region 14 in a planar view is defined as a boundary region 15. A region surrounding the boundary region 15 in a planar view is defined as a termination region 16. The source electrode 5 overlaps with the element region 14 in a planar view. The element region 14 includes an n-type source region 7 partially formed in a surface layer of the base region 8, at least one element region trench 19 extending from an upper surface of the source region 7 to the interior of the drift layer 24, an element region gate electrode 2 surrounded by a gate insulating film 11 inside the element region trench 19, and a p-type element portion sidewall base region 9 formed on the sidewall of the element region trench 19. The boundary region 15 includes at least one boundary region trench 20 extending from an upper surface of the base region 8 to the interior of the drift layer 24, a boundary region gate electrode 3 surrounded by a gate insulating film 11 inside the boundary region trench 20, and a p-type boundary portion sidewall base region 22 formed on the sidewall of the boundary region trench 20. The termination region 16 includes at least one termination region trench 21 extending from an upper surface of the base region 8 to the interior of the drift layer 24, and a p-type termination portion sidewall base region formed on the sidewall of the termination region trench 21. Here, the termination sidewall base region corresponds to, for example, termination sidewall base region 12, termination sidewall one-side base region 29, etc. The p-type concentration of element sidewall base region 9 is higher than the p-type concentration of termination sidewall base region 12.

[0329] With this configuration, the device region 14, where current easily flows when a high voltage is applied, and the termination region 16, where the impact ionization rate is high, are separated by the boundary region 15. This increases the distance between the current concentration point and the high ionization rate point, making avalanche breakdown less likely to occur and increasing the breakdown voltage of the semiconductor device. Furthermore, the distance between the source electrode 5 and the edge of the chip can be increased, thereby suppressing the occurrence of discharge. Furthermore, because the p-type concentration of the boundary sidewall base region 22 is higher than the p-type concentration of the termination sidewall base region 12, potential is transmitted to the high-concentration boundary sidewall base region 22, even without covering the surface with a source electrode, and the entire boundary region 15 becomes the source potential, thereby suppressing potential changes along the main surface. Furthermore, since the p-type concentration of the element sidewall base region 9 is higher than the p-type concentration of the termination sidewall base region 12, the element sidewall base region 9 has the role of connecting the source electrode 5, the surface base region 18, and the base region 8 at the same potential, while the termination sidewall base region 12 draws equipotential lines therefrom and can gradually relax the potential.

[0330] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0331] Furthermore, according to the embodiment described above, the power conversion device includes the above-mentioned semiconductor device, and also includes a conversion circuit 2201 that converts input power and outputs it, a drive circuit 2202 that outputs a drive signal to the semiconductor device for driving the semiconductor device, and a control circuit 2203 that outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202. With such a configuration, a high-voltage power conversion device can be realized.

[0332] <Regarding Modifications of the Multiple Embodiments Described Above> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0333] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0334] Furthermore, in at least one embodiment described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0335] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may be provided.

[0336] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to a part of a structure, and even cases where multiple components are provided in one structure.

[0337] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0338] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0339] Various aspects of the present disclosure are summarized below as appendices.

[0340] a first conductivity type semiconductor substrate; a first conductivity type drift layer formed on an upper surface of the semiconductor substrate; a second conductivity type diffusion region formed in a surface layer of the drift layer; an upper surface electrode formed on an upper surface of the drift layer; and a lower surface electrode formed on a lower surface of the semiconductor substrate, wherein an element region is an area where a switching element that switches between the upper surface electrode and the lower surface electrode is formed, an area surrounding the element region in a planar view is an boundary region, and an area surrounding the boundary region in a planar view is an termination region, wherein the upper surface electrode overlaps only the element region and the boundary region in a planar view, and wherein the element region comprises: a first conductivity type source region partially formed in a surface layer of the diffusion region; at least one element region trench extending from an upper surface of the source region to the inside of the drift layer; a gate insulating film disposed inside the boundary region trench; and a gate electrode disposed inside the boundary region trench, the gate insulating film being formed on the gate insulating film and surrounding the element region in a plan view.

[0341] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, further comprising a boundary sidewall base region of a second conductivity type formed on a sidewall of the boundary region trench.

[0342] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, further comprising a termination sidewall base region of a second conductivity type formed on a portion of a sidewall of the termination region trench, wherein the concentration of the second conductivity type in the termination sidewall base region is equal to the concentration of the second conductivity type in the element portion sidewall base region.

[0343] (Supplementary Note 4) The semiconductor device according to Supplementary Note 1 or 2, further comprising a termination sidewall base region of a second conductivity type formed on a sidewall of the termination region trench, wherein the concentration of the second conductivity type in the element sidewall base region is higher than the concentration of the second conductivity type in the termination sidewall base region.

[0344] (Supplementary Note 5) The semiconductor device according to Supplementary Note 3, further comprising a first conductivity type electric field spread prevention sidewall region formed in place of the termination sidewall base region on the sidewall of the termination region trench located farthest from the element region.

[0345] (Supplementary Note 6) The semiconductor device according to Supplementary Note 4, further comprising a first conductivity type electric field spread prevention sidewall region formed in place of the termination sidewall base region on the sidewall of the termination region trench located furthest from the element region.

[0346] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein a plurality of the boundary region trenches are provided, and the boundary region gate electrodes in the plurality of the boundary region trenches are electrically connected to each other.

[0347] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the boundary region gate electrode and the upper surface electrode are in ohmic contact.

[0348] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the semiconductor substrate is made of SiC.

[0349] (Supplementary Note 10) A semiconductor device according to any one of Supplementary Notes 1 to 9, wherein a plurality of the element region trenches are provided, a plurality of the boundary region trenches are provided, a plurality of the termination region trenches are provided, and the spacing between the boundary region trenches and the spacing between the termination region trenches are narrower than the spacing between the element region trenches.

[0350] (Supplementary Note 11) The semiconductor device according to any one of Supplementary Notes 1 to 10, wherein a plurality of the termination region trenches are provided, and the spacing between the termination region trenches increases with increasing distance from the element region.

[0351] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 1 to 11, further comprising: a first bottom base region of a second conductivity type formed on a lower surface of the element region trench; and a second bottom base region of the second conductivity type formed on a lower surface of the boundary region trench, wherein a width of the second bottom base region is wider than a width of the first bottom base region.

[0352] (Supplementary Note 13) The semiconductor device according to any one of Supplementary Notes 1 to 12, further comprising: a first bottom base region of a second conductivity type formed on a lower surface of the element region trench; and a third bottom base region of the second conductivity type formed on a lower surface of the termination region trench, wherein a width of the third bottom base region is wider than a width of the first bottom base region.

[0353] (Supplementary Note 14) The semiconductor device according to any one of Supplementary Notes 1 to 13, further comprising a plurality of fourth bottom base regions of a second conductivity type formed on a lower surface of the termination region trench, wherein widths of the fourth bottom base regions decrease with increasing distance from the element region.

[0354] (Supplementary Note 15) The semiconductor device according to any one of Supplementary Notes 1 to 14, further comprising a first conductivity type electric field spread prevention region formed in a surface layer of the drift layer surrounding all of the termination region trenches in a planar view, wherein the concentration of the first conductivity type in the electric field spread prevention region is equal to the concentration of the first conductivity type in the source region.

[0355] (Supplementary Note 16) The semiconductor device according to any one of Supplementary Notes 1 to 15, wherein the source region is formed in a surface layer of the diffusion region in the boundary region and the termination region.

[0356] (Supplementary Note 17) The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the thickness of the gate insulating film inside the boundary region trench is greater than the thickness of the gate insulating film inside the element region trench.

[0357] (Supplementary Note 18) The semiconductor device according to any one of Supplementary Notes 1 to 17, wherein the thickness of the gate insulating film inside the termination region trench is greater than the thickness of the gate insulating film inside the element region trench.

[0358] (Supplementary Note 19) The semiconductor device according to any one of Supplementary Notes 1 to 18, further comprising an edge termination gate electrode surrounded by the gate insulating film inside the edge termination trench.

[0359] (Supplementary Note 20) The semiconductor device according to any one of Supplementary Notes 1 to 19, further comprising a first insulating film filled inside the termination region trench.

[0360] (Supplementary Note 21) The semiconductor device according to any one of Supplementary Notes 1 to 20, wherein a plurality of the boundary region trenches are provided, and further comprising a second insulating film filled inside some of the boundary region trenches.

[0361] (Supplementary Note 22) The semiconductor device according to Supplementary Note 1, further comprising: a boundary sidewall base region of a first conductivity type formed on a sidewall of the boundary region trench; and a termination sidewall base region of a first conductivity type formed on a sidewall of the termination region trench.

[0362] a first conductivity type semiconductor substrate; a first conductivity type drift layer formed on an upper surface of the semiconductor substrate; a second conductivity type diffusion region formed in a surface layer of the drift layer; an upper surface electrode formed on an upper surface of the drift layer; and a lower surface electrode formed on a lower surface of the semiconductor substrate, wherein a region where a switching element that switches between the upper surface electrode and the lower surface electrode is formed is defined as an element region, a region surrounding the element region in a planar view is defined as a boundary region, and a region surrounding the boundary region in a planar view is defined as a termination region, wherein the upper surface electrode overlaps only the element region in a planar view, and wherein the element region comprises: a first conductivity type source region partially formed in a surface layer of the diffusion region; at least one element region trench extending from an upper surface of the source region to the inside of the drift layer; a gate insulating film formed on a sidewall of the boundary region trench; and a second conductivity type boundary sidewall base region formed on a sidewall of the boundary region trench. 10. A semiconductor device comprising: at least one boundary region trench extending from an upper surface of the diffusion region to an interior of the drift layer; a boundary region gate electrode surrounded by the gate insulating film within the boundary region trench; and a second conductivity type boundary sidewall base region formed on a sidewall of the boundary region trench; and in the termination region, at least one termination region trench extending from an upper surface of the diffusion region to an interior of the drift layer; and a second conductivity type termination sidewall base region formed on a sidewall of the termination region trench;

[0363] (Supplementary Note 24) The semiconductor device according to Supplementary Note 23, further comprising a source electrode formed on an upper surface of the source region, wherein the boundary region gate electrode and the source electrode are short-circuited.

[0364] (Supplementary Note 25) The semiconductor device according to Supplementary Note 1, further comprising a source electrode formed on an upper surface of the source region, wherein the boundary region gate electrode formed continuously inside the boundary region trench and on the upper surface of the source region is short-circuited to the source electrode.

[0365] (Supplementary Note 26) The semiconductor device according to Supplementary Note 25, wherein the top surface of the source region and the source electrode are not short-circuited.

[0366] (Supplementary Note 27) The semiconductor device according to Supplementary Note 1, wherein the diffusion region is not formed in the surface layer of the drift layer in the termination region.

[0367] APPENDIX 28. The semiconductor device of appendix 1, further comprising a third bottom base region of the second conductivity type formed on a lower surface of the termination region trench.

[0368] (Supplementary Note 29) The semiconductor device according to Supplementary Note 28, further comprising a termination sidewall base region of a second conductivity type formed on a sidewall of the termination region trench, wherein the termination sidewall base region is formed by scattering ion implantation in air or by implanting ions at an angle when forming the third bottom base region.

[0369] (Supplementary Note 30) The semiconductor device according to Supplementary Note 19, wherein the adjacent termination region gate electrodes in the termination region are electrically independent.

[0370] (Supplementary Note 31) The semiconductor device according to Supplementary Note 1, wherein the curvature of the chip corners of the termination region trench or the boundary region trench increases toward the outer periphery.

[0371] (Supplementary Note 32) A power conversion device comprising: a conversion circuit having a semiconductor device according to any one of Supplementary Notes 1 to 31, and converting and outputting input power; a drive circuit outputting a drive signal to the semiconductor device for driving the semiconductor device; and a control circuit outputting a control signal to the drive circuit for controlling the drive circuit.

[0372] 1 SiC substrate, 2 Element region gate electrode, 3 Boundary region gate electrode, 3A Boundary region gate electrode, 4 Termination region gate electrode, 4A Termination region gate electrode, 4B Termination region gate electrode, 5 Source electrode, 7 Source region, 8 Base region, 9 Element sidewall base region, 10 Bottom base region, 10A Bottom base region, 10B Bottom base region, 11 Gate insulating film, 12 Termination sidewall base region, 13 Drain electrode, 14 Element region, 15 Boundary region, 16 Termination region, 17 Interlayer insulating film, 18 Surface base region, 19 Element region trench, 20 Boundary region trench, 21 Termination region trench, 22 Boundary sidewall base region, 23 High impact ionization region, 24 Drift layer, 25 Trench resist, 26 Element sidewall base region resist, 27 Boundary sidewall base region resist, 28 Termination sidewall base region resist, 28A Resist for termination sidewall base region, 28B mask, 29 termination sidewall one-side base region, 29A termination sidewall one-side base region, 30 electric field spread prevention region, 31 electric field spread prevention sidewall region, 34 thick gate insulating film, 34A gate insulating film, 34B gate insulating film, 1000 trench, 1000A trench, 1000B trench, 1002 equipotential line, 1004 current flow direction, 2100 power supply, 2200 power conversion device, 2201 conversion circuit, 2202 drive circuit, 2203 control circuit, 2300 load.

Claims

a first conductivity type semiconductor substrate; a first conductivity type drift layer formed on an upper surface of the semiconductor substrate; a second conductivity type diffusion region formed in a surface layer of the drift layer; an upper surface electrode formed on the upper surface of the drift layer; and a lower surface electrode formed on a lower surface of the semiconductor substrate, wherein an element region is an area where a switching element that switches between the upper surface electrode and the lower surface electrode is formed, an area surrounding the element region in a planar view is an boundary region, and an area surrounding the boundary region in a planar view is an termination region, wherein the upper surface electrode overlaps only the element region and the boundary region in a planar view, and wherein the element region comprises: a first conductivity type source region partially formed in a surface layer of the diffusion region; at least one element region trench extending from an upper surface of the source region to the inside of the drift layer; a gate insulating film disposed inside the boundary region trench; and a gate electrode disposed inside the boundary region trench, the gate insulating film being formed on the gate insulating film and surrounding the element region in a plan view.

2. The semiconductor device according to claim 1, further comprising a boundary sidewall base region of a second conductivity type formed on a sidewall of said boundary region trench.

3. A semiconductor device according to claim 1 or 2, further comprising a termination sidewall base region of a second conductivity type formed on a portion of the sidewall of the termination region trench, wherein the concentration of the second conductivity type in the termination sidewall base region is equal to the concentration of the second conductivity type in the element sidewall base region.

4. A semiconductor device according to claim 1 or 2, further comprising a termination sidewall base region of a second conductivity type formed on the sidewall of the termination region trench, wherein the concentration of the second conductivity type in the element sidewall base region is higher than the concentration of the second conductivity type in the termination sidewall base region.

5. A semiconductor device according to claim 3, further comprising a first conductivity type field spread prevention sidewall region formed in place of said termination sidewall base region on the sidewall of said termination region trench located furthest from said element region.

6. A semiconductor device according to claim 4, further comprising a first conductivity type field spread prevention sidewall region formed in place of said termination sidewall base region on the sidewall of said termination region trench located furthest from said element region.

7. A semiconductor device according to any one of claims 1 to 6, wherein a plurality of the boundary region trenches are provided, and the boundary region gate electrodes in the plurality of boundary region trenches are electrically connected to each other.

8. A semiconductor device according to any one of claims 1 to 7, wherein the boundary region gate electrode and the upper surface electrode are in ohmic contact.

9. A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate is made of SiC.

10. A semiconductor device according to any one of claims 1 to 9, wherein a plurality of the element region trenches are provided, a plurality of the boundary region trenches are provided, a plurality of the termination region trenches are provided, and the spacing between the boundary region trenches and the spacing between the termination region trenches are narrower than the spacing between the element region trenches.

11. A semiconductor device according to any one of claims 1 to 10, wherein a plurality of the termination region trenches are provided, and the spacing between the termination region trenches increases with increasing distance from the element region.

12. A semiconductor device according to any one of claims 1 to 11, further comprising: a first bottom base region of a second conductivity type formed on the lower surface of the element region trench; and a second bottom base region of a second conductivity type formed on the lower surface of the boundary region trench, wherein the width of the second bottom base region is wider than the width of the first bottom base region.

13. A semiconductor device according to any one of claims 1 to 12, further comprising: a first bottom base region of a second conductivity type formed on the lower surface of the element region trench; and a third bottom base region of the second conductivity type formed on the lower surface of the termination region trench, wherein the width of the third bottom base region is wider than the width of the first bottom base region.

14. A semiconductor device according to any one of claims 1 to 13, further comprising a plurality of fourth bottom base regions of the second conductivity type formed on the lower surface of the termination region trench, the widths of the fourth bottom base regions narrowing with increasing distance from the element region.

15. A semiconductor device according to any one of claims 1 to 14, further comprising a first conductivity type electric field spread prevention region formed in the surface layer of the drift layer surrounding all of the termination region trenches in a plan view, wherein the concentration of the first conductivity type in the electric field spread prevention region is equal to the concentration of the first conductivity type in the source region.

16. A semiconductor device according to any one of claims 1 to 15, wherein the source region is formed in the surface layer of the diffusion region in the boundary region and the termination region.

17. A semiconductor device according to any one of claims 1 to 16, wherein the thickness of the gate insulating film inside the boundary region trench is greater than the thickness of the gate insulating film inside the element region trench.

18. A semiconductor device according to any one of claims 1 to 17, wherein the thickness of the gate insulating film inside the termination region trench is greater than the thickness of the gate insulating film inside the element region trench.

19. A semiconductor device according to any one of claims 1 to 18, further comprising an edge termination region gate electrode surrounded by the gate insulating film inside the edge termination region trench.

20. A semiconductor device according to any one of claims 1 to 19, further comprising a first insulating film filled inside the termination region trench.

21. A semiconductor device according to any one of claims 1 to 20, wherein a plurality of the boundary region trenches are provided, and further comprising a second insulating film filled inside some of the boundary region trenches.

22. The semiconductor device according to claim 1, further comprising: a boundary sidewall base region of a first conductivity type formed on a sidewall of the boundary region trench; and a termination sidewall base region of a first conductivity type formed on a sidewall of the termination region trench.

23. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on an upper surface of the semiconductor substrate; a diffusion region of a second conductivity type formed in a surface layer of the drift layer; an upper surface electrode formed on the upper surface of the drift layer; and a lower surface electrode formed on a lower surface of the semiconductor substrate, wherein a region in which a switching element that switches between the upper surface electrode and the lower surface electrode is formed is defined as an element region; a region surrounding the element region in a planar view is defined as a boundary region; and a region surrounding the boundary region in a planar view is defined as a termination region, wherein the upper surface electrode overlaps only the element region in a planar view, and wherein the element region comprises: a source region of the first conductivity type partially formed in a surface layer of the diffusion region; at least one element region trench extending from an upper surface of the source region to the inside of the drift layer; an element region gate electrode surrounded by a gate insulating film inside the element region trench; and an element portion sidewall base region of a second conductivity type formed on a sidewall of the element region trench, and wherein in the boundary region, a gate insulating film formed on a sidewall of the boundary region trench; and a second conductivity type boundary sidewall base region formed on a sidewall of the boundary region trench.

10. A semiconductor device comprising: at least one boundary region trench extending from an upper surface of the diffusion region to an interior of the drift layer; a boundary region gate electrode surrounded by the gate insulating film within the boundary region trench; and a second conductivity type boundary sidewall base region formed on a sidewall of the boundary region trench; and in the termination region, at least one termination region trench extending from an upper surface of the diffusion region to an interior of the drift layer; and a second conductivity type termination sidewall base region formed on a sidewall of the termination region trench; 24. A semiconductor device according to claim 23, further comprising a source electrode formed on an upper surface of said source region, said boundary region gate electrode and said source electrode being short-circuited.

25. A semiconductor device according to claim 1, further comprising a source electrode formed on an upper surface of the source region, wherein the boundary region gate electrode formed continuously inside the boundary region trench and on the upper surface of the source region is short-circuited to the source electrode.

26. A semiconductor device according to claim 25, wherein the top surface of the source region and the source electrode are not short-circuited.

27. A semiconductor device according to claim 1, wherein the diffusion region is not formed in the surface layer of the drift layer in the termination region.

28. The semiconductor device of claim 1, further comprising a third bottom base region of the second conductivity type formed on a lower surface of said termination region trench.

29. A semiconductor device according to claim 28, further comprising a termination sidewall base region of the second conductivity type formed on a sidewall of the termination region trench, wherein the termination sidewall base region is formed by scattering ion implantation in air or by implanting ions at an angle when forming the third bottom base region.

30. A semiconductor device according to claim 19, wherein adjacent termination region gate electrodes in the termination region are electrically independent.

31. A semiconductor device according to claim 1, wherein the curvature of the chip corners of the termination region trench or the boundary region trench increases toward the outer periphery.

32. A power conversion device comprising a semiconductor device according to any one of claims 1 to 31, a conversion circuit that converts input power and outputs it, a drive circuit that outputs a drive signal to the semiconductor device for driving the semiconductor device, and a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit.

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