Cryogenic constant voltage generation circuit for quantum computing environment

Abstract

The present invention relates to a cryogenic constant voltage generation circuit for a quantum computing environment and, particularly, to a cryogenic constant voltage generation circuit for a quantum computing environment, the circuit enabling maintenance of a constant reference voltage not only in a room temperature area but also within a wide temperature range. A cryogenic constant voltage generation circuit for a quantum computing environment according to the present invention comprises a startup circuit and a main circuit, thereby enabling maintenance of a constant reference voltage not only in a room temperature area but also within a wide temperature range, wherein the startup circuit provides, when power is first applied, a constant current to turn on a transistor of the main circuit and cause the circuit to operate, and the main circuit generates a temperature-independent voltage by combining a voltage across a transistor exhibiting a CTAT component that decreases as an absolute temperature increases and is derived from a gate-source voltage of a MOSFET, and a voltage across a resistor exhibiting a PTAT component of a thermal voltage, the PTAT component increasing in proportion to the absolute temperature.

Description

Cryogenic constant voltage generation circuit for quantum computing environments

[0001] The present invention relates to a cryogenic constant voltage generation circuit for a quantum computing environment, and more particularly, to a cryogenic constant voltage generation circuit for a quantum computing environment capable of maintaining a constant reference voltage not only in the room temperature region but also in a wide temperature range.

[0002] Figure 1 is a diagram showing a conventional constant voltage generation circuit. As shown in Figure 1, conventionally, V is generated using a BJT element. be Complementary to Absolute Temperature (CTAT) components and V T By combining the PTAT (Proportional to Absolute Temperature) components, it maintains a temperature coefficient close to 0. In addition, it is implemented by generating the PTAT current through the 1-stage and receiving it with the Q3 (CTAT) of the 2-stage to generate the BGR (Bandgap Voltage Reference).

[0003] Here, V be The CTAT (Complementary to Absolute Temperature) component of a bipolar junction transistor (BJT) is the base-emitter voltage (V be ) and decreases as the absolute temperature (T) increases. This component appears between the base and emitter of the transistor in the circuit and can be observed through Q5. V T The PTAT (Proportional to Absolute Temperature) component of the thermal voltage (V T) and increases in proportion to the absolute temperature. In this circuit, it is typically generated by exploiting the collector current ratio of the matched transistors (Q1 and Q2), which is related to the emitter area ratio of the two transistors. In this circuit, Q1 and Q2 generate the PTAT current, which appears as the base-to-emitter voltage difference between the two transistors.

[0004] Q1 and Q2 have different emitter areas, which induce different base currents. This creates a PTAT current component. V be appears at the base-emitter junction of Q1 and Q2. Q4 creates a mirror for the base current of Q1, and Q5 creates a mirror for the base current of Q2. This causes a CTAT component to appear in the base-emitter voltage of Q5. Q3 is used to set the output voltage, and combines the PTAT currents generated by Q1 and Q2 with the CTAT voltage generated by Q5 to make the overall temperature coefficient close to zero. Consequently, the CTAT component appears in the base-emitter voltage of Q5, and the PTAT component is generated by the base-emitter voltage difference between Q1 and Q2. By appropriately combining these two components, a constant reference voltage is generated regardless of temperature.

[0005] This can output a constant voltage independent of PVT variation (Process, Voltage, Temperature variation), but at low temperatures, the current gain β decreases significantly, and the base resistance also increases, so there is a problem that a constant constant voltage cannot be generated using the existing method using BJT characteristics in an ultra-low temperature environment close to 0K. In addition, it does not have an advantage in fields that use low power.

[0006] [Prior Art Literature]

[0007] [Patent Document]

[0008] (Patent Document 1) Republic of Korea Patent Publication No. 2004-0102314 (December 4, 2004)

[0009] The purpose of the present invention is to propose an ultra-low temperature constant voltage generation circuit for a quantum computing environment that can maintain a constant reference voltage not only in the room temperature region but also in a wide temperature range in order to solve the above-described problem.

[0010] The ultra-low temperature constant voltage generation circuit for a quantum computing environment according to the present invention includes a startup circuit that provides a constant current when power is first applied to turn on a transistor of a main circuit and operate the circuit, and a main circuit that generates a temperature-independent voltage by combining a voltage across a transistor having a CTAT component that decreases as the absolute temperature increases with the gate-source voltage of a MOSFET and a resistor having a PTAT component of a thermal voltage that increases in proportion to the absolute temperature.

[0011] The startup circuit is disabled after the main circuit receives the bias voltage.

[0012] The main circuit is made up of MOSFETs with different widths, which generate PTAT currents, but the PTAT currents are generated by the current ratio caused by the difference in gate-source voltages.

[0013] The main circuit drives the MOSFET's operating region in the sub-threshold region, combining the voltage across Q5 with CTAT and the voltage across the resistor with PTAT to generate a temperature-independent voltage.

[0014] The main circuit fine-tunes the level of the reference voltage by adjusting the body voltage of the NMOS transistor through resistor trimming.

[0015] According to the present invention, all components (elements) of the circuit operate in a subthreshold region, thereby generating a reference voltage at low power. The subthreshold region refers to the operating region when the gate voltage of a transistor is lower than the threshold voltage. In this region, the leakage current passing through the transistor is very small, thereby reducing the power consumption of the entire circuit.

[0016] Furthermore, the cryogenic constant voltage generation circuit for quantum computing environments maintains a stable reference constant voltage even at cryogenic temperatures by setting the channel length of each device to be long. Transistors with long channel lengths have a low temperature coefficient, meaning that the electrical characteristics of the device do not change significantly with temperature changes.

[0017] Furthermore, the cryogenic constant voltage generation circuit for quantum computing environments can maintain a constant reference voltage not only at room temperature but also over a wide temperature range. This allows for consistent performance in both high and low temperature environments.

[0018] Figure 1 is a diagram showing a conventional constant voltage generation circuit.

[0019] FIG. 2 is a diagram illustrating an ultra-low temperature constant voltage generation circuit for a quantum computing environment according to one embodiment of the present invention.

[0020] FIG. 3 illustrates an ultra-low temperature constant voltage generation circuit for a quantum computing environment according to another embodiment of the present invention.

[0021] Hereinafter, a cryogenic constant voltage generation circuit for a quantum computing environment according to one embodiment of the present invention will be described with reference to the attached drawings.

[0022] FIG. 2 is a diagram illustrating an ultra-low temperature constant voltage generation circuit for a quantum computing environment according to one embodiment of the present invention.

[0023] As illustrated in FIG. 2, the ultra-low temperature constant voltage generation circuit for a quantum computing environment includes a startup circuit (110) and a main circuit (120).

[0024] The startup circuit (110) consists of MOSFETs M1, M2, M3, and M4 and initiates the circuit's operation when the power is turned on. Initially, V_out is 0, so M3 turns on, causing current to flow through the startup circuit. This current turns on Q1, initiating the main circuit's operation.

[0025] The startup circuit (110) of the ultra-low temperature constant voltage generation circuit for a quantum computing environment according to the present embodiment ensures that the circuit can start operating stably when the power is turned on.

[0026] Looking at the operation of the startup circuit (110), when power is applied, when power (VDD) is first applied, V_out is close to 0V, so initially, sufficient bias voltage is not yet formed in the main circuit.

[0027] In this state, M3 is placed at a relatively higher voltage than M4, which turns it on. As M3 turns on, current begins to flow through the startup circuit.

[0028] The current flowing through the startup circuit biases Q3, which turns on Q1 and initiates the main circuit. "Turning on" here means that the transistor is operating—that is, receiving sufficient voltage or current to send signals to other parts of the circuit.

[0029] When Q1 is turned on, the other transistors of the main circuit (120) also sequentially receive appropriate bias and begin to operate. This ultimately generates a stable voltage at V_out.

[0030] When the main circuit is operating normally, the voltage formed at V_out turns off the MOSFETs of the startup circuit, preventing the startup circuit from supplying any more current. The current flowing to M4 is not turned off, but a large resistor is connected to ensure that a low current flows. This is a measure to reduce power consumption, as the startup circuit is no longer needed. In other words, the startup circuit is no longer needed once the main circuit is sufficiently biased and operating normally, and is thereafter disabled.

[0031] In Fig. 2, t1, t2, t3, and t4 are labels indicating the order in which the biased current flows.

[0032] The main circuit (120) consists of Q1 - Q6 MOSFETs, R1, and R2.

[0033] Q1 receives current from M3 in the startup circuit and starts the main circuit. The drain of Q1 is connected to the gate of Q2, and the source is connected to VSS (ground).

[0034] Q2 is located at the point where the gates of Q1 and Q3 are connected. The drain of Q2 is connected to the gate of Q4, and the source is connected to VSS, just like Q1.

[0035] Q3 connects the gates of Q2 and Q6. Its drain is connected to the drain of Q5 and V_out, and its source is connected to VSS.

[0036] Q4 mirrors the drain current of Q2 to Q5. The source of Q4 is connected to the source of Q5, and the drain is connected to the gate of Q5.

[0037] Q5 receives the drain current of Q4 and generates the CTAT voltage. The drain and source of Q5 are connected to V_out and the source of Q4, respectively.

[0038] Q6 receives the gate of Q3 and combines the CTAT voltage of Q5 and the PTAT voltage through R2 to adjust the temperature-independent voltage V_out.

[0039] R1 is connected between the drain and source of Q6 and contributes to the stabilization of V_out.

[0040] R2 is connected between VSS and the source of Q6 and serves to generate the PTAT voltage.

[0041] VDD is the positive supply of the main circuit, connected to M1, M4, and the drains of Q3 and Q6. VSS is the negative supply (ground) of the main circuit, connected to the sources of Q1, Q2, Q3, Q4, Q5, and Q6. V_out is the final output of the main circuit, formed by the drains of Q3 and Q5 and R1.

[0042] This circuit is designed to generate a stable, temperature-independent voltage output through a complex feedback loop and biasing network. The startup circuit sets the initial bias conditions, and the main circuit maintains a constant reference voltage regardless of temperature changes.

[0043] In summary, the cryogenic constant voltage generation circuit for quantum computing environments utilizes the CTAT and PTAT characteristics to maintain accurate V_out. The startup circuit ensures that the circuit automatically starts when power is applied, and the main circuit maintains a constant output despite temperature fluctuations.

[0044] Looking at the operation of the main circuit (120), the main function of the main circuit is to generate a constant voltage (bandgap voltage) that is almost invariant to temperature. This minimizes the influence of temperature changes by combining PTAT (Proportional to Absolute Temperature) and CTAT (Complementary to Absolute Temperature) characteristics.

[0045] Regarding PTAT current generation, Q1 and Q2 are used to generate PTAT (Proportional to Absolute Temperature) current. They have different gate widths, resulting in different drain currents for a given gate voltage. This current difference increases with increasing temperature, generating the PTAT voltage.

[0046] Regarding CTAT voltage generation, Q5 has a CTAT (Complementary to Absolute Temperature) characteristic for the gate-source voltage (Vgs). This means that the voltage characteristic decreases as the temperature increases, and this is controlled by Q4. Q4 mirrors the drain current of Q2 to Q5, which generates the CTAT voltage.

[0047] Regarding voltage combination, Q3 and Q6 are used to combine the PTAT and CTAT. Q3 is affected by the PTAT current, and Q6 combines the CTAT voltage generated by Q5 with the PTAT voltage generated through R2. Combining these two effects produces a temperature-independent voltage, V_out.

[0048] Regarding the stabilization of the output voltage, Q6 provides the final output voltage V_out stabilized through R1 after combining CTAT and PTAT.

[0049] The entire circuit is powered from VDD, and the circuit is completed with VSS (ground).

[0050] The startup circuit of the cryogenic constant voltage generation circuit for a quantum computing environment according to the present embodiment provides an initial bias so that the main circuit can immediately start operating when the power is turned on, and the main circuit generates a constant voltage that maintains a constant value even when the temperature changes.

[0051] The ultra-low temperature constant voltage generation circuit for the quantum computing environment of Fig. 2 drives the operating region of the configured MOSFET in the sub-threshold region, and generates a temperature-independent voltage by combining the Vgs of Q5 having CTAT and the voltage across R2 having PTAT.

[0052] The circuit according to the present embodiment includes a main circuit (120) that generates a constant voltage that is not affected by temperature changes using CMOS technology, and a startup circuit (110) that provides the current required when the circuit first starts operating.

[0053] The important part here is that the gate-source voltage (Vgs) of Q5 in the main circuit and the voltage generated by resistor R2 have CTAT and PTAT characteristics.

[0054] With respect to the CTAT (Complementary to Absolute Temperature) voltage, Q5 operates in the sub-threshold region, which is when the gate voltage of the transistor is below the threshold voltage (Vth).

[0055] MOSFET operation in the subthreshold region tends to have a gate-source voltage that decreases with increasing temperature. This indicates that the transistor's current varies with temperature, exhibiting a CTAT characteristic in which Vgs decreases with increasing temperature.

[0056] Regarding PTAT (Proportional to Absolute Temperature) voltage, R2 has a PTAT characteristic, where the voltage across the resistor increases proportionally to the temperature. This occurs because the temperature coefficient of the resistor is positive.

[0057] As the temperature increases, the voltage drop generated by the current passing through the resistor increases, which causes the voltage across resistor R2 to have a PTAT characteristic.

[0058] Regarding temperature-independent voltage generation, the main circuit combines these two characteristics to generate a temperature-independent output voltage (Vout). By appropriately combining the CTAT and PTAT voltages, the respective effects of temperature changes can be offset.

[0059] For example, as temperature increases, the CTAT voltage decreases, but the PTAT voltage increases. By offsetting these two changes, a stable voltage (Vout) is obtained that is largely unaffected by temperature changes.

[0060] In other words, Vout remains relatively constant even when temperature changes. This is crucial for quantum computing environments that require a stable power supply even under ultra-low temperature conditions.

[0061] When implemented with the configuration of Fig. 2, the transfer function of the generated constant voltage can be expressed as follows.

[0062]

[0063]

[0064] Here, the transfer function presented is a constant voltage V generated in a CMOS bandgap reference circuit. ref It is. V gs·Q5 is the gate-source voltage of transistor Q5, 2.01 is a coefficient close to 2, which can reflect the size difference between two MOSFETs (Q6 and Q5) with different widths. That is, it is a constant representing the ratio of the channel widths of the two transistors (the current flowing through R1 divided by the current flowing through R2, a value that is independent of the channel width). n is a process variation coefficient, which is the current mirror ratio for the load transistor. W Q6 / L Q6 ,W Q5 / L Q5 represents the channel width to channel length ratio of transistors Q6 and Q5, respectively. V Tis the thermal voltage, which is proportional to the absolute temperature.

[0065] The first part of the transfer function is represents the PTAT (Proportional to Absolute Temperature) voltage component, which increases proportionally to temperature. The second part, V gs·Q5 represents the CTAT (Complementary to Absolute Temperature) component, which is inversely proportional to the temperature. By appropriately combining these two components, the voltage V ref It becomes almost invariant with temperature.

[0066] Note that the PTAT current is usually determined by the difference in gate-source voltage across the two MOSFETs, which is based on the ratio of the channel width (W) to length (L) of each transistor. This ratio is V T (critical voltage) and V GS (gate-source voltage) is used to calculate the reference voltage (V) of the entire circuit. ref ) contributes to.

[0067] In the PTAT voltage section, the natural logarithm of the ratios of WQ6 / LQ6 and WQ5 / LQ5 reflects the current ratio based on the difference in channel sizes of these two MOSFETs, which plays a significant role in determining the magnitude of the PTAT voltage. The value of 2.01 is used to reflect the actual circuit constant to account for the current change rate caused by this ratio. The value of 2.01 is a value representing the current ratio, and is rather related to the ratio of the widths of Q1, Q2, and Q3.

[0068] Accordingly, the ultra-low temperature constant voltage generation circuit for a quantum computing environment according to the present embodiment can provide a constant voltage reference that is robust to temperature changes, which enables electronic devices to operate stably in various environments.

[0069] In the main circuit (120) according to the present embodiment, the PTAT (Proportional To Absolute Temperature) current is based on the difference in current that typically occurs when two MOSFETs have different channel widths. In this configuration, one transistor Q_6 mirrors the other transistor Q_5, and different currents flow between the two drains due to the difference in physical dimensions (width W and length L) of these two transistors. The currents in the two branches are almost the same, because the current flows as a current mirror of the PMOS, and therefore the current difference due to the physical dimensions does not appear.

[0070] As temperature increases, the transistor's conductivity increases in proportion to its intrinsic carrier concentration, which increases with temperature. This results in a temperature-dependent increase in the ratio of the currents generated between the gate-source voltages VGS of Q_6 and Q_5. The current in Q_6 exhibits a PTAT characteristic compared to the current in Q_5, because the threshold voltages of both transistors vary with temperature.

[0071] Consequently, this difference in current flows through R1, and since the current increases in proportion to the temperature, the voltage drop across R1 forms the PTAT voltage. This PTAT voltage is combined with another voltage (e.g., the CTAT voltage) to create a stable reference V_out that is not affected by temperature changes.

[0072] The CTAT voltage according to this embodiment is generated by a circuit element having a Complementary to Absolute Temperature (CTAT) characteristic, which means a voltage that decreases as the temperature increases. The CTAT voltage is generated by the gate-source voltage (V_GS) of the MOSFET.

[0073] With respect to CTAT voltage generation, the gate-source voltage (V_GS) has a negative temperature coefficient (NTC). That is, as the temperature increases, this voltage decreases.

[0074] Regarding MOSFET operation in the subthreshold region, when the MOSFET operates in the subthreshold region, the gate-source voltage (V_GS) exhibits CTAT characteristics with respect to temperature. In the subthreshold region, the current increases exponentially between the source and drain, which is very sensitive to temperature. In this region, V_GS tends to decrease with temperature, and this decreasing voltage serves as the basis for the CTAT voltage.

[0075] Regarding the current through R2, the current flowing through the R2 resistor is determined by the V_GS of the MOSFET mentioned above. The voltage drop that occurs as this current passes through R2 exhibits a CTAT voltage characteristic that decreases with increasing temperature.

[0076] In the main circuit (120), the CTAT voltage is generated by V_GS of Q5, which is regulated by the current passing through R2 and ultimately contributes to V_out. The CTAT voltage is combined with the PTAT voltage and plays an important role in generating a stable voltage reference, i.e., a bandgap reference voltage, against temperature changes.

[0077] By adjusting the resistance value of the R2 element through the relationship in Equation 1 above, the temperature coefficient of the reference constant voltage can be adjusted to suit the situation.

[0078] Each sizing of the circuit in Fig. 2 can be summarized as follows.

[0079] NameWidthLengthMultiplierQ10.5um20um3Q20.5um20um300Q30.5um20um300Q40.5um20um3Q50.5um20um300Q60.5um20um400R11um12um×21R21um12um×111

[0080] The ultra-low-temperature constant voltage generation circuit for a quantum computing environment according to this embodiment can generate a reference voltage at low power by having all components (elements) of the circuit operate in the subthreshold region. The subthreshold region refers to the operating region when the gate voltage of a transistor is lower than the threshold voltage.

[0081] Additionally, the ultra-low temperature constant voltage generation circuit for quantum computing environments ensures a reference constant voltage with a low temperature coefficient even in the ultra-low temperature region by setting the channel length of each element long.

[0082] Furthermore, the cryogenic constant voltage generation circuit for quantum computing environments can maintain a constant reference voltage not only at room temperature but also over a wide temperature range. This allows for consistent performance in both high and low temperature environments.

[0083] That is, it has three main advantages: low power consumption, stable operation at extremely low temperatures, and constant voltage output over a wide temperature range.

[0084] Figure 3 illustrates a cryogenic constant voltage generation circuit for a quantum computing environment according to another embodiment of the present invention. As illustrated in Figure 3, the cryogenic constant voltage generation circuit for a quantum computing environment includes a main circuit (130) and a resistor trimming structure (140).

[0085] The main circuit (130) and resistance trimming structure (140) illustrated in Fig. 3 are part of a cryogenic constant voltage generation circuit for a quantum computing environment. The configuration and operation of this circuit are described as follows.

[0086] In the main circuit (130), a plurality of MOSFETs are connected to each other to perform a constant voltage generation function. V_DD is the positive power source of the circuit and is the voltage supplied to the drains of the multiple MOSFETs.

[0087] V_out is the output voltage of the circuit, which is set via several MOSFETs and resistors.

[0088] V_body is the body (substrate) voltage of the NMOS transistor, which is used to adjust the threshold voltage of the transistor.

[0089] In the operation of the main circuit (130), in relation to the generation of a constant voltage, the MOSFET receives power from V_DD and generates a constant V_out through a complex feedback mechanism.

[0090] In relation to the threshold voltage adjustment of the main circuit (130), the threshold voltage of the NMOS transistor is changed by adjusting V_body, thereby precisely controlling the level of V_out.

[0091] For reference, the feedback mechanism is explained as follows:

[0092] In relation to reference voltage generation, the main circuit (130) internally generates a reference voltage. This voltage is typically used for comparison with a base voltage, such as a bandgap reference. This reference voltage is designed to have temperature-independent characteristics, making it stable even under temperature changes.

[0093] The output voltage V_out is controlled by adjusting the voltage applied to the gate of the transistor. This gate voltage is set by a reference voltage.

[0094] Although not shown in the diagram, a feedback loop can be implemented to detect when the output V_out deviates from the target value and adjust the transistor's operation to compensate. For example, if the output voltage is detected to be too low, the feedback loop can adjust the transistor to allow more current to pass, thereby increasing the voltage.

[0095] This feedback loop continuously monitors and regulates the output voltage, ensuring that it remains stable. This regulation is automatic and maintains V_out constant despite temperature changes and other external conditions.

[0096] The connection relationship of the resistance trimming structure (140) is described as follows.

[0097] A trimming resistor is a resistor that allows for fine tuning of the circuit and is connected to the body voltage (V_body) of the NMOS transistor.

[0098] The trimming resistor of the NMOS transistor is connected to the body of the NMOS to allow adjustment of the body voltage.

[0099] In relation to voltage regulation, the threshold voltage of the NMOS transistor can be finely adjusted by adjusting V_body via a trimming resistor. This can affect the constant voltage level of the main circuit (130).

[0100] With regard to the feedback loop, V_out generated in the main circuit (130) is indirectly controlled by the resistor trimming structure (140). Changes in V_out can be corrected through V_body adjustment.

[0101] Regarding the adjustment via trimming resistors, V_body can be changed by adjusting the trimming resistors, which finely adjusts the operation of the transistor.

[0102] The operation of the resistance trimming structure (140) is described as follows.

[0103] The operating principle of the resistor trimming structure (140) is to adjust the threshold voltage of the NMOS transistor by adjusting V_body, thereby adjusting the level of the constant voltage generated in the main circuit (130). This adjustment compensates for errors caused by PVT fluctuations, thereby ensuring that the constant voltage is robustly maintained against temperature, process, and voltage changes.

[0104] According to this embodiment, in relation to adjustment through trimming, V_body can be changed by adjusting the resistance value, which adjusts the offset of the reference constant voltage.

[0105] In relation to PVT (Pressure, Voltage, Temperature) fluctuation compensation, the resistance trimming structure allows the error caused by PVT fluctuation to be compensated, allowing the circuit to maintain a constant constant voltage even under various environmental conditions.

[0106] VDD represents the positive supply voltage of the circuit, and Vbody represents the body (bulk) voltage. These two voltages provide the power necessary for the circuit to function properly. Vout is the circuit's output voltage, which is a bandgap reference that must remain stable over temperature changes. The labels t1, t2, and t3 indicate the order in which the biased current flows.

[0107] The main circuit (130) and resistor trimming structure (140) according to this embodiment are designed to provide a stable constant voltage in a quantum computing environment. The primary objective of this design is to maintain a constant constant voltage level despite temperature, process, and voltage variations, i.e., PVT variations. To achieve this, the circuit operates as follows.

[0108] In relation to the generation of a constant voltage of the main circuit (130), the main circuit generates a reference voltage using a number of transistors and a power supply VDD. This reference voltage depends on the threshold voltage of the number of transistors.

[0109] Regarding voltage regulation, the level of the reference voltage is finely adjusted by adjusting the body voltage (V_body) of the NMOS transistor. This directly affects the threshold voltage of the NMOS.

[0110] Regarding threshold voltage adjustment, the threshold voltage of a transistor determines the point at which the transistor begins to turn on. By adjusting (V_body), the main circuit changes the threshold voltage, thereby adjusting the level of the resulting constant voltage.

[0111] Regarding PVT variation compensation, PVT variation is a major factor affecting the performance of electronic devices. The main circuit must maintain a stable constant voltage despite these variations.

[0112] With respect to the resistor trimming structure (140), the resistor trimming structure may include a fixed resistor and a variable resistor (trimming resistor), thereby precisely controlling the body voltage of the NMOS.

[0113] Regarding variable resistors, the level of body voltage can be changed by adjusting the trimming resistor. This allows the level of constant voltage generated by the main circuit to be controlled.

[0114] In terms of compensation, resistance trimming can compensate for changes in threshold voltage due to process variations, changes in transistor performance due to temperature variations, and changes in power supply voltage.

[0115] The circuit according to this embodiment consists of a combination of MOSFET transistors. The MOSFETs are used for a function similar to a current mirror. The right side of the circuit represents a current mirror circuit. This circuit replicates the current generated in the left circuit section and transmits it to other parts of the circuit.

[0116] This ultra-low-temperature constant voltage generation circuit for quantum computing environments utilizes ultra-low-temperature band-gap constant voltage generation technology. It utilizes a resistor trimming structure to adjust the body voltage of the NMOS to control the level of the reference constant voltage. To ensure that the reference constant voltage remains temperature-independent, it consists solely of the NMOS threshold voltage. By adjusting the voltage applied to the body, the offset of the reference constant voltage is adjusted.

[0117] The main circuit (130) is composed of a main circuit that generates a reference constant voltage. The indicated Vout is the final output voltage of the circuit, which must maintain a value that is almost constant with temperature.

[0118] This circuit generates a reference voltage using the threshold voltage of an NMOS transistor, which varies with temperature. VDD is a positive supply, and Vbody represents the body (or bulk) voltage of the NMOS transistor.

[0119] Controlling the body voltage of an NMOS transistor affects its threshold voltage, which in turn affects the output voltage of the entire circuit. This allows for precise control of the constant voltage level.

[0120] A resistor trimming structure (140) is used to adjust the Vbody voltage. This structure can finely adjust the Vbody voltage, thereby adjusting the offset of the reference constant voltage.

[0121] In conclusion, the main circuit (130) performs the core function of generating a reference constant voltage, and the resistor trimming structure (140) adjusts the level of this reference constant voltage and reduces its sensitivity to temperature changes. This cryogenic constant voltage generation circuit for quantum computing environments enables precise voltage control even in cryogenic environments and ensures stable circuit operation over a wide temperature range.

[0122]

[0123] Here, V ref is the gate-source voltage V of transistor Q5 gs·Q5 Depends on V gs·Q5 is the overdrive voltage V ov·Q5 and threshold voltage V th is divided into . This equation is based on the reference voltage V ref To control the level of the threshold voltage V of transistor Q5 th Indicates that it can be adjusted.

[0124] Here, the threshold voltage V th is one of the basic characteristics of a transistor, and refers to the minimum value of the gate voltage at which the transistor switches to a conducting state.

[0125] That is, by adjusting the threshold voltage, the level of the constant voltage can be adjusted. This allows for compensation of errors caused by PVT variation. One way to compensate for the effects of PVT variation is to utilize the body effect. In the case of NMOS transistors, the threshold voltage can be changed by adjusting the voltage Vbody between the body and source.

Claims

1. A startup circuit that provides a constant current when power is first applied to turn on the transistors of the main circuit and make the circuit operate. An ultra-low temperature constant voltage generation circuit for a quantum computing environment, characterized by including a main circuit that generates a temperature-independent voltage by combining a voltage across a transistor having a CTAT component that decreases as the absolute temperature increases with the gate-source voltage of the MOSFET and a resistor having a PTAT component of thermal voltage that increases in proportion to the absolute temperature.

2. In paragraph 1, An ultra-low temperature constant voltage generation circuit for a quantum computing environment, characterized in that the above startup circuit is deactivated after the main circuit receives a bias voltage.

3. In paragraph 1, The above main circuit is an ultra-low temperature constant voltage generation circuit for a quantum computing environment, characterized in that it generates PTAT current by a current ratio generated by a difference in gate-source voltage using MOSFETs having different widths.

4. In paragraph 1, The above main circuit is an ultra-low temperature constant voltage generation circuit for a quantum computing environment, characterized in that it drives the operating region of the MOSFET in the sub-threshold region, and generates a temperature-independent voltage by combining the voltage of Q5 exhibiting CTAT and the voltage across the resistor exhibiting PTAT.

5. In paragraph 1, The above main circuit is an ultra-low temperature constant voltage generation circuit for a quantum computing environment, characterized in that it finely adjusts the level of the reference voltage by adjusting the body voltage of the NMOS transistor through resistor trimming.

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