CIM device and method using booth algorithm-based multiplier

Abstract

The present invention relates to a CIM device using a booth algorithm-based multiplier and an operation method therefor, the CIM device being a CIM using a booth algorithm for calculating an input array and a weight array, and comprising a booth encoder for converting the input array into a P value, an N value, and an S value, wherein the P value means whether a converted value of the input array is 0, the N value means whether the converted value of the input array is negative, and the S value means whether the converted value of the input array is x2. Accordingly, efficiency may be increased by using the booth algorithm, and accuracy may be increased by performing a digital-based operation, thereby making it possible to implement a digital CIM with high efficiency and low power.

Description

CIM device and method using a multiplier based on the Booth algorithm

[0001] The present invention relates to a CIM (Compute-in-Memory) device using a Booth algorithm-based multiplier, and more particularly, to a CIM device and method using a Booth algorithm-based multiplier for improving the in-memory computational efficiency of a CIM circuit.

[0002] Fig. 1 shows a diagram of a 2T1C DRAM. It includes a WWL (120) (Write Word Line) for reading and writing data and a WBL (Write Bit Line) (110) for writing data, and M1 (130) is referred to as an access transistor. It also includes a RWL (Read Word Line) (150) and an RBL (Read Bit Line) (140) for reading data without loss, and M2 (160) is referred to as a readout transistor.

[0003] Compute-in-Memory (CIM) is a technology that reduces the computational burden on the CPU (Core Process Unit) by providing information processing capabilities within the memory itself, thereby reducing overall energy consumption.

[0004] CIM is divided into analog and digital methods. Analog CIM mainly drives all memory cells corresponding to one column, performs analog calculations in charge or current format, and then converts them into digital code using an Analog-to-Digital Converter (ADC) and outputs them. However, this method is difficult to obtain accurate values ​​due to noise or loss (leakage), and is inefficient in terms of operating time and power consumption because it requires high ADC resolution to achieve the target number of output bits or high accuracy.

[0005] CIM operates analogically, activating all cells connected to a column simultaneously and outputting signals based on the stored data. This then accumulates analog data in the column using either a charge or current method for computation. However, this computational method has the disadvantage of producing inaccurate results due to noise or loss. Furthermore, analog data cannot be read or reused as is, so it must be converted back into digital code using an ADC. While using a low-power ADC allows for lower power consumption, accuracy is reduced, creating a trade-off between accuracy and power consumption.

[0006] The present invention is intended to solve the above problems, and provides a CIM device and method using a Booth algorithm-based multiplier capable of implementing a high-efficiency, low-power digital CIM by increasing efficiency using the Booth algorithm tailored to a 2T1C cell and increasing accuracy through digital-based calculation.

[0007] According to one embodiment of the present invention, a CIM device using a Booth algorithm-based multiplier is a CIM using a Booth algorithm that calculates an input array and a weighted array, and includes a Booth encoder that converts the input array into a P value, an N value, and an S value, wherein the P value indicates whether a conversion value of the input array is 0, the N value indicates whether a conversion value of the input array is negative, and the S value indicates whether a conversion value of the input array is x2.

[0008] Additionally, the input array may be composed of an MSB portion and an LSB portion.

[0009] Additionally, the above booth encoder can also convert the MSB part after converting the LSB part.

[0010] In addition, the above booth encoder converts the input array into P value, N value, and S value according to Table 1, and A, B, and C are each bit of the LSB part or MSB part, respectively.

[0011] [Table 1]

[0012]

[0013] In addition, it includes a weighted array selector for selecting a weighted array, and when the P value is 0, the weighted array selector does not select the weighted array, and when the P value is 1, the weighted array selector may select the weighted array and transmit it to the read block.

[0014] In addition, the reading block may calculate the weighted array selected by the weighted array as it is when the N value is 0, and may calculate the weighted array selected by the weighted array by converting it to a negative number when the N value is 1.

[0015] The above reading block may calculate the weighted array selected by the weighted array as it is when the S value is 0, and may calculate the weighted array selected by the weighted array by shifting it when the S value is 1.

[0016] In addition, a CIM operation method using a multiplier based on a Booth algorithm, which is another embodiment of the present invention, is a CIM operation method using a Booth algorithm for calculating an input array and a weighted array, comprising: a step of a column selector selecting the input array; and a step of a Booth encoder converting the input array into a P value, an N value, and an S value, wherein the P value indicates whether a conversion value of the input array is 0, the N value indicates whether a conversion value of the input array is negative, and the S value indicates whether a conversion value of the input array is X2.

[0017] Additionally, the input array may be composed of an MSB portion and an LSB portion.

[0018] Additionally, the step of converting by the above booth encoder may be a step of converting the MSB part after converting the LSB part.

[0019] In addition, the above booth encoder converts the input array into P value, N value, and S value according to Table 1, and A, B, and C are each bit of the LSB part or MSB part, respectively.

[0020] [Table 1]

[0021]

[0022] Additionally, the weighted array selector may include a step of not selecting the weighted array when the P value is 0, and selecting the weighted array and transmitting it to the read block when the P value is 1.

[0023] In addition, the reading block may include a step of calculating the weighted array selected by the weighted array as it is when the N value is 0, and calculating the weighted array selected by the weighted array by converting it to a negative number when the N value is 1.

[0024] The above reading block may include a step of calculating the weighted array selected by the weighted array as it is when the S value is 0, and calculating the weighted array selected by the weighted array by shifting it when the S value is 1.

[0025]

[0026] The CIM device and method using a multiplier based on the Booth algorithm of the present invention enables implementation of a high-efficiency, low-power digital CIM by increasing efficiency using the Booth algorithm and increasing accuracy through digital-based calculation.

[0027]

[0028] Figure 1 shows a diagram of a 2T1C DRAM.

[0029] Figure 2 shows a block diagram of a digital CIM according to the present invention.

[0030] Fig. 3 shows a circuit diagram of a booth encoder (230) operating according to Table 1.

[0031] Figure 4 shows the calculation results according to the booth algorithm according to an embodiment of the present invention.

[0032] Figure 5 is a timing diagram showing the entire MAC operation process.

[0033]

[0034] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided only to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals designate like elements throughout the specification.

[0035] Embodiments described herein will be described with reference to cross-sectional and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of components are exaggerated for the purpose of effectively explaining the technical contents. Accordingly, the components illustrated in the drawings have a schematic nature, and the shapes of the components illustrated in the drawings are intended to illustrate specific forms of the components and are not intended to limit the scope of the invention. Although terms such as first, second, and third are used to describe various components in various embodiments of the present specification, these components should not be limited by such terms. These terms are used only to distinguish one component from another. The embodiments described and illustrated herein also include complementary embodiments thereof.

[0036] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise. As used herein, the terms "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, operations, and / or elements to the mentioned components, steps, operations, and / or elements.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used in their common sense to those of ordinary skill in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0038] Hereinafter, with reference to the drawings, the concept of the present invention and embodiments thereof will be described in detail.

[0039] The DRAM cell of the present invention applies a 2T1C structure, uses WWL and WBL when writing, and uses RWL (150) and RBL (140) when reading to prevent loss of stored data.

[0040] Referring back to Figure 1, RBL (140) is set to 0V as an initial value, and when VDD voltage is applied to RWL (150), current may or may not flow to RBL (140) depending on whether the stored data is 0 or 1. At this time, when current flows, the voltage of the RBL (140) node increases, and when current does not flow, the voltage remains at 0V, so that data can be read.

[0041] The Booth algorithm is used for binary multiplication operations. It creates 3-bit groups, each sharing 1 bit depending on the multiplier value. Based on these groups, the multiplicand can be used as is, converted to its 2's complement, converted to a multiple of 2, or written as a zero value. Simply adding these rearranged values ​​yields the result of the multiplication. Therefore, by applying this algorithm, multiplication and addition can be performed simply by reading data from memory and performing the addition.

[0042] Fig. 2 shows a block diagram of a digital CIM according to the present invention. The proposed structure separates an input array (220) and a weight array (250), and instead of directly transmitting the input array (220) to the weight array (250), first converts the data into something easy to process through a Booth encoder (230) and then transmits it, thereby performing efficient operations. Here, the input array (220) acts as a multiplier, and the weight array (250) acts as a multiplicand.

[0043] In this case, when a signal is applied to RWL depending on whether the data of the readout transistor of the 2T1C DRAM is 0 or 1, the signal may or may not be output as is, so if the value obtained through the Booth algorithm is applied to RWL as is, a multiplication operation is possible.

[0044] In the case of 4-bit data of 1101 as shown in the first line of the input array (220) of Fig. 2, the first group (221) and the second group (222) are grouped so that one digit (the value "0" in this drawing) is duplicated and applied to the algorithm. In this case, the first group (221) is referred to as the MSB portion, and the second group (222) is referred to as the LSB portion. The second group (222) should originally be grouped into 3 bits, but it is applied to the algorithm assuming that there is 0 after 01. That is, the 4-bit number 1101 is divided into 110 and 010 and used.

[0045] The Booth encoder (230) reads the multiplier input, i.e., the input array, and converts a 4-bit signal into a 3-bit signal based on each RBL value. In this case, the Booth encoder (230) generates signals of P, N, and S according to the input-output relationship table of Table 1 below.

[0046]

[0047]

[0048] Accordingly, the MSB portion and the LSB portion are changed to P, N, and S signals, respectively, according to Table 1. Here, A, B, and C are each bit of the LSB portion or MSB portion, respectively.

[0049] For example, the MSB part 110 of 1101 in Fig. 2 is applied to A, B, and C in order. As a result, it changes to 1, 1, and 0 for P, N, and S. The LSB part 010 changes to 1, 0, and 0 for P, N, and S. The circuit diagram of the booth encoder (230) operating according to Table 1 is illustrated in Fig. 3.

[0050] When P, N, and S are output for inputs A, B, and C from the booth encoder (230), the 4-bit data is divided into a first bundle (221) and a second bundle (222) as shown in FIG. 2, and the MSB and LSB are encoded separately and output in order from the LSB portion. In this way, the input array (220) data is converted into P, N, and S values ​​and transferred to a maximum of 4 rows of the weighted array (250) to perform calculations.

[0051] The output P, ​​N, and S values ​​represent Pulse, Negative, and Shift, respectively, and are signals that enable direct calculation of 4-bit data according to the Booth algorithm. P represents whether the result of the 3-bit bundle according to the Booth algorithm is 0 or not. N represents whether the result of the 3-bit bundle according to the Booth algorithm is negative or positive. S represents whether the result of the 3-bit bundle according to the Booth algorithm contains x2 or not. The output P, ​​N, and S values ​​are transmitted to the row selector (240) of the weighted array (250) as illustrated in FIG. 2. In addition, the N and S values ​​are transmitted to the read-out block (260).

[0052] If the P value is low, the multiplicand becomes 0 according to the Booth algorithm, so the row selector (240) does not send a signal to the RWL of the weighted array (250), causing the reading block (260) to recognize it as 0. Conversely, if the P value is high, the row selector (240) sends a signal to the RWL of the weighted array (250), thereby reading the data of the weighted array (250).

[0053] Next, if both N and S are low, it means that 'the multiplicand is neither negative nor has a double value' according to the Booth algorithm, so the data of the weighted array (250) is used as is.

[0054] When N is low and S is high, it means that 'the multiplicand is not negative and has a value twice', so the data in the weighted array (250) is used by shifting it by one digit. For example, 0101 (5) becomes 01010 (10).

[0055] When N is high and S is low, it means that 'the multiplicand is negative and does not have a double value', so the data of the weighted array (250) is used in 2's complement form. For example, 0101 (5) becomes 1011 (-5).

[0056] Finally, if both N and S are high, it means 'the multiplicand is negative and has a value of 2', so the data of the weighted array (250) is converted to 2's complement and then shifted by one digit and used. For example, 0101 (5) becomes 10110 (-10). Consequently, the 4-bit data of the weighted array (250) is converted to 5-bit and output.

[0057] For example, consider the case where the first row of the input array (220) and the first row of the weighted array (250) are multiplied, as shown in FIG. 2. 1101 of the input array (220) has a value of -3 according to 2's complement, and 0110 of the weighted array (250) has a value of 6. That is, when these two numbers are multiplied, a result of -18 should be obtained. In addition, 1101 of the input array (220) is converted to 110 for the MSB and 100 for the LSB, respectively, according to Table 1. The order is transmitted to the read block (260) starting from 100, which is the LSB.

[0058] Since P is 1, N and S are 0, if the value of the first row of the weighted array (250) is selected, 0110(6) is read as is and added. Then, the digits are shifted by two, and the MSB part, 110, is passed. Since P and N are 1, and S is 0, 0110(6) is converted to a negative number in 2's complement form and added. That is, it is changed to 1010(-6) and added.

[0059] In this way, when adding the initial 0110 and the two-digit shifted (x4) 1010, the MSB part is added by shifting by 2 bits as shown in Fig. 4.

[0060] Referring to Figure 4, the remaining surplus bits in the first digit are filled with "1" according to the 2's complement rule. However, in the case of a single calculation as in this example, the surplus bits are 3, but if the calculation is applied repeatedly, the number of calculated numbers itself increases, so the surplus bits can become smaller.

[0061] As a result, we get a 9-bit result of 111101110 on the system, which in 2's complement is the original value of -18.

[0062] To implement this, the read block (260) reads data from the weighted array (250) and includes a selector (261) that receives N, S signals from the booth encoder (230) and selects which signal to output.

[0063] As described above, the multiplicands are converted into 5-bits and output from the weighted array (250). That is, the Booth encoder (230) sequentially inputs from the LSB to the MSB, and the multiplicands converted into 5-bits from the weighted array (250) are repeatedly output. In each case, the multiplicands output are cyclically added using the main cache (263) and the digital adder (262). If only the addition is performed in this way, the result of the multiplication of the input data and the weighted data can be obtained because the data of the input array (220) has been converted according to the Booth algorithm. In addition, since the P, N, and S signals are applied to and operate on up to 4 rows of the weighted array (220), the result of adding all the multiplication results corresponding to the 4 rows can be obtained.

[0064] In addition, since a maximum of four 5-bit data items must be added in the process of performing cyclic addition, the digital adder (262) of Fig. 2 must be capable of performing at least 7-bit operations. Consequently, since the final output is a value obtained by adding the results of 4-bit and 4-bit multiplication four times, the main cache (263) of Fig. 2 must have a size of at least 9 bits.

[0065] The timing diagram of Fig. 5 shows the process of the entire MAC operation. First, a specific RWL of the input array (220) is selected and the corresponding value is read. Immediately thereafter, Booth encoding is performed for half a clock and stored in a shift register within the input unit. Then, each P, S, and N signal is transmitted to the weighted array and the weighting unit over one clock from the LSB. In this case, the weighted array selector (240) selects a specific RWL and reads the corresponding value each time. However, if P is 0, it is not read at all. Then, as soon as the value passed through the selector (261) is output, an addition is performed with the value fetched from the main cache (263). Comparison, summation, and reading the value from the main cache (263) are performed simultaneously for half a clock, and then the value is stored in the main cache (263) again for the next half clock. After this process is performed on the LSB of all values ​​read from the input array (220), the value stored in the main cache (263) is shifted by 2 bits to prepare an operation on the MSB. The shift operation is performed for one clock, during which the P, N, and S signals are stopped, and access to the weighted array (250) is also stopped. After that, the operation is completed by performing the same process on the MSB as on the LSB.

[0066] As described above, the present invention implements Process-In-Memory (PIM) technology in 2T1C DRAM using the Booth algorithm. While reading data from the input array, a Booth encoder is used to convert the data into P, N, and S for calculation in the weighted array according to the Booth algorithm. Based on this, multiplication and addition are performed simultaneously in the weighted array and the read block.

[0067] The circuit proposed in the present invention is preferably implemented to enable MAC operations for Core VDD = 1.8 V, 100 MHz System clock, and up to 4 combinations (4-bit x 4-bit).

Claims

1. As a CIM that uses the Booth algorithm to calculate the input array and the weighted array, A Booth encoder that converts the above input array into P values, N values, and S values, A CIM device using a multiplier based on the Booth algorithm, wherein the above P value means whether the conversion value of the input array is 0, the above N value means whether the conversion value of the input array is negative, and the above S value means whether the conversion value of the input array is x2.

2. In paragraph 1, A CIM device using a Booth algorithm-based multiplier, wherein the above input array is composed of an MSB part and an LSB part.

3. In paragraph 2, The above Booth encoder is a CIM device using a multiplier based on the Booth algorithm that converts the MSB part after converting the LSB part.

4. In paragraph 2, The above booth encoder converts the input array into P values, N values, and S values ​​according to Table 1 below. [Table 1] A CIM device using a multiplier based on the Booth algorithm, where A, B, and C in the above Table 1 represent each bit of the LSB or MSB portion, respectively.

5. In paragraph 1, A weighted array selector for selecting the above weighted array, If the above P value is 0, the weighted array selector does not select the weighted array, A CIM device using a Booth algorithm-based multiplier that selects the weighted array and transmits it to a read block when the above P value is 1.

6. In paragraph 5, The above reading block is, If the above N value is 0, the weighted array selected by the above weighted array is calculated as is, A CIM device using a multiplier based on the Booth algorithm, which calculates by converting the weighted array selected by the weighted array into a negative number when the above N value is 1.

7. In paragraph 5, The above reading block is, If the above S value is 0, the weighted array selected by the above weighted array is calculated as is, A CIM device using a multiplier based on the Booth algorithm, which calculates by shifting the weighted array selected by the weighted array when the above S value is 1.

8. A CIM operation method using a Booth algorithm that calculates an input array and a weighted array, a step of selecting the input array by a column selector; and A Booth encoder comprising a step of converting the input array into P values, N values, and S values, A CIM operation method using a multiplier based on the Booth algorithm, wherein the above P value means whether the conversion value of the input array is 0, the above N value means whether the conversion value of the input array is negative, and the above S value means whether the conversion value of the input array is X2.

9. In paragraph 8, A CIM operation method using a Booth algorithm-based multiplier, wherein the above input array is composed of an MSB part and an LSB part.

10. In paragraph 9, A CIM operation method using a Booth algorithm-based multiplier, wherein the step of converting the above Booth encoder converts the MSB part after converting the LSB part.

11. In paragraph 8, The above booth encoder converts the input array into P values, N values, and S values ​​according to Table 1 below. [Table 1] A CIM operation method using a multiplier based on the Booth algorithm, where A, B, and C in the above Table 1 are each bit of the LSB or MSB portion.

12. In paragraph 8, Weighted array selector, If the above P value is 0, the above weighted array is not selected, A CIM operation method using a Booth algorithm-based multiplier, comprising a step of selecting the weighted array and transmitting it to a read block when the above P value is 1.

13. In paragraph 12, The above reading block is, If the above N value is 0, the weighted array selected by the above weighted array is calculated as is, A CIM operation method using a multiplier based on the Booth algorithm, comprising a step of calculating by converting the weighted array selected by the weighted array into a negative number when the above N value is 1.

14. In paragraph 12, The above reading block is, If the above S value is 0, the weighted array selected by the above weighted array is calculated as is, A CIM operation method using a multiplier based on the Booth algorithm, comprising a step of calculating by shifting the weighted array selected by the weighted array when the above S value is 1.

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