Packaging module, electronic device, and preparation method for packaging module

Abstract

Embodiments of the present application provide a packaging module, an electronic device, and a preparation method for a packaging module. The packaging module comprises a substrate, at least one passive device based on the substrate being formed in the substrate; the substrate comprises an accommodating cavity, a chip being located in the accommodating cavity; and the substrate is one of a silicon substrate or a ceramic substrate. In the embodiments of the present application, the passive device is directly formed in the substrate, the space of the substrate can be effectively utilized, and external attachment to an outermost conductive structure of the packaging module is not needed; thus a packaging module having a higher level of integration can be obtained. Moreover, multiple passive devices prepared on the basis of the substrate are at a close distance, so that the line power loss of a circuit is reduced, while the problem of short circuiting can be effectively avoided by using the substrate as an insulating structure between the passive devices. The chip is also disposed in the accommodating cavity of the substrate, and there is a shorter distance between the chip and the passive device based on the substrate, such that an electrical connection between the chip and the passive device is easy to achieve, and signal loss is reduced.

Description

A packaging module, an electronic device, and a method for manufacturing the packaging module.

[0001] This application claims priority to Chinese Patent Application No. 202410540491.2, filed on April 30, 2024, entitled "A Packaging Module, Electronic Device and Method for Preparing Packaging Module", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor device technology, specifically to a packaging module, an electronic device, and a method for preparing the packaging module. Background Technology

[0003] Typically, complex circuits used to power devices and provide overall control are integrated into a single packaged module and then installed in the device. However, the market demand for packaged modules with high-density device integration is increasing. To meet the performance requirements of the packaged module while avoiding a significant increase in its size, a method has been proposed to embed chips and other devices into a printed circuit board within the packaged module, effectively reducing the size of the packaged module. Summary of the Invention

[0004] In view of this, this application provides a packaging module, an electronic device, and a method for manufacturing the packaging module, in order to solve the problems in the prior art.

[0005] In a first aspect, embodiments of this application provide a packaging module, including: a substrate and a chip, the chip being located within a cavity of the substrate, and at least one passive device based on the substrate being formed therein. Positioning the chip and passive device within the substrate helps reduce the size of the packaging module and decrease the space occupied by the packaging module in the device. Forming at least one passive device within the substrate using substrate materials and structures helps save consumables. The substrate is either a silicon substrate or a ceramic substrate. Using silicon or ceramic materials to form the substrate helps improve the performance of the packaging module in terms of heat dissipation, moisture resistance, high-temperature resistance, burn resistance, and electrostatic discharge prevention.

[0006] In one possible implementation of the first aspect, the packaging module further includes a filling structure, which is located within the receiving cavity and covers the chip, thus facilitating chip fixation.

[0007] In one possible implementation of the first aspect, the filling structure is flush with the surface of the substrate away from the chip surface, which helps to ensure that the substrate can provide a flat bearing surface for the subsequent film layers and improve the yield of the packaging module.

[0008] In one possible implementation of the first aspect, the filling structure is an organic material. Organic materials with good heat dissipation and moisture resistance can be selected as the filling structure, which helps to dissipate the heat generated during chip operation in a timely manner and helps to prevent the chip from being corroded by water and oxygen.

[0009] In one possible implementation of the first aspect, at least one passive device includes a resistor and / or a capacitor.

[0010] In one possible implementation of the first aspect, at least one passive device includes a device for implementing the filtering function. The device for the filtering function is also located in the substrate, which helps to reduce the distance between the chip and the filtering device and improves the filtering effect.

[0011] In one possible implementation of the first aspect, a first passive device, a second passive device, and an electrical connection structure are formed in the substrate, and the first passive device and the second passive device are electrically connected through the electrical connection structure. Having part of the electrical connection structure located in the substrate is beneficial for further reducing the size of the packaging module and for protecting the electrical connection structure in the substrate from external pulling forces and water / oxygen corrosion.

[0012] In one possible implementation of the first aspect, the cavity extends through the substrate, which helps to increase the space of the cavity, allowing for the placement of larger or multiple active devices.

[0013] In one possible implementation of the first aspect, the containment cavity does not penetrate the substrate, which helps to reduce the number of openings in the containment cavity and thus reduce the risk of water and oxygen seeping into the substrate from the containment cavity.

[0014] Secondly, embodiments of this application provide a method for preparing a packaging module, the method comprising:

[0015] A substrate is provided; at least one passive device based on the substrate is formed therein, and the substrate includes a receiving cavity;

[0016] The chip is fixed inside the receiving cavity.

[0017] One possible implementation of the second aspect is to provide a substrate, including:

[0018] Provide the initial substrate;

[0019] At least one passive device based on the initial substrate is formed in the initial substrate, and a receiving cavity is formed on the initial substrate to obtain the substrate.

[0020] In one possible implementation of the second aspect, the receiving cavity extends through the substrate and fixes the chip within the receiving cavity, including:

[0021] The carrier substrate is attached to one side of the substrate, and the carrier substrate covers the receiving cavity along the thickness direction perpendicular to the packaging module.

[0022] Place the chip inside the receiving cavity;

[0023] The cavity is filled with a filling structure and then cured.

[0024] Remove the substrate.

[0025] In one possible implementation of the second aspect, at least one passive device based on the initial substrate is formed in the initial substrate, including:

[0026] A first passive device, a second passive device, and an electrical connection structure are formed on the initial substrate. The first passive device and the second passive device are electrically connected through the electrical connection structure.

[0027] Thirdly, embodiments of this application provide an electronic device including the packaging module provided in the first aspect. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a schematic diagram of the ECP module provided in this application being applied to a power supply equipment scenario;

[0030] Figure 2 is a structural schematic diagram of a packaging module provided in an embodiment of this application;

[0031] Figure 3 is a structural schematic diagram of a packaging module provided in an embodiment of this application;

[0032] Figure 4 is a structural schematic diagram of a packaging module provided in an embodiment of this application;

[0033] Figure 5 is a schematic diagram of the structure of a packaging module provided in an embodiment of this application;

[0034] Figure 6 is a schematic diagram of the structure of a packaging module provided in an embodiment of this application;

[0035] Figure 7 is a flowchart illustrating the fabrication process of a packaging module according to an embodiment of this application;

[0036] Figure 8 is a flowchart illustrating the fabrication process of a packaging module provided in an embodiment of this application.

[0037] Figure 9 is a flowchart illustrating the fabrication process of a packaging module according to an embodiment of this application.

[0038] Figure 10 is a schematic diagram of the structure of a packaging module provided in an embodiment of this application;

[0039] Figure 11 is a flowchart of the manufacturing process of a packaging module provided in an embodiment of this application;

[0040] Figure 12 is a flowchart of the manufacturing process of a packaging module provided in an embodiment of this application. Detailed Implementation

[0041] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0043] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0045] Traditional integrated circuit packaging involves attaching the IC chip and other components to the surface of a printed circuit board. This packaging method limits the placement of the chip and other components, resulting in a larger integrated circuit package module size and thus occupying more equipment space, which is not conducive to improving the space utilization of the equipment.

[0046] To address the issue of large size in integrated circuit (IC) packaging modules, a packaging module that embeds the IC chip within a printed circuit board (PCB) has been proposed, known as an embedded chip package (ECP) module. Embedding the IC chip within the PCB effectively increases the space utilization of the PCB, thus resulting in a relatively smaller IC packaging module.

[0047] Figure 1 is a schematic diagram of the ECP module provided in this application being applied in a power supply equipment scenario.

[0048] As shown in Figure 1, the ECP module can be applied in the power supply device 100. Specifically, the ECP module can be located in the power supply module of the power supply device 100, and the ECP module and related components included in the power supply module can be attached to the same circuit board as the voltage converter, controller, external chips, etc. Because the power supply device 100 generates excessive heat, it generally also includes a heat sink.

[0049] However, embedding the chip of the circuit in the package module within the insulating dielectric layer of the printed circuit board (PCB) requires setting up cavities that penetrate multiple insulating dielectric layers to accommodate the chip, which is challenging. Furthermore, when passive components such as resistors and capacitors in integrated circuits are surface-mounted on the PCB, the difficulty of electrically connecting the embedded chip to the passive component increases. Similarly, when passive components such as resistors and capacitors in integrated circuits are also embedded in the PCB, cavities penetrating multiple insulating dielectric layers are still required to accommodate them. However, creating too many cavities penetrating multiple insulating dielectric layers on the PCB reduces the available space for component mounting, resulting in lower space utilization for component mounting on the PCB.

[0050] Figure 2 is a schematic diagram of the structure of a packaging module provided in an embodiment of this application.

[0051] This application provides a packaging module A, as shown in Figure 2, including a substrate A10, passive devices A20, and a chip IC, wherein at least a portion of the passive devices A20 and the chip IC are embedded in the substrate A10. Therefore, the substrate A10 serves not only as a bridge for electrical connection between the chip IC and the passive devices A20 and the packaging board, but also as a carrier for receiving the embedded passive devices A20 and the chip IC. It should be noted that the substrate A10 can be a single-layer structure, rather than a multi-layer structure formed by stacking multiple film layers.

[0052] A passive device A20 refers to an electronic component that can exhibit its characteristics without receiving an external power supply, such as a resistor, capacitor, or inductor. In the embodiments of this application, at least one passive device A20 based on the substrate A10 is formed in the substrate A10. The passive device A20 based on the substrate A10 means a passive device formed by relying on the substrate A10. For example, a portion of the substrate A10 serves as the insulating medium of the passive device A20, or a portion of the substrate A10 serves as the carrier of the passive device A20.

[0053] In some embodiments, if the substrate A10 is a silicon substrate and the passive device A20 includes a capacitor C, then the passive device A20, which serves as the capacitor C, can be a silicon capacitor with a portion of the silicon substrate as the insulating dielectric layer. Specifically, the fabrication process involves drilling holes in the substrate A10 to form structural spaces that respectively accommodate two capacitor plates. Conductive material is then filled into these structural spaces to form conductive electrode plates. The insulating dielectric between the two conductive electrode plates is the portion of the substrate A10 located between the two electrode plates.

[0054] In some embodiments, if the substrate A10 is a silicon substrate and the passive device A20 includes a resistor R, then the passive device A20 serving as the resistor R can be a silicon resistor with a portion of the silicon substrate as its carrier. Specifically, the fabrication process involves drilling holes in the substrate A10 to form a structural space to accommodate the resistor. Depending on the required resistance value, a suitable conductive material is filled into the drilled space to form a silicon resistor with a specific resistance value. The structural space accommodating the resistor can be spiral-shaped, in which case the formed silicon resistor is a wire-wound resistor, and the insulating framework of this wire-wound resistor is the portion of the substrate surrounded by the spiral-shaped structural space.

[0055] The method of forming passive device A20 in integrated circuit based on substrate A10 is advantageous for utilizing the material of substrate A10 to fabricate passive device A20, saving consumables and improving the space utilization of substrate A10, and making passive device A20 more stable.

[0056] In this embodiment, the substrate A10 includes a receiving cavity A101, and the chip IC is located within the receiving cavity A101. The size of the opening of the receiving cavity A101 can be set according to the size of the chip IC to be accommodated.

[0057] The passive device A20 based on substrate A10 can be at least partially embedded in substrate A10 and the chip IC is located in the receiving cavity A101. This can effectively utilize the space of substrate A10 without having to attach the chip IC and passive device A20 to the outermost conductive structure of the package module A. Therefore, a package module A with higher integration can be obtained.

[0058] The passive device A20 fabricated based on substrate A10 can be selectively placed according to the overall circuit structure. The distance between multiple passive devices A20 fabricated based on substrate A10 is relatively close, which reduces the power loss of the circuit. At the same time, the passive device A20 can use substrate A10 as an insulating structure to effectively avoid short circuit problems.

[0059] Since the IC chip is also housed within the substrate's receiving cavity A101, there is a shorter distance between the IC chip and the passive device A20 based on substrate A10, facilitating electrical connection and reducing signal loss. Furthermore, in some cases, the performance of the circuit containing the IC chip and the passive device A20 can be improved. For example, if the passive device A20 based on substrate A10 includes resistors and capacitors with filtering functions, a smaller distance between the IC chip and these filtering elements allows for better filtering of the signals transmitted and / or received by the IC chip.

[0060] In addition, other active devices besides the IC chip can also be placed in the cavity A101.

[0061] It should be noted that the chip IC located within the receiving cavity A101 can be connected to the substrate A101 through a fixing structure. For example, a filling structure is included between the chip IC and the substrate sidewalls surrounding the receiving cavity A101. The filling structure contacts and surrounds the substrate A101. It should also be noted that the passive device A20 formed based on the substrate A10 can be fabricated within the substrate A10 using the same material and structure, forming a structure where the substrate A10 surrounds the passive device A20. Generally, the passive device A20 within the substrate A10 incorporates a portion of the substrate A10 as part of itself, thus eliminating the need for a filling structure for fixation.

[0062] Current packaging methods that embed chips within printed circuit boards (PCBs) suffer from drawbacks. Because the insulating dielectric layer in PCBs is made of organic materials, and the thermal conductivity of this layer is typically below 0.5 W / (m·K), meaning it has high thermal resistivity, heat generated by the chip is difficult to dissipate, impacting chip performance. Furthermore, the melting point of the insulating dielectric layer in PCBs is usually below 400°C, making it prone to burn-through. Additionally, the high moisture absorption and poor moisture resistance of organic insulating dielectric layers can easily lead to micro-short circuits in the embedded chips.

[0063] In one embodiment of this application, the substrate A10 is either a silicon substrate or a ceramic substrate. The passive device A20 formed based on the substrate A10 can be either a passive device A20 formed on the silicon substrate A10 or a passive device A20 formed on the ceramic substrate. In this case, the passive device A20 formed based on the substrate A10 can be formed using semiconductor processes, such as photolithography to form a groove, followed by thin film deposition processes such as chemical vapor deposition to form a conductive structure. Furthermore, the receiving cavity A101 of the substrate A10 can be formed using semiconductor processes, such as dry etching or wet etching.

[0064] Silicon and ceramic substrates are both important semiconductor materials with excellent electrical and mechanical properties. Silicon and ceramic substrates, in particular, exhibit superior performance in high and low temperature resistance, electrical insulation, oxidation stability, hydrophobicity, and corrosion resistance. In the technical solution of this application, when substrate A10 is a silicon or ceramic substrate, its excellent insulation reduces the short-circuit risk between passive devices A20 formed on the silicon or ceramic substrate, and also reduces the short-circuit risk between the conductive structures on the upper and lower sides of the silicon substrate, effectively preventing electrostatic interference. The high-temperature resistance of silicon or ceramic substrates reduces the amount of heat generated during the operation of passive devices A20 and the IC chip, preventing high-temperature damage. Furthermore, silicon or ceramic substrates can block water and oxygen, thus reducing the risk of water and oxygen erosion damage to passive devices A20 and the IC chip located within the silicon or ceramic substrate's containment cavity. In addition, the heat generated by the passive device A20 fabricated on substrate A10 and the chip IC embedded in substrate A10 during operation can also be effectively dissipated by substrate A10.

[0065] Figure 3 is a schematic diagram of the structure of a packaging module provided in an embodiment of this application.

[0066] In one embodiment of this application, as shown in FIG3, the packaging module A includes a filling structure A30, which is located within a receiving cavity A101, i.e., the filling structure A30 is used to fill the receiving cavity A101 of the substrate A10. By providing the filling structure A30 within the receiving cavity A101 of the substrate A10, the filling structure A30 can fix the chip IC within the receiving cavity A101, stabilizing the chip IC within the receiving cavity A101 of the substrate A1 and preventing damage from shaking. Furthermore, the filling structure A30 can serve as a buffer structure between the chip IC and the side of the receiving cavity A101.

[0067] In one implementation, the filling structure A30 covers the chip IC. That is, after the chip IC is embedded in the receiving cavity A101, the filling structure A30 is filled into the receiving cavity A101 and covers the chip IC. Covering the chip IC with the filling structure A30 has two advantages: firstly, the filling structure A30 can more effectively fix the chip IC; secondly, it can prevent the film layer fabricated later on the substrate from damaging the chip IC.

[0068] In one embodiment of this application, continuing to refer to FIG3, the surface of the filling structure A30 away from the chip IC is flush with the surface of the substrate A10, that is, the filling structure A30 fills the receiving cavity A101 flat. This embodiment helps to ensure that the substrate A10 can provide a flat bearing surface for the subsequently prepared film layer, thereby improving the preparation yield of the packaging module A.

[0069] In one embodiment of this application, the filling structure A30 is an organic material. Using an organic material to fill the cavity A101 facilitates both filling the cavity A101 and fixing the IC chip, without damaging the IC chip within the cavity A101. Furthermore, the density of the filling structure A30 within the cavity A101 is relatively uniform. Specifically, the filling structure A30 can be one of polyethylene terephthalate (PET) or polyvinyl chloride (PVC).

[0070] In this embodiment, an organic material with good heat dissipation, good moisture resistance, and relatively high temperature resistance can be selected as the filling structure A30. This helps to dissipate the heat generated by the operation of the chip IC in a timely manner, avoids the accumulation of high temperature that could damage the components, and also helps to prevent the chip IC from being corroded by water and oxygen.

[0071] Of course, in some other embodiments, other materials may be selected as the filling structure A30 according to the material properties and actual usage requirements.

[0072] In one embodiment of this application, continuing to refer to Figures 2-3, at least one passive device A20 includes a resistor R and / or a capacitor C. The resistor R can be fabricated based on substrate A10; or the capacitor C can be fabricated based on substrate A10; or both resistor R and capacitor C can be fabricated based on substrate A10. In integrated circuits, resistor R and capacitor C are two frequently used components. Since at least a portion of resistor R and capacitor C are formed based on substrate A10, the number of surface-mount resistors R and capacitors C can be effectively reduced, and the area requirement for the package module A is lowered when other components are surface-mounted, effectively improving the integration density of the package module A. The above description focuses on using the material of substrate A10 as the insulating medium for resistor R and capacitor C, and will not be repeated here.

[0073] In one embodiment of this application, continuing to refer to Figures 2-3, at least one passive device A20 includes a device for implementing a filtering function. A chip IC is embedded in the substrate A10, which receives or outputs signals to external devices. The signals exchanged between the chip IC and the external devices should be accurate and effective; therefore, it is necessary to filter out signal noise, high-frequency waves, low-frequency waves, etc., to obtain useful signals. Thus, it is necessary to include a device with filtering functionality in the integrated circuit fabricated based on substrate A10.

[0074] In this application, at least one passive device A20 formed on substrate A10 is used to implement the filtering function, thus eliminating the need for or reducing the number of filtering devices outside substrate A10. For example, an RC filter circuit based on resistor R and capacitor C can be fabricated in substrate A10 to filter signals output or received by the chip IC. Alternatively, at least one capacitor C can be fabricated to filter out DC or AC signals when the circuit receives a power supply signal. Embedding both the chip IC and the filtering device within substrate A10 helps reduce the distance between the chip IC and the filtering device, thereby improving the filtering effect.

[0075] Figure 4 is a schematic diagram of another packaging module provided in the embodiment of this application.

[0076] In one embodiment of this application, as shown in FIG4, a first passive device A21, a second passive device A22, and an electrical connection structure A40 are formed in a substrate A10. The first passive device A21 and the second passive device A22 are electrically connected through the electrical connection structure A40. The first passive device A21 and the second passive device A22 belong to the passive device A20 formed on the substrate A10.

[0077] In this embodiment, an electrical connection structure A40 is fabricated in substrate A10 to electrically connect the first passive device A21 and the second passive device A22. The electrical connection structure A40 can be fabricated simultaneously with the first passive device A21 and / or the second passive device A22 based on substrate A10. The fabrication process of the electrical connection structure A40 is essentially the same as the fabrication process of the resistor R and / or capacitor C formed on substrate A10, and will not be repeated here. Furthermore, a filling structure can also be fabricated in the slots or openings that accommodate the conductive structure forming the electrical connection structure A40. The electrical connection structure is also embedded within substrate A10, avoiding excessive external space occupation and reducing the electrical connection paths between components embedded in substrate A40. Simultaneously, under the protection of substrate A10, the electrical connection structure A40 is less susceptible to external pulling, water and oxygen erosion, acid and alkali corrosion, etc., improving the long-term reliability of the electrical connection structure A40.

[0078] Of course, in some other embodiments, at least a portion of the conductive structure of the electrically connected first passive device A21 and second passive device A22 may be located on substrate A10, for example, it may be a metal interconnect structure spanning multiple passive dielectric layers including substrate A10.

[0079] Figure 5 is a structural schematic diagram of another packaging module provided in an embodiment of this application.

[0080] In one embodiment of this application, as shown in FIG. 5, the cavity A101 penetrates the substrate A10. That is, when the cavity A101 is formed, a through-hole structure is created in the thickness direction H of the cavity A101. This is beneficial for increasing the space of the cavity A101, allowing for the placement of larger chip ICs or multiple active devices under certain application requirements.

[0081] The IC chip inside the cavity A101 also needs to be electrically connected to other components (such as passive components A20) to transmit signals. When the cavity A101 penetrates the substrate A10, it is easy to make electrical connections between the IC chip inside the cavity A101 and the components disposed on both sides of the substrate A10 along its thickness direction H.

[0082] In one embodiment of this application, as shown in Figures 2-4, the receiving cavity A101 does not penetrate the substrate A10. That is, when the receiving cavity A101 is formed, no through-holes are created in the thickness direction H. This allows the chip IC to be fixed inside the substrate A10 using a portion of the substrate A10 as a carrier, which facilitates placing the chip IC within the receiving cavity A101 and improves the stability of the chip IC within the substrate A10. Furthermore, reducing the number of openings in the receiving cavity A101 helps reduce the risk of moisture seeping into the receiving cavity A101, thereby improving the operating performance of the chip IC.

[0083] Figure 6 is a schematic diagram of another packaging module provided in an embodiment of this application.

[0084] Furthermore, as shown in Figure 6, the packaging module A may also include, in addition to the substrate A10, an insulating dielectric layer C10 stacked with the substrate A10, and the insulating dielectric layer C10 is preferably an inorganic insulating layer. For example, the insulating dielectric layer C10 in the packaging module A can be a ceramic film formed from ceramic slurry, a glass film formed from glass slurry, etc.

[0085] The substrate A10 and the insulating dielectric layer C10 may include a metal interconnect structure, and adjacent insulating dielectric layers C10 may also include a metal interconnect structure. In addition, the outermost insulating dielectric layer C10 may also be used to surface mount component A60.

[0086] Figure 7 is a flowchart of the manufacturing process of a packaging module provided in an embodiment of this application.

[0087] This application provides a method for preparing a packaging module A, which can be used to prepare the packaging module A provided in any of the above embodiments. As shown in Figure 7, the preparation method includes:

[0088] B1: Provide a substrate A10. At least one passive device A20 is formed in the substrate A10 and the substrate A10 includes a receiving cavity A101.

[0089] The substrate A10 is a single-layer structure and can be either a silicon substrate or a ceramic substrate. The passive device A20 is a passive device such as a resistor R, capacitor C, and inductor formed based on the substrate A10.

[0090] B2: Fix the IC chip inside the receiving cavity A101.

[0091] Figure 8 is a flowchart illustrating the fabrication process of another packaging module provided in an embodiment of this application.

[0092] In one embodiment of this application, as shown in FIG8, a substrate A10 is provided, including:

[0093] B11: Provides the initial substrate A11.

[0094] The initial substrate A11 can be a silicon substrate or a ceramic substrate excluding devices.

[0095] B12: At least one passive device A20 based on the initial substrate A11 is formed in the initial substrate A11 and a receiving cavity A101 is formed on the initial substrate A11 to obtain substrate A10.

[0096] The step of creating the receiving cavity A101 can be performed simultaneously with some of the process steps in fabricating the passive device A20. For example, the spatial structure for creating the receiving cavity A101 and accommodating the passive device A20 can be fabricated simultaneously. Alternatively, the step of creating the receiving cavity A101 and the step of fabricating the passive device A20 can be performed at different times.

[0097] Figure 9 is a flowchart illustrating the fabrication process of another packaging module provided in an embodiment of this application.

[0098] In one embodiment of this application, as shown in FIG9, the receiving cavity A101 penetrates the substrate A10 and fixes the chip IC within the receiving cavity A101, including:

[0099] B21: The carrier substrate A50 is attached to one side of the substrate A10, and the carrier substrate A50 covers the receiving cavity A101 along the thickness direction H perpendicular to the packaging module A.

[0100] When the receiving cavity A101 penetrates the substrate A10, that is, when the receiving cavity A101 forms a through hole in the substrate A10 in the thickness direction H, a structure capable of supporting the chip IC is required to place the chip IC inside the receiving cavity A101. Therefore, before placing the chip IC in the receiving cavity A101, a carrier substrate A50 is provided to cover the receiving cavity A101. The carrier substrate A50 is used to support the chip IC placed inside the receiving cavity A101. The carrier substrate A50 can be attached to the lower surface of the substrate A10 in the thickness direction H, and the carrier substrate A50 can completely block the opening of the receiving cavity A101 on the side attached to the substrate A10, ensuring the reliable load-bearing capacity of the carrier substrate A50.

[0101] B22: Place the IC chip inside the receiving cavity A101.

[0102] When the chip IC is placed in the receiving cavity A101, it is supported by the carrier substrate A50, which prevents the chip IC from protruding from the surface of the substrate A10.

[0103] B23: Fill the cavity A101 with filling structure A30 and cure it.

[0104] The filling structure A30 is filled into the receiving cavity A101, at which point the carrier substrate A50 can simultaneously support the chip IC and the filling structure A30. The filling structure A30 can be filled until the side away from the chip IC is flush with the surface of the substrate A10. Then, the filling structure A30 is cured to fix it to the chip IC and the substrate A10, thereby fixing the chip IC in the receiving cavity A101.

[0105] B24: Remove the substrate A50.

[0106] After the solidified filling structure A30 is completed, the chip IC is also fixed inside the substrate A10. At this point, the carrier substrate A50 can be removed.

[0107] Figure 10 is a structural schematic diagram of another packaging module provided in an embodiment of this application.

[0108] In one embodiment of this application, as shown in FIG10, at least one passive device A20 based on the initial substrate A11 is formed in the initial substrate A11, including:

[0109] A first passive device A21, a second passive device A22, and an electrical connection structure A40 are formed on the initial substrate A11. The first passive device A21 and the second passive device A22 are electrically connected through the electrical connection structure A40.

[0110] As shown in Figure 10, when fabricating the first passive device A21 and the second passive device A22, an electrical connection structure A40 is prepared in the initial substrate A11 by means of opening holes, and a conductive material is filled in it, so that the first passive device A21 can be electrically connected to the second passive device A22 through the electrical connection structure A40.

[0111] In addition, after placing the IC chip inside the cavity A101 of the substrate A10 and fixing it with the filling structure A30, the IC component can be electrically connected to the passive device A20 in the circuit by opening the electrical connection structure A40, and finally the substrate A10 is electrically connected to the external device.

[0112] Figure 11 is a flowchart illustrating the fabrication process of another packaging module provided in an embodiment of this application.

[0113] Furthermore, as shown in Figure 11, the method for fabricating the packaging module provided in this application may further include:

[0114] B31: Fabricate traces on at least one surface of substrate A10; for example, as shown in FIG11, traces A40' are fabricated on the upper and lower surfaces of substrate A10 to form corresponding lines laid on substrate A10, and when fabricating traces A40' on the surface of substrate A10, electrical connection structures A40 for passive devices A20 located on both sides of substrate A10 can be formed in through-holes penetrating substrate A10. Conductive layers can be fabricated by chemical plating, electroplating, or printing, and the conductive layers can be patterned to form traces A40'.

[0115] B32: Fabricate a conductive post electrically connected to trace A40' on trace A40'. The conductive post can be made of the same material as trace A40'; for example, conductive post A41 can be a copper post. Conductive post A41 can be formed using an additive process.

[0116] B33: Prepare an insulating dielectric layer C10 stacked with substrate A10, wherein the insulating dielectric layer C10 exposes conductive pillars A41.

[0117] The insulating dielectric layer C10 can be prepared by printing and sintering the paste, and the thickness of the insulating dielectric layer C10 can be controlled to expose the conductive pillar A41.

[0118] B34: An outer layer trace A40' and pins are fabricated on the insulating dielectric layer C10, and the outer layer trace A40' is electrically connected to the conductive pillar A41. The fabrication method of the outer layer trace A40' can be the same as that of the trace A40' on the surface of the substrate A10, and will not be described in detail here.

[0119] B35: Surface mount component A60 is electrically connected to its pins. The surface mount component A60 can be electrically connected to its pins via soldering or adhesive bonding.

[0120] Figure 12 is a flowchart illustrating the fabrication process of another packaging module provided in an embodiment of this application.

[0121] Furthermore, as shown in Figure 12, the method for fabricating the packaging module provided in this application may also include:

[0122] B41: Fabricate traces A40' on at least one surface of substrate A10; for example, as shown in FIG12, traces A40' are fabricated on the upper and lower surfaces of substrate A10 to form corresponding lines laid on substrate A10, and when fabricating traces A40' on the surface of substrate A10, electrical connection structures A40 for passive devices A20 located on both sides of substrate A10 can be formed in through-holes penetrating substrate A10. Conductive layers can be fabricated by chemical plating, electroplating, or printing, and the conductive layers can be patterned to form traces A40'.

[0123] B42: Prepare an insulating dielectric layer C10 stacked with the substrate A10, and drill holes in the stacked insulating dielectric layer C10 to reserve the position of the connection trace A40'.

[0124] An insulating dielectric layer C10 can be prepared by printing and sintering a paste, and a through hole C11 can be formed on the insulating dielectric layer so that the trace A40' prepared on the insulating dielectric layer C10 can be electrically connected to the trace A40' formed in method B41.

[0125] B43: A conductive layer is prepared on the entire surface of the insulating dielectric layer. The conductive layer can be prepared by chemical plating, electroplating, or printing, wherein a portion of the conductive layer is filled with through-holes C11 during the preparation of the conductive layer.

[0126] B44: The conductive layer on the surface of the insulating dielectric layer C10 is patterned to form traces A40' and pins.

[0127] B45: Surface mount component A60 is electrically connected to its pins. The surface mount component A60 can be electrically connected to its pins via soldering or adhesive bonding.

[0128] It should be noted that the insulating dielectric layer located on one side of substrate A10 and stacked with substrate A10 can be a single layer, as shown in Figures 10 and 11, or it can be multiple layers. When the insulating dielectric layer C10 located on one side of substrate A10 and stacked with substrate A10 is multiple layers, the traces between adjacent layers are also included.

[0129] This application provides an electronic device 100, including the packaging module A as described in the above embodiments. The electronic device 100 may be a power supply device, a host, or other device that requires the packaging module A, as shown in FIG1.

[0130] In electronic device B, substrate A10 includes a receiving cavity A101, and the chip IC is located within the receiving cavity A101. A passive device A20 based on substrate A10 can be at least partially embedded within substrate A10, with the chip IC located within the receiving cavity A101. This effectively utilizes the space of substrate A10 without requiring it to be externally mounted on the outermost conductive structure of package module A. Therefore, a package module A with higher integration can be obtained, and it helps to avoid a significant increase in the size of package module A.

[0131] The passive device A20 fabricated based on substrate A10 can be selectively placed according to the overall circuit structure. The close proximity between multiple passive devices A20 fabricated based on substrate A10 helps reduce the power loss of the circuit. At the same time, the substrate A10 can be used as an insulating structure between these passive devices A20 to effectively avoid short circuit problems.

[0132] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A packaging module, characterized in that, include: A substrate in which at least one passive device is formed; the substrate includes a receiving cavity; The chip is located within the receiving cavity; The substrate is either a silicon substrate or a ceramic substrate.

2. The packaging module according to claim 1, characterized in that, The packaging module also includes: A filling structure is located within the receiving cavity and covers the chip.

3. The packaging module according to claim 2, characterized in that, The surface of the filling structure away from the chip is flush with the surface of the substrate.

4. The packaging module according to claim 2, characterized in that, The filling structure is an organic material.

5. The packaging module according to any one of claims 1-4, characterized in that, The at least one passive device includes a resistor and / or a capacitor.

6. The packaging module according to any one of claims 1-5, characterized in that, The at least one passive device includes a device for implementing filtering functions.

7. The packaging module according to any one of claims 1-6, characterized in that, The substrate has a first passive device, a second passive device, and an electrical connection structure formed thereon, and the first passive device and the second passive device are electrically connected through the electrical connection structure.

8. The packaging module according to any one of claims 1-7, characterized in that, The receiving cavity extends through the substrate.

9. The packaging module according to any one of claims 1-7, characterized in that, The cavity does not penetrate the substrate.

10. A method for preparing a packaging module, characterized in that, The preparation method includes: A substrate is provided; at least one passive device based on the substrate is formed therein, and the substrate includes a receiving cavity; The chip is fixed inside the receiving cavity; The substrate is either a silicon substrate or a ceramic substrate.

11. The preparation method according to claim 10, characterized in that, Provide substrate, including: Provide the initial substrate; At least one passive device based on the initial substrate is formed in the initial substrate, and the receiving cavity is formed on the initial substrate to obtain the substrate.

12. The preparation method according to claim 10, characterized in that, The receiving cavity extends through the substrate; fixing the chip within the receiving cavity includes: The carrier substrate is attached to one side of the substrate, and the carrier substrate covers the receiving cavity along the thickness direction perpendicular to the packaging module; Place the chip inside the receiving cavity; The cavity is filled with a filling structure and then cured. Remove the carrier substrate.

13. The preparation method according to claim 11, characterized in that, The process of forming at least one passive device based on the initial substrate in the initial substrate includes: A first passive device, a second passive device, and an electrical connection structure are formed on the initial substrate, and the first passive device and the second passive device are electrically connected through the electrical connection structure.

14. An electronic device, characterized in that, Includes the packaging module as described in any one of claims 1-9.

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