Method for executing fast NTT, apparatus and computer device

Abstract

The embodiments disclosed in the present application belong to the technical field of computers, particularly relate to a method for executing a fast NTT, an apparatus and a computer device. The method is executed by a processor, and the method comprises: a processor receiving an execution instruction for a fast NTT sent by an application, and acquiring a data sequence on which the fast NTT will be executed; on the basis of a length value of the data sequence, determining in a candidate radix set radixes respectively corresponding to a plurality of calculation stages comprised in the fast NTT, the candidate radix set comprising a plurality of candidate radixes, and the value of each candidate radix being greater than 2 and being an integer power of 2; acquiring a twiddle factor corresponding to each calculation stage; and, on the basis of the data sequence and the twiddle factor corresponding to each calculation stage, successively executing the calculation stages so as to obtain a result of executing the fast NTT. Using the present application can improve the efficiency of executing fast NTTs.

Description

Method, device and computer equipment for performing fast NTT

[0001] The present application claims priority from the Chinese patent application No. 202410545086.X filed on April 30, 2024 and entitled "Method, device and computer equipment for performing fast NTT", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of computer, and in particular, to a method, device and computer equipment for performing fast NTT. BACKGROUND

[0003] Number-theoretical Transform (NTT) is a discrete Fourier Transform on the finite field of integers. Fast NTT is an efficient implementation of the Number-theoretical Transform.

[0004] Similar to Fast Fourier Transform (FFT), the calculation process of fast NTT can be divided into multiple calculation stages according to the divide-and-conquer method, and the calculation result of fast NTT can be obtained by executing the butterfly calculation included in each calculation stage by the processor in turn. The number of calculation stages is related to the base selected by the calculation stage. The smaller the base selected by each calculation node, the more the number of calculation stages included in the calculation process of fast NTT, and the higher the calculation complexity of fast NTT.

[0005] At present, a single base is generally used in the method for performing fast NTT, and the base of each calculation stage is set to 2 by default, which leads to low flexibility, high complexity and low efficiency of performing fast NTT. SUMMARY

[0006] The embodiments of the present application provide a method, device and computer equipment for performing fast NTT, which can improve the execution efficiency of fast NTT, and the corresponding technical solutions are as follows:

[0007] In a first aspect, a method for performing fast Number-theoretical Transform (NTT) is provided, which is executed by a processor. The method includes: receiving an execution instruction of fast NTT sent by an application program, and obtaining a data sequence to be subjected to fast NTT. Based on a length value of the data sequence, determining a base corresponding to each calculation stage included in the fast NTT from a candidate base set, wherein the candidate base set includes a plurality of candidate bases, and each candidate base has a value greater than 2 and is an integer power of 2. Obtaining a rotation factor corresponding to each calculation stage. Based on the data sequence and the rotation factor corresponding to each calculation stage, executing each calculation stage in turn to obtain a result of performing fast NTT.

[0008] In the scheme shown in the present application, before performing the fast NTT on the data sequence, the processor can determine each base of each calculation stage in the fast NTT in the candidate base set according to the length value of the data sequence. Since each candidate base included in the candidate base set is greater than 2, compared with directly determining the base of the calculation stage as 2, selecting the base of the calculation stage in the candidate base set can reduce the number of calculation stages, reduce the calculation complexity of each calculation stage, and further improve the flexibility and efficiency of performing the fast NTT.

[0009] In an implementable manner, based on the length value of the data sequence, determining the base corresponding to each calculation stage in the fast NTT in the candidate base set comprises: in the case that there is at least one candidate base in the candidate base set, whose integer power is equal to the length value, determining the base corresponding to each calculation stage in the at least one candidate base.

[0010] In the scheme shown in the present application, if there is a candidate base in the candidate base set, whose integer power is equal to the length value of the data sequence, it means that the candidate base can be used as the base of each calculation stage. When the base of each calculation stage is the same, the same set of rotation factors can be used for each calculation stage, which can reduce the calculation amount of the rotation factors and improve the efficiency of performing the fast NTT.

[0011] In an implementable manner, determining the base corresponding to each calculation stage in the at least one candidate base comprises: determining a first candidate base greater than or equal to a specified value in the at least one candidate base as the base corresponding to each calculation stage, wherein the specified value is equal to the ratio of the instruction bit width corresponding to the calculation instruction of the processor to the data bit width corresponding to each data in the data sequence.

[0012] The value of the base is the input data amount of the one butterfly calculation included in the calculation stage, and the ratio of the instruction bit width to the data bit width corresponding to each data in the data sequence is the maximum data amount that can be calculated in parallel by the calculation unit in the processor at one time. In this way, selecting the candidate base equal to or greater than the ratio can improve the utilization rate of the calculation performance of the calculation unit. In an example, the candidate base equal to the ratio or an integer multiple of the ratio can be selected.

[0013] In an implementable manner, based on the length value of the data sequence, the multiple calculation stages included in the fast NTT corresponding to the bases in the candidate base set respectively include: in the case that there is no candidate base in the candidate base set whose integer power is equal to the length value, the base of the first calculation stage in the multiple calculation stages is determined as 2. For other calculation stages in the multiple calculation stages, at least one candidate base corresponding to the integer power equal to one-half of the length value is determined in the candidate base set, and the other calculation stages correspond to the bases in the at least one candidate base respectively.

[0014] Generally, the length value of the data sequence is an integer multiple of 2, and if there is no candidate base in the candidate base set whose integer power is equal to the length value, the base of one calculation stage can be set as 2, so that the length value of the data sequence can be decomposed as 2*N / 2, where N is the length value of the data sequence. Since N is an integer power of 2, the remaining N / 2 is at least an integer power of 4. Therefore, the remaining N / 2 can be decomposed by the candidate bases in the candidate base set. In this way, the fast NTT can be performed in a mixed base manner, and the mixed base includes bases with values greater than 2, so that the number of calculation stages can be reduced, the calculation complexity of each calculation stage can be reduced, and the flexibility and efficiency of performing the fast NTT can be improved.

[0015] In an implementable manner, the first calculation stage is the first calculation stage or the last calculation stage in the multiple calculation stages.

[0016] In an implementable manner, in the at least one candidate base, the other calculation stages correspond to the bases in the at least one candidate base respectively, including: a second candidate base in the at least one candidate base greater than or equal to a specified value is determined as the base corresponding to the other calculation stages respectively, where the specified value is equal to the ratio of the instruction bit width corresponding to the calculation instruction of the processor to the data bit width corresponding to each data in the data sequence. In this way, the candidate base equal to or greater than the ratio is selected, and the utilization rate of the calculation performance of the calculation unit can be improved.

[0017] In an implementable manner, the processor includes a data carrying unit and a data operation unit, and based on the data sequence and the rotation factor corresponding to each calculation stage, each calculation stage is sequentially executed to obtain the result of performing the fast NTT, including: for each calculation stage, the data carrying unit inputs the input data of the calculation stage and the corresponding rotation factor to the data operation unit, where the input data of the first calculation stage is the data sequence, and the input data of each calculation stage after the first calculation stage is the output data of the corresponding previous calculation stage; the data operation unit performs butterfly calculation on the input data and the rotation factor to obtain the output data of each calculation stage, where the output result of the last calculation stage is the result of performing the fast NTT.

[0018] In an implementable manner, the corresponding rotation factors of each calculation stage are stored according to the first storage order and the second storage order respectively, wherein, when the corresponding rotation factors of each calculation stage are stored according to the first storage order, the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when the fast NTT is performed according to the time domain decimation manner, and when the corresponding rotation factors of each calculation stage are stored according to the second storage order, the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when the fast NTT is performed according to the frequency domain decimation manner.

[0019] The data carrying unit inputs the input data and the corresponding rotation factors of each calculation stage into the data operation unit, and includes:

[0020] In the case of performing the fast NTT according to the time domain decimation manner, for each calculation stage, the data carrying unit reads the input data of the calculation stage and the rotation factors stored according to the first storage order, and inputs the read input data and the rotation factors into the data operation unit. In the case of performing the fast NTT according to the frequency domain decimation manner, for each calculation stage, the data carrying unit reads the input data of the calculation stage and the rotation factors stored according to the second storage order, and inputs the read input data and the rotation factors into the data operation unit.

[0021] In the embodiments of the present application, the rotation factors are stored according to the order of the input data when the fast NTT is performed according to the time domain decimation manner and the frequency domain decimation manner. In this way, the rotation factors in the corresponding storage order can be read according to the manner of performing the fast NTT. In this way, the non-continuous reading of the input data and the rotation factors can be avoided, and the efficiency of performing the fast NTT can be improved.

[0022] In a second aspect, an apparatus for performing fast NTT is provided, and the apparatus is configured in a processor, and includes:

[0023] The obtaining module is configured to receive an execution instruction of fast NTT sent by an application program, and obtain a data sequence to be subjected to fast NTT.

[0024] The candidate base selection module is configured to determine, based on a length value of the data sequence, a plurality of calculation stages included in the fast NTT to correspond to bases respectively in a candidate base set, wherein the candidate base set includes a plurality of candidate bases, and each candidate base has a value greater than 2 and is an integer power of 2.

[0025] The obtaining module is configured to obtain a rotation factor corresponding to each calculation stage.

[0026] The calculation module is configured to sequentially perform each calculation stage based on the data sequence and the rotation factor corresponding to each calculation stage, and obtain a result of performing fast NTT.

[0027] In an implementable manner, the selected base module is configured to: in the case that there is at least one candidate base whose integer power is equal to the length value in the candidate base set, determine the bases corresponding to the plurality of calculation stages respectively in the at least one candidate base.

[0028] In an implementable manner, the selected base module is configured to: determine the first candidate base greater than or equal to a specified value in the at least one candidate base as the base corresponding to the plurality of calculation stages respectively, wherein the specified value is equal to the ratio of the instruction bit width corresponding to the calculation instruction of the processor to the data bit width corresponding to each data in the data sequence.

[0029] In an implementable manner, the selected base module is configured to: in the case that there is no candidate base whose integer power is equal to the length value in the candidate base set, determine the base of the first calculation stage in the plurality of calculation stages as 2. For the other calculation stages in the plurality of calculation stages, determine at least one candidate base corresponding to the integer power equal to one half of the length value in the candidate base set, and determine the bases corresponding to the other calculation stages respectively in the at least one candidate base.

[0030] In an implementable manner, the selected base module is configured to: determine the second candidate base greater than or equal to a specified value in the at least one candidate base as the base corresponding to the other calculation stages respectively, wherein the specified value is equal to the ratio of the instruction bit width corresponding to the calculation instruction of the processor to the data bit width corresponding to each data in the data sequence.

[0031] In an implementable manner, the first calculation stage is the first calculation stage or the last calculation stage in the plurality of calculation stages.

[0032] In an implementable manner, the processor comprises a data carrying unit and a data operation unit, and the calculation module is configured to: for each calculation stage, control the data carrying unit to input the input data of the calculation stage and the corresponding rotation factor to the data operation unit, wherein the input data of the first calculation stage is the data sequence, and the input data of each calculation stage after the first calculation stage is the output data of the corresponding previous calculation stage; control the data operation unit to perform butterfly calculation on the input data and the rotation factor to obtain the output data of each calculation stage, wherein the output result of the last calculation stage is the result of performing the fast NTT.

[0033] In an implementable manner, the corresponding rotation factors of each calculation stage are stored according to the first storage order and the second storage order respectively, wherein the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when the fast NTT is performed according to the time domain decimation manner, and the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when the fast NTT is performed according to the frequency domain decimation manner.

[0034] The computing module is configured to: in the case of performing the fast NTT according to the time domain decimation manner, for each calculation stage, control the data carrying unit to read the input data of the calculation stage, the rotation factors stored according to the first storage order, and input the read input data and rotation factors to the data operation unit. In the case of performing the fast NTT according to the frequency domain decimation manner, for each calculation stage, control the data carrying unit to read the input data of the calculation stage, the rotation factors stored according to the second storage order, and input the read input data and rotation factors to the data operation unit.

[0035] In a third aspect, a processor is provided, which is configured to perform the method of the first aspect and / or any one of the first aspect.

[0036] In a fourth aspect, a computer device is provided, which includes a processor and a memory. The processor is configured to execute instructions stored in the memory, so that the computer device performs the method of the first aspect and / or any one of the first aspect.

[0037] In a fifth aspect, a computer program product is provided, which includes instructions, when executed by a processor of a computer device, cause the processor of the computer device to perform the method of the first aspect and / or any one of the first aspect.

[0038] In a sixth aspect, a computer readable storage medium is provided, which includes computer program instructions, when executed by a processor of a computer device, cause the processor of the computer device to perform the method of the first aspect and / or any one of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is a flowchart of a fast NTT execution provided by an embodiment of the present application;

[0040] FIG. 2 is a schematic diagram of a calculation manner of a butterfly unit in a fast NTT according to an embodiment of the present application;

[0041] Figure 3 is a structural schematic diagram of a computer device for performing a fast NTT according to an embodiment of the present application;

[0042] Figure 4 is a flowchart of a method for performing a fast NTT according to an embodiment of the present application;

[0043] Figure 5 is a flowchart of a fast NTT execution according to an embodiment of the present application;

[0044] Figure 6 is a flowchart of a fast NTT execution according to an embodiment of the present application;

[0045] Figure 7 is a flowchart of a fast NTT execution according to an embodiment of the present application;

[0046] Figure 8 is a flowchart of a fast NTT execution according to an embodiment of the present application;

[0047] Figure 9 is a flowchart of a fast NTT execution according to an embodiment of the present application;

[0048] Figure 10 is a transposed structural schematic diagram of a method for performing a fast NTT according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0050] In order to facilitate the understanding of the method for performing a fast NTT according to the embodiments of the present application, some names involved in the embodiments of the present application will be explained first below:

[0051] Polynomial: a polynomial is an expression composed of variables and coefficients, such as f(x) = a0+ a1x+ … + a n-1 x n-1 . The variable can also be referred to as an indeterminate. Polynomials can be added, subtracted, multiplied, and divided. When a polynomial is expressed by a vector, the indeterminate is implicitly expressed, and only the coefficients [a0, a1, a2, …, a n-1 ] are recorded.

[0052] Dimension: the number of coefficients of a polynomial, or the number of elements of a vector, which is generally represented by n.

[0053] Modulus: a prime number represented by q, which is the modulus of the coefficients of a polynomial (the elements of a vector), i.e., the maximum value of the coefficients of a polynomial is q-1.

[0054] Number-theoretical transform (NTT): A polynomial can be represented in two ways, namely, in coefficient representation and in point-value representation. The former is the most common representation, while the latter is used in the NTT. The two representations have different advantages in polynomial arithmetic. The conversion between the two representations is called the NTT, which is a forward transform from the coefficient representation to the point-value representation and an inverse transform from the point-value representation to the coefficient representation. i i n

[0055] Fast NTT: The fast NTT is a fast algorithm of the NTT with a divide-and-conquer operation. The algorithm logic is similar to that of the fast Fourier transform (FFT).

[0056] Radix: Similar to the FFT, the fast NTT can be divided into multiple stages, each of which can include multiple blocks. The length of the input sequence of each block is the radix. The product of the radices of the multiple stages is equal to the length of the data sequence on which the fast NTT is performed.

[0057] Single instruction multiple data (SIMD): A traditional general-purpose processor is a scalar processor, and one instruction execution only obtains one data, namely, single instruction single data (SISD). The concept of SIMD is proposed in comparison with SISD, and has a significant performance gain for parallel operation of a large amount of data in images, signals, and encryption and decryption. The SIMD technology splits a certain bit register (such as 64 bits, 128 bits, etc.) into multiple 8-bit, 16-bit, and 32-bit forms to realize parallel computation of byte, half word, and word type data.

[0058] The roots of unity: A term in mathematics. If the smallest positive integer power n that satisfies ωn≡1(mod q) satisfies n|(q-1), ω is called the root of unity of q, and is also denoted as ωq. where q is the modulus of the polynomial, and n is the dimension of the polynomial.

[0059] The twiddle factors: The integers obtained by the different exponential powers (generally 0-n-1) of the roots of unity modulo q, where ​​​

[0060] Periodicity property: the rotation factor has a property of .

[0061] Binary property: the rotation factor has a property of .

[0062] Elimination property: the rotation factor has a property of .

[0063] Decimation-in-time (DIT): a way of calculating fast NTT, which means that the data sequence for which fast NTT is performed is decomposed in time domain, and generally, there is a certain step length between the elements of the data sequence.

[0064] Decimation-in-frequency (DIF): another way of calculating fast NTT, which means that the data sequence for which fast NTT is performed is decomposed in frequency domain, and generally, the elements of the data sequence are continuous.

[0065] Fig. 1 is a flowchart of an exemplary fast NTT performed in a way of decimation-in-frequency according to an embodiment of the present application. In Fig. 1, the data sequence for which fast NTT is performed has a length of 16, which is divided into two sub-sequences for solving, and then each sub-sequence is recursively divided in this way. In this way, the fast NTT includes four calculation stages, and the base of each calculation stage is 2. In an example, x(0)-x(15) in the data sequence for which fast NTT is performed are coefficients included in a polynomial. The execution result X(0)-X(15) of fast NTT is a point value representing the polynomial. 0 -W 7 are rotation factors in each calculation stage. In the fast NTT shown in Fig. 1, the first calculation stage includes one block, the block includes eight butterfly units, the second calculation stage includes two blocks, each block includes four butterfly units, the third calculation stage includes four blocks, each block includes two butterfly units, and the fourth calculation stage includes four blocks, each block includes one butterfly unit.

[0066] Fig. 2 is a schematic diagram of a calculation way of a butterfly unit in fast NTT according to an embodiment of the present application. As shown in Fig. 2, a and b are inputs of the butterfly unit, c and d are outputs of the butterfly unit, w1 and w2 are rotation factors corresponding to a and b, and q is a modulus corresponding to a polynomial. Wherein, c≡a+b*w1(mod q), d≡a+b*w2(mod q).

[0067] In some embodiments, when performing the fast NTT, the processor defaults the base of each calculation stage to 2 because the length of the data sequence performing the fast NTT is generally a power of 2, and the base cannot be adjusted according to the length of the data sequence performing the fast NTT, resulting in a large number of calculation stages in which the fast NTT is divided, high calculation complexity, and low efficiency of the processor performing the fast NTT.

[0068] In other embodiments, the fast NTT can also be performed by a field programmable logic gate array (FPGA). In the FPGA, a radix-4 base NTT core can be used to implement the radix-4 fast NTT calculation, which can improve the efficiency of performing the fast NTT compared with the processor performing the fast NTT based on radix-2. However, the FPGA cannot flexibly select the base of each calculation stage, and if the value of the base needs to be adjusted, the hardware also needs to be improved, and the flexibility is very low.

[0069] Embodiments of the present application provide a method for performing a fast NTT, which can flexibly select the base of each calculation stage according to the length of the data sequence performing the NTT, thereby improving the efficiency of the processor performing the fast NTT. FIG. 3 is a schematic diagram of the computer device structure of a method for performing a fast NTT according to an embodiment of the present application. As shown in FIG. 3, the computer device 100 includes a bus 102, a processor 104, a memory 106, and a communication interface 108. The processor 104, the memory 106, and the communication interface 108 communicate through the bus 102. The computer device 100 can be a server or a terminal device. It should be understood that the number of processors and memories in the computer device 100 is not limited in the present application.

[0070] The bus 102 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one line is shown in FIG. 3, but it does not mean that there is only one bus or only one type of bus. The bus 102 can include a path for transmitting information between the components (e.g., the memory 106, the processor 104, the communication interface 108) of the computer device 100.

[0071] The processor 104 can include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP), etc. In an example, the processor 104 can further include a vector operation unit or a matrix operation unit, which can be used to perform a butterfly calculation included in a fast NTT.

[0072] The memory 106 can include a volatile memory, such as a random access memory (RAM), and can further include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0073] The memory 106 stores executable program code, and the processor 104 executes the executable program code to implement a method for performing a fast NTT provided by an embodiment of the present application. For example, the method includes receiving an execution instruction of a fast NTT sent by an application program, and obtaining a data sequence to be subjected to the fast NTT. Based on a length value of the data sequence, a plurality of calculation stages included in the fast NTT are determined to correspond to bases in a candidate base set, respectively. A rotation factor corresponding to each calculation stage is obtained. Based on the data sequence and the rotation factor corresponding to each calculation stage, each calculation stage is executed in sequence to obtain a result of performing the fast NTT.

[0074] The communication interface 108 uses a transceiving module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 100 and other devices or communication networks.

[0075] FIG. 4 is a flowchart of a method for performing a fast NTT provided by an embodiment of the present application, which can be executed by the processor of the above computer device. Referring to FIG. 4, the method includes:

[0076] Step 401: receiving an execution instruction of a fast NTT sent by an application program, and obtaining a data sequence to be subjected to the fast NTT.

[0077] The application program is an application program related to fast NTT calculation. For example, the application program includes cryptographic applications, image processing, or signal processing, etc. In an example, the polynomial multiplication operation included in cryptography can be implemented by fast NTT calculation, the convolution operation included in image processing can be implemented by fast NTT calculation, and the signal coding included in signal processing can also be implemented by fast NTT calculation.

[0078] In implementation, during the running of the application program, when fast NTT calculation needs to be performed, an execution instruction of fast NTT can be sent to the processor. After receiving the execution instruction of fast NTT, the processor can read the data sequence to be executed for fast NTT from the memory of the computer device to the memory. The processor executing the application program and the processor executing the fast NTT can be the same processor or different processors. For example, during the execution of the application program on the processor of computer device A, when fast NTT calculation needs to be performed, the processor of computer device A can send the execution instruction of fast NTT and the corresponding data sequence to the processor of computer device B through the communication link between computer device A and computer device B, and then the processor of computer device B can perform fast NTT calculation on the received data sequence.

[0079] Step 402, based on the length value of the data sequence, determine the base corresponding to each calculation stage included in fast NTT in the candidate base set, wherein the candidate base set includes a plurality of candidate bases, and the value of each candidate base is greater than 2 and is an integer power of 2.

[0080] The length value of the data sequence is the number of elements included in the data sequence. Generally, the length value of the data sequence is an integer power of 2. The candidate base can be a base set by the technician in advance, for example, including 4, 8, 16, 32, etc. For the selection of candidate bases, the following two cases can be divided:

[0081] Case one: there is at least one candidate base in the candidate base set whose integer power is equal to the length value.

[0082] If there is a candidate base in the candidate base set whose integer power is equal to the length value of the data sequence, the candidate base can be determined as the base corresponding to each calculation stage. For example, the candidate base set includes 4, 8, and 16, and the length value of the data sequence is 64, wherein 64 is an integer power of 4 or 8, so 4 or 8 can be used as the base of each calculation stage.

[0083] The number of calculation stages included in the fast NTT is related to the base selected for the calculation stage. Continuing with the previous example, if 4 is selected as the base for the calculation stage, the fast NTT can be executed in three calculation stages. If 8 is selected as the base for each calculation stage of the fast NTT, the fast NTT can be executed in two calculation stages.

[0084] In an example, if there are multiple candidate bases whose integer powers are equal to the length value N in the candidate base set, the base corresponding to the maximum value among the multiple candidate bases can be selected as the base for each calculation stage. For example, in the previous example, the base for the calculation stage can be selected as 8. Selecting a larger candidate base as the base for the calculation stage can reduce the number of calculation stages, reduce the calculation complexity, and thus improve the efficiency of executing the fast NTT.

[0085] In another example, if there are multiple candidate bases whose integer powers are equal to the length value N in the candidate base set, the first candidate base greater than or equal to a specified value among the multiple candidate bases can be selected as the base corresponding to each calculation stage. The specified value is equal to the ratio of the instruction bit width corresponding to the calculation instruction of the processor to the data bit width corresponding to each data in the data sequence.

[0086] The processor includes a data operation unit, such as a vector operation unit or a matrix operation unit. The calculation instruction of the processor can be a SIMD instruction. The instruction bit width corresponding to the SIMD instruction is the number of bits of the data that can be executed in parallel by one instruction. The ratio of the instruction bit width corresponding to the SIMD instruction to the data bit width corresponding to each data in the data sequence is also the maximum amount of data that can be calculated in parallel by the data operation unit at one time. Since the value of the base is equal to the amount of input data of one butterfly unit in the calculation stage, when selecting the candidate base, the candidate base greater than or equal to the above ratio among the multiple candidate bases can be selected as the base for the calculation stage. In this way, using the SIMD instruction, the data operation unit (such as the vector operation unit) can be controlled to at least execute the butterfly calculation corresponding to one butterfly unit in the calculation stage in parallel, without wasting the performance of the vector operation unit, and the calculation efficiency of the butterfly calculation can be improved. In some embodiments, a candidate base that is an integer multiple of the above ratio can be selected. In this way, the vector operation unit can execute the butterfly calculation corresponding to each butterfly unit included in one block in batches, and each calculation will not waste the calculation performance of the vector operation unit, and the calculation efficiency of the butterfly calculation can be improved.

[0087] Case two: there is no candidate base whose integer power is equal to the length value in the candidate base set.

[0088] If there is no candidate base in the candidate base set whose integer power equals the length value of the data sequence, the base of the first calculation stage in the plurality of calculation stages can be determined as 2. The first calculation stage can be any calculation stage in the plurality of calculation stages. The length value N of the data sequence for which the fast NTT is performed is generally an integer power of 2. In the case where the length value N of the data sequence is not an integer power of 2, the length value N of the data sequence can be first decomposed by "base 2", that is, the base of one calculation stage in the plurality of calculation stages is determined as 2. Then the remaining calculation stages need to decompose N / 2, that is, the product of the bases of the remaining calculation stages needs to equal N / 2. Since N is an integer power of 2, N / 2 is at least an integer power of 4. That is, there is at least one candidate base in the candidate base set whose integer power equals half of the length value of the data sequence. Therefore, the bases of the remaining calculation stages can be determined in the candidate base set.

[0089] For example, the length value N of the data sequence is 128, and the candidate base set includes 4, 8, and 16. Since 128 is not an integer power of 4, 8, or 16, 128 can be first decomposed into 2*64, that is, the base of one calculation stage is first determined as 2, and the remaining calculation stages decompose 64. Since 64 is an integer power of 4 and 8, the base of each of the remaining calculation stages can be determined as 4 or 8. If the base of each of the remaining calculation stages is determined as 4, the data sequence with the length value of 64 can be decomposed into four calculation stages, and the corresponding bases are 2, 4, 4, and 4, respectively. If the base of each of the remaining calculation stages is determined as 8, the data sequence with the length value of 64 can be decomposed into three calculation stages, and the corresponding bases are 2, 8, and 8, respectively.

[0090] In an example, the first calculation stage can be the first calculation stage or the last calculation stage in the fast NTT calculation. That is, if there is no candidate base in the candidate base set whose integer power equals the length value, the base of the first calculation stage or the last calculation stage can be determined as 2, and the bases of the remaining calculation stages are determined as candidate bases greater than 2 and being an integer power of 2. In this way, on the one hand, when the FFT is performed using the mixed base, the number of calculation stages can be reduced, and the calculation amount of the rotation factor can be reduced. On the other hand, by setting the plurality of consecutive calculation stages to the same base, the rotation factor can be multiplexed, and the execution efficiency can be improved.

[0091] As shown in FIG. 5, when the first computing stage is the last computing stage, each computing stage before the first computing stage can be a fast NTT computation performed by k1 n / k1 points (k1 is the base of the last computing stage), and the base of each computing stage is k2. As shown in FIG. 6, when the first computing stage is the first computing stage, each computing stage after the first computing stage can be a fast NTT computation performed by k1 n / k1 points (k1 is the base of the first computing stage), and the base of each computing stage is k2.

[0092] It should be noted that if the length of the data sequence is not an integer power of 2, the length of the data sequence can be supplemented to an integer power of 2 by supplementing 0 at the end of the data sequence. For example, if the length of the data sequence is 60, four 0s can be supplemented at the end of the data sequence, and then the length of the data sequence is supplemented to 64.

[0093] Similarly, when selecting the base for other computing stages from the plurality of candidate bases, a candidate base greater than the specified value can be selected, for example, a candidate base equal to the specified value or an integer multiple of the specified value, so that the execution efficiency of the other computing stages can be improved.

[0094] In step 403, the rotation factor corresponding to each computing stage is obtained.

[0095] The rotation factor is an integer obtained by taking different exponential powers of the primitive root modulo q. The primitive root can be calculated according to q and n, where q is the modulus of the coefficients of the polynomial, and n is the dimension of the polynomial, that is, the length of the data sequence to be subjected to fast NTT. In implementation, after the base of each computing stage of fast NTT is determined, the rotation factor corresponding to the input data of each computing stage can be determined according to the primitive root.

[0096] The method for obtaining the rotation factor is described below:

[0097] For the polynomial , the calculation process of the DIT with the base k when n is an integer power of k is as follows (the calculation process below includes the "mod q" operation by default):

[0098] Similarly, the calculation process of the DIF is as follows:

[0099] where q is the modulus of the polynomial, j is the sequence number of the input data, ω is the primitive root of q, ω kij , ω i , ω i(k-1) , and so on are the rotation factors of each computing stage, and j is the sequence number of the input data.

[0100] In the calculation of the rotation factor, the periodicity, symmetry and elimination of the rotation factor can also be combined.

[0101] For example, take n = 16, then A = a0+a1x+…+a 15 x 15 mod q, k = 4, then according to the DIT mode:

[0102] According to the DIF mode:

[0103] In the case of using mixed bases to perform fast NTT, the rotation factor is calculated as follows:

[0104] DIT mode calculation of mixed bases divides the original n coefficients into k1 parts (k1 is the base of the first calculation stage), each part has coefficients, which are extracted from the original sequence every k1 positions to form:

[0105] For a single part (i.e. within the summation symbol“∑”), the NTT calculation with base k2 (k2 is the base of the first calculation stage) can be used; for multiple part results, the NTT calculation with base k1 can be used.

[0106] DIF mode calculation of mixed bases is similar to DIT, except that each part of the coefficient is extracted from the continuous position:

[0107] Where x is the rotation factor of each calculation stage, x = ω i , i = 0, 1, …, (n-1).

[0108] In an example, for the rotation factor of each calculation stage, it can be calculated according to the base of each calculation stage after determining the base of each calculation stage in the fast NTT.

[0109] In another example, since the length of the data sequence and the basis selection strategy are determined, the number of computation stages for the fast NTT, the basis of each computation stage, and the twist factor of each computation stage only change with the length of the data sequence. Therefore, in this embodiment, a skilled craftsman can pre-calculate the twist factor corresponding to each computation stage for data sequences of different lengths, and then the computer device executing the fast NTT can store the correspondence between the length value, the computation stage, and the twist factor. When the processor executes the fast NTT, after determining the basis corresponding to each computation stage, it can obtain the twist factor of each computation stage from the stored correspondence based on the length of the data sequence and the order of the computation stages. For example, the processor can obtain the twist factor of each computation stage from the stored correspondence based on the correspondence including 16—2—(w0~w 15 When the length of the data sequence is 16, the rotation factors corresponding to the input data in the second calculation stage are w0 to w0, respectively. 15 In this process, when pre-calculating the rotation factor corresponding to each computation stage for data sequences of different lengths, the basis for each computation stage can be determined according to the length value of the data sequence, and the determination method is the same as step 402.

[0110] Step 404: Based on the data sequence and the rotation factor corresponding to each computation stage, execute each computation stage in sequence to obtain the result of executing Fast NTT.

[0111] In implementation, after obtaining the twiddle factor for each computation stage, the processor can sequentially execute the butterfly calculations included in each computation stage to obtain the execution result of the fast NTT. After sequentially executing the butterfly calculations included in each computation stage, the processor can return the calculation result of the last computation stage as the result of executing the fast NTT to the application that sent the fast NTT execution instruction.

[0112] For a fast NTT with size n and basis k, the number of computational stages is logn. k The overall computational complexity is O(nlog n). k As shown in Figure 7, for a data sequence of length 16, the Fast NTT can be divided into two computational stages with a base of 4. Compared to dividing the Fast NTT into four computational stages as shown in Figure 1, this reduces the number of computational stages and lowers the computational complexity of each stage, thereby improving execution efficiency.

[0113] In an implementable manner, the processor can include a data carrying unit and a data operation unit, wherein the data carrying unit can read the data sequence, the rotation factor or the operation result of the data operation unit included in the memory, and input the read data sequence, the rotation factor or the operation result of the data operation unit to the data operation unit. The data operation unit can perform a butterfly calculation on the input data.

[0114] In order to further improve the execution efficiency of the calculation of the fast NTT, the rotation factor of each calculation stage can be stored in two storage sequences, including a first storage sequence corresponding to the time domain extraction and a second storage sequence corresponding to the frequency domain extraction.

[0115] When the corresponding rotation factor of each calculation stage is stored in the first storage sequence, the storage sequence of each rotation factor corresponds to the arrangement sequence of the input data of each calculation stage when the fast NTT is executed in the time domain extraction mode. When the corresponding rotation factor of each calculation stage is stored in the second storage sequence, the storage sequence of each rotation factor corresponds to the arrangement sequence of the input data of each calculation stage when the fast NTT is executed in the frequency domain extraction mode.

[0116] The storage sequence of the rotation factor of one calculation stage corresponding to the arrangement sequence of the input data of the calculation stage means that the rotation factor at the Nth position in the storage sequence needs to perform the rotation factor calculation included in the butterfly calculation with the input data at the Nth position in the arrangement sequence. The arrangement sequence of the input data is the storage sequence of the input data.

[0117] As shown in FIG. 8, when the 16-point fast NTT calculation is performed in a time-sequential manner, it can be divided into two calculation stages, and the base of each calculation stage is 4. The arrangement order of the input data of the first calculation stage can be x[0], x[4], x[8], x

[0012] , x[1], x[5], x[9], x

[0013] , x[2], x[6], x

[0010] , x

[0014] , x[3], x[7], x

[0011] , x

[0015] . In this case, the data carrying unit can continuously read the rotation factors of the first calculation stage stored in the first storage order. The first rotation factor read in this way is the rotation factor for calculating with x[0], the second rotation factor read is the rotation factor for calculating with x[4], and the Nth rotation factor read is the rotation factor for calculating with the Nth data in the input data. For example, in FIG. 8, the data carrying module can read the input data x[0], x[4], x[8], x

[0012] corresponding to the first block in the first calculation stage, input the read x[0], x[4], x[8], x

[0012] to the vector register A, and can read the rotation factors corresponding to x[0], x[4], x[8], x

[0012] stored continuously in the first storage order, and input the read rotation factors to the vector register B. The vector operation unit can perform vector operation on the input data in the vector register A and the rotation factors in the vector register B to realize the butterfly calculation included in the block. In this way, the rotation factors and the input data can be carried to the data operation unit by continuous reading, non-continuous access to the rotation factors or the input data can be avoided, the efficiency of data carrying can be improved, and the efficiency of performing fast NTT can be improved.

[0118] As shown in FIG. 9, when the 16-point fast NTT calculation is performed in a frequency domain manner, the calculation can be divided into two calculation stages, and the base of each calculation stage is 4. The arrangement order of the input data of the first calculation stage can be x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x

[0010] , x

[0011] , x

[0012] , x

[0013] , x

[0014] , x

[0015] . In this case, the data carrying unit can continuously read the rotation factors of the first calculation stage stored in the first storage order. The first rotation factor read is the rotation factor used for the calculation of x[0], the second rotation factor read is the rotation factor used for the calculation of x[1], and the Nth rotation factor read is the rotation factor used for the calculation of the Nth data in the input data. For example, in FIG. 9, the data carrying module can read the input data x[0], x[1], x[2], x[3] corresponding to the first block in the first calculation stage, input the read x[0], x[1], x[2], x[3] to the vector register C, and can read the rotation factors corresponding to x[0], x[1], x[2], x[3] stored continuously in the first storage order, and input the read rotation factors to the vector register D. The vector operation unit can perform vector operation on the input data in the vector register C and the rotation factors in the vector register D to realize the butterfly calculation included in the block. In this way, the rotation factors and the input data can be carried to the data operation unit by continuous reading, non-continuous access to the rotation factors or the input data can be avoided, the efficiency of data carrying can be improved, and the efficiency of performing fast NTT can be improved.

[0119] In the embodiments of the present application, the storage order of the rotation factors can be set according to the arrangement order of the input data of the fast NTT calculation stage when the time domain decimation and the frequency domain decimation are performed respectively. In actual calculation, the rotation factors corresponding to the storage order can be obtained according to the fast NTT calculation manner, non-continuous access to the rotation factors or the input data can be avoided, the efficiency of data carrying can be improved, and the efficiency of performing fast NTT can be improved.

[0120] FIG. 10 is an apparatus for performing fast NTT provided by an embodiment of the present application, which is configured in a processor, and the apparatus comprises:

[0121] The obtaining module 1010 is configured to receive the execution instruction of fast NTT sent by an application program, and obtain a data sequence to be subjected to fast NTT.

[0122] The base selecting module 1020 is configured to determine, based on the length value of the data sequence, a plurality of calculation stages corresponding to bases respectively in a candidate base set, where the candidate base set includes a plurality of candidate bases, and each candidate base has a value greater than 2 and is an integer power of 2.

[0123] The obtaining module 1010 is configured to obtain a rotation factor corresponding to each calculation stage.

[0124] The calculation module 1030 is configured to perform each calculation stage based on the data sequence and the rotation factor corresponding to each calculation stage, to obtain a result of performing the fast NTT.

[0125] In an implementable manner, the base selecting module 1020 is configured to, in a case where there is at least one candidate base in the candidate base set whose integer power is equal to the length value, determine, in the at least one candidate base, the plurality of calculation stages corresponding to bases respectively.

[0126] In an implementable manner, the base selecting module 1020 is configured to determine, as the bases corresponding to the plurality of calculation stages respectively, a first candidate base greater than or equal to a specified value in the at least one candidate base, where the specified value is equal to a ratio of an instruction bit width corresponding to a calculation instruction of the processor to a data bit width corresponding to each data in the data sequence.

[0127] In an implementable manner, the base selecting module 1020 is configured to, in a case where there is no candidate base in the candidate base set whose integer power is equal to the length value, determine, as a base of a first calculation stage in the plurality of calculation stages, 2. For other calculation stages in the plurality of calculation stages except the first calculation stage, determine, in the candidate base set, at least one candidate base corresponding to an integer power equal to one half of the length value, and determine, in the at least one candidate base, the other calculation stages corresponding to bases respectively.

[0128] In an implementable manner, the base selecting module 1020 is configured to determine, as the bases corresponding to the other calculation stages respectively, a second candidate base greater than or equal to a specified value in the at least one candidate base, where the specified value is equal to a ratio of an instruction bit width corresponding to a calculation instruction of the processor to a data bit width corresponding to each data in the data sequence.

[0129] In an implementable manner, the first calculation stage is a first calculation stage or a last calculation stage in the plurality of calculation stages.

[0130] In an implementable mode, the processor includes a data carrying unit and a data operation unit, and the calculation module 1030 is configured to: for each calculation stage, control the data carrying unit to input input data of the calculation stage and a corresponding rotation factor to the data operation unit, wherein the input data of the first calculation stage is the data sequence, and the input data of each calculation stage after the first calculation stage is the output data of the corresponding previous calculation stage; control the data operation unit to perform a butterfly calculation on the input data and the rotation factor to obtain output data of each calculation stage, wherein the output result of the last calculation stage is the result of performing the fast NTT.

[0131] In an implementable mode, the corresponding rotation factors of each calculation stage are stored according to a first storage order and a second storage order respectively, wherein when the corresponding rotation factors of each calculation stage are stored according to the first storage order, the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when the fast NTT is performed according to the time domain decimation manner, and when the corresponding rotation factors of each calculation stage are stored according to the second storage order, the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when the fast NTT is performed according to the frequency domain decimation manner.

[0132] The calculation module 1030 is configured to: in the case of performing the fast NTT according to the time domain decimation manner, for each calculation stage, control the data carrying unit to read the input data of the calculation stage, the rotation factor stored according to the first storage order, and input the read input data and the rotation factor to the data operation unit. In the case of performing the fast NTT according to the frequency domain decimation manner, for each calculation stage, control the data carrying unit to read the input data of the calculation stage, the rotation factor stored according to the second storage order, and input the read input data and the rotation factor to the data operation unit.

[0133] It should be noted that the apparatus for performing the fast NTT provided in the above embodiments is only taken as an example for the division of the above functional modules in performing the fast NTT, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above described functions. In addition, the apparatus for performing the fast NTT provided in the above embodiments and the method embodiment for performing the fast NTT belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0134] The device for fast NTT provided in the application can determine each base of each calculation stage in the fast NTT from the candidate base set according to the length value of the data sequence before the processor performs the fast NTT on the data sequence. Since the candidate bases included in the candidate base set are all greater than 2, the number of calculation stages can be reduced, the calculation complexity of each calculation stage can be reduced, and the flexibility and efficiency of performing the fast NTT can be improved, compared with directly determining the base of the calculation stage as 2.

[0135] The embodiment of the application provides a computer program product containing instructions, which, when executed by a computer device, cause the computer device to perform the method for performing fast NTT described in the above embodiment.

[0136] In the above embodiment, all or part of the embodiment can be implemented by software, hardware, firmware or any combination thereof, and when the software is used for implementation, the software can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions, which, when loaded and executed on a device, produce the processes or functions described in the embodiment of the application in whole or in part. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.). The computer readable storage medium can be any available medium that can be accessed by a device or a data storage device such as a server, data center, etc. containing one or more available media sets. The available storage medium can be a magnetic medium (such as floppy disk, hard disk and magnetic tape, etc.), an optical medium (such as digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as solid state disk, etc.).

[0137] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program to instruct related hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0138] The terms "first", "second", etc. are used to distinguish between similar or identical items having substantially the same function, and it should be understood that there is no logical or chronological dependency between "first" and "second", nor is there any limitation on the number and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more.

[0139] The above description is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for performing the Fast Number Theory Transform (NTT), characterized in that, The method is executed by a processor, and the method comprises: receiving an execution instruction of a fast NTT sent by an application program, and obtaining a data sequence to be subjected to the fast NTT; determining, based on a length value of the data sequence, a plurality of calculation stages included in the fast NTT to correspond to bases in a candidate base set respectively, wherein the candidate base set comprises a plurality of candidate bases, and each candidate base has a value greater than 2 and is an integer power of 2; obtaining a rotation factor corresponding to each calculation stage; based on the data sequence and the rotation factor corresponding to each calculation stage, sequentially executing each calculation stage to obtain a result of executing the fast NTT.

2. The method of claim 1, wherein, The method is executed by a processor, and the method comprises: in a case where an integer power of at least one candidate base in the candidate base set is equal to the length value, determining the plurality of calculation stages to correspond to bases in the at least one candidate base respectively.

3. The method of claim 2, wherein, The method is executed by a processor, and the method comprises: determining, in the at least one candidate base, a second candidate base greater than or equal to a specified value as a base corresponding to each of the other calculation stages, wherein the specified value is equal to a ratio of an instruction bit width corresponding to a calculation instruction of the processor to a data bit width corresponding to each data in the data sequence.

4. The method of claim 1, wherein, The method is executed by a processor, and the method comprises: in a case where an integer power of at least one candidate base in the candidate base set is equal to the length value, determining the plurality of calculation stages to correspond to bases in the at least one candidate base respectively. The method is executed by a processor, and the method comprises:

5. The method of claim 4, wherein, determining, in the at least one candidate base, a second candidate base greater than or equal to a specified value as a base corresponding to each of the other calculation stages, wherein the specified value is equal to a ratio of an instruction bit width corresponding to a calculation instruction of the processor to a data bit width corresponding to each data in the data sequence. The first calculation stage is the first calculation stage or the last calculation stage in the plurality of calculation stages.

6. The method according to claim 4 or 5, characterized in that, The processor comprises a data carrying unit and a data operation unit, and the method comprises:

7. The method according to any one of claims 1 to 6, characterized in that, determining, in the at least one candidate base, a second candidate base greater than or equal to a specified value as a base corresponding to each of the other calculation stages, wherein the specified value is equal to a ratio of an instruction bit width corresponding to a calculation instruction of the processor to a data bit width corresponding to each data in the data sequence. The data carrying unit inputs the input data of each calculation stage and corresponding rotation factors to the data operation unit, wherein the input data of the first calculation stage is the data sequence, and the input data of each calculation stage after the first calculation stage is the output data of the corresponding previous calculation stage; The data operation unit performs a butterfly calculation on the input data and rotation factors to obtain the output data of each calculation stage, wherein the output result of the last calculation stage is the result of performing the fast NTT.

8. The method of claim 7, wherein, The corresponding rotation factors of each calculation stage are stored according to a first storage order and a second storage order respectively, wherein when the corresponding rotation factors of each calculation stage are stored according to the first storage order, the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when performing the fast NTT according to a time domain decimation manner, and when the corresponding rotation factors of each calculation stage are stored according to the second storage order, the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when performing the fast NTT according to a frequency domain decimation manner. The data carrying unit inputs the input data of each calculation stage and corresponding rotation factors to the data operation unit, and the method comprises the following steps: In the case of performing the fast NTT according to the time domain decimation manner, for each calculation stage, the data carrying unit reads the input data of the calculation stage, the rotation factors stored according to the first storage order, and inputs the read input data and rotation factors to the data operation unit; In the case of performing the fast NTT according to the frequency domain decimation manner, for each calculation stage, the data carrying unit reads the input data of the calculation stage, the rotation factors stored according to the second storage order, and inputs the read input data and rotation factors to the data operation unit.

9. An apparatus for performing the Fast Number Theory Transform (NTT), characterized in that, The device is configured in a processor, and the device comprises: An obtaining module configured to receive an execution instruction of a fast NTT sent by an application program, and obtain a data sequence to be subjected to the fast NTT; A base selecting module configured to determine, based on a length value of the data sequence, a plurality of calculation stages included in the fast NTT to correspond to bases respectively in a candidate base set, wherein the candidate base set comprises a plurality of candidate bases, and each candidate base has a value greater than 2 and is an integer power of 2; An obtaining module configured to obtain a corresponding rotation factor of each calculation stage; A calculation module configured to perform the plurality of calculation stages based on the data sequence and the corresponding rotation factor of each calculation stage in sequence to obtain a result of performing the fast NTT.

10. The apparatus of claim 9, wherein, The base selecting module is configured to: In the case that an integer power of at least one candidate base in the candidate base set is equal to the length value, determine the plurality of calculation stages to correspond to bases respectively in the at least one candidate base.

11. The apparatus of claim 10, wherein, The base selecting module is configured to: The first candidate base greater than or equal to a specified value in the at least one candidate base is determined as the base corresponding to the plurality of calculation stages respectively, wherein the specified value is equal to a ratio of an instruction bit width corresponding to a calculation instruction of the processor to a data bit width corresponding to each data in the data sequence.

12. The apparatus of claim 9, wherein, The base selecting module is configured to: In a case where an integer power of the candidate base does not exist in the candidate base set and is equal to the length value, a base of a first calculation stage in the plurality of calculation stages is determined as 2; For other calculation stages in the plurality of calculation stages except the first calculation stage, at least one candidate base corresponding to an integer power equal to one-half of the length value in the candidate base set is determined, and a base corresponding to each of the other calculation stages is determined in the at least one candidate base.

13. The apparatus of claim 12, wherein, The base selecting module is configured to: A second candidate base greater than or equal to a specified value in the at least one candidate base is determined as the base corresponding to the other calculation stages respectively, wherein the specified value is equal to a ratio of an instruction bit width corresponding to a calculation instruction of the processor to a data bit width corresponding to each data in the data sequence.

14. The apparatus of claim 12 or 13, wherein, The first calculation stage is a first calculation stage or a last calculation stage in the plurality of calculation stages.

15. The apparatus of any one of claims 9 to 14, wherein, The processor includes a data carrying unit and a data operation unit, and the calculation module is configured to: For each calculation stage, the data carrying unit is controlled to input input data of the calculation stage and a corresponding rotation factor to the data operation unit, wherein the input data of the first calculation stage is the data sequence, and the input data of each calculation stage after the first calculation stage is output data of a corresponding previous calculation stage; The data operation unit is controlled to perform a butterfly calculation on the input data and the rotation factor to obtain output data of each calculation stage, wherein the output result of the last calculation stage is a result of performing the fast NTT.

16. The apparatus of claim 15, wherein, The corresponding rotation factor of each calculation stage is stored according to a first storage order and a second storage order respectively, wherein when the corresponding rotation factor of each calculation stage is stored according to the first storage order, the storage order of each rotation factor corresponds to an arrangement order of the input data of each calculation stage when the fast NTT is performed according to a time domain decimation manner, and when the corresponding rotation factor of each calculation stage is stored according to the second storage order, the storage order of each rotation factor corresponds to the arrangement order of the input data of each calculation stage when the fast NTT is performed according to a frequency domain decimation manner; The calculation module is configured to: In a case where the fast NTT is performed according to the time domain decimation manner, for each calculation stage, the data carrying unit is controlled to read the input data of the calculation stage, the rotation factor stored according to the first storage order, and input the read input data and the rotation factor to the data operation unit; In a case where the fast NTT is executed in accordance with the frequency domain decimation method, for each calculation stage, the data carrying unit is controlled to read input data of the calculation stage, a twiddle factor stored in the second storage order, and input the read input data and the twiddle factor to the data operation unit.

17. A computer device, comprising: The computer device comprises a processor and a memory; The processor is configured to execute instructions stored in the memory, so that the computer device performs the method of any one of claims 1 to 8.

18. A computer program product, characterised in that, The computer program product comprises instructions which, when executed by a processor of a computer device, cause the processor to perform the method of any one of claims 1 to 8.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium comprises computer program instructions which, when executed by a processor of a computer device, cause the processor to perform the method of any one of claims 1 to 8.

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