Quantum chip

Abstract

Quantum chip (101, 102, 103, 104, 105, 106, 107, 108, 109) comprising a qubit array (1) comprising first and second sets (6a, b) of boundary qubits (2) on opposite sides (1a, b) of the array (1) and a set of bulk qubits (3) inside the array (1 ), said set of bulk qubits (3) being comprised between the first and second sets (6a, b) of boundary qubits (2), wherein a boundary coupling structure (8, 8a, 8b) providing connectivity between at least a boundary qubit (2) of the first set (6a) and a boundary qubit (2) of the second set (6b) is provided between said boundary qubits (2).

Description

[0001] Quantum Chip

[0002] The invention relates to a quantum chip, in particular a quantum chip comprising an array of qubits.

[0003] A quantum chip comprising an array of qubits comprising a plurality of qubits located at the boundary of the array and a plurality of qubits located in the bulk of the array, in between the boundary qubits. In such a quantum chip first and second boundary qubits of the first and second sets of boundary qubits, respectively, are physically separated from each other by a distance that scales with the number of bulk qubits located therebetween. In case that the array is in the form of a square grid, the distance grows as the square root of the total number of qubits and will also depend on the size of the individual qubit structure. Naturally, information between boundary qubits on opposite sides of the array can be transported across the chip by using SWAP gates. However, this involves an overhead cost, which can in the worst case mean a cost of 2L-1 additional SWAP gates per desired two-qubit gate, for a chip of L2qubits. If one is treating fermionic systems, where fermionic modes are transported between qubits using fSWAP gates, the number of additional operations can be as high as the number of qubits. Furthermore, if one wants to implement a Toric code, the errors occurring while the SWAP gates are performed can degrade the performance of the code.

[0004] It is thus an object of the present invention to provide a quantum chip of the abovereferenced type with an improved qubit connectivity.

[0005] This object is solved in accordance with the invention by a quantum chip comprising a qubit array comprising first and second sets of boundary qubits on opposite sides of the array and a set of bulk qubits inside the array, said set of bulk qubits being comprised between the first and second sets of boundary qubits, wherein a boundary coupling structure for providing connectivity between at least a boundary qubit of the first set of boundary qubits and a boundary qubit of the second set of boundary qubits is provided between said boundary qubits. As a result, a coupling is provided between at least a boundary qubit of the first set of boundary qubits and a boundary qubit of the second set of boundary qubits.

[0006] According to the invention, qubit arrays with closed boundary conditions (CBC) may be implemented. Some of the problems to be solved by quantum computers involve CBC. For example, in classical simulations of fermionic or spin system, it is common to use CBC to ease the conversions of the studied properties with the size of the system, sometimes halving the required system size. Different CBC will converge at a different rate. This can also be extended to quantum simulation to reduce the number of qubits required to achieve meaningful simulations. Two well-known types of CBC are periodic boundary conditions (PBC) and twisted boundary conditions (TBC).

[0007] These CBC may also be useful in other applications. For example, in variational algorithms CBC may create entanglement faster in the system and produce better results. In quantum approximate optimization algorithms (QAOA) one needs to bring close some pairs of qubits and this takes L SWAPS in the worst case in a square grid with open boundary conditions. However, having CBC, this can be done in L / 2, where L is the linear chip size.

[0008] In quantum error correction, there are codes, such as the Toric code or other qLDPC codes, which implies stabilizers that may not be easily implemented in a square grid with open boundaries. CBC can improve the threshold required to reach fault-tolerant quantum computing over codes that can be realized without CBC.

[0009] The additional qubit connectivity between boundary qubits on opposite sides of the array that is provided in accordance with the invention facilitates implementing CBC without any major technological hardware advances and without any significance sacrifices in terms of the quality of the quantum chip, like fidelities, coherence etc.

[0010] In one example, only boundary qubits and no bulk qubits may couple to the boundary coupling structure, but the invention is not limited to this.

[0011] In a simple example, the qubit array of the invention may be a one-dimensional chain of qubits. In this case, each of the first and second sets of boundary qubits contains a single boundary qubit, namely the one or the other of the terminal qubits located at the ends of the chain. In most cases, although not limited thereto, the array is two-dimensional. In this case, the boundary qubits of the first and second sets may form first and second one-dimensional chains of qubits, respectively. Each of the chains is neighboured by bulk qubits on one side thereof while no qubits are located on the other side thereof. In rectilinear arrays the chains may be straight, while in circular arrays the chains may be curvilinear.

[0012] In one embodiment, the quantum chip further comprises at least one bulk coupling structure for providing connectivity between at least some of the bulk qubits and / or between at least one bulk qubit and at least one boundary qubit. In one example, there may be a plurality of bulk coupling structures for providing connectivity at least between pairs of neighbouring qubits in the bulk and in the bulk and at the boundary. In one example, the bulk coupling structure or structures may provide all-to-all connectivity between a plurality of qubits of the arrangement. In one example, the bulk coupling structure may comprise a tunable coupler for providing connectivity between neighbouring qubits of the array.

[0013] In another example, the quantum chip further comprises a plurality of bulk coupling structures such that at least one pair of boundary qubits for which the qubits are located on two further opposite sides of the array, respectively, and without connectivity provided by the boundary coupling structure is connected via the plurality of bulk coupling structures and the bulk qubits to which they connect. This embodiment may allow to avoid problems of crossings between boundary coupling structures. Namely, the CBC between the boundary qubits of the first and second sets on the opposite sides of the array may be provided by hardware connections via the boundary coupling structure while the CBC between the at least one pair of boundary qubits on the further opposite sides are realizable via SWAP gates between bulk and boundary qubits along the path between the pair of boundary qubits which is provided by the bulk coupling structures. In particular, the spatial separation between the two further opposite sides is smaller than the spatial separation between the opposite sides having the boundary coupling structure therebetween. Thereby, the number of SWAPs is limited in accordance with the smaller separation, while there is virtually no limit on designing the hardware of the boundary coupling structure so as to establish the connection over the larger separation.

[0014] In a useful embodiment, the number of boundary qubits in each of the first and second sets of boundary qubits is more than one. Specifically, the number of boundary qubits of the first set equals the number of boundary qubits of the second set. In particular, for each of the boundary qubits of the first set there exists a boundary qubit of the second set having a coupling provided therebetween. More particular, for each of the boundary qubits of the first set there exists a boundary qubit of the second set having a coupling path of the coupling structure provided therebetween. In this case, the quantum chip may comprise a plurality of boundary coupling structures. The number of boundary coupling structures equals the number of boundary qubits in each of the first and second sets, and the boundary coupling structures establish a one-to-one correspondence between the boundary qubits of the first and second sets of boundary qubits.

[0015] The qubit array may be configured in accordance with various geometries. In one embodiment, the boundary qubits of the first and second sets are located on first and second parallel straight lines, respectively. An example is a planar regular linear grid of qubits that is bounded in one dimension by the first and second sets of opposite boundary qubits. In one example, the quantum chip may also comprise the at least one pair of boundary qubits for which the qubits are located on the two further opposite sides of the array, respectively, and without connectivity provided by the boundary coupling structure, and wherein the two further opposite sides are transverse to the parallel straight lines.

[0016] In a specific embodiment, the array is confined within a parallelogram having first and second pairs of first and second opposite sides with the qubits located on the first and second opposite sides of the first pair forming a first pair of first and second sets of boundary qubits, respectively, and the qubits located on the first and second opposite sides of the second pair forming a second pair of first and second sets of boundary qubits, respectively. In the limiting case, the parallelogram is a rectangle, in particular a square.

[0017] In all these cases, one or more boundary coupling structures may only be provided between boundary qubits of one of the pairs of first and second sets of boundary qubits while interaction between the boundary qubits of the other pair of first and second sets of boundary qubits is not via a boundary coupling structure provided therebetween but interaction between these boundary qubits is mediated through SWAPs that use connectivity between bulk qubits and between bulk and boundary qubits, e.g., as provided by the bulk coupling structure(s) explained above.

[0018] In a further embodiment, there may be for each qubit of one of the first sets a respective qubit of the corresponding second set and a boundary coupling structure for providing connectivity between the two qubits.

[0019] In specific embodiments, each of the bulk qubits is located on one of the crossings of straight lines that extend between the boundary qubits on opposite sides of the parallelogram in parallel with the sides of the parallelogram. In these embodiments, the array of boundary qubits is configured according to regular parallelogram, rectangle or square lattices, respectively.

[0020] In embodiments according to another type of geometry, the qubits of the array are located on at least one closed curve, in particular on first and second parallel closed curves with the qubits located on the first and second parallel closed curves forming a radial pair of first and second sets of boundary qubits, respectively. This geometry of the array may be derived from the array that corresponds to a rectangular grid geometry by deforming parallel straight lines of the latter grid into the parallel curves with the result that the boundary qubits at the end of the straight lines become neighbouring qubits on the curves. These neighbouring qubits on each of the parallel closed curves thereby correspond to an azimuthal pair of first and second sets of boundary qubits. Further, it is preferred that each bulk qubit is located on an additional parallel closed curve that is between and parallel to the first and second parallel closed curves. In these embodiments, the couplings between the first azimuthal pair of first and second sets of boundary qubits may be nearest neighbour. On the other hand, the coupling between the boundary qubits on the first and second curves may optionally be realised by SWAPs in the transverse direction of the curves. To this end, the quantum chip may comprise a plurality of bulk couplers for providing connectivity between neighbouring bulk qubits and neighbouring bulk and boundary qubits in the radial direction. In a further embodiment, the quantum chip may comprise a boundary coupling structure for providing connectivity between the boundary qubits on the first and second parallel closed curves.

[0021] Specifically, the parallel closed curves are concentric circles or concentric ellipses. Further, the boundary qubits of the azimuthal pair of first and second sets of boundary qubits may be located on first and second radially extending straight lines, respectively. Further, in expedient embodiments, the qubits on the neighbouring parallel closed curves are mutually offset in the circumferential direction. I.e., qubits on a closed curve are mutually offset in the circumferential direction to qubits on a neighbouring parallel closed curve. In this way, there is more space between the qubits to reduce crosstalk.

[0022] In a useful embodiment, the boundary coupling structure comprises a non-local on-chip coupler. In major embodiments, the distance between the boundary qubits to be coupled by the boundary coupling structure is in the order of one of the linear dimensions of the chip. This may in particular be attained by a long-distance coupling structure, in particular a long-distance resonator or a long-distance tuneable coupler as it is disclosed, e.g., in F. Marxer et.al, “Longdistance transmon coupler with gate fidelity above 99.8 %”, arxiv:2208.09460”. In the case of a square layout, this distance grows as the square root of the total number of qubits and will also depend on the size of individual qubit structures. This distance is still within the range of resonator chip components, at least for intermediate sized systems. Although the coupling strength of the resonator will decay with distance, this effect will only pick up slowly.

[0023] The boundary coupling structures between boundary qubits at pairs of opposite sides of the chip must cross in the two-dimensional plane of the chip or boundary coupling structures cross bulk coupling structures in the two-dimensional plane of the chip. In a useful embodiment that deals with this problem, the boundary coupling structure is implemented using air bridge technology. This existing technology can be repeatedly applied to resolve any coupling structure crossings, like for example resonator or tunable coupler crossings. Since air bridges result in a slight drift of frequency, it is advantageous to keep the number of bridges per coupling structure the same for all coupling structure.

[0024] The qubits of the quantum chip are not limited to a special kind. In one embodiment, the qubits of the quantum chip are superconducting qubits. Further, in expedient embodiments, the qubits are transmons. The qubits may be fluxoniums or unimons in one example.

[0025] As explained above, the boundary coupling structures between the boundary qubits at pairs of opposite sides of the chip must cross in the two-dimensional plane of the chip. In a further useful embodiment that deals with this problem, the quantum chip comprises a set of layers, in particular superimposed planar layers, and the qubit array and at least one of the boundary coupling structures are located on different layers of the set In a particular useful example, the boundary coupling structures are located on different layers of the set such that there is no crossing between them on the same layer. In further expedient embodiments, the boundary coupling structures and / or the bulk coupling structures are distributed over the layers such that coupling structures located on the same layers avoid crossings between themselves. In this way, the problem of frequency drift as encountered by the use of airbridges may be prevented.

[0026] In one particular example, said quantum chip comprises first and second boundary coupling structures which extend transversally to each other and are located on different layers of the set of layers. Thereby, there is no crossing between the first and second boundary coupling structures on the same layer. In a further embodiment, the qubit array, the first boundary coupling structure and the second boundary coupling structure may be located on different layers of the set of layers, respectively. That is, the quantum chip comprises at least three layers. The chip may further comprise a plurality of bulk coupling structures for providing connectivity between bulk qubits or between bulk qubits and boundary qubits of the chip. In a useful example, the bulk coupling structures are located on the same layer as the qubit array. In this way, crossings between the bulk and boundary coupling structures may be completely prevented.

[0027] In a further embodiment where the qubit array is confined within a parallelogram, as explained above, the coupling path of each boundary coupling structure in each layer may extend in parallel to one of the pairs of first and second opposite sides of the parallelogram, respectively. Coupling between the qubits and the coupling structures located on different layers may be realized via various technologies. In expedient examples, the connections between layers may be implemented by means of vias, in particular through silicon vias (TSV). Additionally, or alternatively, the layers of the chip may be arranged according to a flip-chip architecture. Thereby, the coupling between the qubits and the coupling structures may be realized by the connectivity between the layers, for example using indium bumps.

[0028] In one embodiment, the boundary coupling structure comprises resonators with a crossing therebetween formed as an airbridge.

[0029] According to another object of the invention, a method for performing quantum error detection and / or correction on a quantum chip as described above is achieved, wherein said method comprises implementing the quantum error correction by use of the connectivity between the qubits. As the quantum chip according to any one of the above may provide the necessary connectivities for implementing the stabilizer operators of a quantum error correction code, the method according to present invention is an efficient method for performing error correction.

[0030] In the following, the invention is explained in greater detail by way of example with reference to the drawings. In the drawings,

[0031] Figure 1 is a schematic representation of a qubit of a quantum chip according to the present invention;

[0032] Figure 2 is a schematic representation of a quantum chip according to a first embodiment of the present invention wherein closed boundary conditions (CBC) in two directions are implemented using boundary coupling structures and air bridge technology;

[0033] Figure 3 is a schematic representation of a quantum chip according to a second embodiment of the present invention wherein CBC in one direction are implemented using boundary coupling structures and air bridge technology;

[0034] Figure 4 is a schematic representation of a quantum chip according to a third embodiment of the present invention wherein CBC in one direction are implemented by use of boundary coupling structures and the topology of the qubit array;

[0035] Figure 5 is a schematic representation of a quantum chip according to a fourth embodiment of the present invention which is a modification of the third embodiment shown in Figure 4; Figures 6a and 6b are schematic representations of two layers of a quantum chip according to a fifth embodiment of the present invention wherein qubits and boundary coupling structures for implementing CBC in one direction are located on different layers of the chip;

[0036] Figures 7a and 7b are schematic representations of two layers of a quantum chip according to a sixth embodiment of the present invention which is a modification of the quantum chip according to the fifth embodiment shown in Figures 6a and 6b;

[0037] Figures 8a and 8b are schematic representations of two layers of a quantum chip according to a seventh embodiment of the present invention wherein first and second boundary coupling structures for providing CBC in two directions are located on different layers of the chip;

[0038] Figure 9a and 9b are schematic representations of two layers of a quantum chip according to an eighth embodiment of the present invention which is a modification of the quantum chip according to the seventh embodiment;

[0039] Figures 10a,

[0040] 10b, 10c are schematic representations of three layers of a quantum chip according to a ninth embodiment of the present invention wherein the array of qubits, the first and second boundary coupling structures are located on the three different layers of the chip.

[0041] Figure 11 is a schematic representation of a part of a qubit chip where multiple air bridges connect different parts of the chip;

[0042] Figure 1 is a schematic representation of a transmon qubit 2, 3 of a quantum chip 101 , 102 according to the present invention. The qubit comprises six connection ports 4 for connecting the qubits to other qubits or control electronics. In particular, two of the connection ports 4 may be used for control and readout while the other four connection ports 4 may be used for connections with tunable couplers to thereby provide connectivity between the qubits or for connecting the qubits to resonators or other signal-carrying transmission lines. In a given array of qubits, for example if the qubits are arranged in standard lattice structures like square grids, hexagonal or triangular lattices, some of the ports of the qubits located at the edges of the lattice are not being used for providing connectivity with their neighbours, and they may be used for providing connections between qubits at opposite sides of the array.

[0043] Figure 2 is a schematic representation of a quantum chip 101 according to a first embodiment of the present invention, wherein CBC in two directions are implemented using boundary coupling structures and airbridge technology. The quantum chip 101 comprises an array 1 of qubits 2, 3 which are arranged on a substrate 10. The qubits 2, 3 comprise boundary qubits 2 and bulk qubits 3. In particular, the qubits 2, 3 may be superconducting qubits, e .g., transmons, unimons or fluxoniums. In Fig. 2 the array 1 of qubits 2, 3 is confined within a square having a first pair of first and second opposite sides 1a, b in an X direction and a second pair of first and second opposite sides 1c, d in a Y direction. Boundary qubits 2 located on the first and second opposite sides 1 a, b of the first pair of sides form a first pair of first and second sets 6a, b of boundary qubits 2. Similarly, boundary qubits 2 located on the first and second opposite sides 1c, d of the second pair of sides form a second pair of first and second sets 7a, b of boundary qubits 2. The four boundary qubits 2 at the four corners of the square are each a member of two sets of boundary qubits. The boundary qubits 2 of the first and second sets 6a, 6b, 7a, 7b are located on first and second parallel straight lines, respectively. In each of the four sets 6a, 6b, 7a, 7b of boundary qubits 2, the individual qubits 2 are thus arranged in a one-dimensional chain which extends along a straight line in parallel to the X- or Y-directions, respectively.

[0044] Furthermore, the qubit array 1 comprises a set of bulk qubits 3 inside the array 1 , said set of bulk qubits 3 being comprised between the first and second sets of boundary qubits 2. Each bulk qubit 3 is located on one of the crossings of straight lines that extend between the boundary qubits on opposite sides of the square in parallel with the sides of the square.

[0045] The quantum chip 101 further comprises a plurality of bulk coupling structures 9 (dashed lines) for providing connectivity between neighboring bulk qubits 3, between neighboring boundary qubits 2 and between neighboring bulk and boundary qubits 2, 3. The bulk coupling structure 9 may provide coupling based on direct coupling between the qubits 2,3 via capacitive or inductive coupling. In a variant, the bulk coupling structure 9 may comprise a tunable coupler coupling two bulk qubits 9 together. In Fig. 2, the quantum chip 101 comprises a bulk coupling structure provided between each pair of neighboring bulk qubits and between each pair of neighboring bulk and boundary qubits.

[0046] The quantum chip 101 further comprises for each boundary qubit 2 of the first set 6a of the first pair of sets of qubits, a boundary qubit 2 of the second set 6b of the first pair of sets of qubits such that the two boundary qubits 2 have a connectivity provided by a boundary coupling structure 8 of the chip 101 which has a coupling path provided between the two boundary qubits 2. Furthermore, the quantum chip 101 comprises for each boundary qubit 2 of the first set 7a of the second pair of sets of qubits a boundary qubit 2 of the second set 7b of the second pair of sets of qubits such that the two boundary qubits 2 have a connectivity provided by a boundary coupling structure 8 of the chip 101. That is, the quantum chip 1 comprises in total eight individual boundary coupling structures 8 for providing connectivity between pairs of boundary qubits 2. The boundary coupling structure 8 provides connectivity between boundary qubits 2 of opposite sides of the square. The boundary qubits 2 on each of the pairs of opposite sides extend along the first and second sets of parallel straight lines, respectively. Each individual boundary structure 8 provides connectivity between only two boundary qubits 2 of the boundary qubits 2 of the array 101.

[0047] In order to avoid crossings between the boundary coupling structures 8 as well as between the boundary coupling structures 8 and the bulk coupling structures 9, the boundary coupling structures 8 are implemented using air bridge technology. In this way, the qubit array 101 has closed boundary conditions both in the X direction and the Y direction provided by hardware connections. The boundary coupling structure 8 can comprise resonators, long distance couplers, etc.

[0048] In another variant of the invention, the boundary coupling structure 8 does not extend above the bulk qubits 9. For example, the boundary coupling structure 8 could be located on the side of the bulk qubits 9 or of the array 101 of qubits, in particular on the outside side of the bulk qubits 9 or of the array 101 of qubits.

[0049] Figure 3 is a schematic representation of a quantum chip 102 according to a second embodiment of the present invention wherein closed boundary conditions in only one direction are implemented using boundary coupling structures and air bridge technology.

[0050] The quantum chip 102 shown in Figure 3 is similar to the quantum chip 101 shown in Figure 2 in that a qubit array 1 is arranged on a substrate 10 in a plane. The array 1 is confined within a rectangle having first and second pairs of first and second opposite sides 1a, b, and 1c, d, respectively, with the boundary qubits 2 located on the first and second opposite sides 1a, b of the first pair forming the first pair of first and second sets 6a, b of boundary qubits 2, respectively, and the boundary qubits 2 located on the first and second opposite sides 7a, b of the second pair forming the second pair of first and second sets 7a, b of boundary qubits 2, respectively. A plurality of bulk qubits 3 is located inside the array 1 , said bulk qubits 3 being comprised between the first and second sets of boundary qubits 2. The qubit array 1 has a long side in the X direction and a short side in the Y direction. The quantum chip 102 also comprises a plurality of bulk coupling structures 9 (dashed lines) for providing connectivity between neighboring qubits 2, 3 in the bulk, neighboring boundary qubits 2 and between neighbouing bulk qubits 3 and boundary qubits 2. In particular, each bulk coupling structure 9 may comprise a resonator or a tunable coupler in one example. In another example, each bulk coupling structure 9 may perform a direct coupling between qubits, being capacitive or inductive coupling.

[0051] Apart from the different number of qubits in the X and Y directions, the quantum chip 102 shown in Figure 3 differs from the quantum chip 101 shown in Figure 2 in that CBC are provided by hardware connections only in the X direction. That is, the quantum chip 102 comprises only four boundary coupling structures 8 which provide connectivity between pairs of boundary qubits in the first and second sets 6a, 6b of the first pair of sets. The boundary coupling structures 8 only connect two boundary qubits 2, the boundary qubits 2 being on different sides of the array 101 , opposite to each other.

[0052] If CBS are also to be implemented in the Y direction, this may be achieved by using the connectivity between bulk qubits 3 and boundary qubits 2 provided via the bulk coupling structures 9 in the Y direction. That is, a qubit state of a boundary qubit 2 in the first set 7a of the second pair of boundary qubits may be mapped to a bulk qubit 3 which is a neighbor of one of the boundary qubits 2 in the second set 7b of the second pair. Thus, in the quantum chip 102 shown in Figure 3, the CBC in the X direction are implemented through hardware connections, and the CBC in the Y direction are implemented through SWAP gates. In this way, one may minimize the number of SWAP gates that are required and further limit the problems when implementing CBC through hardware connection using air bridges. It may be expedient to use the hardware connections between the more remote boundary qubits 2 mutually opposing in the X-direction while using the SWAPs for the connection between the less remote boundary qubits 2 mutually opposing in the Y-direction, since the reach of the hardware connections is large while the acceptable number of SWAPs is limited.

[0053] Figure 4 is a schematic representation of a quantum chip 103 according to a third embodiment of the present invention wherein CBC in one direction are implemented by use of boundary coupling structures 8 and topology of the array 1 . The array 1 is confined between first and second parallel closed curves 11 , 12 with the qubits located on the first and second parallel closed curves 11 ,12 thereby forming a radial pair of first and second sets 7a, 7b of boundary qubits 2, respectively, which are spaced apart in the radial direction. In the embodiment shown in Figure 4, the curves are concentric circles. This geometry of the array

[0054] 1 may be derived from the array 1 of the quantum chip 102 shown in Figure 3 by deforming parallel straight lines of the latter grid into the parallel curves 11 , 12, 13 with the result that the boundary qubits 2 at the end of the straight lines (i.e. , the boundary qubits in the sets 6a, b of the array shown in Fig. 3) become neighboring bulk qubits 2’ on the curves. These azimuthally neighboring qubits 2’ on the curves thereby correspond to a pair of first and second sets 6a, 6b of boundary qubits 2 in Fig. 3. The quantum chip 103 comprises a plurality of bulk coupling structures 8 for providing connectivity between neighboring bulk qubits 3 and neighboring bulk and boundary qubits 2, 2’, 3.

[0055] The azimuthally neighboring qubits 2’ corresponding to the pair of first and second sets 6a, 6b of Fig. 3 have connectivity provided by a boundary coupling structure 8 connecting nearest neighbors. In one example, the boundary coupling structure 8 connecting the neighboring qubits 2’ corresponding to the first and second sets 6a, 6b of Fig. 3 may be of the same type as the bulk coupling structure 9 of Fig. 3 providing connectivity between neighboring bulk qubits 3 or between neighboring bulk and boundary qubits 2, 3. The azimuthally neighboring qubits corresponding to the pair of first and second sets 6a, 6b of boundary qubits

[0056] 2 may be located on first and second radially extending straight lines 14a, 14b, respectively. Further, each bulk qubit 3 is located on an additional closed curve 13 that is parallel to the first and second parallel closed curves 11 , 12. Furthermore, qubits on neighboring parallel closed curves are arranged on further radially extending lines. In the case of superconducting qubits, all connections between qubits or some connections between qubits may be realized by tunable couplers. Alternatively, capacitive or inductive coupling or coupling with a resonator may be used.

[0057] While the quantum chip 103 shown in Figure 4 allows to implement CBC via hardware connections in the circumferential direction, the implementation of CBC in the radial direction may require the implementation of SWAP gates as explained above in one example. One may, however, also envision an example wherein the quantum chip 103 further comprises a further plurality of boundary coupling structures for providing connectivity between pairs of qubits of the first and second sets 7a, b of the radial pair.

[0058] Figure 5 is a schematic representation of a quantum chip 104 according to a fourth embodiment of the present invention which is a modification of the quantum chip 103 according to the third embodiment shown in Figure 4. The quantum chip 104 shown in Figure 5 differs from the quantum chip 103 shown in Figure 4 in that bulk and boundary qubits 2, 3 on neighboring parallel closed curves 11 , 12, 13 are mutually offset in the circumferential direction. In this way, crosstalk can be reduced as this arrangement allows for bigger spacing between the qubits 2, 3.

[0059] The quantum chips 101 - 104 according to the first to fourth embodiment are all such that the qubits 2, 3, as well as the bulk and boundary coupling structures 8, 9 are located on the same layer on the substrate 10. The crossings between the coupling structures 8, 9 may be implemented using airbridge technologies. An alternative solution to this crossing problem is shown with reference to Figs. 6a to 10c representing a plurality of quantum chips 105, 106, 107, 108, 109, wherein the qubit array, as well as the bulk and boundary coupling structures are distributed over a plurality of layers. The qubits located on one of the layers, e.g. first layer 21 , are depicted by black circles. White circles surrounded by dotted lines on layers different from the first layer 21 (e.g. the second and third layers 22, 23) depict the corresponding location of a qubit on the first layer when the layers 21 , 22, 23 are superimposed, but the dotted lines do not represent a qubit. The layers may be superimposed according to flip-chip technology in one example. In another example, connections between the layers 21 , 22, 23 may be implemented by means of vias, in particular through silicon vias (TSV).

[0060] Figs. 6a and 6b are schematic representations of two layers 21 , 22 of a quantum chip 105 according to a fifth embodiment of the present invention, wherein the qubit array 1 and boundary coupling structures 8 for implementing CBCs in one direction are located on different layers 21 , 22 of the chip 105.

[0061] To be more precise, the qubit array 1 comprising a plurality of bulk qubits 3 and a plurality of boundary qubits 2 is located on the first layer 21. Also located on the first layer 21 is a plurality of bulk coupling structures 9 (dashed lines) for providing connectivity between neighboring qubits in the bulk, neighboring boundary qubits and between neighboring bulk qubits and boundary qubits. The qubits 2, 3 of the array 1 are arranged in a regular two- dimensional lattice structure and the array 1 is confined within a square. The array 1 comprises first and second pairs of first and second opposite sides 1a, b, and 1c, d, respectively. Boundary qubits 2 located on the first and second opposite sides 1a, b of the first pair form the first pair of first and second sets of boundary qubits 6a, 6b, respectively. Boundary qubits 2 located on the first and second opposite sides 1c, d of the second pair form the second pair of first and second sets of boundary qubits 6a, 6b, respectively. In each of the four sets 6a, 6b, 7a, 7b of boundary qubits 2 the individual qubits 2 are thus arranged in a one-dimensional chain which extends along a straight line in parallel to the X- or Y-directions, respectively. On the second layer 22, there is located a plurality of boundary coupling structures 8. The boundary coupling structures 8 are provided such that when the first and second layers 21 , 22 are superimposed, the boundary coupling structures 8 provide connectivity between the boundary qubits 2 located in the first and second sets 6a, 6b of the first pair. That is, in the quantum chip 105 according to the fifth embodiment, CBC are provided by hardware connections in the X-direction. In order to implement CBC in the Y-direction, a plurality of SWAP gates is required, as explained above. More generally, in a quantum chip comprising a qubit array and a coupling structure distributed over two or more superimposed layers, the qubit array may be located on one of the layers together with a first portion of the coupling structure, while a second portion of the coupling structure is located on at least another one of the layers. In particular, the second portion may include all or part of the boundary coupling structure, more particularly a part that extends along the sides of the array or a part that extends across the bulk of the array.

[0062] Figs. 7a and 7b are schematic representations of two layers 21 , 22 of a quantum chip 106 according to a sixth embodiment of the present invention which is a modification of the quantum chip 105 according to the fifth embodiment depicted in Figs. 6a and 6b. The quantum chip 106 differs from the quantum chip 105 of the fifth embodiment in the distribution of the bulk coupling structures 9 over the two layers 21 , 22. For the quantum chip 105 shown in Figs. 6a and 6b above, the bulk coupling structures 9 are all located on the first layer 21 . In contrast, for the quantum chip 106 shown in Figs. 7a and 7b, the bulk coupling structures 9 (dashed lines) for providing connectivity between neighboring qubits in the Y-direction are located on the first layer 21 together with the qubit array 1. The bulk coupling structures 9 for providing connectivity between neighboring qubits in the X-direction are located, together with the boundary coupling structures 8, on the second layer 22. This arrangement allows to avoid crossings between the different coupling structures 8, 9 located on the same layer.

[0063] Figs. 8a and 8b are schematic representations of two layers 21 , 22 of a quantum chip 107 according to a seventh embodiment of the present invention, wherein first and second boundary coupling structures for providing closed boundary conditions in two directions are located on different layers 21 , 22 of the chip 107. To be more precise, the quantum chip 107 comprises the same qubit array 1 as the quantum chips 105, 106. I.e., the qubit array 1 is located on the first layer 21. Also located on the first layer 21 is a plurality of bulk coupling structures 9 for providing connectivity between neighboring qubits 2, 3 in the Y-direction. Even further, the quantum chip 107 comprises a plurality of boundary coupling structures 8 located on the first layer 21 for providing connectivity between pairs of boundary qubits in the first and second sets 7a, 7b of the second set of boundary qubits 2. There are no crossings between the coupling structures 8, 9 located on the first layer 21.

[0064] The quantum chip 107 further comprises a second layer 22. On the second layer 22, a plurality of bulk coupling structures 9 for providing connectivity between neighboring qubits 2, 3 in the X-direction is provided. Furthermore, a plurality of boundary coupling structures 8 for providing connectivity between pairs of boundary qubits 2 located in the first and second sets of boundary qubits 6a, 6b of the first pair is provided. In this way, all coupling structures 8, 9 for providing the required connectivities in the X-direction (Y-direction) are located on the second (first) layer. Thereby, crossings between the coupling structures 8, 9 on the same layer are prevented.

[0065] Figs. 9a and 9b are schematic representations of two layers 21 , 22 of a quantum chip 108 according to an eight embodiment of the present invention which is a modification of the quantum chip 107 according to the seventh embodiment shown in Figs. 8a and 8b.

[0066] Again, as in the quantum chips 105, 106, 107, the quantum chip 108 comprises a qubit array 1 located on the first layer 21 . Furthermore, the quantum chip 108 comprises on the first layer 21 three boundary coupling structures which provide all-to-all connectivity between all qubits in two neighboring columns. Each of the boundary coupling structures comprises a first part 8a extending in the Y-direction along a coupling path located intermediate between the two neighboring columns of qubits towards the chains of boundary qubits 2 in the first and second sets on two opposite sides 1c, d of the array 1 , and a second part 8b for coupling the bulk or boundary qubits 2, 3 of the two neighboring columns and the first part 8a. In one example, the first part 8a may comprise a resonator or other signal-conducting transmission line, and the second part 8b may comprise a tunable coupler, e.g., a transmon qubit. Thereby, the boundary coupling structure also acts as bulk coupling structure. Furthermore, the quantum chip 108 comprises at its second layer 22 three boundary coupling structures similar to the ones on the first layer 21 but turned by 90 degrees and providing all-to-all connectivity between qubits in neighboring rows of the chip when the first layer 21 and the second layer 22 are superimposed. Thereby the first part 8a extends in the X-direction and a quantum chip having closed boundary conditions (CBC) in two directions is provided.

[0067] Figs. 10a, b, c are schematic representations of three layers of a quantum chip 109 according to a ninth embodiment of the present invention, wherein the array of qubits 1 , and first and second boundary coupling structures 8 are located on three different layers of the chip 109. To be more precise, the quantum chip 109 comprises a first layer 21 on which the qubit array 1 is located. The qubit array 1 is the same as the qubit array 1 of the quantum chips of the fifth to eighth embodiment shown above. A plurality of bulk coupling structures 9 is also provided on the first layer 21 , said bulk coupling structures (dashed lines) being configured for providing connectivity between neighboring qubits of the array 1 . At the second layer 22, four individual boundary coupling structures 8 are located for providing connectivity between pairs of boundary qubits 2 in first and second sets 7a, 7b of the second pair of boundary qubits in the Y-direction. Furthermore, the quantum chip 109 comprises a third layer 23, wherein four individual boundary coupling structures 8 are located for providing connectivity between pairs of boundary qubits 2 in the first and second sets of boundary qubits in the X-direction. In this way, closed boundary conditions CBC in two directions are implemented without any crossings between coupling structures located on the same layer. In this embodiment, closed boundary conditions CBC are achieved in two directions on different layers of the chip.

[0068] Figure 11 is a schematic representation of an area of a quantum chip 101 of the present invention wherein multiple air bridges 5 are used for connecting different parts of the chip 101. In an implementation which uses air bridges 5, connections between qubits, like part of boundary or bulk coupling structures or pairs thereof, are lifted above one another.

Claims

PATENT CLAIMS1. Quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) comprising a qubit array (1 ) comprising first and second sets (6a, b) of boundary qubits (2) on opposite sides (1a, b) of the array (1 ) and a set of bulk qubits (3) inside the array (1 ), said set of bulk qubits (3) being comprised between the first and second sets (6a, b) of boundary qubits (2), wherein a boundary coupling structure (8, 8a, 8b) providing connectivity between at least a boundary qubit (2) of the first set (6a) and a boundary qubit (2) of the second set (6b) is provided between said boundary qubits (2).

2. Quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) according to claim 1 , said quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) further comprising at least one bulk coupling structure (9) for providing connectivity between at least some of the bulk qubits (3) and / or between at least one bulk qubit (3) and at least one boundary qubit (2).

3. Quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) according to claim 2, said quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) comprising a plurality of bulk coupling structures (8, 8a, 8b) such that at least one pair of boundary qubits (2) for which the qubits are located on two further opposite sides (1c, d) of the array (1 ), respectively, and without connectivity provided by the boundary coupling structure (8, 8a, 8b) is connected via the plurality of bulk coupling structures (9) and the bulk qubits (3) to which they connect, in particular wherein the spatial separation between the two further opposite sides (1c, 1d) is smaller than the spatial separation between the opposite sides (1a, 1 b) having the boundary coupling structure therebetween.

4. Quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) according to anyone of the preceding claims, wherein the number of boundary qubits (2) of the first set (6a, 7a) equals the number of boundary qubits (2) of the second set (6b, 7b), in particular wherein for each of the boundary qubits (2) of the first set (6a, 7a) there exists a boundary qubit (2) of the second set (6b, 7b) having a coupling path of the boundary coupling structure (8, 8a, 8b) provided therebetween.

5. Quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) according to anyone of the preceding claims, wherein the boundary qubits (2) of the first and second sets (6a, 6b, 7a, 7b) are located on first and second parallel straight lines, respectively.

6. Quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) according to claim 5, wherein the array (1 ) is confined within a parallelogram having first and second pairs of first and second opposite sides (1a, b, c, d) with the qubits (2) located on the first and second opposite sides (1a, b) of the first pair forming a first pair of first and second sets (6a, b) of boundary qubits (2), respectively, and the qubits (2) located on the first and second opposite sides (1 c, d) of the second pair forming a second pair of first and second sets (7a, b) of boundary qubits (2), respectively, in particular wherein each of the bulk qubits (3) is located on one of the crossings of straight lines that extend between the boundary qubits (2) on opposite sides (1a, b, 1c, d) of the parallelogram in parallel with the sides of the parallelogram.

7. Quantum chip (103, 104), in particular according to anyone of claims 1-4, wherein the qubits of the array (1 ) are located on at least one closed curve, in particular on first and second parallel closed curves (11 , 12) with the qubits (2) located on the first and second parallel closed curves (11 , 12) forming a radial pair of first and second sets (7a, b) of boundary qubits, respectively.

8. Quantum chip (103, 104) according to claim 7, wherein each bulk qubit (3) is located on an additional parallel closed curve (13) that is between and parallel to the first and second parallel closed curves (11 , 12), in particular wherein the parallel closed curves (11 , 12, 13) are concentric circles or concentric ellipses.

9. Quantum chip (104) according to claim 8, wherein qubits on a closed curve (11 , 12, 13) are mutually offset in the circumferential direction to qubits on a neighbouring parallel closed curve.

10. Quantum chip (101 , 102, 103, 104, 105, 106, 107, 108, 109) according to anyone of the preceding claims, wherein the boundary coupling structure (8, 8a) comprises a non-local on-chip coupling structure, such as a long-distance coupling structure, in particular a longdistance resonator or a long-distance tuneable coupler.

11. Quantum chip (101 , 102) according to anyone of the preceding claims, wherein the boundary coupling structure (8, 8a, 8b) is implemented using air bridge technology.

12. Quantum chip (105, 106, 107, 108, 109) according to anyone of the preceding claims, wherein the chip (105, 106, 107, 108, 109) comprises a set of superimposed layers (21 , 22, 23), in particular the layers (21 , 22, 23) of the chip (105, 106, 107, 108, 109) are arranged according to a flip-chip architecture, and wherein the qubit array (1 ) and at least one of the boundary coupling structures (8, 8a, 8b) are located on different layers of the set, in particular wherein the boundary coupling structures (8,8a, 8b) and / or the bulk coupling structures (9) are distributed over the layers (21 , 22, 23) such that coupling structures located on the same layer avoid crossings between themselves.

13. Quantum chip (107, 108, 109) according to claim 12, said quantum chip (107, 108, 109) comprising first and second boundary coupling structures (8) which extend transversally to each other and are located on different layers (21 , 22, 23) of the set of layers, in particular wherein the qubit array (1 ), the first boundary coupling structure (8) and the second boundary coupling structure (8) are located on different layers (21 , 22, 23) of the set of layers, respectively.

14. Quantum chip (105, 106, 107, 108, 109) according to claim 6 and according to anyone of claims 12 or 13, wherein the coupling paths of each boundary coupling structure (8) in each layer (21 , 22, 23) extend in parallel to one of the pairs of first and second opposite sides of the parallelogram, respectively.

15. Quantum chip (105, 106, 107, 108, 109) according to anyone of claims 12 to 14, wherein connections between layers (21 , 22, 23) of the chip (101 ) are implemented by means of vias, in particular through silicon vias (TSV).

16. Quantum chip (105, 106, 107, 108, 109) according to anyone of the preceding claims, wherein the boundary coupling structure (8) comprises resonators with a crossing therebetween formed as an airbridge.

17. Method for performing quantum error detection and / or correction on a quantum chip (105, 106, 107, 108, 109) according to anyone of claims 1-16, wherein said method comprises implementing the quantum error correction by use of the connectivity between the qubits.

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