Phase-shifted discontinuous pulse-width modulation method and three-phase converter

Abstract

Disclosed are a phase-shifted discontinuous pulse-width modulation method and a three-phase converter. The phase-shifted discontinuous pulse-width modulation method comprises: when the three-phase converter is operating, within any switching period, switching devices of one-phase bridge arm are kept switched on or kept switched off, and a phase shift ratio delta phi exists between driver signals of the switching devices of the other two-phase bridge arms, so that at any moment a high-side switching device of each phase bridge arm in the three-phase bridge arm is not switched on or switched off at the same time. Compared with the prior art, the phase-shifted discontinuous pulse-width modulation method provided by the present invention optimizes three-phase converter efficiency on the basis of simplifying sampling circuit design and optimizing costs.

Description

A phase-shift discontinuous pulse width modulation method and a three-phase converter Technical Field

[0001] This invention relates to the field of discontinuous pulse width modulation technology, and in particular to a phase-shift discontinuous pulse width modulation method and a three-phase converter. Background Technology

[0002] Three-phase converters, as interface circuits between DC and AC power networks, have always occupied an important position in power electronics technology. In recent decades, industry and academia have been conducting research on these two types of converters, resulting in a wealth of academic achievements and technical solutions. Among these, optimizing the efficiency and cost of these two converters is undoubtedly an important research direction.

[0003] In existing technologies, the topology of a three-phase converter can be simplified as shown in Figure 1. Discontinuous Pulse Width Modulation (DPWM) is considered a mature and reliable efficiency optimization scheme. DPWM modulation allows one or two phase arms of the converter to remain inactive at the peaks and troughs of the AC current, significantly reducing switching losses. However, with existing DPWM modulation strategies, a large common-mode voltage exists between the midpoint M of the DC-side capacitor and the neutral point N of the AC-side filter capacitor. This necessitates isolation circuits between the DC-side and AC-side sampling circuits to ensure safe and stable hardware operation. The additional cost of these isolation circuits undoubtedly limits the application of DPWM modulation technology in three-phase converters.

[0004] Due to the current trend towards high frequency and high power density in power electronic converters, processes such as metal casings and multi-layer PCB structures are widely used in power electronic products. The journal article "Analysis and Improvement of the Effect Distributed Parasitic Capacitance on High-Frequency High-Density Three-Phase Buck Rectifier" points out that these processes create a common-mode interference path between the AC and DC sides of the three-phase converter, which severely degrades the AC side current quality. Therefore, a common-mode rejection circuit is generally required to reduce the impact of common-mode interference on the AC side current quality. The common-mode (CM) rejection circuit consists of a common-mode filter capacitor C... p and C nThe system consists of a Common Mode Suppressor Unit (CMSU), as shown in Figure 2. However, when using the existing DPWM modulation strategy, a large common-mode voltage v is introduced between points M and N. MN This common-mode voltage will generate a common-mode current on the common-mode suppression unit. This common-mode current circulates between the AC side inductor, the three-phase rectifier bridge arm and the common-mode suppression circuit, resulting in certain losses.

[0005] Chinese patent document CN116686201A discloses a discontinuous pulse width modulation (DPWM) method and a three-phase inverter modulation circuit. In this patent, the zero-sequence component is obtained by comparing the magnitudes of the three-phase AC voltages and then based on the maximum and minimum phase voltages. A coefficient "k" is introduced to adjust the zero-sequence component. This patent proposes a simplified implementation of the DPWM modulation strategy while retaining some of the high efficiency of the DPWM method. In this scheme, the zero-sequence component is calculated from the three-phase AC voltages and can be considered a constant value. The modulation signal, however, needs to be calculated using a loop. Therefore, when the loop fluctuates, the DPWM modulation strategy is difficult to implement.

[0006] Chinese patent document CN116827157A discloses a photovoltaic grid-connected inverter system and control method based on discontinuous modulation. In this patent, multi-objective optimization of the multi-level inverter is achieved by constructing a square wave signal. The intersection of the square wave and the three-phase sinusoidal modulation signal is used to divide the clamping interval. Common-mode current compensation and neutral point potential balancing are both achieved by adjusting the pulse width and amplitude of the square wave signal, making the implementation relatively simple. However, in this scheme, common-mode current compensation and neutral point potential balancing cannot be achieved simultaneously; a preset priority must be used to optimize one of the objectives. Furthermore, common-mode current compensation depends on the common-mode current loop, meaning the compensation has significant lag and can only compensate for the DC component of the common-mode current; therefore, the compensation effect is unsatisfactory.

[0007] Chinese patent document CN115566918A discloses a three-level inverter and its discontinuous pulse width modulation method and device. In this patent, clamping constraints and common-mode voltage constraints are applied using the three-phase modulation voltage and the initial minimum three-phase modulation voltage to generate multiple vector combinations. The optimal vector combination is selected based on the minimum neutral current to achieve effective control of the neutral point potential. However, this approach requires storing multiple vector combinations in the controller, consuming significant controller memory; it also necessitates frequent calculations of the minimum neutral current to select the optimal vector combination, slowing down software operation; furthermore, the modulation strategy requires frequent switching, leading to severe distortion of the three-phase AC side current. Summary of the Invention

[0008] To address the problems existing in the prior art, this invention proposes a phase-shift discontinuous pulse width modulation method and a three-phase converter.

[0009] The technical solution of the present invention is to design a phase-shift discontinuous pulse width modulation method, including: during the operation of a three-phase converter, in any switching cycle, the switching device of one phase bridge arm remains on or off, and there is a phase shift ΔΦ between the drive signals of the switching devices of the other two phase bridge arms, so that at any time, the upper bridge arm switching device of each phase bridge arm in the three-phase bridge arm does not simultaneously turn on or off.

[0010] Furthermore, in any given switching cycle, one phase arm's switching device remains either on or off, and there is a shift ratio ΔΦ between the drive signals of the switching devices in the other two phase arms, including:

[0011] When the modulation signal of the switching device of one phase of the three-phase converter is clamped to the carrier peak value, at any given time, at most one phase drive signal of the upper bridge arm switching device of the other two phases is at a high level; when the modulation signal of the switching device of one phase of the three-phase converter is clamped to the carrier valley value, at any given time, at least one phase drive signal of the upper bridge arm switching device of the other two phases is at a high level.

[0012] Furthermore, the provision that during any switching cycle, one phase arm's switching device remains on or off, and the drive signals of the other two phase arms' switching devices have a shift ratio ΔΦ, further includes:

[0013] First modulation strategy: In the three-phase converter, the switching device of one phase arm remains on or off, and the high-level midpoint of the drive signal of the upper arm switching device of the other two phase arms with the larger phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a smaller phase voltage is Φ2T. s ;

[0014] Second modulation strategy: In the three-phase converter, the switching device of one phase arm remains on or off, and the high-level midpoint of the drive signal of the upper arm switching device of the other two phase arms with the smaller phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a larger phase voltage is Φ2T. s ;

[0015] Among them, T s The switching period of the drive signal is ΔΦ = Φ2 - Φ1, and Φ2 > Φ1.

[0016] Furthermore, the AC cycle of the three-phase converter is divided into 3Z clamping intervals, each clamping interval including at least one switching cycle, and the clamping interval in which any phase modulation signal is clamped to the carrier peak or carrier valley is the clamping interval of the phase corresponding to the modulation signal.

[0017] Where Z is a positive integer.

[0018] Furthermore, the switching time between any two adjacent clamping intervals is the start or end time of the switching cycle of the drive signal.

[0019] Furthermore, within the clamping interval where any one phase modulation signal is in the rising and falling phases, the high-level midpoint position of the drive signal of the upper bridge arm switching device of the bridge arm corresponding to the modulation signal is different, so that at any given time, the upper bridge arm switching device of each phase bridge arm in the three-phase bridge arm is not simultaneously turned on or off.

[0020] Furthermore, including:

[0021] The high-level midpoint position of the driving signal of the bridge arm corresponding to the modulation signal can be changed when the modulation signal enters the clamping interval of the phase corresponding to the modulation signal, when it exits the clamping interval of the phase corresponding to the modulation signal, or within the clamping interval of the phase corresponding to the modulation signal.

[0022] Furthermore, the AC cycle of the three-phase converter is divided into 6 clamping intervals, and the switching times of the 6 clamping intervals are t1, t2, t3, t4, t5, and t6 in sequence.

[0023] The A-phase modulation signal of the three-phase converter changes the high level of the upper bridge arm switching device at the intermediate times of t1, t3, t4, t6; the B-phase modulation signal changes the high level of the upper bridge arm switching device at the intermediate times of t2, t3, t5, t6; and the C-phase modulation signal changes the high level of the upper bridge arm switching device at the intermediate times of t1, t2, t4, t5.

[0024] Furthermore, the AC cycle of the three-phase converter is divided into 12 clamping intervals, and the switching times of the 12 clamping intervals are t0, t1, t2, t3, t4, t5, t6, t7, t8, t9 ... 10 t 11 ;

[0025] When the three-phase converter operates under the first modulation strategy, the A-phase modulation signal of the three-phase converter is at t0, t1, t5, t6, t7, t... 11 By changing the midpoint of the high-level signal of the upper bridge arm switching device, the B-phase modulation signal is at t3, t4, t5, t9, t 10 t11 By changing the high-level midpoint of the upper bridge arm switching device, the C-phase modulation signal changes the high-level midpoint of the upper bridge arm switching device at t1, t2, t3, t7, t8, and t9.

[0026] The present invention also proposes a three-phase converter employing the above-mentioned phase-shift discontinuous pulse width modulation method, comprising: an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm; wherein in any switching cycle, the switching device of one phase bridge arm of the A-phase bridge arm, the B-phase bridge arm, and the C-phase bridge arm remains on or off, and there is a phase shift ΔΦ between the drive signals of the switching devices of the other two phase bridge arms, so that at any given time, the upper bridge arm switching device of each phase bridge arm in the three-phase bridge arm does not simultaneously turn on or off.

[0027] Compared with the prior art, the present invention has at least the following beneficial effects:

[0028] The phase-shift discontinuous pulse width modulation method proposed in this invention maintains one phase arm's switching device on or off during any switching cycle, while the drive signals of the other two phase arms' switching devices have a phase shift ΔΦ. This ensures that at any given time, the upper arm switching devices of each of the three phase arms are not simultaneously on or off, reducing the common-mode voltage and common-mode current between the DC-side capacitor midpoint M and the AC-side filter capacitor neutral point N, thus reducing the overall loss of the three-phase converter to a certain extent. Furthermore, using the phase-shift discontinuous pulse width modulation method proposed in this invention eliminates the need for the additional isolation circuit used in existing DPWM modulation, and the reference ground of the sampling circuit can be uniformly placed at the DC-side capacitor midpoint or the AC-side filter capacitor neutral point. In other words, the phase-shift discontinuous pulse width modulation method proposed in this invention optimizes the efficiency of the three-phase converter while simplifying the sampling circuit design and optimizing costs. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 is a schematic diagram of the three-phase converter circuit topology;

[0031] Figure 2 is a schematic diagram of the circuit topology of a three-phase converter with a common-mode rejection circuit;

[0032] Figures 3(a) to 3(f) are schematic diagrams of six existing DPWM modulation strategies;

[0033] Figure 4 is a schematic diagram of the six-interval division method of the PSDPWM modulation strategy of the present invention;

[0034] Figures 5(a) to 5(f) are schematic diagrams of the PWM timing of the DPWM1, PSDPWM_1 and PSDPWM_2 modulation strategies in regions R1 and R2;

[0035] Figure 6 is a schematic diagram of a three-phase voltage source rectifier topology;

[0036] Figures 7(a) to 7(c) show the common-mode voltage v of DPWM1 and the proposed PSDPWM modulation strategy during one switching cycle in the X1 interval. MN Schematic diagram;

[0037] Figures 8(a) to 8(d) show the simulation waveforms of the PSDPWM modulation strategy;

[0038] Figure 9 shows the PWM timing of the PSDPWM_SS1 modulation strategy in the X1 to X3 intervals;

[0039] Figure 10 shows the PWM timing of the PSDPWM_SS2 modulation strategy in the X1 to X3 intervals;

[0040] Figures 11(a) to 11(b) show the simulation results of the 6-interval PSDPWM_1 and PSDPWM_SS1 modulation strategies when the interval is updated within the switching cycle;

[0041] Figure 12 shows the simulation results of the 6-interval PSDPWM_1 modulation strategy when the interval is updated at the beginning or end of the switching cycle;

[0042] Figure 13 is a schematic diagram of the interval division method of the PSDPWM modulation strategy 12 of the present invention;

[0043] Figure 14 shows the PWM timing of the PSDPWM_TS1 modulation strategy in the S1 to S6 intervals;

[0044] Figure 15 shows the PWM timing of the PSDPWM_TS2 modulation strategy in the S1 to S6 intervals.

[0045] Figures 16(a) and 16(b) show the simulation results of the 12-interval PSDPWM_1 and PSDPWM_TS1 modulation strategies when the interval is updated within the switching cycle;

[0046] Figure 17 shows the simulation results of the 12-interval PSDPWM_1 modulation strategy when the interval is updated at the beginning of the switching cycle;

[0047] Figure 18 shows the overall control logic of this invention. Detailed Implementation

[0048] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0049] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0050] The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0051] In existing technologies, the three-phase converter topology can be simplified as shown in Figure 1. When using the existing DPWM modulation strategy, a large common-mode voltage exists between the midpoint M of the DC-side capacitor and the neutral point N of the AC-side filter capacitor. This necessitates the use of isolation circuits between the DC-side sampling circuit and the AC-side sampling circuit to ensure the safe and stable operation of the hardware circuitry. The additional cost of the isolation circuit undoubtedly limits the application of DPWM modulation technology in three-phase converters.

[0052] This invention proposes a phase-shift discontinuous pulse width modulation method. By controlling the phase shift ΔΦ, it reduces the voltage across the common-mode suppression unit and the current flowing through it, thereby optimizing the efficiency of the three-phase converter while simplifying the sampling circuit design and optimizing costs. The common-mode suppression unit can be composed of components such as capacitors, inductors, and resistors, or even a single wire.

[0053] Figures 3(a) to 3(f) illustrate six existing DPWM modulation strategies. The improved phase-shift discontinuous pulse width modulation method proposed in this invention is not limited to these six examples of DPWM. The following section uses the DPWM1 modulation strategy in Figure 3(a) as an example to elaborate on the specific implementation measures and theoretical derivation of the proposed improved modulation strategy.

[0054] Specifically, the present invention provides a phase-shift discontinuous pulse width modulation method, comprising:

[0055] During the operation of the three-phase converter, in any switching cycle, the switching device of one phase arm remains on or off, and there is a shift ratio ΔΦ between the drive signals of the switching devices of the other two phase arms, so that at any time, the upper arm switching device of each phase arm in the three-phase bridge arm does not simultaneously turn on or off.

[0056] Here, the three-phase converter referred to in this article can be a three-phase AC / DC converter or a three-phase DC / AC converter, both of which can be applied to the design concept of this invention, and this invention does not impose any specific limitations on them.

[0057] This invention can significantly reduce the voltage across the common-mode suppression unit and the current flowing through it by controlling the shift ratio ΔΦ, thereby achieving the goal of optimizing the efficiency of the three-phase converter while simplifying the sampling circuit design and optimizing costs.

[0058] The modulation strategies proposed in this invention include a first modulation strategy (hereinafter referred to as PSDPWM_1 modulation strategy) and a second modulation strategy (hereinafter referred to as PSDPWM_2 modulation strategy).

[0059] In the above scheme, for the shift ratio ΔΦ, if the switching device of one phase arm remains on or off during any switching cycle, the phase of the drive signal of the switching device of the other two phase arms is determined, which means the shift ratio ΔΦ is determined. By reasonably selecting the shift ratio ΔΦ, the voltage across the common mode suppression unit and the current flowing through it can be significantly reduced.

[0060] Specifically, in this invention, when one phase arm's switching device remains on or off during any switching cycle, and there is a shift ratio ΔΦ between the drive signals of the other two phase arms' switching devices, the two modulation strategies included are as follows:

[0061] First modulation strategy: In the three-phase converter, the switching device of one phase arm remains on or off, and the high-level midpoint of the drive signal of the upper arm switching device of the other two phase arms with the larger phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a smaller phase voltage is Φ2T. s ;

[0062] Second modulation strategy: In the three-phase converter, the switching device of one phase arm remains on or off, and the high-level midpoint of the drive signal of the upper arm switching device of the other two phase arms with the smaller phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a larger phase voltage is Φ2T. s ;

[0063] Where Ts is the period of the modulated signal, ΔΦ = Φ2 - Φ1, and Φ2 > Φ1.

[0064] Please refer to Figure 18. The overall control logic of this invention is that, during the operation of the three-phase converter, the switching device of one phase bridge arm is kept on or off during any switching cycle, and there is a shift ratio ΔΦ between the drive signals of the switching devices of the other two phase bridge arms.

[0065] When the first modulation strategy is used, the switching device of one phase arm in the three-phase converter is kept on or off. The high-level midpoint of the drive signal for the upper arm switching device of the other two phase arms with the larger phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a smaller phase voltage is Φ2T. s ;

[0066] When the second modulation strategy is used, the switching device of one phase arm of the three-phase converter is kept on or off. The high-level midpoint of the drive signal for the upper arm switching device of the other two phase arms with the smaller phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a larger phase voltage is Φ2T. s ;

[0067] As shown in Figure 4, existing literature has presented various clamping implementation methods for the DPWM1 modulation strategy, mainly including: clamping methods based on sector division and clamping methods based on zero-sequence component injection. Clamping refers to the situation where the switching transistor of a certain phase arm does not operate, and the modulation signal of that phase is clamped to the carrier peak value or carrier valley value.

[0068] Taking regions R1 and R2 in Figure 4 as examples, the PWM timing diagrams of the two proposed modulation strategies are shown in Figure 5. Figures 5(a) and 5(d) show the PWM timing diagrams of the DPWM1 modulation strategy in regions R1 and R2, respectively. Within one switching cycle, the equivalent upper and lower switches of phase A bridge arm do not operate, and the high-level midpoint of the equivalent upper switch drive signal of phases B and C bridge arms is Φ. c T s , usually Φ c =0.5.

[0069] Figures 5(b) and 5(c) show the PWM timing diagrams for the two PSDPWM modulation strategies present in the R1 region, respectively.

[0070] As shown in Figure 5(b), within one switching cycle, the PWM timing of the PSDPWM_1 modulation strategy is as follows: the equivalent upper and lower switches (S1 and S4) of the A-phase bridge arm do not operate, and the high-level midpoint of the drive signal of the equivalent upper switch (S3) of the B-phase bridge arm is Φ1T. s The midpoint of the high level of the equivalent upper switch (S5) drive signal of phase C bridge arm is Φ2T. s .

[0071] Here, the equivalent upper and lower switches (S1 and S4) of phase A bridge arm are the switching devices of the non-operating phase bridge arm mentioned above.

[0072] The equivalent upper switch (S3) of the B-phase bridge arm is the upper bridge arm switching device of the bridge arm with a larger phase voltage as mentioned above.

[0073] The equivalent upper switch (S5) of the C-phase bridge arm is the upper bridge arm switching device of the bridge arm with the smaller phase voltage mentioned above.

[0074] Φ1 and Φ2 are both phases. The shift ratio ΔΦ mentioned above is the difference between Φ1 and Φ2. Here, we set Φ2>Φ1.

[0075] As shown in Figure 5(c), within one switching cycle, the PWM timing of the PSDPWM_2 modulation strategy is as follows: the equivalent upper and lower switches (S1 and S4) of the A-phase bridge arm do not operate, and the midpoint of the high level of the drive signal of the equivalent upper switch (S5) of the C-phase bridge arm is Φ1T. s The midpoint of the high level of the equivalent upper switch (S3) drive signal of phase B bridge arm is Φ2T. s .

[0076] Here, the equivalent upper and lower switches (S1 and S4) of phase A bridge arm are the switching devices of the non-operating phase bridge arm mentioned above.

[0077] The equivalent upper switch (S3) of the B-phase bridge arm is the upper bridge arm switching device of the bridge arm with a larger phase voltage as mentioned above.

[0078] The equivalent upper switch (S5) of the C-phase bridge arm is the upper bridge arm switching device of the bridge arm with the smaller phase voltage mentioned above.

[0079] Φ1 and Φ2 are both phases. The shift ratio ΔΦ mentioned above is the difference between Φ1 and Φ2. Here, we set Φ2>Φ1.

[0080] Furthermore, based on the above control logic, during any switching cycle, the switching device of one phase arm remains on or off, and there is a shift ratio ΔΦ between the drive signals of the switching devices of the other two phase arms, including:

[0081] When the modulation signal of the switching device of one phase arm of the three-phase converter is clamped to the carrier peak value, at any given time, at most one phase drive signal of the upper bridge arm switching device of the other two phase arms is at a high level; when the modulation signal of the switching device of one phase arm of the three-phase converter is clamped to the carrier valley value, at any given time, at least one phase drive signal of the upper bridge arm switching device of the other two phase arms is at a high level.

[0082] In the control logic described above, the drive signals of the upper and lower bridge arm switching devices of any phase bridge arm in the three-phase converter are complementary, and a dead time is set when the upper bridge arm switching device and the lower bridge arm switching device of the same bridge arm switch state switch.

[0083] It is used to prevent the upper and lower equivalent switching devices from being turned on simultaneously during the turn-on and turn-off delay time of the switching device, which would cause a capacitor short circuit fault.

[0084] The equivalent switching drive signals for the remaining two phases are defined as follows: The PSDPWM_1 modulation strategy is defined as the high-level midpoint of the switching device of the upper bridge arm with the larger phase voltage, with the midpoint of the high level being Φ1T. s The midpoint of the high-level switching device of the upper bridge arm with a smaller phase voltage is Φ2T. s And ΔΦ = Φ2 - Φ1 > 0. Conversely, it is a PSDPWM_2 modulation strategy.

[0085] Please refer to Figure 6, taking a three-phase voltage source rectifier as an example, to illustrate the common-mode voltage v of the DPWM1 and PSDPWM_1 modulation strategies. MN Perform theoretical derivation.

[0086] To simplify the analysis, a unipolar binary logic switching function s is defined for the three-phase voltage source rectifier. x for:

[0087] (1)

[0088] Where "1" represents the upper transistor being on and the lower transistor being off, and "0" represents the upper transistor being off and the lower transistor being on. Based on Kirchhoff's voltage law, the voltage loop equation for the three-phase voltage source rectifier is as follows:

[0089] (2)

[0090] Where v xE =s x V o (x=A,B,C).

[0091] Considering a three-phase symmetrical system, we have

[0092] (3)

[0093] Combining formulas (1), (2), and (3), we can obtain

[0094] (4)

[0095] v ME For capacitor C n The voltage across the two ends is generally considered to be .

[0096] Therefore, within one switching cycle, the common-mode voltage v of the DPWM1 modulation strategy and the proposed PSDPWM modulation strategy... MN The schematic diagram is shown in Figure 7. As can be seen from Figure 7, compared to the DPWM1 modulation strategy, the common-mode voltage v of the PSDPWM_1 and PSDPWM_2 modulation strategies... MN The peak value has decreased significantly.

[0097] Figures 8(a) and 8(b) show the circuits without common-mode rejection, and V o At 600V, the common-mode voltage v of the DPWM1 modulation strategy and the PSDPWM_1 modulation strategy. MN ;

[0098] Figures 8(c) and 8(d) respectively show the common-mode rejection circuit (using a CMSU composed of capacitors as an example), and V o At 600V, the common-mode voltage v of the DPWM1 modulation strategy and the PSDPWM_1 modulation strategy. MN and common-mode current i MN The simulated waveform.

[0099] As shown in Figures 8(a) to 8(d), the theoretical and simulation results of the DPWM1 modulation strategy and the PSDPWM_1 modulation strategy are completely consistent when the common-mode rejection circuit is not included.

[0100] With common-mode rejection circuitry, the common-mode voltage v of the PSDPWM_1 modulation strategy is reduced due to the addition of the common-mode rejection unit. MN The peak-to-peak value is significantly reduced; therefore, compared to the DPWM1 modulation strategy, the common-mode voltage v of the PSDPWM_1 modulation strategy is significantly lower. MN Peak-to-peak value and common-mode current i MN The effective values ​​were all significantly reduced.

[0101] The theory and simulation results of the PSDPWM_2 modulation strategy are similar to those of the PSDPWM_1 modulation strategy, and will not be elaborated further here.

[0102] Furthermore, the aforementioned phase-shift discontinuous pulse width modulation strategy includes: the AC cycle of the three-phase converter is divided into 6 clamping intervals, and the switching times of the 6 clamping intervals are t1, t2, t3, t4, t5, and t6 respectively. The A-phase modulation signal of the three-phase converter exits the clamping interval at times t1 and t4 and enters the clamping interval at times t3 and t6. The B-phase modulation signal of the three-phase converter exits the clamping interval at times t3 and t6 and enters the clamping interval at times t5 and t2. The C-phase modulation signal of the three-phase converter exits the clamping interval at times t5 and t2 and enters the clamping interval at times t1 and t4.

[0103] The A-phase modulation signal of the three-phase converter changes the high level of the upper bridge arm switching device at the intermediate times of t1, t3, t4, t6; the B-phase modulation signal changes the high level of the upper bridge arm switching device at the intermediate times of t2, t3, t5, t6; and the C-phase modulation signal changes the high level of the upper bridge arm switching device at the intermediate times of t1, t2, t4, t5.

[0104] As shown in Figure 4, the corresponding waveform of the A-phase modulated signal is M. A The corresponding waveform of the B-phase modulated signal is M. B The corresponding waveform of the C-phase modulated signal is M. C .

[0105] In this invention, the AC cycle of the three-phase converter is divided into 3Z clamping intervals, and each clamping interval includes at least one switching cycle.

[0106] Where Z is a positive integer.

[0107] In this embodiment, Z is 2, and the AC cycle of the three-phase converter is divided into 6 clamping intervals.

[0108] As shown in Figure 4, the DPWM1 modulation strategy divides the AC cycle of a three-phase converter into 6 clamping intervals (X1~X6). According to the improvement method described above, the DPWM1 modulation strategy can be improved into a PSDPWM modulation strategy. However, in order to reduce the distortion of AC side inductor current, the modulation strategies of adjacent intervals still need to be coordinated to a certain extent.

[0109] The improved modulation strategy proposed in this invention includes: within the clamping interval where any phase modulation signal is in the rising and falling phases, the high-level intermediate position of the drive signal of the upper bridge arm switching device of the bridge arm corresponding to the modulation signal is different, so that at any time, the upper bridge arm switching device of each phase bridge arm in the three phase bridge arms is not simultaneously turned on or off.

[0110] It also includes: any one of the phase modulation signals can be selected to change the midpoint of the high level of the drive signal of the corresponding phase bridge arm when entering the clamping interval, exiting the clamping interval, or within the clamping interval.

[0111] The specific method is as follows:

[0112] Please refer to Figure 4. Within the clamping interval where the modulation signal is in the rising and falling phases, the midpoint of the high-level driving signal of the upper bridge arm switching device of the bridge arm corresponding to the modulation signal is different. If the midpoint of the high-level driving signal of the upper bridge arm switching device of the bridge arm corresponding to the modulation signal in the rising phase interval is Φ1T s Then, during the falling phase interval, the midpoint of the high-level drive signal of the upper bridge arm switching device corresponding to the modulation signal is Φ2T. s ;vice versa.

[0113] That is, the midpoint of the high level of the drive signal of the upper bridge arm switching device of the A phase bridge arm in intervals 2 and 3 should be different from that in intervals 5 and 6;

[0114] The midpoint of the high-level driving signal of the upper bridge arm switching device in the B-phase bridge arm in intervals 1 and 2 should be different from that in intervals 4 and 5.

[0115] The midpoint of the high-level modulation signal of the upper bridge arm switching device drive signal in intervals 3 and 4 should be different from that in intervals 1 and 6.

[0116] The high-level midpoint of the driving signal of the bridge arm corresponding to the modulation signal can be changed when entering the clamping interval of the phase corresponding to the modulation signal, exiting the clamping interval of the phase corresponding to the modulation signal, or within the clamping interval of the phase corresponding to the modulation signal.

[0117] Please refer to Figure 4. The A-phase modulation signal of the three-phase converter changes the high level of the upper bridge arm switching device at the midpoints of t1, t3, t4, and t6. The B-phase modulation signal changes the high level of the upper bridge arm switching device at the midpoints of t2, t3, t5, and t6. The C-phase modulation signal changes the high level of the upper bridge arm switching device at the midpoints of t1, t2, t4, and t5.

[0118] Based on the above ideas, it is clear that there are multiple overall modulation strategies based on 6 intervals (hereinafter referred to as PSDPWM_SS modulation strategies) within an AC cycle. Two of these PSDPWM_SS modulation strategies (PSDPWM_SS1 and PSDPWM_SS2) are given as examples below, as shown in Figures 9 and 10.

[0119] The PWM timing of the PSDPWM_SS1 modulation strategy in the X1 to X3 intervals are shown in Figure 9. The PWM timing in the other intervals can be derived by themselves based on the modulation improvement ideas mentioned above, and specific PWM timing diagrams are not given here.

[0120] The PWM timing of the PSDPWM_SS2 modulation strategy in the X1 to X3 intervals is shown in Figure 10. The PWM timing in the other intervals can be derived by themselves based on the modulation improvement ideas mentioned above, and specific PWM timing diagrams are not given here.

[0121] Figures 11(a) and 11(b) show the simulation results for the PSDPWM_1 and PSDPWM_SS1 modulation strategies in six intervals, respectively. As can be seen from Figures 11(a) and 11(b), the PSDPWM_SS1 modulation strategy, without changing v... MN and i MN Based on this, the distortion of AC side inductor current during interval switching was eliminated.

[0122] Furthermore, the improved modulation strategy proposed in this invention also includes: the switching time between any two adjacent clamping intervals is the start or end time of the switching cycle of the driving signal.

[0123] Its specific description is as follows:

[0124] The cause of AC side inductor current distortion: An abnormality occurred in the AC side inductor voltage, leading to an imbalance in the volt-second product of the AC side inductor within a short period of time, causing the inductor current to change in one direction and resulting in distortion. Taking the update from interval 1 to interval 2 as an example, Figure 12 shows the simulation results of AC side inductor voltage and current when the interval is updated at the beginning or end of the switching cycle.

[0125] As shown in Figure 11(a), the voltage of the B-phase inductor is abnormal when switching between intervals, which causes the volt-second product to be greater than 0 in a short time, and the inductor current to increase rapidly, resulting in distortion.

[0126] As shown in Figure 12, the inductor voltage of phase B also exhibits anomalies during the interval switching, but the change in the volt-second product is significantly reduced compared to Figure 11(a), so the distortion of the inductor current is not obvious.

[0127] Furthermore, the aforementioned phase-shift discontinuous pulse width modulation strategy also includes: dividing the AC cycle of the three-phase converter into 12 clamping intervals, with the switching times of the 12 clamping intervals being t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t... 10 t 11 The A-phase modulation signal of the three-phase converter exits the clamping interval at times t1 and t7, and at times t5 and t6... 11 When the three-phase converter enters the clamping interval, the B-phase modulation signal is at t5 and t6. 11 The C-phase modulation signal of the three-phase converter exits the clamping interval at times t9 and t3, and enters the clamping interval at times t1 and t7.

[0128] When the three-phase converter operates under the first modulation strategy, the A-phase modulation signal of the three-phase converter is at t0, t1, t5, t6, t7, t... 11 By changing the midpoint of the high-level signal of the upper bridge arm switching device, the B-phase modulation signal is at t3, t4, t5, t9, t 10 t 11 By changing the high-level midpoint of the upper bridge arm switching device, the C-phase modulation signal changes the high-level midpoint of the upper bridge arm switching device at t1, t2, t3, t7, t8, and t9.

[0129] As shown in Figure 13, the corresponding waveform of the A-phase modulated signal is M. A The corresponding waveform of the B-phase modulated signal is M. B The corresponding waveform of the C-phase modulated signal is M. C .

[0130] In this invention, the AC cycle of the three-phase converter is divided into 3Z clamping intervals, and each clamping interval includes at least one switching cycle.

[0131] Where Z is a positive integer.

[0132] In this embodiment, Z is 4, and the AC cycle of the three-phase converter is divided into 12 clamping intervals.

[0133] Dividing Figure 4 into 12 intervals (S1~S12) within one AC cycle yields Figure 13. Based on the improvement method described above, the DPWM1 modulation strategy can be improved to a PSDPWM modulation strategy. However, to reduce AC side inductor current distortion, the modulation strategies of adjacent intervals still need to be coordinated to a certain extent.

[0134] The improved modulation strategy proposed in this invention includes: within the clamping interval where the modulation signal is in the rising and falling phases, the high-level midpoint position of the driving signal of the upper bridge arm switching device of any phase bridge arm is different.

[0135] It also includes: any one of the phase modulation signals can be selected to change the midpoint of the high level of the drive signal of the corresponding phase bridge arm when entering the clamping interval, exiting the clamping interval, or within the clamping interval.

[0136] The specific method is as follows:

[0137] The approach to resolving AC-side inductor current distortion at the interval switching point within interval 12 is similar to that within interval 6. The difference is that, in addition to changing the midpoint of the high-level time of the modulated signal when it enters or exits the clamping interval, the midpoint of the high-level time of the modulated signal can also be changed when switching between clamping intervals.

[0138] That is: the A-phase modulation signal of the three-phase converter at t0, t1, t5, t6, t7, t 11 By changing the midpoint of the high-level signal of the upper bridge arm switching device, the B-phase modulation signal is at t3, t4, t5, t9, t 10 t 11 By changing the high-level midpoint of the upper bridge arm switching device, the C-phase modulation signal changes the high-level midpoint of the upper bridge arm switching device at t1, t2, t3, t7, t8, and t9.

[0139] Furthermore, consistent with the idea of ​​the 6-interval improvement measures, in order to ensure the implementation of the PSDWPM modulation strategy, the midpoint of the high level of the modulation signal in the interval where the rising phase of the modulation signal and the falling phase of the modulation signal are located should be different. This is consistent with the idea of ​​the 6-interval improvement measures, please refer to the above, and will not be repeated here.

[0140] Taking phase A as an example, if phase A is driven at t1, t5, t7, t... 11 When the change occurs, the modulation strategy improvement measures in the 12th interval are equivalent to those in the 6th interval, which will not be elaborated here. If the A-phase drive is changed at t0 or t6, there are two modulation strategies in the 12th interval (hereinafter referred to as PSDPWM_TS1 and PSDPWM_TS2 modulation strategies) that can eliminate the distortion of the AC side inductor current interval switching point.

[0141] The PWM timing of the PSDPWM_TS1 modulation strategy in the S1 to S6 intervals is shown in Figure 14. The PWM timing in the other intervals can be derived by themselves based on the modulation improvement ideas mentioned above, and specific PWM timing diagrams are not given here.

[0142] The PWM timing of the PSDPWM_TS2 modulation strategy in the S1 to S6 intervals is shown in Figure 15. The PWM timing in the other intervals can be derived by themselves based on the modulation improvement ideas mentioned above, and specific PWM timing diagrams are not given here.

[0143] Figures 16(a) and 16(b) show the simulation results for the PSDPWM_1 and PSDPWM_TS1 modulation strategies within 12 intervals, respectively. As can be seen from Figure 16, the PSDPWM_TS1 modulation strategy, without changing v... MN and i MN Based on this, the distortion of AC side inductor current during interval switching was eliminated.

[0144] Furthermore, the improved modulation strategy proposed in this invention also includes: the switching time between any two adjacent clamping intervals is the start or end time of the switching cycle of the driving signal.

[0145] Both the 12-interval and 6-interval division methods can employ interval switching at the end or beginning of the switching cycle to reduce distortion at the switching point of the AC side inductor current sector. When updating from interval 2 to interval 3, the inductor L... a Taking the voltage as an example, Figure 17 shows the simulation results of the AC side inductor voltage and current at the beginning of the switching cycle update of the interval.

[0146] As shown in Figure 16(a), the inductor voltage of phase B is abnormal when switching between zones, which causes the volt-second product to be greater than 0 in a short period of time, and the inductor current to increase rapidly, resulting in distortion. As shown in Figure 17, the inductor voltage of phase B is also abnormal when switching between zones, but the change in the volt-second product is smaller than that in Figure 16(a), so the distortion of the inductor current is not obvious.

[0147] In summary, this invention proposes a phase-shift discontinuous pulse width modulation method applicable to both AC / DC and DC / AC converters. Within the switching cycle, this method modifies the PWM timing based on existing DPWM modulation strategies, adding a phase shift between the equivalent switching drive signals of two non-clamped phases.

[0148] During the AC cycle, two improvement measures are implemented: any one phase modulation signal can be selected to change the high-level midpoint position of the drive signal of the bridge arm corresponding to the modulation signal when entering the clamping interval of the phase corresponding to the modulation signal, when exiting the clamping interval of the phase corresponding to the modulation signal, or within the clamping interval of the phase corresponding to the modulation signal.

[0149] It significantly eliminates the distortion of AC-side inductor current during interval switching in cases of 6-interval division and 12-interval division. At the same time, for various existing DPWM modulation strategies, the same idea (adding a phase shift between the equivalent switching drive signals of two non-clamped phases and two improvement measures) can be used to improve different DPWM modulation strategies.

[0150] The phase-shift discontinuous pulse width modulation (PWM) method proposed in this invention can significantly reduce the common-mode voltage between the midpoint of the DC-side capacitor and the neutral point of the AC-side capacitor. When a common-mode rejection circuit is applied in the converter, the proposed PWM method can also significantly reduce the common-mode current in the common-mode rejection unit. Due to the reduction in common-mode voltage and current, the common-mode rejection circuit can be easily applied in AC / DC converters and DC / AC converters, and the proposed PWM method improves the AC-side current quality. Because of the reduced common-mode voltage, the reference ground of the sampling circuit can be uniformly set to the midpoint of the DC-side capacitor or the neutral point of the AC-side filter capacitor, ensuring the safe and stable operation of the controller without additional isolation circuitry, thus simplifying the design of the sampling circuit. Due to the reduced common-mode current, the losses of the AC-side filter capacitor and inductor, switching devices, and the common-mode rejection circuit will all be reduced, thus optimizing the converter efficiency.

[0151] The present invention also proposes a three-phase converter using the above-mentioned phase-shift discontinuous pulse width modulation method, comprising: phase A bridge arm, phase B bridge arm, and phase C bridge arm;

[0152] In any switching cycle, one phase of the bridge arm (A-phase, B-phase, and C-phase) has a switching device that remains either on or off. The drive signals of the switching devices of the other two phases have a shift ratio ΔΦ, so that at any given time, the upper bridge arm switching device of each phase of the three-phase bridge arm is not simultaneously on or off.

[0153] Compared with the prior art, the present invention has at least the following beneficial effects:

[0154] The phase-shift discontinuous pulse width modulation method proposed in this invention ensures that, during any switching cycle, one phase arm's switching device remains either on or off, while the drive signals of the other two phase arms' switching devices have a phase shift ΔΦ. This prevents the upper arm switching devices of each of the three phase arms from simultaneously being on or off at any given time. This reduces the common-mode voltage and common-mode current between the DC-side capacitor midpoint M and the AC-side filter capacitor neutral point N, thereby reducing the overall loss of the three-phase converter to some extent. Furthermore, by employing the phase-shift discontinuous pulse width modulation method proposed in this invention, the additional isolation circuit used in existing DPWM modulation can be eliminated, and the reference ground of the sampling circuit can be uniformly placed at the DC-side capacitor midpoint or the AC-side filter capacitor neutral point. In other words, the phase-shift discontinuous pulse width modulation method proposed in this invention optimizes the efficiency of the three-phase converter while simplifying the sampling circuit design and optimizing costs.

[0155] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A phase-shift discontinuous pulse width modulation method, characterized in that, include: During the operation of the three-phase converter, in any switching cycle, the switching device of one phase arm remains on or off, and there is a shift ratio ΔΦ between the drive signals of the switching devices of the other two phase arms, so that at any time, the upper arm switching device of each phase arm in the three-phase bridge arm does not simultaneously turn on or off.

2. The phase-shift discontinuous pulse width modulation method according to claim 1, characterized in that, During any given switching cycle, one phase arm's switching device remains either on or off, and there is a shift ratio ΔΦ between the drive signals of the other two phase arms' switching devices, including: When the modulation signal of the switching device of one phase of the three-phase converter is clamped to the carrier peak value, at any given time, at most one phase drive signal of the upper bridge arm switching device of the other two phases is at a high level; when the modulation signal of the switching device of one phase of the three-phase converter is clamped to the carrier valley value, at any given time, at least one phase drive signal of the upper bridge arm switching device of the other two phases is at a high level.

3. The phase-shift discontinuous pulse width modulation method according to claim 1, characterized in that, During any given switching cycle, one phase arm's switching device remains either on or off, and there is a shift ratio ΔΦ between the drive signals of the switching devices in the other two phase arms. This also includes: First modulation strategy: In the three-phase converter, the switching device of one phase arm remains on or off, and the high-level midpoint of the drive signal of the upper arm switching device of the other two phase arms with the larger phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a smaller phase voltage is Φ2T. s ; Second modulation strategy: In the three-phase converter, the switching device of one phase arm remains on or off, and the high-level midpoint of the drive signal of the upper arm switching device of the other two phase arms with the smaller phase voltage is Φ1T. s The midpoint of the high-level drive signal of the upper bridge arm switching device in the bridge arm with a larger phase voltage is Φ2T. s ; Among them, T s The switching period of the drive signal is ΔΦ = Φ2 - Φ1, and Φ2 > Φ1.

4. The phase-shift discontinuous pulse width modulation method according to claim 3, characterized in that, The AC cycle of the three-phase converter is divided into 3Z clamping intervals, each clamping interval including at least one switching cycle. The clamping interval in which any phase modulation signal is clamped to the carrier peak or carrier valley is the clamping interval of the corresponding phase of the modulation signal. Where Z is a positive integer.

5. The phase-shift discontinuous pulse width modulation method according to claim 4, characterized in that, The switching time between any two adjacent clamping intervals is the start or end time of the switching cycle of the drive signal.

6. The phase-shift discontinuous pulse width modulation method according to claim 4, characterized in that, Within the clamping interval where any one phase modulation signal is in the rising and falling phases, the high-level midpoint position of the drive signal of the upper bridge arm switching device of the bridge arm corresponding to the modulation signal is different, so that at any time, the upper bridge arm switching device of each phase of the three-phase bridge arm is not simultaneously turned on or off.

7. The phase-shift discontinuous pulse width modulation method according to claim 6, characterized in that, include: The high-level midpoint position of the driving signal of the bridge arm corresponding to the modulation signal can be changed when the modulation signal enters the clamping interval of the phase corresponding to the modulation signal, when it exits the clamping interval of the phase corresponding to the modulation signal, or within the clamping interval of the phase corresponding to the modulation signal.

8. The phase-shift discontinuous pulse width modulation method according to claim 7, characterized in that, include: The AC cycle of the three-phase converter is divided into 6 clamping intervals, and the switching times of the 6 clamping intervals are t1, t2, t3, t4, t5, and t6, respectively. The A-phase modulation signal of the three-phase converter changes the high level of the upper bridge arm switching device at the intermediate times of t1, t3, t4, t6; the B-phase modulation signal changes the high level of the upper bridge arm switching device at the intermediate times of t2, t3, t5, t6; and the C-phase modulation signal changes the high level of the upper bridge arm switching device at the intermediate times of t1, t2, t4, t5.

9. The phase-shift discontinuous pulse width modulation method according to claim 7, characterized in that, The AC cycle of the three-phase converter is divided into 12 clamping intervals, and the switching times of the 12 clamping intervals are t0, t1, t2, t3, t4, t5, t6, t7, t8, t9 ... 10 t 11 ; When the three-phase converter operates under the first modulation strategy, the A-phase modulation signal of the three-phase converter is at t0, t1, t5, t6, t7, t... 11 By changing the midpoint of the high-level signal of the upper bridge arm switching device, the B-phase modulation signal is at t3, t4, t5, t9, t 10 t 11 By changing the high-level midpoint of the upper bridge arm switching device, the C-phase modulation signal changes the high-level midpoint of the upper bridge arm switching device at t1, t2, t3, t7, t8, and t9.

10. A three-phase converter employing the phase-shift discontinuous pulse width modulation method as described in any one of claims 1 to 9, characterized in that, include: Phase A, Phase B, and Phase C bridge arms; in any switching cycle, the switching device of one phase bridge arm of each of the three phase bridge arms remains on or off, and there is a shift ratio ΔΦ between the drive signals of the switching devices of the other two phase bridge arms, so that at any given time, the upper bridge arm switching device of each phase bridge arm is not simultaneously on or off.

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