Multi-electron-beam emission array chip and preparation method therefor

Abstract

Disclosed in the present invention are a multi-electron-beam emission array chip and a preparation method therefor. The preparation method for a multi-electron-beam emission array chip comprises: a) first film formation; b) first etching; c) second film formation; d) film removal; e) third film formation; f) second etching; g) fourth film formation; h) third etching; and i) post-treatment. By using production processes commonly used in micron-scale integrated circuit production technology, multiple film formation and etching operations can be performed on 6-inch or 8-inch inorganic non-metallic or metallic wafer substrates, and conical nano-scale electron emission tips made of micron-scale metal or semiconductor materials can be manufactured on the basis of the dimensions required for applications, such that the overall preparation process is simple, mature, stable and cost-effective, and the integrated manufacturing of systems such as electron beam focusing and detection can also be realized.

Description

Multi-electron beam emission array chip and its fabrication method Technical Field

[0001] This invention relates to the technical field of electron beam exposure, and in particular to the technical field of multi-electron beam emission array chips and their fabrication methods. Background Technology

[0002] Multi-electron beam lithography (MEB) devices, commonly used in nanoscale integrated circuit manufacturing, are core production equipment for electron beam lithography. They generate and control a focused electron beam to directly write onto a photomask or semiconductor wafer according to the circuit design layout. Their working principle is similar to a scanning electron microscope, typically including a "beam column" for generating and controlling the electron beam deflection, an electron beam splitter, an electron beam detection system, and a reflected electron detection system. They can control a highly focused electron beam spot with a diameter of 1–2 nm to achieve sub-nanometer precision positioning in the XY plane, as illustrated in invention publication CN1193129 (electron beam lithography system and its usage method) and invention publication CN1708729 (electron beam lithography method and apparatus). When a photomask (or semiconductor wafer) sample coated with electron-electron resist is located on the focal plane of an electromagnetic lens, an exposure pattern smaller than 10 nm can be obtained using a pattern generator, an electromagnetic lens group, and a scanning coil.

[0003] In electron beam lithography, the exposure rate is typically proportional to the electron beam current. However, if the beam current is too high, the Coulomb effect, which causes electrons to repel each other, limits the accuracy of the beam spot. To improve the exposure rate without compromising accuracy, electron beam lithography has evolved from Gaussian beams from single electron filaments and deformed beams from single electron filaments to multi-beam parallel exposure with single filaments split into multiple beams (i.e., existing multi-beam electron beam lithography techniques, such as the electron source used in multi-beam electron offset printing equipment disclosed in invention publication number CN1147753).

[0004] In existing multi-beam electron beam lithography technology, the tens of thousands of electron beams used in parallel exposure all originate from a single electron-emitting filament. To reduce the Coulomb effect between electron beams, the maximum beam current of each sub-electron beam in parallel exposure is on the order of 1 nA, and the stable beam current of each sub-electron beam needs to be consistent. Currently, the exposure time for a 7nm process photomask is within several hours, which cannot meet the needs of large-scale mass production of integrated circuits. Summary of the Invention

[0005] The purpose of this invention is to solve the problems in the prior art and to propose a multi-electron beam emission array chip and its fabrication method. This chip can manufacture high-density electron beam emission matrices of micron- or nano-scale metal or semiconductor materials at low cost and on a large scale, according to the size required for the application. Furthermore, the single or multiple electron beam emission needles in the matrix can be independently controlled or modulated.

[0006] To achieve the above objectives, this invention proposes a method for fabricating a multi-electron-beam emission array chip, comprising the following steps:

[0007] a) One-time film formation: An insulating first film layer is formed on the top surface of the substrate;

[0008] b) Single etching: Several corresponding through-holes and No. 1 film holes are etched on the substrate and the No. 1 film layer respectively (the size of the tip of the etched recess can determine the size of the emitting needle tip).

[0009] c) Secondary film formation: A second film layer capable of emitting electrons is formed on the top surface of the first film layer (i.e., the second film layer is made of a material that can cause electrons to escape from the atomic nucleus after absorbing a certain amount of energy and emit electrons), and the second film layer is deposited into each corresponding concave part and the first film pore to form emission needles respectively.

[0010] d) Membrane removal: Remove the portion of membrane layer 2 that is exposed on the top surface of membrane layer 1;

[0011] e) Three-stage film formation: An insulating third film layer is formed on the top surface of the first film layer and the third film layer covers the tips of each transmitting needle;

[0012] f) Secondary etching: Several No. 3 film holes that can be connected to each of the emission needles are etched on the No. 3 film layer;

[0013] g) Four-stage film formation: A conductive fourth film layer is formed on the top surface of the third film layer and the fourth film layer is deposited into each of the third film pores to form conductive pillars.

[0014] h) Three-stage etching: A connection circuit with emitter contact points is etched on the top surface of the fourth film layer;

[0015] i) Post-processing: Remove the substrate and encapsulate the package with a number of positioning holes corresponding to each conductive post on the top surface of the fourth film layer.

[0016] Preferably, each of the recesses is inverted conical in shape.

[0017] Preferably, the substrate is a metal substrate, a crystalline silicon substrate, or a silicon dioxide substrate, and the encapsulation sheet is a ceramic sheet, a carbon-based thin film, or an organic insulating thin film.

[0018] Furthermore, the metal substrate is an aluminum substrate. Aluminum has the advantages of being inexpensive and easy to remove (due to its low melting point).

[0019] Furthermore, when using crystalline silicon to prepare the substrate, 6-12 inch wafers can be selected, with 8-inch wafers being preferred.

[0020] Preferably, both the first and third film layers are inorganic insulating films deposited using chemical vapor deposition (CVD) technology.

[0021] Furthermore, the inorganic insulating film is a SiO2 film or a Si3N4 film.

[0022] Furthermore, the thickness of the first film layer is 1–100 μm, and the thickness of the third film layer is 1–100 μm.

[0023] Preferably, the second film layer is a tungsten thin film, other metal thin film, or semiconductor thin film deposited using tungsten plug cavitation (WCVD) technology, and the fourth film layer is a metal thin film with strong conductivity.

[0024] Furthermore, for the second film layer, the other metal films are titanium films, rhenium films, ruthenium films, platinum films, or zirconium films. That is, platinum can also be used to form the emission needle, but compared to tungsten, it is more difficult to produce and more expensive.

[0025] Furthermore, for the second film layer, the semiconductor thin film is a gallium arsenide thin film or an indium phosphide thin film.

[0026] Furthermore, for the fourth film layer, the metal film is a gold film, copper film, tungsten film, aluminum film, titanium film, or nickel film.

[0027] Furthermore, the thickness of the second film layer is 0.1–50 μm, and the thickness of the fourth film layer is 0.1–50 μm.

[0028] Preferably, steps b), f), and h) are all completed by photoresist etching or maskless laser etching, and step d) is completed by mechanical polishing or chemical mechanical polishing (CMP) to remove the film.

[0029] As a preferred embodiment, step j) external connection wires are also included: metal contact connection wires are installed at each positioning hole.

[0030] Furthermore, the metal contact wire is made of gold.

[0031] The multi-electron-beam split-emission array core is manufactured by the aforementioned preparation method.

[0032] The beneficial effects of this invention are:

[0033] 1) This invention employs a manufacturing process commonly used in micron-level integrated circuit production technology to perform multiple film deposition and etching operations on a 6-inch or 8-inch inorganic non-metallic or metal wafer substrate. This allows for the fabrication of micron-level metal or semiconductor tapered nanoscale electron emission needles according to the required size for the application. The overall fabrication process is simple, mature, stable, and low-cost, and it also enables the integrated manufacturing of electron beam focusing, detection, and other systems.

[0034] 2) This invention uses photoresist etching or maskless laser etching to etch the substrate and each film layer. By adjusting the etching area, duration and number, it can achieve precise control over the length and shape of a single electron emitting needle and the number of emitting needles per unit area in the electron emitting needle array (if the root diameter of each electron emitting needle is 10 μm and the spacing between the emitting needles is 10 μm, more than 25,000 electron emitting needles can be formed on an area of ​​1 square centimeter, and the tip size of each emitting needle is less than 1 nanometer).

[0035] 3) This invention achieves a high-strength and high-temperature resistant electron beam metal emitting needle body by using CVD tungsten (tungsten plug) technology, which can produce a uniform and high-density electron beam emitting array;

[0036] 4) This invention uses thin-film chemical vapor deposition technology to generate each film layer, which can ensure the uniformity and density of the film layer generation, so that the electron beam emission array chip can complete the electron emission work normally when applied in a multi-beam electron beam exposure machine.

[0037] 5) By forming nanoscale emission tips, this invention can greatly reduce the current passing through each emission needle, thereby reducing the electron Coulomb effect between emission needles and improving the resolution of electron beam exposure;

[0038] 6) Each emission point of the multi-electron beam emission chip of the present invention can be controlled individually, and the emission of the electron beam can be programmed and modulated according to the exposure pattern of the circuit design. This not only greatly improves the exposure efficiency of the photolithography mask, but also provides key technical support for breaking through the maskless electron beam lithography process of integrated circuits.

[0039] The features and advantages of the present invention will be described in detail through embodiments and in conjunction with the accompanying drawings. Attached Figure Description

[0040] Figure 1 is a flowchart of steps a) to d) of the fabrication method of the multi-electron beam emission array chip of the present invention;

[0041] Figure 2 is a flowchart of steps e) to g) of the fabrication method of the multi-electron beam emission array chip of the present invention;

[0042] Figure 3 is a flowchart of steps h) to i) of the fabrication method of the multi-electron beam emission array chip of the present invention;

[0043] Figure 4 is a three-dimensional structural schematic diagram of the multi-electron beam emission array chip of the present invention from one view.

[0044] Figure 5 is a three-dimensional structural diagram of the multi-electron beam emission array chip of the present invention from another perspective.

[0045] In the figure: 1-substrate, 11-recessed portion, 2-first film layer, 21-first film hole, 3-first photoresist layer, 31-first photoresist hole, 4-second film layer, 41-emitting needle, 5-third film layer, 51-third film hole, 6-second photoresist layer, 61-second photoresist hole, 7-fourth film layer, 71-conductive pillar, 72-connection circuit with emitter contact point, 8-third photoresist layer, 81-third photoresist hole, 9-encapsulation chip, 91-positioning hole, 10-metal contact connection wire. Detailed Implementation

[0046] Referring to Figures 1 to 3, the fabrication method of the multi-electron beam emission array chip of the present invention includes the following steps:

[0047] a) One-time film formation: An insulating first film layer 2 (an inorganic insulating film with a thickness of 1 to 50 μm deposited by chemical vapor deposition) is formed on the top surface of substrate 1 (metal substrate, crystalline silicon substrate or silicon dioxide substrate).

[0048] b) Single etching: Several corresponding and interconnected recesses 11 and membrane holes 21 are etched on the substrate 1 and the first film layer 2 respectively (using photoresist etching technology or maskless laser etching technology). (The recesses 11 are inverted cone shape, and the blind holes formed by the recesses 11 and the first film hole 21 are also inverted cone shape).

[0049] For photoresist etching technology, photoresist is first coated on the top surface of substrate 1 to form a first photoresist layer 3. After drying, a mask is used to block the light so that light can irradiate a part of the first photoresist layer 3. Then, a developer is used to dissolve the exposed or unexposed areas of the first photoresist layer 3 to form a first photoresist hole 31. Plasma generated under the action of an electric field passes through the first photoresist hole 31 and bombards and erodes the substrate 1 and the first film layer 2 until the concave part 11 and the first film hole 21 are generated (the plasma will first etch the first film layer 2 and then etch the substrate 1. Because there is photoresist material in the etching chamber, some photoresist material will cover the etched interface under ion bombardment and protect the interface from further etching, thereby obtaining an inverted conical cavity. By adjusting the parameters in the plasma etching chamber, cavities with different tapers can be etched). Finally, the remaining first photoresist layer 3 is removed and cleaned.

[0050] Photoresist etching technology can also be replaced by maskless laser etching technology (that is, using a high energy density laser to irradiate the top surface of the substrate 1, so that the surface material of the irradiated area undergoes a series of complex physical and even chemical processes such as heating, melting, vaporization, plasma formation, volatilization and sputtering to form the concave portion 11 and the first membrane hole 21).

[0051] c) Secondary film formation: A second film layer 4 capable of emitting electrons is formed on the top surface of the first film layer 2 (a metal or semiconductor thin film with a thickness of 0.1 to 50 μm deposited using tungsten plug technology) and the second film layer 4 is deposited into each corresponding recess 11 and the first film hole 21 to form emission needles 41 respectively.

[0052] d) Film removal: Remove the portion of film layer 4 exposed on the top surface of film layer 2 using mechanical polishing or chemical mechanical polishing techniques;

[0053] e) Three-stage film formation: An insulating third film layer 5 (an inorganic insulating film with a thickness of 1 to 50 μm deposited by chemical vapor deposition) is formed on the top surface of the first film layer 2, and the third film layer 5 covers the top of each emitting needle 41.

[0054] f) Secondary etching: Etch on the third film layer 5 separately (using photoresist etching technology, the same as step b), only replacing the first photoresist layer 3 and the first photoresist hole 31 with the second photoresist layer 6 and the second photoresist hole 61) to create several third film holes 51 that can be connected to each of the emission needles 41.

[0055] g) Quadruple film formation: A conductive fourth film layer 7 (a metal thin film with a thickness of 0.1 to 50 μm deposited using tungsten plug technology) is formed on the top surface of the third film layer 5, and the fourth film layer 7 is deposited into each of the third film holes 51 to form conductive pillars 71 respectively.

[0056] h) Third etching: Etch on the top surface of the fourth film layer 7 (using photoresist etching technology, same as step b), only the first photoresist layer 3 and the first photoresist hole 31 are replaced with the third photoresist layer 8 and the third photoresist hole 81) to form the connection circuit 72 with the emitter contact point;

[0057] i) Post-processing: Remove substrate 1 (if substrate 1 is aluminum substrate, it can be directly melted at high temperature to remove the substrate) and encapsulate a package 9 (ceramic sheet, carbon-based film or organic insulating film) with a number of positioning holes 91 corresponding to each conductive post 71 on the top surface of the fourth film layer 7. It can also be cut to the specified size.

[0058] j) External connection wire: Install metal contact connection wire 10 (gold wire) at each positioning hole 91.

[0059] Furthermore, the multi-electron beam split-emission array core manufactured by the aforementioned preparation method is shown in Figures 4 and 5 (the actual chip contains at least hundreds of thousands of electron emission needles, only a small number are shown in the figure).

[0060] The above embodiments are illustrative of the present invention and are not intended to limit the present invention. Any simple modifications to the present invention are within the scope of protection of the present invention.

Claims

1. A method for fabricating a multi-electron beam emission array chip, characterized in that, Includes the following steps: a) One-time film formation: An insulating first film layer (2) is formed on the top surface of the substrate (1). b) First etching: Several corresponding through recesses (11) and membrane holes (21) are etched on the substrate (1) and the first film layer (2), respectively. c) Secondary film formation: A second film layer (4) capable of emitting electrons is generated on the top surface of the first film layer (2), and the second film layer (4) is sunk into each corresponding recess (11) and the first film hole (21) to form emission needles (41) respectively. d) Membrane removal: Remove the portion of membrane layer 2 (4) that is exposed on the top surface of membrane layer 1 (2); e) Three-stage film formation: An insulating third film layer (5) is formed on the top surface of the first film layer (2) and the third film layer (5) covers the top of each transmitting needle (41); f) Secondary etching: Several No. 3 film holes (51) that can be connected to each of the emission needles (41) are etched on the No. 3 film layer (5). g) Four-stage film formation: A conductive fourth film layer (7) is formed on the top surface of the third film layer (5) and the fourth film layer (7) is deposited into each of the third film pores (51) to form conductive pillars (71) respectively. h) Third etching: A connection circuit (72) with emitter contact points is etched on the top surface of the fourth film layer (7). i) Post-processing: Remove the substrate (1) and encapsulate the package (9) with a number of positioning holes (91) corresponding to each conductive post (71) on the top surface of the fourth film layer (7).

2. The method for fabricating a multi-electron beam emission array chip as described in claim 1, characterized in that: Each of the aforementioned concave portions (11) is inverted conical in shape.

3. The method for fabricating a multi-electron beam emission array chip as described in claim 1, characterized in that: The substrate (1) is a metal substrate, a crystalline silicon substrate, or a silicon dioxide substrate, and the encapsulation sheet (9) is a ceramic sheet, a carbon-based thin film, or an organic insulating thin film.

4. The method for fabricating a multi-electron beam emission array chip as described in claim 1, characterized in that: Both the first film layer (2) and the third film layer (5) are inorganic insulating films deposited using chemical vapor deposition technology.

5. The method for fabricating a multi-electron beam emission array chip as described in claim 4, characterized in that: The thickness of the first film layer (2) is 1 to 100 μm, and the thickness of the third film layer (5) is 1 to 100 μm.

6. The method for fabricating a multi-electron beam emission array chip as described in claim 1, characterized in that: The second film layer (4) is a tungsten thin film, other metal thin film or semiconductor thin film deposited using tungsten plug technology, and the fourth film layer (7) is a metal thin film with strong conductivity.

7. The method for fabricating a multi-electron beam emission array chip as described in claim 6, characterized in that: The thickness of the second film layer (4) is 0.1 to 50 μm, and the thickness of the fourth film layer (7) is 0.1 to 50 μm.

8. The method for fabricating a multi-electron beam emission array chip as described in claim 1, characterized in that: Steps b), f), and h) are all completed using photoresist etching or maskless laser etching, and step d) is completed using mechanical polishing or chemical mechanical polishing.

9. The method for fabricating a multi-electron beam emission array chip as described in claim 1, characterized in that: It also includes step j) external connection line: metal contact connection wire (10) is installed at each positioning hole (91).

10. A multi-electron beam emission array chip, characterized in that: It is prepared by any one of claims 1 to 9.

Images