Low-dropout regulator in gate-all-around process

Abstract

The present disclosure describes various aspects of implementing a low-dropout regulator in a gate-all-around process. In some aspects, a low-dropout (LDO) regulator circuit includes an amplifier and a power transistor with a source terminal coupled to a power rail. The LDO circuit may also include protection circuitry configured to prevent devices of the circuit from exceeding inter-terminal voltage ratings, which may protect the devices from damage when the LDO circuit is active or inactive. In some implementations, the protection circuitry includes a transistor coupled in series with the power transistor, voltage sources that provide signals or bias at intermediate voltages below a voltage of the power rail, and other transistors that operate based on or apply the intermediate voltages to the devices of the circuit. By so doing, the LDO circuit can be implemented in advanced fabrication processes (e.g., gate-all-around) in which devices may have reduced inter-terminal voltage ratings.

Description

LOW-DROPOUT REGULATOR IN GATE-ALL-AROUND PROCESSBACKGROUND

[0001] To achieve further power, performance, and area (PPA) optimizations with each generation of semiconductor process technology, silicon designers typically shrink device geometries or implement more-complex device structures. Generally, this allows for increased device densities, better performance, or reduced power consumption in circuits fabricated using newer process technologies. In many cases, the decrease in device size and advanced geometries enable circuits of devices, such as transistors, to operate at lower voltages and thereby reduce power consumption over similar circuits fabricated with preceding generations of process technology. These smaller and more-complex device structures, however, often have lower interterminal voltage ratings and are therefore susceptible to damage when exposed to higher interterminal voltage levels commonly used with earlier process technologies. Because many circuit designs are typically carried forward from an earlier process technology with higher voltage tolerances, moving these circuit designs to a next generation process technology or process node can result in circuits that expose devices to voltage levels that exceed the lower inter-terminal voltage ratings of the devices. As such, circuit designs implemented in the next generation process technology may include circuits in which devices are damaged when voltages throughout the circuit exceed the lower inter-terminal voltage ratings of the devices.SUMMARY

[0002] This disclosure describes apparatuses of and techniques for implementing a low-dropout (LDO) regulator in a gate-all-around process or other advanced process technology. In various aspects, an LDO regulator circuit includes an amplifier and a power transistor with a source terminal coupled to a power rail. The LDO circuit may also include protection circuitry configured to prevent devices of the circuit from exceeding inter-terminal voltage ratings, which may prevent device damage when the LDO circuit is active, inactive, or transitioning between various operating states. In some implementations, the protection circuitry includes a transistor coupled in series (e.g., cascode) with the power transistor, voltage sources that provide signals or bias at intermediate voltages below a voltage of the power rail, and other transistors that operate based on or apply the intermediate voltages to the devices of the circuit. By doing so, the LDO circuit can be implemented in an advanced fabrication processes (e.g., gate-all-around) in which devices may have inter-terminal voltage ratings that are lower than preceding process technologies.

[0003] In some aspects, a circuit for regulating power includes a first transistor having a source terminal coupled to a power rail and a second transistor having a source terminal coupled to a drain terminal of the first transistor, a drain terminal coupled to an output node of the circuit, and a gate terminal coupled to a first selectively controlled intermediate voltage source. The first selectively controlled intermediate voltage source can be configured to provide a first signal at a voltage lower than the voltage of the power rail. The circuit also includes a first resistor having a first terminal coupled to the output node of the circuit and a second resistor having a first terminal coupled to a second terminal of the first resistor and a second terminal coupled to a ground reference. An amplifier has a power input coupled to the power rail, a ground node coupled to the ground reference, a first input coupled to a reference voltage source, a second input coupled to the first terminal of the second resistor, and an output coupled to a gate of the first transistor.

[0004] The circuit may further comprise a third transistor having a drain terminal coupled to the drain terminal of the first transistor, a source terminal coupled to an intermediate bias voltage source, and a gate terminal coupled to a second selectively controlled intermediate voltage source. The intermediate bias voltage source may be configured to provide power at a voltage lower than the voltage of the power rail. The second selectively controlled intermediate voltage source may be configured to provide a second signal at a voltage lower than the voltage of the power rail.

[0005] The circuit may further comprise a fourth transistor having a source terminal coupled to the power rail, a drain terminal coupled to the gate terminal of the first transistor, and a gate terminal coupled to a third selectively controlled intermediate voltage source. The third selectively controlled intermediate voltage source may be configured to provide a third signal at a voltage lower than the voltage of the power rail.

[0006] The circuit may further comprise a fifth transistor having a drain terminal coupled to the output node of the circuit, a source terminal coupled to the ground reference, and a gate terminal coupled to a fourth selectively controlled intermediate voltage source. The fourth selectively controlled intermediate voltage source may be configured to provide a fourth signal at a voltage lower than the voltage of the power rail.

[0007] The gate terminal of the second transistor and the gate terminal of the fifth transistor may be coupled to the same selectively controlled intermediate voltage source. That is, the first selectively controlled intermediate voltage source and the fourth selectively controlled intermediate voltage source may be the same selectively controlled intennediate voltage source, control signal, and / or configured with a same signaling polarity (e.g., for power up or power down states).

[0008] The first selectively controlled intermediate voltage source may comprise level shifting logic coupled to the power rail. The level shifting logic may be configured to provide the signal at the voltage lower than the voltage of the power rail.

[0009] The first selectively controlled intermediate voltage source may be configured to apply the signal at the voltage lower than the voltage of the power rail to the gate terminal of the second transistor when the circuit for regulating power is in an inactive state.

[0010] The amplifier may comprise an amplifier circuit, the amplifier circuit comprising: a first amplifier transistor having a source terminal coupled to the power rail and a drain coupled, as the output of the amplifier, to the gate of the first transistor; a second amplifier transistor having a source terminal coupled to the power rail, a gate terminal coupled to a gate terminal of the first amplifier transistor; and a drain terminal coupled to the gate terminal of the first amplifier transistor; a third amplifier transistor having a drain terminal coupled to the drain terminal of the first amplifier transistor and a gate terminal coupled to a fifth selectively controlled intermediate voltage source, the fifth selectively controlled intermediate voltage source configured to provide a fifth signal at a voltage lower than the voltage of the power rail; a fourth amplifier transistor having a drain terminal coupled to the drain terminal of the second amplifier transistor and a gate terminal coupled a sixth selectively controlled intennediate voltage source, the sixth selectively controlled intermediate voltage source configured to provide a sixth signal at a voltage lower than the voltage of the power rail; a fifth amplifier transistor having a drain terminal coupled to a source terminal of the third amplifier transistor and a gate terminal coupled, as the first input of the amplifier, to the reference voltage source; a sixth amplifier transistor having a drain terminal coupled to a source terminal of the fourth amplifier transistor, a gate terminal coupled, as the second input of the amplifier, to the first terminal of the second resistor, and a source terminal coupled to a source terminal of the fifth amplifier transistor; and a seventh amplifier transistor having a drain terminal coupled to the source of the sixth amplifier transistor and a source terminal coupled to the ground reference.

[0011] The gate terminal of the third amplifier transistor and the gate terminal of the fourth amplifier transistor may be coupled to a same selectively controlled intermediate voltage source. That is, the fifth selectively controlled intermediate voltage source and the sixth selectively controlled intermediate voltage source may be the same selectively controlled intermediate voltage source, control signal, and / or configured with a same signaling polarity (e.g., for power up or power down states).

[0012] In some instances, the fifth selectively controlled intermediate voltage source and the second and / or third selectively controlled intermediate voltage source may be the same selectivelycontrolled intermediate voltage source, control signal, and / or configured with a same signaling polarity (e.g., for power up or power down states).

[0013] The amplifier circuit may further comprise an eighth amplifier transistor having a drain terminal coupled to a current source, a source tenninal coupled to the ground reference, and a gate terminal coupled to the current source and a gate terminal of the seventh amplifier transistor.

[0014] The amplifier circuit may further comprise a ninth amplifier transistor having a drain terminal coupled to the gate terminal of the eighth amplifier transistor, a source terminal coupled to the ground reference, and a gate tenninal coupled a seventh selectively controlled intermediate voltage source. The seventh selectively controlled intermediate voltage source may be configured to provide a seventh signal at a voltage lower than the voltage of the power rail.

[0015] The seventh selectively controlled intermediate voltage source and the first and / or fourth selectively controlled intermediate voltage source may be the same selectively controlled intermediate voltage source, control signal, and / or configured with a same signaling polarity (e.g., for power up or power down states).

[0016] The amplifier circuit may further comprise a tenth amplifier transistor having a source terminal coupled to the power rail, a drain terminal coupled to the gate terminal of the second amplifier transistor, and a gate tenninal coupled to an eighth selectively controlled intennediate voltage source. The eighth selectively controlled intermediate voltage source may be configured to provide an eighth signal at a voltage lower than the voltage of the power rail.

[0017] The gate terminal of the tenth amplifier transistor and at least one of the gate terminal of the third amplifier transistor or the gate terminal of the fourth amplifier transistor may be coupled to a same selectively controlled intermediate voltage source. That is, the eighth selectively controlled intermediate voltage source and the fifth and / or sixth selectively controlled intermediate voltage source may be the same selectively controlled intermediate voltage source, control signal, and / or configured with a same signaling polarity (e.g., for power up or power dow n states).

[0018] The amplifier circuit may further comprise an eleventh amplifier transistor having a source terminal coupled to the drain terminal of the third amplifier transistor, a drain terminal coupled to an intermediate bias voltage source, and a gate terminal coupled to a ninth selectively controlled intennediate voltage source. The amplifier circuit may further comprise a twelfth amplifier transistor having a source terminal coupled to the drain terminal of the fourth amplifier transistor, a drain terminal coupled to the intermediate bias voltage source, and a gate terminal coupled to the ninth selectively controlled intermediate voltage source. The ninth selectively controlled intermediate voltage source may be configured to provide a ninth signal at a voltage lower than the voltage of the power rail.

[0019] The ninth selectively controlled intermediate voltage source and the fifth and / or sixth selectively controlled intermediate voltage source may be the same selectively controlled intermediate voltage source, control signal, and / or configured with a same signaling polarity (e.g., for power up or power down states).

[0020] In other aspects, a method for operating the circuit for regulating power includes operating the circuit in an active state and operating the circuit in an inactive state. When operating in the active state, the circuit provides regulated power at the output node of the circuit, and the selectively controlled intermediate voltage source of the circuit does not apply the signal at the lower voltage to the gate of the second transistor. Alternatively, when operating in the inactive state, the circuit does not provide the regulated power at the output node of the circuit, and the selectively controlled intermediate voltage source applies the signal at the lower voltage to the gate of the second transistor. By so doing, the second transistor may prevent inter-terminal voltages of the power transistor from exceeding a voltage rating of devices fabricated using a process that yields devices with voltage ratings that are less than the voltage of the power rail.

[0021] The above described method may optionally include one or more further features described above in the context of the circuit for regulating pow er.

[0022] The details of one or more implementations of an LDO regulator in a gate-all-around process are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description and drawings, and from the claims. This summary is provided to introduce subject matter that is further described in the Detailed Description and Drawings. Accordingly, this summaij’ is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.BRIEF DESCRIPTION OF THE DRAWINGS

[0023] This disclosure describes apparatuses of and techniques for implementing a low-dropout (LDO) regulator in a gate-all-around process with reference to the following drawings. The use of same or similar reference numbers throughout the description and the figures may indicate like features or components:FIG. 1 illustrates an example operating environment that includes user devices in which aspects of an LDO regulator in a gate-all-around process can be implemented;FIG. 2 illustrates an example system environment that includes a power system and a system-on-chip in which an LDO regulator is implemented in accordance with one or more aspects;FIG. 3 illustrates an example configuration of an LDO regulator implemented with device protection circuitry in accordance with one or more aspects;FIG. 4 illustrates another example configuration of an LDO regulator implemented with protection circuitry in accordance with one or more aspects;FIG. 5 illustrates an example of the LDO regulator of FIG. 4 in an active state in accordance with one or more aspects;FIG. 6 illustrates an example of the LDO regulator of FIG. 4 in an inactive state in accordance with one or more aspects;FIG. 7 illustrates an example method for transitioning an LDO regulator to a powerdown state in accordance with one or more aspects;FIG. 8 illustrates example method for transitioning an LDO regulator to a power-up state in accordance with one or more aspects;FIG. 9 illustrates an example method for operating an LDO regulator in accordance with one or more aspects; andFIG. 10 illustrates an example system on chip (SoC) environment in which aspects of a low-dropout regulator in a gate-all-around process may be implemented.DETAILED DESCRIPTION

[0024] As process technologies for semiconductor fabrication advance, circuit designers often migrate integrated-circuit (IC) designs from an existing process technology to a next-generation process technology. Next-generation or subsequent process technologies typically feature smaller device geometries, increased device densities, and lower operating voltages than preceding processes, which can improve performance and reduce power consumption of the IC designs. The smaller and more-complex device structures of the newer process technologies, however, often have lower inter-terminal voltage ratings than preceding processes and are therefore susceptible to damage when exposed to higher inter-terminal voltage levels commonly used with the earlier process technologies. For example, many ICs include an input / output (I / O) power supply from which I / O circuitry operates. Although the I / O power supply typically operates at a higher voltage (e.g., 1.2 volts (1.2V)) than other IC power supplies, devices produced with preceding generations of process technology (e.g., a fin field-effect transistor (FinFET) process) were rated to operate with inter-terminal voltages of 1.2 V. In other words, various transistors or diodes produced through a FinFET process are '‘true” 1.2V devices that could safely operate from a 1.2V power supply without damage. A next generation process technology, such as a gate-all-around (GAA) process, however, may produce devices with lower inter-terminal voltage ratings (e.g., 0.85V). As such, when IC designs migrate from an existing process technology (e.g., FinFET) to a nextgeneration process technology (e.g., GAA), circuits of devices with lower inter-terminal voltage ratings (0.7-0.9 V) can be exposed to voltages (e.g., 1.2V I / O supply) that exceed the ratings of those devices. This can result in circuit designs that fail safe operation area (SOA) checks for devices during schematic capture or devices that sustain damage when powered on after fabrication.

[0025] In contrast with these preceding design methodologies, this disclosure describes aspects for implementing a low-dropout (LDO) regulator in a gate-all-around (GAA) process or other advanced process. Generally, the described aspects may enable a circuit design to pass SOA checks for a GAA process and ensure that devices of the circuit operate within specified interterminal voltage ratings. In some implementations, an LDO regulator circuit includes power down circuitry and is configured to operate from a power supply or power rail with a voltage that exceeds inter-terminal voltage ratings of devices of the circuit (e.g., GAA devices). In accordance with one or more aspects, the LDO regulator circuit includes protection circuitry configured to shield or buffer the devices of the LDO regulator circuit from voltage that exceeds the inter-terminal voltage ratings of the devices. For example, the protection circuitry may include or implement a series or cascode device for a power switch of the LDO regulator circuit, intermediate bias voltages, a buffer device, level shifters, or the like. By ensuring that inter-terminal voltages of the devices of the LDO regulator circuit do not exceed rated values during operation of the circuit, the described aspects may enable the LDO regulator circuit to pass SOA checks and / or operate safely from a supply voltage in excess of the inter-terminal voltage ratings of the devices.

[0026] In various aspects, an LDO regulator circuit includes an amplifier and protection circuitry as described herein, which may prevent devices of the LDO regulator circuit from being exposed to voltages that exceed respective inter-terminal voltage ratings of the devices. In some aspects, an LDO regulator circuit includes an amplifier and a power transistor with a source terminal coupled to a power rail. The LDO circuit may also include protection circuitry7configured to prevent devices of the circuit from exceeding inter-terminal voltage ratings, which may protect the devices from damage when the LDO circuit is active or inactive. In some implementations, the protection circuitry includes a transistor coupled in cascode with the power transistor, voltage sources that provide signals or bias at intermediate voltages below7a voltage of the pow er rail, and other transistors that operate based on or apply the intermediate voltages to the devices of the circuit. By so doing, the LDO circuit can be implemented in advanced fabrication processes (e.g., gate-all-around) in which devices may have reduced inter-terminal voltage ratings.

[0027] The following discussion describes an operating environment, techniques that may be employed in the operating environment, and various devices or systems in which components of the operating environment can be embodied. In the context of the present disclosure, reference ismade to the operating environment by way of example only.Example Environment

[0028] FIG. 1 illustrates an example environment 100 that includes a user device 102 in which aspects of a low-dropout (LDO) regulator in a gate-all-around (GAA) process or another advanced process technology can be implemented. The user device 102 may be implemented as any suitable device, some of which are illustrated as a smart-phone 104, a tablet computer 106, a laptop computer 108, a wearable computing device 110 (e.g., smart-watch), a broadband router 112 (e.g., mobile hotspot), and automotive computing system 114 (e.g.. navigation and entertainment system). Although not shown, the user device 102 may also be implemented as any of a mobile station (e.g., fixed- or mobile-STA), a mobile communication device, a client device, a user equipment, a mobile phone, an entertainment device, a gaming device, a mobile gaming console, a personal media device, a media playback device, a health monitoring device, a drone, a camera, a wearable smart-device, an Internet home appliance capable of wireless Internet access and browsing, an loT device, and / or other types of user devices. The user device 102 may provide other functions or include components or interfaces omitted from FIG. 1 for the sake of clarity7or visual brevity.

[0029] In this example, some components of the user device 102 are implemented as a system- on-chip 116 (SoC 116), although these components may be implemented separately or in other configurations (e.g., integrated circuits or systems). As shown in FIG. 1, the SoC 116 includes a processor core 118 and memory7120, which may include computer-readable media, memory7media, and / or storage media. The processor core 118 may be implemented as a general-purpose processor core (e.g., of a multicore central-processing unit (CPU) or application processor (AP)), an application-specific integrated circuit (ASIC), graphics processing unit (GPU), or a processor core with other components of the user device 102 integrated therewith. The memory7120 can include any suitable type of computer-readable media, memory media, and / or storage media. For example, the memory 120 may include read-only7memory (ROM), programmable ROM (PROM), random access memory7(RAM), dynamic RAM (DRAM), static RAM (SRAM), or Flash memory. In the context of this disclosure, the memory' 120 of the user device 102 is implemented as a hardware-based or physical storage device, which does not include transitory signals or carrier waves. Applications, firmware, and / or an operating system (not shown) of the user device 102 can be embodied on the memory 120 as processor-executable instructions, which the processor core 118 may execute to provide various functionalities of the user device 102. The memory7120 may also store device data, such as user data or user media that is accessible by the applications, firmware, or operating system of the user device 102.

[0030] In this example, the SoC 116 also includes instances of input / output logic 122 (I / O logic 122), a first power rail 124, a low-dropout regulator 126 (LDO regulator 126), device protection circuitry7128, and a second power rail 130. The I / O logic 122 may include circuitry' configured to interface control logic of the processor core 118 with various analog and / or digital I / O circuits of the user device 102. For example, the I / O logic 122 can enable the processor core 118 or other control logic to interface with sensors, data ports, transceivers, or other components of the user device 102. In various implementations, respective circuitry of the processor core 118, memory' 120, and I / O logic 122 may operate at different voltages provided by a power system 132 of the user device 102 that includes a power supply 134. In some aspects, the first power rail 124 of the SoC 116 is coupled to and receives power from the power supply 134 at a first voltage. The LDO regulator 126 may be coupled to the first power rail 124 and convert or regulate power received from the first power rail 124 to provide power to the second power rail 130 at a second voltage that is lower than the first voltage. Generally, the I / O logic 122 may operate from the power provided by the first power rail 124 at the first voltage and other circuitry’ of the SoC 116 may operate from the power provided by' the LDO regulator 126 on the second power rail 130 at the second voltage. In aspects, the LDO regulator 126 includes device protection circuitry 128 configured to enable devices of circuitry of the LDO regulator 126 to operate at the first voltage, which may exceed inter-terminal voltage ratings of the devices of the LDO regulator 126. How the device protection circuitry 128 is implemented and used varies, and is described throughout the disclosure.

[0031] In aspects, the power system 132 includes one or more power supplies 134, which provide regulated power to the components of the user device 102 and / or the SoC 116. In various implementations, a user device 102 may include or be configured with a display 136, transceivers 138, I / O ports 140, or sensors 142, which can receive power from the power supplies 134 of the power system 132. The power supplies 134 of the power system 132 may include any suitable type of power supply, such as linear regulators, switch-mode power supplies, multiphase switching regulators, or the like. In some cases, the power supplies 134 are configured to provide power at different respective voltage levels for the various components of the user device 102. For example, one of the power supplies 134 may include a switching regulator configured to step battery power (e.g., 3.7 to 4.2 V) or external power (e.g., 5.0 V) down to power at a voltage (e.g., 1.2 V) at which the I / O logic 122 is configured to operate.

[0032] The display 136, transceivers 138, I / O ports 140 and / or sensors 130 of the user device 102 may be configured in any suitable fashion and can be operably^ coupled with the I / O logic 122. For example, the display 136 may be coupled with the processor core 118 or another processor of the SoC 116 (e.g., graphics processing unit (GPU), not shown) and configured tographically present an operating system or applications of the user device 102. The transceivers 138 enable the user device 102 to communicate data (e.g., device data) over wired or wireless networks according to any suitable communication protocol. The I / O ports 140 of the user device 102 may include USB ports, coaxial cable ports, and other serial or parallel connectors (including internal connectors) useful to couple the user device to various components, peripherals, or accessories such as keyboards, microphones, or cameras. Alternatively or additionally, the sensors 130 can enable the user device 102 to sense various properties, variances, stimuli, or characteristics of an environment in which the user device 102 operates. For example, the sensors 130 may include a motion sensor, an ambient light sensor, an acoustic sensor, a capacitive sensor, an infrared sensor, a temperature sensor, a radar sensor, or a magnetometer.

[0033] FIG. 2 illustrates at 200 an example of a powder system that includes an LDO regulator 126 and device protection circuitry 128 shown in FIG. 1. Generally, the power system 132 provides pow er to a load, which in this example includes components and circuitry of the SoC 116. The components of the SoC 116 that draw power from the power system 132 may include the I / O logic 122 and other circuitry' 202 of the SoC 116, which may include the processor core 118 or memory' 120. In some cases, the other circuitry' 202 includes processor circuits, memory' circuits, intellectual property blocks (IP blocks), communication circuits, or circuitry that operates from a voltage lower than a voltage at which the I / O logic 122 operates. The power system 132 may receive input power from an external power source 204 (e.g., external AC / DC adapter) or one or more battery cells 206 of a battery' or battery pack electrically coupled to the user device 102. Switchover circuitry 208, which may include charging or other power management circuits, electrically couples the external power source 204 or the battery cell 206 to the power supply 134.

[0034] Generally, the power supply 134 can regulate power received from the external power source 204 or the battery' cell 206 to provide power to the components of the user device 102 at a voltage at which the components operate. Thus, the power supply 134 or an intermediate pow er supply (not shown) can be configured to regulate upstream power to provide power at a voltage at which the SoC 116 operates. As shown in FIG. 2, an output of the power supply 134 is operably coupled to an input of the SoC 116 to provide the power to the first power rail 124 at a first voltage. In aspects, the first pow er rail is coupled to components of the SoC 116 that are configured to operate at the first voltage, which in this example include the I / O logic 122 and the LDO regulator 126. In aspects, the LDO regulator 126 is configured to regulate power received from the first power rail 124 to provide power to the second power rail 130 at a second voltage that is lower than the first voltage. The second power rail 130 may then provide power to the other circuitry' 202 (e.g., processor or memory' circuits) of the SoC 116 coupled to the second pow er rail, which operates at the second voltage level.

[0035] As described herein, devices of circuitry that form the LDO regulator 126 or other SoC circuits may have inter-terminal voltage ratings that are less than the first voltage of the first power rail 124. For example, devices (e.g., transistors or diodes) of the LDO regulator 126 fabricated in a GAA process or other advanced process technology may have inter-terminal voltage ratings less than the voltage of the first power rail. In aspects of implementing an LDO in a GAA or other advanced process, the LDO regulator 126 includes device protection circuitry 128, which can be configured to protect the devices of the LDO regulator 126 from voltages that exceed respective inter-terminal voltage ratings. In other words, various aspects of the protection circuitry' 128 may enable the LDO regulator 126 to function in various operational modes without the devices of the LDO being exposed to voltage that exceeds the inter-terminal ratings to prevent damage of the devices. In some implementations, the device protection circuitry 128 includes additional transistors or implements signals and / or bias at one or more intermediate voltages from level shifters 210. In aspects, the level shifters 210 may provide reference, control, or bias signals at a voltage less than the first voltage of the first power rail 124, examples of which are described throughout this disclosure.

[0036] FIG. 3 illustrates at 300 an example configuration of an LDO regulator implemented with device protection circuitry' in accordance with one or more aspects. In this example, an LDO regulator circuit is operably coupled to a first power rail from which the LDO receives power at a first voltage and operably coupled to a second power rail to which the LDO regulator provides regulated power at a second voltage, which is lower than the first voltage. In aspects, the LDO regulator circuit includes device protection circuitry of one or more devices (e.g., transistors, switches) operably coupled with and / or between devices or components of the LDO regulator. The illustrated components and architectures of FIGs. 3-6 are presented as anon-limiting example of ways in which an LDO regulator circuit with device protection circuitry' can be implemented. As such, the aspects described herein may be applied or extended to any suitable types of circuitry' or devices to implement various aspects of device protection circuitry. Further any coupling or connection between various components may be direct or indirect, such as made through one or more intervening components. For visual brevity and / or clarity, some components (e g., levelshifters or op-amps) or circuitry' may also be omitted from this or other circuit diagrams. Such an omission is not to be construed as limiting, but rather one example of the many ways in which various aspects may be used or applied to circuitry for implementing LDO regulators or other types of circuits in a GAA process or other advanced process technology. In other words, the aspects (e.g., circuitry) described herein may also be implemented with any7suitable number or combination of switches, transistors, logic, registers, bias circuitry7, amplifiers, current mirrors / sources, or the like.

[0037] In this example, the circuitry of an LDO regulator 126 is coupled between a first power rail 124 from which power received at a first voltage, VDD 302, and provided to a second power rail 130 at a second voltage, Vout 304. The LDO regulator 126 may include an operational amplifier 306 (amplifier 306) and a p-channel metal oxide semiconductor transistor 308 (PMOS) or other type of power transistor coupled between the VDD 302 supply rail and Vout 304 output node of the LDO regulator 126. The p-channel metal oxide semiconductor transistor 308 (PMOS) or other type of power transistor may be referred to as a first transistor. As shown in FIG. 3, the amplifier 306 includes a pow er input node coupled to the VDD 302 supply rail and a ground node coupled to a ground reference (GNDRef) or another node of potential lower than VDD 302. A positive input of the amplifier 306 may be coupled to a reference voltage 310 (VRef 310), which can be set with an external or internal resistor divider of the LDO regulator 126 (not shown). In this example, a negative input, or a VFeedBack 312 input (VFB 312), of the amplifier 306 is coupled to a feedback circuit (e.g., resistor divider) that includes a first resistor 314 with a first terminal coupled to the Vout 304 output node of the LDO regulator 126 and a second resistor 316 with a first terminal coupled to a second terminal of the first resistor and a second terminal coupled to the GNDRef. Based on the VRer 310 and VFB 312 at the respective inputs of the amplifier 306, an output of the amplifier 306 controls the PMOS 308 to regulate power from the VDD 302 supply rail to the Vout 304 output node of the LDO regulator 126.

[0038] In aspects, the circuitry of the LDO regulator 126 is implemented with device protection circuitry 128, which may include one or more devices (e.g., transistors or switches), bias signals, or control signals configured to prevent a device of the LDO circuit (e.g., PMOS 308 or powerdown switches) from being exposed to voltage levels that exceed inter-terminal voltage ratings of that device. For example, the VDD 302 power rail may be configured to operate at 1.0- 1.2 V and devices of the LDO regulator 126, when fabricated as GAA devices or devices of another advanced process, may have inter-terminal (e.g., Voate -Source, Gate-Drain, V Drain- Source) voltage ratings of less than 1.0 V (e.g., 0.85-0.95 V). As such, the terminals of the LDO regulator 126 devices may be exposed to voltages that exceed inter-terminal ratings in various operational states of the LDO regulator 126. In aspects of implementing an LDO in a GAA process, protection circuitry 128 of the LDO regulator 126 may include a pow er-down switch, a node biasing switch, a series switch (e.g., cascode device), or any combination thereof. Alternatively or additionally, the LDO regulator 126 and / or protection circuitry 128 may be operably coupled with an LDO controller or control logic, which may include control circuitry, logic, a microcontroller, or a combination thereof configured to manage operation of the LDO regulator 126 and / or the protection circuitry. For example, the LDO control logic (not shown) may transition the LDO regulator 126 between active (e.g., power up) and inactive (e.g., power down) states, including operation of power-downswitches, applying power down signaling (e.g., PD signals), or inverted power down signaling (e.g., PD# signals). In some cases, the LDO controller or other control logic of the protection circuitry7128 provides control or bias signals to the protection circuitry' 128, which may ensure that inter-terminal voltage ratings of the devices of the LDO regulator 126 are not exceeded in the power up state, power down state, or transitions between those states of the LDO regulator 126.

[0039] In this example, the protection circuitry 128 of the LDO includes a switch DI 318 in cascode with the PMOS 308 and controlled by power down signal 320 (PD 320). The switch DI 318 may be referred to as a second transistor. Note that the terms device or switch may be used to describe a transistor in the circuit diagrams of FIGs. 3-6. The protection circuitry may include a switch D2 322 (e.g., bias or buffer switch) coupled to a drain terminal of the PMOS 308 and configured to apply, based on inverted power-down signal 324, an intermediate bias voltage 326 (Vfiias 326) to the drain terminal of the PMOS 308. The sw itch D2 322 may be referred to as a third transistor. In some implementations, the circuitry includes a switch D3 328 (e.g., power down switch) coupled between the VDD 302 power rail and the gate of the PMOS 308 and controlled by' inverted power-down signal 330. The switch D3 328 may be referred to as a fourth transistor. Alternatively or additionally, the circuitry may also include a switch D4 332 (e.g., power down sw itch) coupled between the Vout 304 output node of the LDO regulator 126 and the ground reference and controlled by power-down signal 334. The switch D4 332 may be referred to as a fifth transistor. In various aspects, the application of the power-down signaling to respective gates of the switches D1-D4 may activate or deactivate the switches to apply intermediate voltages to the respective gates and / or various nodes of the LDO circuitry. By so doing, the device protection circuitry’ may prevent terminals of the devices from being exposed to voltages (e.g.. VDD 302 to ground reference, 1.2 V) that exceed the maximum inter-terminal voltage ratings of the devices (e.g., 0.65-1.0 V).

[0040] FIG. 4 illustrates at 400 another example configuration of an LDO regulator implemented with protection circuitry in accordance with one or more aspects. In this example, the LDO circuit of FIG. 3 is shown with circuitry of the amplifier 306 illustrated in detail along with protection circuitry’ 128 that can be implemented for an amplifier. The LDO regulator circuitry and / or protection circuitry 128 of FIG. 4 may be implemented similarly to or differently from the circuitry' of FIG. 3. For the sake of brevity, duplicate description of the PMOS 308 and protection circuitry’ 128 (e.g., switches D1-D4) as described with reference to FIG. 3 may be omitted. Further, although described with reference to specific transistor or switch configurations (e.g., p-channel MOS or n-channel MOS), the described aspects may be implemented with any suitable types or configurations of transistors and corresponding signaling. For example, a portionof a circuit may be implemented with a different type of transistor using inverted or other appropriately configured control signaling or bias voltage.

[0041] As shown in FIG. 4, the example circuit configuration of this LDO regulator 126 includes an amplifier 306 with an output 402 coupled to a gate of a first transistor (e.g., the PMOS 308). The PMOS 308, which may be referred to as a power transistor or drive transistor of the LDO regulator 126, includes a source terminal operably coupled to the first power rail 124 and a drain terminal operably coupled to the second power rail 130. Generally, the amplifier 306 controls, based on feedback provided by a first resistor (e.g., Ri 314) and second resistor (e.g., R2 316), the regulation of power through the PMOS 308 from the first power rail 124 at VDD 302 to the second power rail 130 at VOUT 304. In aspects, the circuitry may include a second transistor (e.g., DI 318), or cascode transistor, having a source terminal coupled to a drain terminal of the PMOS 308, a drain terminal coupled to the output node of the LDO regulator 126, and a gate terminal coupled to a first selectively controlled intermediate voltage source (e.g., PD 320). The selectively controlled intermediate voltage source can be configured to provide a signal at a voltage lower than the voltage of the powder rail, such as during an inactive or power-down state of the LDO regulator 126. As show n in FIG. 4, the amplifier 306 of the LDO regulator 126 may be configured with a pow er input coupled to the first power rail 124, a ground node coupled to the ground reference, a first input coupled to a reference voltage (e.g., VRef 310). a second input coupled to the resistor divider for feedback (e.g., VFB 312), and the output 402 coupled to the gate of the first transistor (e.g., PMOS 308).

[0042] In aspects, the protection circuitry 128 may include a third transistor and another selectively controlled intemiediate voltage source. In some cases, the transistor includes a switch (e.g., D2 322) that is coupled to a node between the first transistor and the second transistor. For example, the transistor can be implemented as a buffer switch or bias switch with a drain terminal coupled to the drain terminal of the PMOS 308, a source terminal coupled to an intermediate bias voltage source 326 (e.g., VBias 326), and a gate terminal coupled to a second selectively controlled intermediate voltage source (e.g., PD# 324). The intermediate bias voltage source and the second selectively controlled intermediate voltage source may be configured to provide respective power or signaling at a voltage lower than the voltage of the pow er rail. Alternatively or additionally, the circuitry' may include another transistor (e.g., D3 328) implemented as a power down switch with a source terminal coupled to the first power rail 124. a drain terminal coupled to the gate terminal of the PMOS 308, and a gate terminal coupled to another selectively controlled intermediate voltage source (e.g., PD# 330). The selectively controlled intermediate voltage source PD# 330 may be referred to as a third selectively controlled intermediate voltage source. The other selectively controlled intermediate voltage source can be configured to provide a signalat a voltage lower than the voltage of the power rail. The circuit may also include a transistor (e.g., D4 332) implemented as a power down switch coupled to the output node of the LDO regulator 126. The power dow n switch can be implemented with a drain terminal coupled to the output node Vout 304, a source terminal coupled to the ground reference, and a gate terminal coupled to a selectively controlled intermediate voltage source (e.g., PD 334). The selectively controlled intermediate voltage source PD 334 may be referred to as a fourth selectively controlled intermediate voltage source. The selectively controlled intermediate voltage source may be configured to provide a signal at a voltage lower than the voltage of the power rail. In some implementations, the gate terminal of the cascode transistor (e.g., DI 320) and the power down transistor (e.g., D4 332) on the output node of the circuit are coupled to a same selectively controlled intermediate voltage source (e.g., PD 320 / 334).

[0043] In various aspects, the selectively controlled intennediate voltage source(s) of the protection circuitry 128 are configured to provide one or more signals at a voltage below a voltage of a power rail or input power of the LDO regulator 126. For example, a selectively controlled intermediate voltage source may be implemented as level shifting logic coupled to the pow'er rail and configured to provide signaling or bias at the voltage (e.g., 0.4-0.8 V) below' that of the pow'er rail. Alternatively or additionally, other controllers, logic, or modules may provide or selectively apply the intennediate voltages described herein to gates or switches of the LDO regulator 126 and / or protection circuitry 128. Accordingly, the various power down signaling (e.g., PD or PD#) and intermediate bias voltage described with reference to the LDO regulator 126 and protection circuitry7128 may be provided or controlled by any suitable source, which may include level shifters, logic gates, other intermediate power rails, an LDO control circuit, or the like.

[0044] Returning to amplifier 306 of the LDO regulator 126, the amplifier may be implemented as any suitable type of amplifier (e g., operational amplifier, (OA)) and the circuitry of FIG. 4 is but one example in which an amplifier can be implemented with protection circuitry' 128 in accordance with one or more aspects. As shown in FIG. 4, the amplifier 306 includes a pair of transistors. D5 404 and D6 406, with respective source terminals operably coupled to the first power rail 124. The transistor D5 404 may be configured with a drain terminal coupled, as the output 402 of the amplifier, to the gate of the PMOS 308. The transistor D5 404 may be referred to as a first amplifier transistor. The transistor D6 406 may have a gate terminal coupled to a gate terminal of the D5 404 transistor and a drain terminal coupled to the gate terminal of the D5 404 transistor. The transistor D6 406 may be referred to as a second amplifier transistor. Additionally, the amplifier 306 may' include another pair of transistors, D7 408 and D8 410, with respective drain tenninals coupled to the respective drain terminals of the D5 404 and D6 406 transistors. A gate terminal of the D7 408 transistor can be coupled to a selectively controlled intermediatevoltage source (e.g., PD# 412) configured to provide a signal at a voltage lower than the voltage of the power rail. The transistor D7 408 may be referred to as a third amplifier transistor. The selectively controlled intermediate voltage source PD# 412 may be referred to as a fifth selectively controlled intermediate voltage source. Alternatively or additionally, a gate terminal of the D8 410 transistor can be coupled to a selectively controlled intermediate voltage source (e.g., PD# 414) configured to provide a signal at a voltage lower than the voltage of the power rail. The transistor D8 410 may be referred to as a fourth amplifier transistor. The selectively controlled intermediate voltage source PD# 414 may be referred to as a sixth selectively controlled intermediate voltage source. In some implementations, the gates of the D7 408 and D8 410 transistors are coupled to a same selectively controlled intermediate voltage source (e.g. level shifter 210 provided PD#).

[0045] As an input stage, the amplifier includes another pair of transistors, D9 416 and D10 418, with respective drain terminals coupled to respective source terminals of the D7 408 and D8 410 transistors. In aspects, a gate terminal of the D9 416 transistor is coupled, as a first input of the amplifier, to the VRef 310 and a gate terminal of the D10 418 transistor is coupled, as the second input of the amplifier, to the VFB 312 signal provided by the feedback divider formed by the resistors Ri 314 and R2 316. The transistor D9 416 may be referred to as a fifth amplifier transistor. The transistor D10 418 may be referred to as a sixth amplifier transistor. As shown in FIG. 4, respective sources of the D9 416 and D10 418 transistors can be coupled to a drain of a transistor Dl l 420, which has a source coupled to the ground reference or ground node of the amplifier 306. The transistor Dl l 420 may be referred to as a seventh amplifier transistor. The amplifier 306 also includes a transistor D12 422 that may be configured with a drain terminal coupled to a current source 424, a source terminal coupled to the ground reference and a gate terminal coupled to the current source and a gate of the Dl l 420 transistor. The transistor D12 444 may be referred to as an eighth amplifier transistor.

[0046] In various aspects, the amplifier 306 may include protection circuitry' 128 as indicated by one or more of the circled devices D1-D4 and / or D13-D16. which may include power down transistors disposed in the amplifier circuit. In this example, the amplifier includes a transistor D13 426 configured with a drain terminal coupled to the gate terminals of the Dl l 420 and DI 2 422 transistors, a source terminal coupled to the ground reference, and a gate terminal coupled a selectively controlled intennediate voltage source (e.g., PD 428). The transistor D13 426 may be referred to as a ninth amplifier transistor. The selectively controlled intermediate voltage source PD 428 may be referred to as a seventh selectively controlled intermediate voltage source. Alternatively or additionally, the amplifier circuit includes transistor D14 430, which may function as a power down transistor for transistors D5 404 and D6 406. The transistor D14 430may be referred to as a tenth amplifier transistor. The transistor D 14 430 may be configured with a source terminal coupled to the power rail 124, a drain terminal coupled to the gate terminal of the transistor D6 406, and a gate terminal coupled to a selectively controlled intermediate voltage source for power down signaling (e.g.. PD# 432). The selectively controlled intennediate voltage source may be referred to as an eighth selectively controlled intermediate voltage source. In some cases, the gate of the transistor D14 403 may be coupled to a same selectively controlled intermediate voltage source as the gates of transistors D7 408 and / or D8 410 (e.g., PD# 440).

[0047] The amplifier may also include a pair of transistors D15 434 and D16 436, which can function as power down transistors for transistors D7 408 and D8 410. The transistor D15 434 may be referred to as an eleventh amplifier transistor. The transistor D16 436 may be referred to as a twelfth amplifier transistor. In this example, the transistor D15 434 is configured with a source terminal coupled to the source terminal of the D7 408 transistor, a drain terminal coupled to an intermediate bias voltage source 338 (Vuias 338), and agate terminal coupled to a selectively controlled intermediate voltage source (e.g., PD# 440), which may provide power down signaling, and which may be referred to as a ninth selectively controlled intermediate voltage source. The transistor D16 436 can be configured with a source terminal coupled to the source terminal of the D8410 transistor, a drain terminal coupled to the intennediate bias voltage source 338 (VBias 338), and a gate terminal coupled to the selectively controlled intermediate voltage source (e.g., PD# 440), which may provide power down signaling. How the protection circuitry and signaling is implemented or used may vary', some examples of which are described with reference to FIGs. 5 and 6, and / or the methods of FIGs. 7-9.

[0048] FIG. 5 illustrates at 500 an example of the LDO regulator of FIG. 4 in an active state in accordance with one or more aspects. In various aspects of implementing an LDO in a GAA or other advanced process, the device protection circuitry 128 may be configured and / or controlled to protect the devices of the LDO regulator 126 from voltages that exceed respective inter-terminal voltage ratings. In other words, aspects of the protection circuitry 128 may enable the LDO regulator 126 to function in various operational modes without the devices of the LDO being exposed to voltage that exceeds the inter-terminal ratings to prevent damage of the devices. With reference to FIG. 5 and FIG. 6, examples of intermediate bias voltage and / or selectively controlled applications of intermediate voltage are described in the context of the LDO regulator 126 being in an active state (e.g., power up state) or an inactive state (e.g., power down state). As described herein, an intermediate voltage includes a voltage that is below a voltage of a supply rail or power source from which the LDO regulator 126 draws power to operate.

[0049] As show n in FIG. 5 and in the context of an active state, the LDO regulator 126 may be configured to receive power from the first pow er rail 124 at a first voltage, VDD 302, of 1.2 V andprovide power to the second power rail 130 at a second voltage, Vout 304, of 0.9V at the output node of the LDO regulator 126. Here assume that devices or transistors of the LDO regulator 126 are fabricated using a gate-all-around process and have inter-terminal voltage ratings of 0.9 V, such that the voltage between the first power rail 124 and the ground reference (zero volts) may damage the devices of the LDO regulator circuit. Further, while powered up, the power down signaling (PD) may be implemented as logic low levels (VL) and the inverted power down signaling (#PD) may be implemented as logic high levels (VH) as indicated in relation to the respective gate terminals of the transistors. In some aspects, the intermediate bias voltages, such as Vuias 326 and VBias 338, are configured at a voltage below both the first power rail 124 and the second power rail 130 (e.g., a VBias of 0.8V or lower). Control circuitry described in reference to the protection circuitry may include an LDO controller or control logic, such as circuits, logic, a microcontroller, or a combination thereof configured to manage operation of the LDO regulator 126 and / or the protection circuitry in accordance with aspects described herein.

[0050] In aspects, when the LDO regulator 126 is active (e.g., power up state), the cascode switch DI 318 may be turned on to allow the PMOS 308 conduct power to the output node of the LDO regulator 126 and various power down switches of the protection circuitry may be turned off. For example, control circuitry' of the LDO regulator 126 may be configured to apply a logic low PD signal 502 (VL signal 502) of zero volts to the gate of switch DI 318 to turn on the DI switch. In some implementations, the control circuitry is configured to apply a logic high PD# signal 504 (Vn signal 504) of an intermediate voltage (e.g., 0.7 to 0.9 V) to the gate of the switch D2 322 to turn off the D2 sw itch, which prevents the application of the intermediate bias voltage 326 (0.8 V) to the drain of the PMOS 308. Alternatively or additionally, the control circuitry can be configured to apply a logic high PD# signal 506 (VH signal 506) of 1.2 V to the gate of the D3 328 switch and a logic low' PD signal 508 (VL signal 508) of zero volts to the gate of the D4 332 switch to maintain the D3 and D4 sw itches in an off state.

[0051] Turning now to the devices of the amplifier 206, the VRef 310 and VFB 312 at the inputs of the amplifier can vary from 0.7 to 0.9 V while the LDO regulator 126 is powered up. The control circuitry may be configured to apply logic high PD# signals 510 (VH signal 510) of 1.2 V to the respective gates of the D7 408 and D8 410 switches to turn these swatches on and enable the amplifier to operate. In aspects, the control circuitry is configured to apply logic high PD# signals 512 (Vu signal 512) of an intermediate voltage (e.g., 0.7 to 0.9 V) to the respective gates of the D15 434 and D16 436 switches of the protection circuitry to turn these switches off. By turning off D15 434 and D16 436, the protection circuitry does not apply the VBias 338 (e.g., 0.8V) to the drains of the D9 416 and D10 418 switches. While the amplifier 306 is powered up, other various power down switches of the amplifier may also be turned off. For example, the controlcircuitry can be configured to apply a logic low PD signal 514 (VL signal 514) of zero volts to the gate of the D13 426 switch and a logic high PD# signal 516 (Vnsignal 516) of 1.2 V to the gate of the D14 430 switch to maintain the D13 and D14 switches in an off state. By so doing, the described aspects can ensure that devices of the LDO regulator 126 operate with inter-terminal voltages (e.g., V Gate-source, Vsate-Drain- Vurain-Source) below the inter-terminal voltage ratings of the devices (e g., 0.9 V) when the LDO is in an active or powered up state.

[0052] FIG. 6 illustrates at 600 an example of the LDO regulator of FIG. 4 in an inactive state in accordance with one or more aspects. In various aspects of implementing an LDO in a GAA or other advanced process, the device protection circuitry’ 128 may be configured and / or controlled to protect the devices of the LDO regulator 126 from voltages that exceed respective inter-terminal voltage ratings. With reference to FIG. 6, examples of intermediate bias voltage and / or selectively controlled applications of intermediate voltage are described in the context of the LDO regulator 126 being in an inactive state (e.g., power down state). As described herein, an intermediate voltage includes a voltage that is below a voltage of a supply rail or power source from which the LDO regulator 126 draw s power to operate.

[0053] As show n in FIG. 6 and in the context of an inactive state, the first power rail 124 at a VDD 302 of 1.2 V may be configured as an always-on (AO) power rail or the first power rail may collapse slower than the circuitry of the LDO regulator 126. As such, the devices of the LDO regulator 126 may be exposed to VDD 302 while the LDO regulator 126 is powered down or while the LDO transitions to the pow er down state. Here assume that devices or transistors of the LDO regulator 126 are fabricated using a gate-all-around process and have inter-tenninal voltage ratings of 0.9 V, such that the voltage between the first power rail 124 and the ground reference (zero volts) may damage the devices of the LDO regulator circuit. Further, while powered down, the power dow n signaling (PD) may be implemented as logic high levels (VH) and the inverted power dow n signaling (#PD) may be implemented as logic low' levels (VL) as indicated in relation to the respective gate terminals of the transistors. In some aspects, the intennediate bias voltages, such as VBias 326 and VBias 338. are configured at a voltage below both the first power rail 124 and the second power rail 130 (e.g., a VBias of 0.8V or lower). Control circuitry described in reference to the protection circuitry' may include an LDO controller or control logic, such as circuits, logic, a microcontroller, or a combination thereof configured to manage operation of the LDO regulator 126 and / or the protection circuitry in accordance with aspects described herein.

[0054] In aspects, when the LDO regulator 126 is inactive (e.g., power down state), the cascode switch DI 318 may be turned off to prevent the drain of the PMOS 308 from being pulled down to the ground reference and various power down switches of the protection circuitry' may be turned on. For example, control circuitry of the LDO regulator 126 may be configured to apply a logichigh PD signal 602 (VH signal 602) of an intermediate voltage (e.g., 0.7 to 0.9 V) to the gate of switch DI 318 to turn off the DI switch. In some implementations, the control circuitry is configured to apply a logic low PD# signal 604 (VL signal 604) of zero volts to the gate of the switch D2 322 to turn on the D2 switch, which applies the intermediate bias voltage 326 (0.8 V) to the drain of the PMOS 308. Alternatively or additionally, the control circuitry can be configured to apply a logic low PD# signal 606 (VL signal 606) of an intermediate voltage (e.g., 0.3 to 0.5 V) to the gate of the D3 328 switch and a logic high PD signal 608 (VH signal 608) of an intermediate voltage (e.g., 0.7 to 0.9 V) to the gate of the D4 332 switch to transition the D3 and D4 switches in an on state.

[0055] Turning now to the devices of the amplifier 206, the VRef 310 and VFB 312 at the inputs of the amplifier may settle to approximately zero volts while the LDO regulator 126 is powered down. The control circuitry may be configured to apply logic low PD# signals 610 (VL signal 610) of intermediate voltage (e.g., 0.3 to 0.5 V) to the respective gates of the D7 408 and D8 410 switches to prevent the VGD ratings of the D7 and D8 switches from being exceeded by the 1.2 V power provided by the first power rail 124. In aspects, the control circuitry is configured to apply logic low7PD# signals 612 (VL signal 612) of zero volts to the respective gates of the D15 434 and D16 436 switches of the protection circuitry' to turn these switches on. By turning on DI 5 434 and D16 436, the protection circuitry can actively couple the sources of the D7 408 and D8 410 switches to the VBias 338 (e.g., 0.8V) to prevent the VDS ratings of the D7 and D8 switches from being exceeded by the 1.2 V power provided by the first power rail 124. While the amplifier 306 is powered down, various power down switches of the amplifier may also be turned on. For example, the control circuitry can be configured to apply a logic high PD signal 614 (VH signal 614) of an intermediate voltage (e.g., 0.7 to 0.9 V) to the gate of the D13 426 switch and a logic low' PD# signal 616 (VL signal 616) of another intermediate voltage (e g., 0.3 to 0.5 V) to the gate of the D14 430 switch to transition or maintain the D13 and D14 switches in an on state. By so doing, the described aspects can ensure that devices of the LDO regulator 126 operate with interterminal voltages (e.g.. Voate-source. Voate-Drain, VDrain-source) below the inter-terminal voltage ratings of the devices (e.g., 0.9 V) w hen the LDO is in an inactive or powered down state.Example Methods

[0056] Example methods 700, 800, and 900 are described with reference to FIGs. 7-9, respectively, in accordance with one or more aspects of implementing an LDO regulator in a gateall-around process. Generally, the methods 700, 800, and 900 illustrate sets of operations (or acts) that may be performed in, but not necessarily limited to, the order or combinations in which the operations are shown herein. Further, any of one or more of the operations may be repeated,combined, reorganized, skipped, or linked to provide a wide array of additional and / or alternate methods. In portions of the following discussion, reference may be made to the environment 100 of FIG. 1, circuitry or components of FIGs. 2-6, a system of FIG. 10, and / or entities detailed in FIG. 1 or other figures, reference to which is made for example only. The techniques and apparatuses described in this disclosure are not limited to an embodiment or performance by one entity or multiple entities operating on one device or those described with reference to the figures.

[0057] FIG. 7 illustrates an example method 700 for transitioning an LDO regulator to a powerdown state in accordance with one or more aspects, including operations perfonned with the LDO regulator 126 and / or device protection circuitry 128.

[0058] At 702, intermediate voltages are generated that are lower than a voltage of a supply rail of an LDO regulator circuit (LDO circuit). The intermediate voltages may include a supply voltage, a reference voltage, control voltage, or a bias voltage at a voltage level (e.g., 0.3-0.9 V) that is lower than the voltage (e.g., 1.2 V) of the supply rail of the LDO circuit. In some cases, the intermediate voltages are provided by level shifters and / or gates by control logic or switches of protection circuitry associated with the LDO circuit.

[0059] At 704, a controller of the LDO circuit receives an indication to pow er down the LDO circuit. The controller may include control circuitry, logic gates, a microcontroller, or the like that is configured to manage operation of or transition the LDO circuit between active or inactive states. In response to the indication to power down the LDO circuit, the controller or control logic may be configured to apply pow er down signaling to components of the LDO circuit and / or protection circuitry of the LDO circuit.

[0060] At 706, a first intermediate voltage is applied to a gate of a cascode transistor coupled in series with a power transistor (e.g., PMOS device) of the LDO circuit. In some implementations, the cascode transistor is coupled between a drain of the power transistor (or drive transistor) of the LDO circuit and an output node of the LDO circuit. The first intermediate voltage may be set or configured to turn the cascode transistor off without exceeding an interterminal voltage rating of the cascode transistor. For example, the first intermediate voltage applied may be set (e.g., 0.7-0.9 V) such that a VGD rating of the cascode transistor is not exceeded by applying a supply rail voltage (1.2 V) to the gate of the cascode transistor.

[0061] At 708, a second intemiediate voltage is applied, via a first transistor, to a node betw een the cascode transistor and the power transistor of the LDO circuit. The node may be disposed between a drain of the power transistor and a source of the cascode transistor. In some cases, a drain of the first transistor is coupled to the node and a source of the first transistor is coupled to a reference or level shifter that provides the second intermediate voltage. The second intermediate voltage can be set (e g., 0.7-0.9 V) such that a VDS rating of the power transistor is not exceededwhen the cascode transistor is turned off. In some cases, the first transistor is turned on by applying a logic low level signal (e.g., zero volts) to the gate of the first transistor.

[0062] At 710, a third intermediate voltage is applied to a gate of a second transistor coupled between a ground reference and the output of the LDO circuit. In some cases, the second transistor is a power down switch coupled to the output of the LDO circuit. The third intermediate voltage can be set (e.g., 0.7-0.9 V) such that a VGD rating of the transistor is not exceeded when the second transistor is turned on.

[0063] At 712, a fourth intermediate voltage is transitioned to a fifth intermediate voltage at a gate of a third transistor coupled between the supply rail and a gate of the power transistor of the LDO circuit. In some cases, the third transistor is a power down switch coupled to the output of the output of the amplifier and the gate of the power transistor. The fourth voltage may be approximately the supply rail voltage of the LDO circuit and the fifth intermediate voltage can be set (e.g., 0.3-0.4 V) such that a VGSD rating of the third transistor is not exceeded when the third transistor is turned on when the LDO circuit is powered down.

[0064] FIG. 8 illustrates an example method 800 for transitioning an LDO regulator to a power- up state in accordance with one or more aspects, including operations performed with the LDO regulator 126 and / or device protection circuitry 128.

[0065] At 802, intennediate voltages that are lower than a voltage of a supply rail of an LDO regulator circuit (LDO circuit) are applied to transistors and / or nodes of the LDO circuit. The LDO circuit may be in any suitable operation state, which may include a powered dow n or inactive state. For example, the intennediate voltages may correspond to the intermediate voltages as described with reference to FIGs. 3-6 and / or the method 700 of FIG. 7.

[0066] At 804, a controller of the LDO circuit receives an indication to power up the LDO circuit. The controller may include control circuitry, logic gates, a microcontroller, or the like that is configured to manage operation of or transition the LDO circuit between active or inactive states. The controller or control circuitry may be configured to bring up the LDO circuit and protection circuit of the LDO circuit such that control signals and intermediate voltages are applied to devices to avoid exposing the devices to voltage that exceeds the inter-terminal ratings of the devices of the LDO circuit.

[0067] At 806, a first intermediate voltage is removed from a gate of a cascode transistor coupled in series with a power transistor of the LDO circuit. Removing the first intermediate voltage may include transitioning the gate of the cascode transistor from the first intermediate voltage to a lower voltage (e.g., 0 volts) to turn the cascode transistor on. In some implementations, the cascode transistor is coupled between a drain of the power transistor (or drive transistor) of the LDO circuit and an output node of the LDO circuit. The first intermediatevoltage (e.g., 0.7-0.9 V) may be set or configured such that a VGD rating of the cascode transistor is not exceeded when the transistor is off (e.g., prior to removing the first intermediate voltage).

[0068] At 808, a second intermediate voltage is removed, via a first transistor, from a node between the cascode transistor and the power transistor of the LDO circuit. The node may be disposed between a drain of the power transistor and a source of the cascode transistor. In some cases, a drain of the first transistor is coupled to the node and a source of the first transistor is coupled to a reference or level shifter that provides the second intermediate voltage. In some cases, the first transistor is turned off by applying another intermediate voltage level signal 0.7- 0.9 V) to the gate of the first transistor, which may be similar to the second intermediate voltage at the source of the first transistor.

[0069] At 810, a third intermediate voltage is removed from a gate of a second transistor coupled between a ground reference and the output of the LDO circuit. In some cases, the second transistor is a power down switch coupled to the output of the LDO circuit. The third intermediate voltage removed from the gate of the second transistor can be set (e.g., 0.7-0.9 V) such that a VGD rating of the transistor is not exceeded when the second transistor in on (e.g., prior to removing the third intermediate voltage).

[0070] At 812, a fourth intermediate voltage is transitioned to a fifth intermediate voltage at a gate of a third transistor coupled between the supply rail and a gate of the power transistor of the LDO regulator circuit. In some cases, the third transistor is a power down switch coupled to the output of the output of the amplifier and the gate of the power transistor. The fifth voltage may be approximately the supply rail voltage of the LDO circuit and the fourth intermediate voltage can be set (e.g., 0.3-0.4 V) such that a VGSD rating of the third transistor is not exceeded when the third transistor is on when the LDO circuit is powered down (e.g., prior to ).

[0071] FIG. 9 illustrates an example method 900 for implementing an LDO regulator with device protection circuitry in accordance with one or more aspects, including operations performed to design or operate the LDO regulator 126 and / or device protection circuitry 128.

[0072] At 902. a threshold is determined for inter-terminal voltage of a device in a circuit. The inter-terminal voltage rating of the device may include a maximum gate-source voltage rating, a maximum gate-drain voltage rating, a maximum drain-source voltage rating, a maximum gatebody voltage rating, and so forth. In some cases, the threshold for inter-terminal voltage rating is determined based on a fabrication process (e.g. gate-all-around process) or technology node (e.g., 3nm or 2nm technology node) in which the circuit is configured to operate.

[0073] At 904, a determination is made that a voltage at a terminal of the device in the circuit exceeds the threshold for inter-terminal voltage. The determination may be made for the device of the circuit in an active operational state, an inactive operational state, or during transitionsbetween the active and inactive states. For example, the determination can be made for a transistor of an LDO circuit for each inter-terminal voltage when the LDO circuit is power up, powered down, and / or between power up or power down transitions.

[0074] Optionally at 906. a cascode device is inserted into the circuit to reduce the interterminal voltage at the terminal of the device. In response to determining that an inter-terminal voltage rating of the device will be exceeded, a cascode device can be inserted into the circuit, which may reduce inter-terminal voltage of the device. For example, a cascode device can be inserted betw een a pow er transistor of an LDO circuit and an output node of the LDO circuit.

[0075] Optionally at 908, the terminal of the device is coupled to an intermediate voltage to reduce the inter-terminal voltage at the terminal of the device. The terminal of the device may be coupled to an intermediate bias voltage, a selectively controlled source of the intermediate voltage, a level shifter, or the like. For example, gates of power dow n switches of an LDO circuit can be coupled to selectively controlled intermediate voltage sources (e.g., level shifters) to ensure that inter-terminal voltages of the power down switches are not exceeded when the circuit is powered up or powered down.

[0076] Optionally at 910, the terminal of the device is coupled to another device that is configured to apply an intermediate voltage to reduce the inter-terminal voltage of the device. In some cases, a bias or buffer transistor can be used to apply an intermediate voltage to a node of an LDO circuit to prevent devices of the LDO circuit from being exposed to voltages that exceed the interterminal voltage ratings of the devices. From operation 910, the method 900 may return to operation 902 and implement another iteration for one or more other devices of the circuit. In some cases, the method is performed repeatedly for each device in the circuit to ensure that the circuit will pass a safe operation area (SOA) check.

[0077] At 912, the circuit of the device is operated with one or more of the cascode device, the intermediate voltage, and the other device configured to apply the intermediate voltage. For example, an LDO circuit may be operated in an inactive state or active state with protection circuitry configured with a cascode device, additional switches, intermediate voltages, or the like as described throughout this disclosure.Example Systems

[0078] FIG. 10 illustrates an example system-on-chip (SoC) in which aspects of an LDO in a gate-all-around process can be implemented. In aspects, the SoC 1000 may represent similar or alternate configurations of the SoC 116 as described with reference to FIG. 1. Accordingly, the SoC 1000 may be embodied as or within any ty pe of user device 102, user equipment, apparatus, other device, or system as described with reference to FIGs. 1-9 to an LDO regulator or othercircuits. Although described with reference to chip-based packaging, the components shown in FIG. 10 may be embodied as other systems or component configurations, such as, and without limitation, a power management integrated-circuit (PMIC), a power regulation circuit, an LDO integrated-circuit, a Field-Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), an Application-Specific Standard Product (ASSP), a digital signal processor (DSP), Complex Programmable Logic Devices (CPLD), system in package (SiP), package on package (PoP), a graphics processing unit (GPU), a machine-learning engine, processing and communication chip set, communication co-processor, sensor co-processor, or the like.

[0079] In this example, the SoC 1000 includes communication transceivers 1002 and a wireless modem 1004 that enable wired or wireless communication of data 1006 (e.g., received data, data that is being received, data scheduled for broadcast, packetized, or the like). In some aspects, the wireless modem 1004 is implemented as a multi-mode multi -band modem or baseband processor that is configurable to communicate in accordance with various communication protocols and / or in different frequency bands. The wireless modem 1004 may include a transceiver interface (not shown) for communicating encoded or modulated signals with transceiver circuitry, and / or controlling a radio frequency (RF) front end.

[0080] The data 1006 or other system content can include configuration settings of the system or various components, media content stored by the system, and / or information associated with a user of the system. Media content stored on the system on chip 1000 may include any type of audio, video, and / or image data. The system on chip 1000 also includes an instance of I / O logic 1008, which may be configured similar to I / O logic 122 as described throughout this disclosure. In some implementations, the I / O logic 1008 of the SoC 1000 is configured as one or more data inputs 1008 via which any type of data, media content, and / or inputs can be received, such as user input, user-selectable inputs (explicit or implicit), or any other type of audio, video, and / or image data received from a content and / or data source. Alternatively or additionally, the I / O logic 1008 may include various data interfaces, which can be implemented as any one or more of a serial and / or parallel interface, a wireless interface, a network interface, and as any other type of communication interface enabling communication with other devices or systems.

[0081] The system on chip 1000 includes one or more processor cores 1010, which process various computer-executable instructions to control the operation of the system on chip 1000 and to enable any suitable functionalities of the system on chip 1000. Alternatively or additionally, the system on chip 1000 can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry that is implemented in connection with processing and control circuits, which are generally shown at 1012. Although not shown, the system on chip 1000 may alsoinclude a bus, interconnect, crossbar, or fabric that couples the various components within the system.

[0082] The system 1000 also includes a memory' 1014 (e.g., computer-readable media), such as one or more memory circuits that enable persistent and / or non-transitory data storage, and thus do not include transitory signals or carrier waves. Examples of the memory’ 1014 include ROM, RAM, DRAM, SRAM, or Flash memory'. The memory 1014 provides data storage for the system data 1006, as well as for firmware 1016, applications 1018, and any other types of information and / or data related to operational aspects of the system on chip 1000. For example, the firmware 1016 can be maintained as processor-executable instructions of an operating system (e.g., realtime OS) within the memory 1014 and executed on one or more of the processor cores 1010.

[0083] The applications 1018 may include a system manager, such as any form of a control application, software application, signal-processing and control module, code that is native to a particular system, an abstraction module, a machine learning module, or gesture module and so on. The memory 1014 may also store system components or utilities for implementing any' suitable functionalities of the system on chip 1000. In some aspects, the system on chip 1000 also includes additional processors or co-processors to enable other functionalities, such as a graphics processor 1020, audio processor 1022, and image sensor processor 1024. The graphics processor 1020 may render graphical content associated with a user interface, operating system, or applications of the system on chip 1000. In some cases, the audio processor 1022 encodes or decodes audio data and signals, such as audio signals and information associated with voice calls or encoded audio data for playback. The image sensor processor 1024 may be coupled to an image sensor and provide image data processing, video capture, and other visual media conditioning and processing functions.

[0084] In aspects, the system on chip 1000 includes an LDO regulator 126, protection circuitry' 128, and / or a pow er system 132, which may be implemented as described w ith reference to FIGs. 1-9. In some cases, the I / O logic 1008 of the system on chip 1000 is operably coupled with a voltage rail that provides power to the LDO regulator 126. Alternatively or additionally, the processor cores 1010 or other lower-voltage circuitry of the SoC 1000 can be coupled to an output node or rail of the LDO regulator 126. In various aspects, the LDO regulator 126 includes protection circuitry as described herein which is configured to prevent devices of the circuit from exceeding inter-terminal voltage ratings. By so doing, the LDO circuit can be implemented in advanced fabrication processes (e.g., gate-all-around) in which devices may have inter-terminal voltage ratings that are lower than preceding process technologies.

[0085] The system on chip 1000 may also include a security' processor 1026 to support various security, encryption, and cryptographic operations, such as to provide secure communicationprotocols and encrypted data storage. Although not shown, the security processor 1026 may include one or more cryptographic engines, cipher libraries, hashing modules, or random number generators to support encry ption and cryptographic processing of information or communications of the system on chip 1000. Alternatively or additionally, the system on chip 1000 can include an ML engine 1028 and / or a sensor interface 1030. Generally, the ML engine 1028 may include one or more ML models, artificial intelligence (Al) models, or deep neural networks (DNNs) and a processor core for executing the models and / or networks. The sensor interface 1030 can enable the system on chip 1000 to receive data from various sensors, such as capacitance and motion sensors of a user device in which the system on chip is embodied.Variations

[0086] Although the above-described apparatuses and methods are described in the context of an LDO regulator circuit implemented in a gate-all-around process, the described devices, systems, and methods are non-limiting and may apply to other contexts, electrical circuits, semiconductor processes, or power regulation environments.

[0087] Components may be described herein with reference to labels such as “first”, “second”, “third” etc. Such labels are not intended to imply any particular order or significance, other than where explicitly stated. Moreover, the reference to a “first” component does not imply, or require, the existence of a “second” similar component, unless such a second component is indicated. Similarly, reference to a “third” component does not imply, or require, the existence of a “second” similar component, unless such a second component is indicated.

[0088] Generally, the components, modules, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry). manual processing, or any combination thereof. Some operations of the example methods may be described in the general context of executable instructions stored on computer-readable storage memory that is local and / or remote to a computer processing system, and implementations can include software applications, programs, functions, and the like. Alternatively, or in addition, any of the functionality described herein can be performed, at least in part, by one or more hardware logic components, such as, and without limitation, LDOs, PMICs, FPGAs, ASICs, ASSPs, SoCs, CPLDs, GPUs, ML engines, co-processors, context hubs, motion co-processors, sensor coprocessors. or the like.

Claims

CLAIMSWhat is claimed is:

1. A circuit for regulating power (126) comprising: a first transistor (308) having a source terminal coupled to a power rail; a second transistor (318) having a source terminal coupled to a drain terminal of the first transistor, a drain terminal coupled to an output node of the circuit, and a gate terminal coupled to a first selectively controlled intermediate voltage source, the first selectively controlled intermediate voltage source (320) configured to provide a first signal at a voltage lower than the voltage of the power rail; a first resistor (314) having a first terminal coupled to the output node of the circuit; a second resistor (316) having a first terminal coupled to a second terminal of the first resistor and a second terminal coupled to a ground reference; and an amplifier (306) having a power input coupled to the power rail, a ground node coupled to the ground reference, a first input coupled to a reference voltage source, a second input coupled to the first terminal of the second resistor, and an output coupled to a gate of the first transistor.

2. The circuit as recited by claim 1. wherein the circuit further comprises:A third transistor (322) having a drain terminal coupled to the drain terminal of the first transistor, a source terminal coupled to an intermediate bias voltage source, and a gate terminal coupled to a second selectively controlled intermediate voltage source (324), the intermediate bias voltage source configured to provide power at a voltage lower than the voltage of the power rail, the second selectively controlled intermediate voltage source configured to provide a second signal at a voltage lower than the voltage of the power rail.

3. The circuit as recited by claim 1 or 2, wherein the circuit further comprises: a fourth transistor (328) having a source terminal coupled to the power rail, a drain terminal coupled to the gate terminal of the first transistor, and a gate terminal coupled to a third selectively controlled intermediate voltage source (330), the third selectively controlled intermediate voltage source configured to provide a third signal at a voltage lower than the voltage of the power rail.

4. The circuit as recited by any one of claims 1 to 3, wherein the circuit further comprises: a fifth transistor (332) having a drain terminal coupled to the output node of the circuit, a source terminal coupled to the ground reference, and a gate terminal coupled to a fourth selectively controlled intermediate voltage source (334). the fourth selectively controlled intermediate voltage source configured to provide a fourth signal at a voltage lower than the voltage of the power rail.

5. The circuit as recited by claim 4, wherein the gate terminal of the second transistor (318) and the gate terminal of the fifth transistor (332) are coupled to the same selectively controlled intermediate voltage source.

6. The circuit as recited by any preceding claim, wherein the first selectively controlled intermediate voltage source (320) comprises level shifting logic coupled to the power rail, the level shifting logic configured to provide the signal at the voltage lower than the voltage of the power rail.

7. The circuit as recited by any preceding claim, wherein the first selectively controlled intermediate voltage source (320) is configured to apply the signal at the voltage lower than the voltage of the power rail to the gate terminal of the second transistor (318) when the circuit for regulating power is in an inactive state.

8. The circuit as recited by any preceding claim, wherein the amplifier (306) comprises an amplifier circuit, the amplifier circuit comprising: a first amplifier transistor (404) having a source terminal coupled to the power rail and a drain coupled, as the output of the amplifier, to the gate of the first transistor; a second amplifier transistor (406) having a source terminal coupled to the power rail, a gate terminal coupled to a gate terminal of the first amplifier transistor; and a drain terminal coupled to the gate terminal of the first amplifier transistor; a third amplifier transistor (408) having a drain temiinal coupled to the drain terminal of the first amplifier transistor and a gate terminal coupled to a fifth selectively controlled intermediate voltage source, the fifth selectively controlled intermediate voltage source (412) configured to provide a fifth signal at a voltage lower than the voltage of the power rail; a fourth amplifier transistor (410) having a drain temiinal coupled to the drain terminal of the second amplifier transistor and a gate terminal coupled a sixth selectively controlled intermediate voltage source (414), the sixth selectively controlled intermediate voltage source configured to provide a sixth signal at a voltage lower than the voltage of the power rail; a fifth amplifier transistor (416) having a drain terminal coupled to a source terminal of the third amplifier transistor and a gate terminal coupled, as the first input of the amplifier, to the reference voltage source; a sixth amplifier transistor (418) having a drain terminal coupled to a source terminal of the fourth amplifier transistor, a gate terminal coupled, as the second input of the amplifier, to the first terminal of the second resistor, and a source terminal coupled to a source terminal of the fifth amplifier transistor; and a seventh amplifier transistor (420) having a drain terminal coupled to the source of the sixth amplifier transistor and a source terminal coupled to the ground reference.

9. The circuit as recited by claim 8, wherein the gate tenninal of the third amplifier transistor (408) and the gate terminal of the fourth amplifier transistor (410) are coupled to a same selectively controlled intermediate voltage source.

10. The circuit as recited by claim 8 or 9, wherein the amplifier circuit further comprises: an eighth amplifier transistor (422) having a drain terminal coupled to a current source (424), a source terminal coupled to the ground reference, and a gate terminal coupled to the current source and a gate terminal of the seventh amplifier transistor.

11. The circuit as recited by claim 10, wherein the amplifier circuit further comprises: a ninth amplifier transistor (426) having a drain terminal coupled to the gate terminal of the eighth amplifier transistor, a source terminal coupled to the ground reference, and a gate terminal coupled a seventh selectively controlled intermediate voltage source (428), the seventh selectively controlled intermediate voltage source configured to provide a seventh signal at a voltage lower than the voltage of the power rail.

12. The circuit as recited by any one of claims 8 to 11, wherein the amplifier circuit further comprises: a tenth amplifier transistor (430) having a source terminal coupled to the power rail, a drain terminal coupled to the gate terminal of the second amplifier transistor, and a gate terminal coupled to an eighth selectively controlled intermediate voltage source, the eighth selectively controlled intermediate voltage source (432) configured to provide an eighth signal at a voltage lower than the voltage of the power rail.

13. The circuit as recited by claim 12, wherein the gate terminal of the tenth amplifier transistor (430) and at least one of the gate terminal of the third amplifier transistor (408) or the gate terminal of the fourth amplifier transistor (410) are coupled to a same selectively controlled intermediate voltage source.

14. The circuit as recited by any one of claims 8 to 13, wherein the amplifier circuit further compnses: an eleventh amplifier transistor (434) having a source terminal coupled to the drain terminal of the third amplifier transistor, a drain terminal coupled to an intermediate bias voltage source, and a gate terminal coupled to a ninth selectively controlled intermediate voltage source (440); and a twelfth amplifier transistor (436) having a source terminal coupled to the drain terminal of the fourth amplifier transistor, a drain terminal coupled to the intermediate bias voltage source, and a gate terminal coupled to the ninth selectively controlled intermediate voltage source (440), the ninth selectively controlled intermediate voltage source configured to provide a ninth signal at a voltage lower than the voltage of the power rail.

15. A method for operating the circuit for regulating power (126) as recited by any preceding claim, the method comprising: operating the circuit in an active state to provide regulated power at the output node (304) of the circuit, the first selectively controlled intermediate voltage (320) source not applying the first signal at the lower voltage to the gate of the second transistor (318) when operating the circuit in the active state; and operating the circuit in an inactive state when the regulated power is not provided at the output node of the circuit, the first selectively controlled intemiediate voltage source (320) applying the first signal at the lower voltage to the gate of the second transistor (318) when operating the circuit in the inactive state.

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