Semiconductor structure manufacturing method and semiconductor structure

Abstract

A semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate, the substrate comprising a first region and a second region; forming in the first region a stacking structure in which a plurality of first material layers and a plurality of second material layers are stacked alternately; performing first etching, so as to form a groove in one end of the stacking structure, the bottom of the groove exposing the second region; and performing second etching, so as to remove some of the plurality of second material layers by means of the groove and keep the plurality of first material layers arranged at intervals, wherein before performing the second etching, the method further comprises forming a protective layer on the surface of the second region, the protective layer further at least extending towards the surface of the first region. The method can obtain semiconductor devices of higher reliability.

Description

Method for manufacturing semiconductor structure and semiconductor structure

[0001] The present application claims priority to the Chinese patent application No. 202410653075.3, filed on May 22, 2024, and entitled "Method for manufacturing semiconductor structure and semiconductor structure", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure. BACKGROUND

[0003] The development of dynamic random access memory (DRAM) pursues high speed, high integration density, low power consumption and other performance indicators. With the miniaturization of semiconductor device structures, the technical barriers encountered by existing structures become more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers.

[0004] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), generally includes multiple transistors stacked on a substrate, which meets the above-mentioned requirements.

[0005] However, the manufacturing process of the multilayer stacked transistors and capacitors is complex, especially in the process of manufacturing the capacitors, the etching and filling processes are difficult, the process flow needs to be optimized, and the device yield needs to be improved. SUMMARY

[0006] According to a first aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0007] providing a substrate, the substrate comprising a first region and a second region;

[0008] forming a stack structure comprising a plurality of first material layers and a plurality of second material layers alternately stacked on the first region;

[0009] performing a first etching to form a groove at one end of the stack structure, the bottom of the groove exposing the second region;

[0010] performing a second etching to remove part of the plurality of second material layers through the groove and leaving the plurality of first material layers spaced apart;

[0011] wherein, before performing the second etching, further comprising forming a protective layer on the surface of the second region, and the protective layer further extends at least towards the surface of the first region.

[0012] In some embodiments, the forming of the protection layer after the first etching comprises: oxidizing the second region exposed by the bottom of the trench to form an oxide layer on the surface of the second region as the protection layer.

[0013] In some embodiments, the oxidation is wet oxidation.

[0014] In some embodiments, before the oxidizing the second region exposed by the bottom of the trench, the method further comprises: forming a barrier layer on the sidewall of the trench; and after the forming of the oxide layer on the surface of the second region as the protection layer, the method further comprises: removing the barrier layer.

[0015] In some embodiments, the forming of the protection layer before the forming of the stack structure comprises: performing ion implantation on the surface of the substrate and annealing to form a doped layer on the surface of the second region as the protection layer.

[0016] In some embodiments, the ion implantation is performed by boron ions.

[0017] In some embodiments, the doped layer is also on the surface of the first region.

[0018] In some embodiments, after the performing of the second etching to remove part of the plurality of second material layers through the trench and retain the plurality of first material layers arranged in intervals, the method further comprises: filling a capacitor material in the gap between the plurality of first material layers through the trench to form a capacitor structure, the capacitor structure comprising a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence.

[0019] In some embodiments, before the filling of the capacitor material, the method further comprises: performing a metallization process on part of the plurality of second material layers retained after the second etching to form a capacitor contact structure.

[0020] According to a second aspect of the embodiments of the present disclosure, a semiconductor structure is provided, comprising:

[0021] a substrate, the substrate comprising a first region and a second region;

[0022] a stack structure on the first region;

[0023] a trench structure at one end of the stack structure, and the trench structure is on the second region;

[0024] a protection layer on the surface of the second region and the bottom of the trench structure, and the protection layer further extends at least towards the surface of the first region.

[0025] In some embodiments, the protective layer is a wet oxygen layer or a boron doped layer.

[0026] In some embodiments, the first region and the second region are adjacent or at least partially overlap.

[0027] In some embodiments, the trench structure includes a top electrode plate formed by filling a second electrode material.

[0028] In some embodiments, the stack structure includes an alternating stack of a plurality of capacitor structures and isolation structures located between adjacent capacitor structures.

[0029] In some embodiments, the stack structure further includes: an active structure corresponding to each capacitor structure and located at an end of the capacitor structure away from the trench structure; and a capacitor contact structure located between the active structure and the capacitor structure, the active structure being connected to the capacitor structure through the capacitor contact structure. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1 is a schematic diagram showing a substrate according to an exemplary embodiment;

[0031] FIG. 2 is a schematic diagram showing formation of a stack structure according to an exemplary embodiment;

[0032] FIG. 3 is a schematic diagram showing formation of a recess according to an exemplary embodiment;

[0033] FIG. 4 is a schematic diagram showing formation of a barrier layer on a sidewall of the recess according to an exemplary embodiment;

[0034] FIG. 5 is a schematic diagram showing formation of a protective layer according to an exemplary embodiment;

[0035] FIG. 6 is a schematic diagram showing removal of the barrier layer according to an exemplary embodiment;

[0036] FIG. 7 is a schematic diagram showing removal of a portion of a second material layer through the recess according to an exemplary embodiment;

[0037] FIG. 8 is a schematic diagram showing formation of a capacitor contact structure according to an exemplary embodiment;

[0038] FIG. 9 is a schematic diagram showing formation of a capacitor structure according to an exemplary embodiment;

[0039] FIG. 10 is a schematic diagram showing formation of a protective layer according to another exemplary embodiment;

[0040] FIG. 11 is a schematic diagram showing formation of a stack structure according to another exemplary embodiment;

[0041] FIG. 12 is a schematic view of forming a recess, according to another exemplary embodiment;

[0042] FIG. 13 is a schematic view of removing a portion of the second material layer through the recess, according to another exemplary embodiment;

[0043] FIG. 14 is a schematic view of forming a capacitive contact structure, according to another exemplary embodiment;

[0044] FIG. 15 is a schematic view of forming a capacitive structure, according to another exemplary embodiment;

[0045] FIG. 16 is a cross-sectional schematic view of forming a capacitive structure along the A-A' direction, according to another exemplary embodiment;

[0046] FIG. 17a is a schematic view of forming a 3D DRAM, according to an exemplary embodiment;

[0047] FIG. 17b is a schematic view of forming a 3D DRAM, according to another exemplary embodiment. DETAILED DESCRIPTION

[0048] The technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings, which are shown by way of example only. The advantages and features of the present disclosure will become apparent from the following description with reference to the drawings. It should be noted that the drawings are in very simplified form and are not drawn to precise scale, only to facilitate a clear understanding of the embodiments of the present disclosure.

[0050] It can be understood that the meanings of "on", "above" and "over" of the present disclosure should be interpreted in the broadest way, so that the meaning of "on" not only means the meaning of "on" with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" with intervening features or layers therebetween.

[0051] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0052] In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top and bottom surfaces of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers.

[0053] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0054] In the related art, the process flow of a 3D memory structure usually needs to first form a stack of sacrificial materials, then a hole or a groove is opened in the middle or side of the stack, the sacrificial materials in the stack are removed by lateral etching, and then the target material is filled as a replacement. However, the present inventors have found that in order to fully expose the sacrificial materials and better control the removal of the sacrificial materials, the hole or groove previously opened in the middle or side of the stack often needs to penetrate through the entire stack, and the bottom of the hole or groove exposes the substrate surface. Subsequently, the etchant enters the hole or groove, and while etching the sacrificial materials on the side, the etchant also erodes the substrate to form cavities. These cavities introduce instability and uncertainty in subsequent process flows, such as short circuit problems, parasitic effects, conformality problems of upper and lower structures, and in severe cases, structure collapse.

[0055] To solve the above technical problems, the present disclosure provides a preparation method of a semiconductor structure and a semiconductor structure. In the following, an exemplary preparation method of a semiconductor structure and a semiconductor structure provided by the present disclosure will be specifically introduced in combination with FIGS. 1-17b. FIGS. 1-9 are schematic diagrams of a preparation method of a semiconductor structure and a structure according to an exemplary embodiment of the present disclosure. FIGS. 10-15 are schematic diagrams of a preparation method of a semiconductor structure and a structure according to another exemplary embodiment of the present disclosure. FIG. 16 is a schematic diagram of a cross-section of the structure shown in FIG. 15 along the A-A' direction. FIGS. 17a and 17b are schematic diagrams of a 3D DRAM structure according to multiple exemplary embodiments of the present disclosure.

[0056] Referring to FIG. 1, a substrate 10 is provided, which includes a first region 101 and a second region 102.

[0057] A substrate 10 is provided; wherein the material of the substrate 10 can be at least one of the following semiconductor materials or III-V materials: silicon, germanium, silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), germanium-on-insulator (GeOI), and the like. In an exemplary embodiment of the present disclosure, the material of the substrate 10 is monocrystalline silicon.

[0058] The substrate 10 comprises a first region 101 and a second region 102. In some embodiments, the first region 101 is adjacent to the second region 102, as shown in (a) of FIG. 1; in other embodiments, the first region 101 and the second region 102 partially overlap, as shown in (b) of FIG. 1; in yet other embodiments, the second region 102 is entirely located in the first region 101, as shown in (c) of FIG. 1. The specific arrangement of the first region 101 and the second region 102 can be determined according to the requirement of the relative position between the subsequently formed recess and the stacked structure. In an exemplary embodiment of the present disclosure, the first region 101 is adjacent to the second region 102.

[0059] In an exemplary embodiment of the present disclosure, referring to FIG. 2, a stacked structure 30 is formed on the first region 101, which comprises a plurality of first material layers 301 and a plurality of second material layers 302 alternately stacked.

[0060] The material of the first material layer 301 can be at least one of the following materials or any combination thereof: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the material of the first material layer 301 is silicon oxide. The material of the second material layer 302 can be at least one of the following materials or any combination thereof: silicon, germanium, silicon-germanium (SiGe), III-V materials, indium gallium zinc oxide (IGZO), two-dimensional materials. In an exemplary embodiment of the present disclosure, the material of the second material layer 302 is monocrystalline silicon.

[0061] In some embodiments, the stacked structure 30 formed by the plurality of first material layers 301 and the plurality of second material layers 302 alternately stacked is formed on the first region 101. In other embodiments, the stacked structure 30 also extends to a region outside the first region 101.

[0062] In some embodiments, the structure in the same horizontal layer as the second material layer 302 also comprises an insulating material layer and the second material layer 302 arranged alternately, and the insulating material layer herein can have the same material as the first material layer 301. It can be understood that the second material layer 302 in a single horizontal layer is arranged in a long strip shape in parallel and at intervals.

[0063] In some embodiments, the bottom layer of the stack structure 30, i.e. the layer of the stack structure 30 directly contacting the substrate 10, is the first material layer 301 to ensure isolation of the subsequently formed capacitor structure or memory cell from the substrate 10. In some embodiments, the top layer of the stack structure 30, i.e. the layer of the stack structure 30 farthest from the substrate 10, is the first material layer 301 to protect the second material layer 302 thereunder and the subsequently formed capacitor structure from possible damage in subsequent fabrication processes.

[0064] In some embodiments, the method of forming the stack structure 30 comprises: first, forming an initial stack structure on at least the first region 101, specifically, growing an initial stack structure of silicon-germanium silicon (Si-SiGe) alternating stack on at least the first region 101 by epitaxial growth; then, removing the germanium silicon layers in the initial stack structure by a method of selective etching, for example, using a high-selectivity wet chemical etching, which can sufficiently remove the germanium silicon layers and relatively completely retain the silicon layers as the second material layer 302; and finally, filling the gap after removal of the germanium silicon layers with an insulating material as the first material layer 301.

[0065] In some embodiments, before or after forming the stack structure 30 on the first region 101, the method further comprises forming an insulating layer 20 on other regions of the substrate 10, at least including the second region 102, wherein the insulating layer 20 is co-planar with the stack structure 30.

[0066] In some embodiments, after forming the stack structure 30 and the insulating layer 20, the method further comprises forming a mask layer 41 covering the stack structure 30 and the insulating layer 20, wherein the mask layer 41 has an opening 40’ exposing the top surface of the insulating layer 20 or the top surface of part of the stack structure 30. In an exemplary embodiment of the present disclosure, the projection of the opening 40’ on the substrate 10 coincides with the second region 102, specifically, the opening 40’ can be formed by a photolithography method to expose the top surface of part of the insulating layer 20.

[0067] In some embodiments, the material of the mask layer 41 can be one or a combination of photoresist, spin-on hard mask (SOH), spin-on carbon (SOC), amorphous carbon, polysilicon, silicon nitride, silicon oxynitride, silicon carbon nitride.

[0068] In an example embodiment of the present disclosure, taking the case where the first region 101 is adjacent to the second region 102 (i.e. case (a) in FIG. 1) as an example, after forming the mask layer 41 with the opening 40' as shown in FIG. 2, referring to FIG. 3, the first etching is performed, i.e. etching the insulating layer 20 in contact with one end of the stack structure 30 through the opening 40' to form the groove 40, the bottom of the groove 40 exposes the surface of the second region 102, and one sidewall of the groove 40 exposes at least one end of all the second material layers 302 in the stack structure 30.

[0069] In another example embodiment of the present disclosure, taking the case where the first region 101 is partially overlapped with the second region 102 (i.e. case (b) in FIG. 1) as an example, after forming the mask layer 41 with the opening 40' which also exposes part of the top surface of the stack structure 30, the first etching is performed, i.e. etching the insulating layer 20 in contact with one end of the stack structure 30 and the part of the stack structure 30 exposed through the opening 40' to form the groove 40, the bottom of the groove 40 exposes the surface of the second region 102, and one sidewall of the groove 40 exposes at least one end of all the second material layers 302 in the stack structure 30.

[0070] In yet another example embodiment of the present disclosure, taking the case where the second region 102 is completely located in the first region 101 (i.e. case (b) in FIG. 1) as an example, after forming the mask layer 41 with the opening 40' which only exposes part of the top surface of the stack structure 30, the first etching is performed, i.e. etching the part of the stack structure 30 exposed through the opening 40' to form the groove 40, the bottom of the groove 40 exposes the surface of the second region 102, and one sidewall of the groove 40 exposes at least one end of all the second material layers 302 in the stack structure 30.

[0071] In some embodiments, the etching method of the first etching can employ at least one of the following deposition methods: plasma dry etching, ion beam etching (IBE), reactive ion etching (RIE).

[0072] In some embodiments, the mask layer 41 is removed after the first etching to form the groove 40. In other embodiments, the mask layer 41 remains on at least the top of the stack structure 30.

[0073] In an example embodiment of the present disclosure, after the first etching to form the groove 40, a barrier layer 50 is formed on the sidewall of the groove 40 as shown in FIG. 4, which aims to at least protect the sidewall of the stack structure 30 exposed by the groove 40, on one hand, the surface of the second material layer 302 in the stack structure 30 adjacent to the surface of the groove 40 is oxidized due to being exposed to the outside during the subsequent manufacturing of the protective layer, and on the other hand, it prevents water vapor in the air environment from possibly penetrating into the stack structure, affecting the performance of the device structure.

[0074] In some embodiments, the material of the barrier layer 50 can be at least one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride. In an exemplary embodiment of the present disclosure, the material of the barrier layer 50 is silicon nitride.

[0075] In some embodiments, before forming the barrier layer 50 on the sidewall of the recess 40, a barrier material layer (not shown) is formed on the substrate 10, covering the top surface of the insulating layer 20, the top surface of the stack structure 30, and the sidewall and bottom of the recess 40, and then the barrier material layer on the top surface of the insulating layer 20, the top surface of the stack structure 30, and the bottom of the recess 40 is removed by dry etching, while the barrier material layer on the sidewall of the recess 40 is reserved as the barrier layer 50.

[0076] In some embodiments, the barrier material layer can be formed by at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD).

[0077] In an exemplary embodiment of the present disclosure, after forming the recess 40, a protection layer 60a is formed on the surface of the second region 102 exposed at the bottom of the recess 40. Referring to FIG. 5, in some embodiments, after forming the barrier layer 50 to protect the sidewall of the recess 40, the protection layer 60a is formed on the surface of the second region 102 exposed at the bottom of the recess 40.

[0078] In some embodiments, the material of the protection layer 60a includes at least one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, polysilicon. In an exemplary embodiment of the present disclosure, the material of the protection layer 60a is silicon oxide.

[0079] In some embodiments, the method of forming the protective layer 60a can employ at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), thermal oxidation growth, wet oxidation growth, in-situ steam generation (ISSG). In an exemplary embodiment of the present disclosure, the protective layer 60a is formed by wet oxidation growth. The advantage of using wet oxidation is that water (or steam) can be used as the oxidant to fully oxidize the silicon on the surface of the second region 102, while the silicon nitride barrier layer 50 on the sidewall of the recess 40 is not simultaneously oxidized and lost, mainly because the silicon nitride material is resistant to water vapor oxidation penetration.

[0080] In some embodiments, the protective layer 60a formed by wet oxygen oxidation extends from the surface of the second region 102 to a portion of the first region 101, that is, in addition to oxidizing the silicon material on the surface of the second region 102, at least a portion of the region adjacent to the first region 101 and the second region 102 is also oxidized laterally, that is, the protective layer 60a is formed on the surface of the second region 102 exposed at the bottom of the recess 40, as well as the surface of the region below the barrier layer 50 and the surface of the region below at least a portion of the stack structure 30 near the recess 40, which has the advantage that at least the second region 102 and a portion of the first region 101 adjacent to the second region 102 can be fully protected in subsequent etching processes.

[0081] In some embodiments, the thickness of the protective layer 60a formed by wet oxygen oxidation ranges from 5 nm to 50 nm.

[0082] In an exemplary embodiment of the present disclosure, as shown in FIG. 6, after the protective layer 60a is formed, the barrier layer 50 covering the sidewall of the recess 40 is removed to expose the sidewall of the stack structure 30 near the recess 40. Specifically, any one or a combination of selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching can be used, and the high selectivity etching method will not cause damage to the sidewall of the stack structure 30 exposed by the recess 40.

[0083] In an exemplary embodiment of the present disclosure, as shown in FIG. 7, after the protective layer 60a is formed and the side wall of the stack structure 30 is exposed by the groove 40, a second etching is performed to laterally etch the second material layer 302 in the stack structure 30 through the groove 40 to remove part of the second material layer 302. As part of the second material layer 302 is removed, a space is formed between the remaining first material layers 301.

[0084] In some embodiments, the etching method of the second etching can employ any one or a combination of the following etching methods: selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching. In an exemplary embodiment of the present disclosure, the second etching employs selective wet etching, specifically, ammonia mixed solution (ADM) or tetramethylammonium hydroxide (TMAH) as the etchant to selectively etch the second material layer 302.

[0085] In the second etching, the etching selectivity ratio of the protective layer 60a to the second material layer 302 is not more than 1:10. Therefore, due to the presence of the protective layer 60a, at least the surface of the second region 102 exposed by the bottom of the groove 40 and the surface of the part of the first region 101 adjacent to the second region 102 are protected, thereby avoiding damage to the substrate in these regions caused by the etchant in the second etching.

[0086] In an exemplary embodiment of the present disclosure, after performing the second etching to remove part of the second material layer 302, as shown in FIG. 8, a contact material layer 71 is deposited on the surface of the stack structure, the contact material layer 71 covers the surface of the first material layer 301 exposed after part of the second material layer 302 is removed, and is in contact with the remaining part of the second material layer 302. After a thermal annealing process, the contact material layer 71 and the remaining part of the second material layer 302 in the contact area are subjected to a metallization reaction to form a metal-semiconductor contact as the capacitor contact structure 70.

[0087] In some embodiments, the material of the contact material layer 71 can be any one or more of the following metal materials: cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), ruthenium (Ru), platinum (Pt). Accordingly, the material of the capacitor contact structure 70 can be any one or more of the following metal silicide materials: cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), titanium silicide (Ti), tantalum silicide (TaSi), ruthenium silicide (RuSi), platinum silicide (PtSi).

[0088] In some embodiments, after forming the metal-semiconductor contact as the capacitive contact structure 70, the contact material layer 71 that does not participate in the metallization reaction is removed. Specifically, any one or a combination of selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching can be employed.

[0089] In an exemplary embodiment of the present disclosure, after forming the metal-semiconductor contact as the capacitive contact structure 70, and removing the contact material layer 71 that does not participate in the reaction, a capacitive material is filled in the gaps between the adjacent first material layers 301 in the stack structure 30 through the recesses 40 to form the capacitive structure 80, as shown in FIG. 9. Specifically, a first electrode material, a capacitive dielectric material, and a second electrode material are sequentially deposited in the gaps between the adjacent first material layers 301 through the recesses 40 to form a first electrode layer 801, a capacitive dielectric layer 802, and a second electrode layer 803, respectively, as shown in the partial enlarged view in FIG. 9, the first electrode layer 801 is in direct contact with the capacitive contact structure 70.

[0090] In some embodiments, a capacitive structure 80 is filled in each of the gaps between the adjacent first material layers 301, and it is noted that the first electrode layers 801 of the adjacent capacitive structures 80 are disconnected from each other, but the capacitive dielectric layers 802 are connected as a whole to each other, and the second electrode layers 803 are also connected as a whole to each other.

[0091] In some embodiments, the first electrode layers 801 of the adjacent capacitive structures 80 can be formed by depositing a first electrode material on the surface of the stack structure 30 including the inner walls of the gaps between the adjacent first material layers 301, and then disconnecting the first electrode material on the sidewalls of the recesses 40 and etching and removing the first electrode material in other areas to only retain the first electrode material on the inner walls of the gaps between the adjacent first material layers 301 in the stack structure 30 as the first electrode layers 801 by etching.

[0092] In some embodiments, the capacitive dielectric layer 802 is formed on the surface of the stack structure 30 and the surface of the first electrode layer 801 on the inner walls of the gaps between the adjacent first material layers 301, and the capacitive dielectric layer 802 also covers the sidewalls and the bottom of the recesses 40, i.e., the top surface of the protection layer 60a.

[0093] In some embodiments, a second electrode material is deposited to cover the surface of the capacitive dielectric layer 802 and fill each of the gaps between the adjacent first material layers 301 to form the second electrode layer 803, and the second electrode material also fills in the recesses 40 to form a top electrode plate 804 for connecting the second electrode layers 803 as a whole.

[0094] In some embodiments, the material of the first electrode layer 801 and the second electrode layer 803 can be at least one or more of a combination of titanium nitride, tantalum nitride, or tungsten nitride, and the material of the capacitive dielectric layer 802 can be at least one or more of a combination of silicon oxide (SiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), lead zirconate titanate (PZT).

[0095] In some embodiments, the deposition method of the first electrode layer 801, the capacitive dielectric layer 802, and the second electrode layer 803 can employ at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating sputtering.

[0096] In another exemplary embodiment of the present disclosure, after providing the substrate 10 including the first region 101 and the second region 102 as shown in FIG. 1, ion implantation is performed on the substrate 10 and annealing is performed to form a doped layer as the protective layer 60b on the surface of the second region 102, with reference to FIG. 10. In some embodiments, the protective layer 60b is located at least on the surface of the first region 101 as well, specifically, ion implantation can be performed on the first region 101 as well and annealing is performed, or ion implantation is performed only on the second region 102 and the dopant ions diffuse from the surface of the second region 102 to the surface of the first region 101 in the subsequent annealing process. In other embodiments, the protective layer 60b is located on the surface of the entire substrate 10.

[0097] In some embodiments, boron ions are used as the dopant ions for ion implantation on the substrate 10 and annealing to form a boron-doped layer as the protective layer 60b. In some embodiments, the thickness of the protective layer 60b ranges from 20 nm to 40 nm, i.e., the doping depth ranges from 20 nm to 40 nm. In some embodiments, the concentration of the doped element in the protective layer 60b ranges from 1E+13 / cm2to 1E+21 / cm2. 3 ~ 1E+21 / cm 3 It is noted that the concentration of the doped element of the protective layer 60b gradually decreases as the depth of the top surface of the substrate 10 extending to the interior of the substrate 10 increases.

[0098] In some embodiments, as shown in FIG. 11, the stack structure 30 formed by the plurality of first material layers 301 and the plurality of second material layers 302 is formed on the first region 101.

[0099] The material of the first material layer 301 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the material of the first material layer 301 is silicon oxide. The material of the second material layer 302 can be at least one or any combination of the following materials: silicon, germanium, silicon-germanium (SiGe), III-V group material, indium gallium zinc oxide (IGZO), two-dimensional material. In an exemplary embodiment of the present disclosure, the material of the second material layer 302 is single crystal silicon.

[0100] In some embodiments, the stack structure 30 formed by the plurality of first material layers 301 and the plurality of second material layers 302 is formed on the first region 101. In other embodiments, the stack structure 30 also extends to regions outside the first region 101.

[0101] In some embodiments, the structure in the same horizontal layer as the second material layer 302 also includes an insulating material layer and the second material layer 302 arranged alternately, and the insulating material layer can have the same material as the first material layer 301. It can be understood that the second material layer 302 in a single horizontal layer is arranged in a long strip shape in parallel and spaced apart.

[0102] In some embodiments, the bottom layer of the stack structure 30, i.e. the layer of the stack structure 30 in direct contact with the substrate 10, is the first material layer 301, to ensure the isolation of the subsequently formed capacitor structure or storage unit from the substrate 10. In some embodiments, the top layer of the stack structure 30, i.e. the layer of the stack structure 30 farthest from the substrate 10, is the first material layer 301, to protect the second material layer 302 and the subsequently formed capacitor structure below from possible damage in subsequent manufacturing processes.

[0103] In some embodiments, the method of forming the stack structure 30 includes: first, forming an initial stack structure on at least the first region 101, specifically, growing a silicon-germanium (Si-SiGe) alternately stacked initial stack structure on at least the first region 101 by epitaxial growth; then, removing the germanium silicon layer in the initial stack structure by a selective etching method, for example, using a high-selectivity wet chemical etching method, which can more completely remove the germanium silicon layer and more completely retain the silicon layer as the second material layer 302; finally, filling the gap after the removal of the germanium silicon layer with an insulating material as the first material layer 301.

[0104] In some embodiments, before or after forming the stack structure 30 on the first region 101, further comprising forming an insulating layer 20 on other regions (at least including the second region 102) of the substrate 10, wherein the insulating layer 20 is level with the stack structure 30.

[0105] In some embodiments, after forming the stack structure 30 and the insulating layer 20, further comprising forming a mask layer 41 covering the stack structure 30 and the insulating layer 20, wherein the mask layer 41 has an opening 40' exposing a top surface of the insulating layer 20 or a top surface of part of the stack structure 30. In an example embodiment of the present disclosure, the projection of the opening 40' on the substrate 10 coincides with the second region 102, and specifically, the opening 40' can be formed by a photolithography method to expose part of the top surface of the insulating layer 20.

[0106] In some embodiments, the material of the mask layer 41 can be one or a combination of photoresist, spin-on hard mask (SOH), spin-on carbon (SOC), amorphous carbon, polysilicon, silicon nitride, silicon oxynitride, silicon carbon nitride. In an example embodiment of the present disclosure, the material of the mask layer 41 is silicon nitride.

[0107] In an example embodiment of the present disclosure, taking the case where the first region 101 and the second region 102 are contiguous (i.e. case (a) in FIG. 1) as an example, after forming the mask layer 41 with the opening 40' as shown in FIG. 11, referring to FIG. 12, a first etching is performed, i.e. etching the insulating layer 20 located at one end of the stack structure 30 through the opening 40' to form a groove 40, the bottom of the groove 40 exposes the surface of the second region 102, i.e. the surface of the protective layer 60b formed on the surface of the second region 102, and one sidewall of the groove 40 exposes at least one end of all the second material layers 302 in the stack structure 30.

[0108] In another example embodiment, taking the case where the first region 101 and the second region 102 have a partially overlapping region (i.e. case (b) in FIG. 1) as an example, after forming the mask layer 41 with the opening 40', which also exposes part of the top surface of the stack structure 30, a first etching is performed, i.e. etching the insulating layer 20 located at one end of the stack structure 30 and the exposed part of the stack structure 30 through the opening 40' to form a groove 40, the bottom of the groove 40 exposes the surface of the second region 102, i.e. the surface of the protective layer 60b formed on the surface of the second region 102, and one sidewall of the groove 40 exposes at least one end of all the second material layers 302 in the stack structure 30.

[0109] In another exemplary embodiment, taking the case where the second region 102 is completely located in the first region 101 (i.e. case (b) in FIG. 1) as an example, after forming the mask layer 41 with the opening 40', which exposes only part of the top surface of the stack structure 30, a first etching is performed, i.e. etching the exposed part of the stack structure 30 through the opening 40' to form a groove 40, the bottom of the groove 40 exposes the surface of the second region 102, i.e. the surface of the protective layer 60b formed on the surface of the second region 102, and one sidewall of the groove 40 exposes at least one end of all the second material layers 302 in the stack structure 30.

[0110] In some embodiments, the etching method of the first etching can employ at least one of the following deposition methods: plasma dry etching, ion beam etching (IBE), reactive ion etching (RIE).

[0111] In some embodiments, after the groove 40 is formed by performing the first etching, the mask layer 41 is still retained on at least the top of the stack structure 30. In other embodiments, the mask layer 41 is removed in subsequent processes.

[0112] In an exemplary embodiment of the present disclosure, after the groove 40 is formed to expose the sidewall of the stack structure 30 and the top surface of the protective layer 60b in the second region 102, a second etching is performed, as shown in FIG. 13, the second material layer 302 in the stack structure 30 is laterally etched through the groove 40 to remove part of the second material layer 302. As part of the second material layer 302 is removed, a gap is formed between the remaining first material layers 301.

[0113] In some embodiments, the etching method of the second etching can employ any one or a combination of selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching. In an exemplary embodiment of the present disclosure, the second etching employs selective wet etching, specifically, ammonia mixed solution (ADM) or tetramethylammonium hydroxide (TMAH) is used as the etchant for selectively etching the second material layer 302.

[0114] In the second etching, the etching selectivity ratio of the protective layer 60b to the second material layer 302 is not more than 1:10, therefore, due to the presence of the protective layer 60b, at least the surface of the second region 102 exposed by the bottom of the groove 40 and the surface of the part of the first region 101 adjacent to the second region 102 are protected, thereby avoiding damage to the substrate in these regions caused by the etchant in the second etching.

[0115] In an exemplary embodiment of the present disclosure, after performing the second etching to remove part of the second material layer 302, a contact material layer 71 is deposited on the surface of the stack structure 30, as shown in FIG. 14, covering the surface of the first material layer 301 exposed after removing part of the second material layer 302, and contacting the remaining part of the second material layer 302. After heat annealing, the contact material layer 71 and the remaining part of the second material layer 302 in the contact area are subjected to a metallization reaction to form a metal semiconductor contact as a capacitor contact structure 70.

[0116] In some embodiments, the material of the contact material layer 71 can be any one or more of the following metal materials: cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), ruthenium (Ru), platinum (Pt). Correspondingly, the material of the capacitor contact structure 70 can be any one or more of the following metal silicide materials: cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), titanium silicide (TiSi), tantalum silicide (TaSi), ruthenium silicide (RuSi), platinum silicide (PtSi).

[0117] In some embodiments, after forming the metal semiconductor contact as the capacitor contact structure 70, the contact material layer 71 not participating in the metallization reaction is removed. Specifically, any one or more of the following etching methods can be used: selective plasma dry etching, selective wet etching, reactive ion etching (RIE), and vapor phase chemical etching.

[0118] In an exemplary embodiment of the present disclosure, after forming the metal semiconductor contact as the capacitor contact structure 70 and removing the contact material layer 71 not participating in the reaction, a capacitor material is filled into the gaps between the adjacent first material layers 301 in the stack structure 30 through the recesses 40 to form capacitor structures 80, to form a new stack structure 30', as shown in FIG. 15. Specifically, a first electrode material, a capacitor dielectric material, and a second electrode material are sequentially deposited into the gaps between the adjacent first material layers 301 through the recesses 40 to form a first electrode layer 801, a capacitor dielectric layer 802, and a second electrode layer 803, respectively, as shown in the partial enlarged view in FIG. 15, the first electrode layer 801 directly contacts the capacitor contact structure 70.

[0119] In some embodiments, a capacitor structure 80 is filled into each of the gaps between the adjacent first material layers 301, and it is noted that the first electrode layers 801 of the adjacent capacitor structures 80 are disconnected from each other, but the capacitor dielectric layers 802 are connected as a whole, and the second electrode layers 803 are also connected as a whole.

[0120] In some embodiments, the first electrode layer 801 of the adjacent capacitor structure 80 can be formed by depositing a first electrode material on the surface of the stack structure 30 including the inner walls of the gaps between the adjacent first material layers 301, and then removing the first electrode material on the sidewalls of the recesses 40 and other areas by etching to only keep the first electrode material on the inner walls of the gaps between the adjacent first material layers 301 in the stack structure 30 as the first electrode layer 801.

[0121] In some embodiments, the capacitor dielectric layer 802 is formed on the surface of the stack structure 30 and the surface of the first electrode layer 801 on the inner walls of the gaps between the adjacent first material layers 301, wherein the capacitor dielectric layer 802 also covers the sidewalls and the bottom of the recesses 40, i.e., the top surface of the protection layer 60b.

[0122] In some embodiments, a second electrode material is deposited to cover the surface of the capacitor dielectric layer 802 and fill the gaps between the adjacent first material layers 301 to form the second electrode layer 803, wherein the second electrode material also fills in the recesses 40 to form the top electrode plate 804 for connecting the second electrode layers 803 into one whole.

[0123] In some embodiments, the materials of the first electrode layer 801 and the second electrode layer 803 can be at least one or a combination of titanium nitride, tantalum nitride, or tungsten nitride, and the material of the capacitor dielectric layer 802 can be at least one or a combination of silicon oxide (SiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), lead zirconate titanate (PZT).

[0124] In some embodiments, the deposition methods of the first electrode layer 801, the capacitor dielectric layer 802, and the second electrode layer 803 can use at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating sputtering.

[0125] In some embodiments, the structure in the same horizontal layer as the capacitor structure 80 also includes alternating arrangement of the insulating material layer and the capacitor structure 80, and the insulating material layer here can have the same material as the first material layer 301. It can be understood that, for the capacitor structure 80 in a single horizontal layer in a long strip shape and arranged in parallel and at intervals, referring to FIG. 16, which is a schematic cross-sectional view along the A-A' direction of FIG. 15, the capacitor structures 80 are arranged in an array in the stack structure 30.

[0126] The method for manufacturing the semiconductor structure provided by the present disclosure includes the following steps: forming a protective layer on the surface of the substrate at the bottom of the groove and the surrounding area. When the lateral etching of the sacrificial material (part of the second material layer 302) is performed, the surface of the substrate at the bottom of the groove and the surrounding area can be effectively protected, so that the hollow formed by the etchant in the related art is avoided, and the instability and uncertainty introduced in the subsequent process flow are avoided. The process step of forming the protective layer has low implementation difficulty, high feasibility, and can obtain a structure with high device reliability without increasing too much cost.

[0127] Based on the above method for manufacturing the semiconductor structure, the present disclosure further provides a semiconductor structure, as shown in FIG. 9 or FIG. 15, which at least includes: a substrate 10, the substrate 10 including a first region 101 and a second region 102; a stack structure 30' located on the first region 101; a trench structure 400 located at one end of the stack structure 30', and the trench structure 400 is located on the second region 102; a protective layer 60a or 60b located on the surface of the second region 102 and the bottom of the trench structure 400, and the protective layer 60a or 60b also extends at least towards the surface of the first region 101.

[0128] In an example embodiment of the present disclosure, referring to FIG. 9, the protective layer 60a is a wet oxygen layer, that is, an oxide layer formed by wet oxygen oxidation; in some embodiments, the thickness of the protective layer 60a formed by wet oxygen oxidation ranges from 5 nm to 50 nm.

[0129] In another example embodiment of the present disclosure, referring to FIG. 15, the protective layer 60b is a boron-doped layer; in some embodiments, the doping depth of the boron-doped layer is 20 nm to 40 nm, that is, the thickness of the protective layer 60b ranges from 20 nm to 40 nm. In some embodiments, the concentration of the doping element in the protective layer 60b ranges from 1E+13 / cm2to 1E+21 / cm2. 3 3 It should be noted that the concentration of the doping element of the protective layer 60b gradually decreases as the extension depth of the surface of the substrate 10 towards the interior of the substrate 10 increases.

[0130] ​In some embodiments, the first region 101 and the second region 102 are adjacent, as shown in (a) of FIG. 1; in other embodiments, the first region 101 and the second region 102 have partial overlap, as shown in (b) of FIG. 1; in yet other embodiments, the second region 102 is entirely located in the first region 101, as shown in (c) of FIG. 1.

[0131] In some embodiments, the trench structure 400 includes a top electrode plate 804 formed by filling the trench structure 400 with a second electrode material, and the surfaces of the inner walls of the trench structure 400 (including the bottom surface and the sidewalls) are further covered with a capacitor dielectric layer 802. In some embodiments, the electrode material can be at least one or a combination of titanium nitride, tantalum nitride, or tungsten nitride.

[0132] In some embodiments, the stack structure 30’ includes a stack of multiple capacitor structures 80 and isolation structures, the isolation structures including multiple first material layers 301 and insulating material layers arranged in the same horizontal layer of structures alternately with the capacitor structures 80, the isolation structures being located between and spacing apart adjacent capacitor structures 80; in some embodiments, the insulating material layers and the first material layers 301 can have the same material. In an example embodiment of the present disclosure, the first material layers 301 and the insulating material layers are both silicon oxide.

[0133] In some embodiments, the stack structure 30’ further includes active structures (i.e., the remaining second material layers 302 in the stack structure 30) and capacitor contact structures 70, the active structures being located at one end of the capacitor structures 80 away from the trench structure 400, corresponding to the capacitor structures 80 one-to-one, for serving as source / drain electrodes and channel regions between the source / drain electrodes of transistors; the capacitor contact structures 70 are located between the active structures and the capacitor structures 80, and the active structures are connected to the capacitor structures 80 through the capacitor contact structures 70.

[0134] In some embodiments, the material of the active structures can be at least one or any combination of the following materials: silicon, germanium, silicon-germanium (SiGe), III-V group materials, indium-gallium-zinc-oxide (IGZO), two-dimensional materials. In an example embodiment of the present disclosure, the material of the active structures is doped monocrystalline silicon.

[0135] In some embodiments, the material of the capacitor contact structures 70 can be any one or more of the following metal silicide materials: cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), titanium silicide (Ti), tantalum silicide (TaSi), ruthenium silicide (RuSi), platinum silicide (PtSi).

[0136] In an example embodiment of the present disclosure, the semiconductor structure provided by the present disclosure further comprises a word line structure 91a and a bit line structure 92a, as shown in FIG. 17a, the word line structure 91a is connected with the active structures in the same column arranged vertically through the stack structure 30' for controlling the opening or closing of the memory transistors in the column; the bit line structure 92a is located at the end of the active structure away from the capacitor structure 80, and is connected with the active structures in the same row arranged horizontally for providing or sensing the storage charge in the memory capacitor in the row.

[0137] In another example embodiment of the present disclosure, the semiconductor structure provided by the present disclosure further comprises a word line structure 91b and a bit line structure 92b, as shown in FIG. 17b, the word line structure 91b is connected with the active structures in the same row arranged horizontally for controlling the opening or closing of the memory transistors in the row; the bit line structure 92b is connected with the active structures in the same column arranged vertically through the stack structure 30' and at the end of the active structure away from the capacitor structure 80 for providing or sensing the storage charge in the memory capacitor in the column.

[0138] In some embodiments, the steps of forming the word line structure 91a or 91b and the bit line structure 92a or 92b can be performed before the step of forming the capacitor structure 80, i.e. before forming the recess 40, the word line structure 91a or 91b and / or the bit line structure 92a or 92b are formed at the other end of the stack structure 30. In other embodiments, the steps of forming the word line structure 91a or 91b and the bit line structure 92a or 92b can be performed after the step of forming the capacitor structure 80, i.e. after filling the recess 40 with the top electrode plate 804, the word line structure 91a or 91b and / or the bit line structure 92a or 92b are formed at the other end of the stack structure 30'.

[0139] The semiconductor structure provided by the present disclosure comprises a protective layer on the substrate surface at the bottom of the recess and the surrounding area, which solves the problem of the substrate surface at the bottom of the trench being eroded to form a cavity during the lateral etching of the sacrificial layer in the stack structure in the related art, and the related device made of the above semiconductor structure has good device reliability.

[0140] It should be noted that the semiconductor structure in the embodiments of the present disclosure can be used to manufacture 3D DRAM devices, and can also be used to manufacture other 3D devices that require lateral etching of the sacrificial layer in the stack structure, which is not limited here.

[0141] The various semiconductor structures shown in the embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be implemented by a memory, such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0142] The above merely provides the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The method comprises: providing a substrate (10), the substrate (10) comprising a first region (101) and a second region (102); forming a stack structure (30) comprising a plurality of first material layers (301) and a plurality of second material layers (302) alternately stacked on the first region (101); performing a first etching to form a groove (40) at one end of the stack structure (30), the bottom of the groove (40) exposing the second region (102); performing a second etching to remove part of the plurality of second material layers (302) through the groove (40) and leaving the plurality of first material layers (301) arranged at intervals; wherein, before performing the second etching, further comprising forming a protective layer (60a, 60b) on the surface of the second region (302), and the protective layer (60a, 60b) further extends at least towards the surface of the first region (101).

2. The method of fabricating a semiconductor structure of claim 1, wherein, The protective layer (60a, 60b) is formed after performing the first etching, comprising: oxidizing the second region (102) exposed at the bottom of the groove (40) to form an oxide layer on the surface of the second region (102) as the protective layer (60a).

3. The method of fabricating a semiconductor structure of claim 2, wherein, The oxidation is wet oxidation.

4. The method of fabricating a semiconductor structure of claim 2, wherein, Before oxidizing the second region (102) exposed at the bottom of the groove (40), further comprising: forming a barrier layer (50) on the sidewall of the groove (40); and, after forming the oxide layer on the surface of the second region as the protective layer (60a), further comprising: removing the barrier layer (50).

5. The method of fabricating a semiconductor structure of claim 1, wherein, The protective layer (60a, 60b) is formed before forming the stack structure (30), comprising: performing ion implantation on the surface of the substrate (10) and annealing to form a doped layer on the surface of the second region (102) as the protective layer (60b).

6. The method of fabricating a semiconductor structure of claim 5, wherein, The ion implantation is performed using boron ions.

7. The method of fabricating a semiconductor structure of claim 5, wherein, The doped layer is also on the surface of the first region (101).

8. The method of fabricating a semiconductor structure according to any one of claims 1-7, wherein, After performing the second etching to remove part of the plurality of second material layers (302) through the groove (40) and leaving the plurality of first material layers (301) arranged at intervals, further comprising: filling a capacitor material between the plurality of first material layers (301) through the groove (40) to form a capacitor structure (80), the capacitor structure (80) comprising a first electrode layer (801), a capacitor dielectric layer (802), and a second electrode layer (803) stacked in sequence.

9. The method of fabricating a semiconductor structure of claim 8, wherein, Before filling the capacitor material, further comprising: performing a metallization process on part of the plurality of second material layers (302) left after the second etching to form a capacitor contact structure (70).

10. A semiconductor structure, characterized by The method comprises: providing a substrate (10), the substrate (10) comprising a first region (101) and a second region (102); a stack structure (30') on the first region (101); a trench structure (400) at one end of the stack structure (30'), and the trench structure (400) is on the second region (102); A protective layer (60a, 60b) is located on the surface of the second region (102) and the bottom of the trench structure (400), and the protective layer (60a, 60b) also extends at least towards the surface of the first region (101).

11. The semiconductor structure of claim 10, wherein, The protective layer (60a, 60b) is a wet oxygen layer or a boron-doped layer.

12. The semiconductor structure of any of claims 10-11, wherein, The first region (101) and the second region (102) are adjacent or at least partially overlap.

13. The semiconductor structure of any of claims 10-11, wherein, The trench structure (400) includes a top electrode plate (804) formed by filling a second electrode material.

14. The semiconductor structure of any of claims 10-11, wherein, The stack structure (30') includes an alternating stack of a plurality of capacitor structures (80) and isolation structures located between adjacent capacitor structures (80).

15. The semiconductor structure of claim 14, wherein, The stack structure (30') further includes: An active structure located at one end of the capacitor structure (80) away from the trench structure (400) and corresponding to the capacitor structure (80); A capacitor contact structure (70) located between the active structure and the capacitor structure (80), and the active structure is connected to the capacitor structure (80) through the capacitor contact structure (70).

Images