Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided in the embodiments are a display panel and a display apparatus, which are used for improving the light transmittance of display panels. The display panel comprises a substrate, a light shielding layer and a first source-drain conductive layer. The light shielding layer is located on a side of the substrate, the light shielding layer comprising a plurality of first signal lines, and the first signal lines extending in a first direction. The first source-drain conductive layer is located on the side of the light shielding layer away from the substrate, the first source-drain conductive layer comprising a plurality of second signal lines, and the second signal lines extending in the first direction. In a display area of the display panel, the orthographic projections of the first signal lines on the substrate and the orthographic projections of the second signal lines on the substrate at least partially overlap each other. The display panel is used for displaying images.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410628252.2, filed on May 20, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display devices have gradually spread in people's lives. Among them, the organic light-emitting diode (OLED) display panel has been widely used in smart products such as mobile phones, televisions, and notebook computers due to its self-luminous, low power consumption, wide viewing angle, fast response speed, high contrast ratio, and other advantages. SUMMARY

[0004] In one aspect, a display panel is provided, comprising a substrate, a light shielding layer, and a first source-drain conductive layer. The light shielding layer is located on one side of the substrate, and the light shielding layer comprises a plurality of first signal lines extending along a first direction. The first source-drain conductive layer is located on a side of the light shielding layer away from the substrate, and the first source-drain conductive layer comprises a plurality of second signal lines extending along the first direction. In the display area of the display panel, the orthogonal projection of the first signal line on the substrate and the orthogonal projection of the second signal line on the substrate at least partially overlap.

[0005] In some embodiments, in the display area, the orthogonal projection of the first signal line on the substrate and the orthogonal projection of the second signal line on the substrate completely overlap; or, in the display area, the orthogonal projection of the first signal line on the substrate is located within the range of the orthogonal projection of the second signal line on the substrate.

[0006] In some embodiments, the first signal line and the second signal line are both configured to transmit direct current signals.

[0007] In some embodiments, the first signal line is configured to transmit one of a VDD voltage signal, a VSS voltage signal, and an initialization signal, and the second signal line is configured to transmit one of a VDD voltage signal, a VSS voltage signal, and an initialization signal line.

[0008] In some embodiments, the display panel further comprises a plurality of pixel circuits arranged in an array. Along a second direction, at least two pixel circuits are arranged between any two adjacent first signal lines, and the second direction and the first direction are perpendicular to each other.

[0009] In some embodiments, along the second direction, the number of pixel circuits between any two adjacent first signal lines is the same.

[0010] In some embodiments, the light shielding layer further comprises a plurality of third signal lines extending along the second direction. A plurality of first signal lines are connected between any two adjacent third signal lines.

[0011] In some embodiments, along the second direction, a plurality of first signal lines connected to the same third signal line are alternately arranged on both sides of the third signal line.

[0012] In some embodiments, a plurality of first signal lines are arranged in alignment along the first direction, and any two adjacent first signal lines among the plurality of first signal lines are arranged apart from each other.

[0013] In some embodiments, the light shielding layer further comprises a plurality of third signal lines extending along the second direction. Along the second direction, at least two columns of pixel circuits are arranged between any two adjacent first signal lines, and the plurality of third signal lines and the plurality of first signal lines are crossed and connected.

[0014] In some embodiments, the display panel further comprises a first gate layer between the light shielding layer and the first source-drain conductive layer. The pixel circuit of the display panel comprises a storage capacitor, and the storage capacitor comprises a first plate on the first gate layer. The third signal line in the light shielding layer comprises a plurality of light shielding patterns and a plurality of first connecting portions, and any two adjacent light shielding patterns are connected by the first connecting portion. The first plate and the light shielding pattern on the substrate at least partially overlap in the orthographic projection on the substrate. The first signal line and the first connecting portion are connected.

[0015] In some embodiments, the first source-drain conductive layer further comprises a second connecting portion. The pixel circuit further comprises a threshold compensation transistor, and the source or the drain of the threshold compensation transistor is connected to the first plate through the second connecting portion. The light shielding pattern comprises a main body portion and an extension portion connected to one side of the main body portion. In the orthographic projection on the substrate, the main body portion and the first plate overlap, the extension portion and the first plate do not overlap, and the second connecting portion and the extension portion overlap.

[0016] In some embodiments, the display panel further comprises a first scan signal line extending along the second direction, and the gate of the threshold compensation transistor is connected to the first scan signal line. In the orthogonal projection onto the substrate, the first scan signal line and the first plate are adjacent and spaced apart. The second connection portion and the first scan signal line are cross arranged, and the extension portion is located in the spaced apart region between the first scan signal line and the first plate.

[0017] In some embodiments, the display panel further comprises a second gate layer between the light shielding layer and the first source-drain conductive layer. The storage capacitor of the pixel circuit of the display panel further comprises a second plate located in the second gate layer. The display panel further comprises a first voltage signal line. The first source-drain conductive layer comprises a plurality of fourth connection portions, and the first voltage signal line and the second plate are connected through the fourth connection portions.

[0018] In the orthogonal projection onto the substrate, the extension portion and the fourth connection portion do not overlap; and / or, in the orthogonal projection onto the substrate, the extension portion and the first scan signal line do not overlap.

[0019] In some embodiments, the display panel further comprises a second gate layer between the light shielding layer and the first source-drain conductive layer. The storage capacitor of the pixel circuit of the display panel further comprises a second plate located in the second gate layer. The second gate layer further comprises a third connection portion connected between the second plates of the storage capacitors of two pixel circuits adjacent in a second direction, and the second direction is perpendicular to the first direction. The orthogonal projection onto the substrate of at least one of the first connection portions and the orthogonal projection onto the substrate of at least one of the third connection portions at least partially overlap.

[0020] In some embodiments, the display panel further comprises a first semiconductor layer between the light shielding layer and the second gate layer. The pixel circuit comprises a plurality of transistors, and the transistors comprise an active layer pattern located in the semiconductor layer. The orthogonal projection onto the substrate of at least one of the first connection portions and the orthogonal projection onto the substrate of at least one of the active layer patterns of the transistors at least partially overlap.

[0021] In some embodiments, the plurality of transistors comprises a second light emission control transistor. The orthogonal projection onto the substrate of at least one of the first connection portions and the orthogonal projection onto the substrate of the active layer pattern of the second light emission control transistor at least partially overlap.

[0022] In some embodiments, the second plates of the storage capacitors of the plurality of pixel circuits arranged along the second direction comprise a plurality of second plate pairs, one of the second plate pairs comprising two adjacent second plates. The two second plates belonging to one of the second plate pairs are connected by the third connection portions, and the two second plates belonging to different second plate pairs and adjacent in the second direction are arranged with a spacing.

[0023] The plurality of first connection portions comprise first connection portions of a first type and first connection portions of a second type. In the orthogonal projection onto the substrate, the first connection portions of the first type are located between the two second plates belonging to one of the second plate pairs, and the first connection portions of the first type and the third connection portions at least partially overlap. The first connection portions of the second type are located between the two second plates belonging to different second plate pairs and adjacent in the second direction, and the first connection portions of the second type and the active layer pattern of the transistors at least partially overlap.

[0024] In some embodiments, among the second plates of the storage capacitors of the plurality of pixel circuits arranged along the second direction, any two adjacent second plates are connected by the third connection portions. The orthogonal projection onto the substrate of each of the first connection portions and the orthogonal projection onto the substrate of one of the third connection portions at least partially overlap.

[0025] In another aspect, a display device is provided, comprising the display panel according to any one of the above and an optical element. The optical element is located on the non-light-emitting side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0027] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0028] FIG. 2 is a sectional view of the display device in FIG. 1 along the section line B-B;

[0029] FIG. 3 is a structural diagram of a display panel according to some embodiments;

[0030] FIG. 4 is an equivalent circuit schematic diagram of a pixel circuit according to some embodiments;

[0031] FIG. 5A is a plan view of a partial region of a pixel driving layer within a display panel, according to some embodiments;

[0032] FIG. 5B is a plan view of a partial region of a light shielding layer in a pixel driving layer within a display panel, according to some embodiments;

[0033] FIG. 5C is a plan view of a partial region of a first semiconductor layer in a pixel driving layer within a display panel, according to some embodiments;

[0034] FIG. 5D is a plan view of a partial region of a first gate layer in a pixel driving layer within a display panel, according to some embodiments;

[0035] FIG. 5E is a plan view of a partial region of a light shielding layer, a first semiconductor layer, and a first gate layer in a pixel driving layer within a display panel, according to some embodiments;

[0036] FIG. 5F is a plan view of a partial region of a second gate layer in a pixel driving layer within a display panel, according to some embodiments;

[0037] FIG. 5G is another plan view of a partial region of a second gate layer in a pixel driving layer within a display panel, according to some embodiments;

[0038] FIG. 5H is yet another plan view of a partial region of a second gate layer in a pixel driving layer within a display panel, according to some embodiments;

[0039] FIG. 5I is a plan view of a partial region of a second semiconductor layer in a pixel driving layer within a display panel, according to some embodiments;

[0040] FIG. 5J is a plan view of a partial region of a third gate layer in a pixel driving layer within a display panel, according to some embodiments;

[0041] FIG. 5K is a plan view of a partial region of an interlayer dielectric layer in a pixel driving layer within a display panel, according to some embodiments;

[0042] FIG. 5L is a plan view of a partial region of a first source-drain conductive layer in a pixel driving layer within a display panel, according to some embodiments;

[0043] FIG. 5M is a plan view of a partial region of a third gate layer and a first source-drain conductive layer in a pixel driving layer within a display panel, according to some embodiments;

[0044] FIG. 5N is a plan view of a partial region of a first gate layer, a third gate layer, and a first source-drain conductive layer in a pixel driving layer within a display panel, according to some embodiments;

[0045] FIG. 5O is a plan view of a partial region of a second gate layer and a first source-drain conductive layer in a pixel driving layer within a display panel according to some embodiments;

[0046] FIG. 6A is another plan view of a partial region of a pixel driving layer within a display panel according to some embodiments;

[0047] FIG. 6B is another plan view of a partial region of a light-shielding layer in a pixel driving layer within a display panel according to some embodiments;

[0048] FIG. 6C is a plan view of a partial region of a light-shielding layer and a first source-drain conductive layer in a pixel driving layer within a display panel according to some embodiments;

[0049] FIG. 6D is another plan view of a partial region of a light-shielding layer and a first source-drain conductive layer in a pixel driving layer within a display panel according to some embodiments;

[0050] FIG. 6E is yet another plan view of a partial region of a light-shielding layer and a first source-drain conductive layer in a pixel driving layer within a display panel according to some embodiments;

[0051] FIG. 7 is yet another plan view of a partial region of a light-shielding layer in a pixel driving layer within a display panel according to some embodiments;

[0052] FIG. 8 is yet another plan view of a partial region of a light-shielding layer in a pixel driving layer within a display panel according to some embodiments;

[0053] FIG. 9A is a plan view of a partial region of a light-shielding layer, a first semiconductor layer, and a second gate layer in a pixel driving layer within a display panel according to some embodiments;

[0054] FIG. 9B is a plan view of a partial region of a light-shielding layer and a second gate layer in a pixel driving layer within a display panel according to some embodiments;

[0055] FIG. 10 is still another plan view of a partial region of a light-shielding layer in a pixel driving layer within a display panel according to some embodiments;

[0056] FIG. 11 is yet another plan view of a partial region of a pixel driving layer within a display panel according to some embodiments;

[0057] FIG. 12 is a plan view of a partial region of a light-shielding layer, a first gate layer, and a first source-drain conductive layer in a pixel driving layer within a display panel according to some embodiments;

[0058] FIG. 13 is a plan view of a partial region of a light-shielding layer, a first gate layer, a second gate layer, and a first source-drain conductive layer in a pixel driving layer within a display panel according to some embodiments. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0060] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open-ended, i.e. as "including, but not limited to", in the description and the claims. In the description, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are not necessarily referring to the same embodiment or example. Furthermore, the described features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0061] Hereinafter, the terms "first", "second" are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0062] In describing some embodiments, "coupled" and "connected" and their derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0063] “A, B, and C at least one of” has the same meaning as “at least one of A, B, or C,” and includes the following combinations: only A, only B, only C, A and B, A and C, B and C, and A and B and C.

[0064] “A and / or B” includes the following three combinations: only A, only B, and A and B.

[0065] As used herein, the term “if’ is optionally interpreted as meaning “when” or “upon” or “in response to a determination” or “in response to a detection of,” depending on the context. Similarly, the phrase “if it is determined” or “if [stated condition or event] is detected” is optionally interpreted as meaning “upon a determination” or “in response to a determination” or “upon a detection of [stated condition or event]” or “in response to a detection of [stated condition or event],” depending on the context.

[0066] Use of “adapted to” or “configured to” herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0067] Additionally, use of “based on” means open and inclusive, as a process, step, calculation, or other action that is “based on” one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0068] As used herein, “about,” “approximately,” or “circa” includes the recited value and average values within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0069] As used herein, “parallel,” “perpendicular,” “equal” includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation range of, for example, 5°; “perpendicular” includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation range of, for example, 5°. “Equal” includes absolute equality and near equality, where near equality can be within an acceptable deviation range of, for example, less than or equal to 5% of either of the two quantities being equal.

[0070] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0071] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layers of a device structure (e.g., a semiconductor device) are shown in the drawings. For example, layers not essential to the exemplary embodiments are omitted. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the precise shapes of regions illustrated in the drawings. In particular, the exemplary embodiments are intended to encompass structures that are not exactly as illustrated in the drawings, which structures can result from, for example, manufacturing processes. For example, an etched region illustrated as a rectangle will typically have curved or jagged features. Thus, the regions illustrated in the drawings are intended to be schematic and not limiting of the exemplary embodiments. The exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layers of a device structure (e.g., a semiconductor device) are shown in the drawings. For example, layers not essential to the exemplary embodiments are omitted. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the precise shapes of regions illustrated in the drawings. In particular, the exemplary embodiments are intended to encompass structures that are not exactly as illustrated in the drawings, which structures can result from, for example, manufacturing processes. For example, an etched region illustrated as a rectangle will typically have curved or jagged features. Thus, the regions illustrated in the drawings are intended to be schematic and not limiting of the exemplary embodiments.

[0072] For convenience of the following description, an XYZ coordinate system is established. A third direction Z is a thickness direction of the display device, an XY plane is perpendicular to the Z direction, a first direction Y intersects with a second direction X. For example, the first direction Y and the second direction X are perpendicular to each other.

[0073] It should be noted that, for example, T32 / C1 appearing in the drawings of the present disclosure means that the component is both T32 and C1, and other similar designations appearing in the drawings also follow the above description.

[0074] As shown in FIG. 1, some embodiments of the present disclosure provide a display device 100.

[0075] Exemplarily, the above display device 100 can be any device that displays images whether in motion (e.g., video) or stationary (e.g., a still image) and whether textual or pictorial. More specifically, it is contemplated that the described embodiments can be implemented in and / or associated with a variety of electronic devices, such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like. In FIG. 1, the display device 100 is shown as a mobile phone.

[0076] Exemplarily, the display device 100 can be an electroluminescent display device or a photoluminescent display device. In the case where the display device 100 is an electroluminescent display device, the electroluminescent display device can be an Organic Light-Emitting Diode (OLED) display device or a Quantum Dot Light-Emitting Diodes (QLED) display device. In the case where the display device 100 is a photoluminescent display device, the photoluminescent display device can be a Quantum Dot Light-Emitting Diodes (QLED) display device.

[0077] The display device 100 can also be a Micro Light-emitting Diode (Micro LED) display device or a Mini Light-emitting Diode (Mini LED) display device.

[0078] Hereinafter, some embodiments of the present disclosure will be illustratively described with the display device 100 being an Organic Light-Emitting Diode (OLED) display device, but embodiments of the present disclosure include but are not limited to this, and any other display device can also be considered as long as the same technical idea is applied.

[0079] In some embodiments, please continue to refer to FIG. 1, the display device 100 includes a display panel 10 and a circuit board (not shown in the figure). The circuit board is electrically connected with the display panel 10 and is configured to drive the display panel 10 to display an image.

[0080] Exemplarily, the circuit board includes but is not limited to a Printed Circuit Board (PCB) and a Flexible Printed Circuit Board (FPC).

[0081] In some embodiments, as shown in FIG. 2, FIG. 2 is a sectional view of the display device 100 along the sectional line B-B in FIG. 1. The display device 100 further includes an optical element 20. The optical element 20 is located on the non-light-emitting side 10a of the display panel 10.

[0082] It should be noted that the light-emitting side 10b of the display panel 10 refers to a side where the display panel 10 can display a picture. The above-mentioned “non-light-emitting side 10a of the display panel 10” refers to a side opposite to the light-emitting side 10b of the display panel 10.

[0083] Exemplarily, the optical element 20 can include a camera, so that the display device 100 can implement multiple different functions such as photographing, video recording, or face recognition.

[0084] The optical element 20 can also include a sensor or the like. For example, the optical element 20 can include an under-screen fingerprint recognition sensor, so that the display device 100 can implement a function such as fingerprint recognition.

[0085] For another example, the optical element 20 can include an infrared sensor.

[0086] When the optical element 20 is working, external light needs to pass through the display panel 10 to irradiate on the optical element 20, so as to start the corresponding function.

[0087] Exemplarily, when the optical element 20 is a camera, during the working of the camera (i.e., the optical element 20), external light can pass through the display panel 10 to irradiate on the camera (i.e., the optical element 20), so that the camera (i.e., the optical element 20) can collect the light to implement the functions of photographing or video recording.

[0088] The display panel 10 is described in detail below.

[0089] In some embodiments, as shown in FIG. 3, FIG. 3 is a structural diagram of the display panel 10 according to some embodiments. The display panel 10 can have a rectangular structure.

[0090] It should be noted that the above-mentioned “rectangular structure” means that the shape of the boundary of the display panel 10 is generally rectangular, but is not limited to a standard rectangle. That is, the “rectangle” here not only includes the shape of a standard rectangle, but also includes shapes similar to a rectangle considering the process conditions. For example, as shown in FIG. 3, the long side and the short side of the rectangle are curved at each intersection (i.e., the corner G), that is, the corner G is smooth, so that the shape of the boundary of the display panel 10 in the plan view is a rounded rectangle.

[0091] In other embodiments, the display panel 10 can have a circular structure, or other shapes with corners.

[0092] The embodiments of the present disclosure are described below exemplarily taking the display panel 10 as a rectangular structure, but the embodiments of the present disclosure include but are not limited to this, and the shape of the display panel 10 can also consider any other shape.

[0093] In some embodiments, referring to FIG. 3, the display panel 10 has a display area AA for displaying an image, and a peripheral area AN located at least one side of the display area AA.

[0094] Exemplarily, the peripheral area AN of the display panel 10 can be located at one side of the display area AA of the display panel 10.

[0095] Alternatively, the peripheral area AN of the display panel 10 can be located at opposite sides of the display area AA of the display panel 10.

[0096] Alternatively, please continue to refer to FIG. 3, the peripheral area AN of the display panel 10 can surround the display area AA of the display panel 10.

[0097] It should be noted that the specific arrangement of the peripheral area AN of the display panel 10 is related to the specific design of the display panel 10, and can be designed according to actual needs, which is only exemplarily described herein and does not limit the present disclosure.

[0098] Exemplarily, the peripheral area AN of the display panel 10 can be provided with a gate drive circuit (for example, Gate driver On Array, GOA for short), a control signal line (for example, a clock signal line, a power voltage signal line, etc.), and a bonded driving chip (for example, a Source Driver IC, a source driving chip), etc. However, the functions of the peripheral area AN of the display panel 10 include but are not limited to this.

[0099] In some embodiments, please continue to refer to FIG. 3, the display area AA of the display panel 10 is provided with a plurality of sub-pixels 9, and the sub-pixel 9 is the smallest light emitting unit in the display area AA.

[0100] Exemplarily, the plurality of sub-pixels 9 in the display area AA of the display panel 10 can emit light of the same color, and the display panel 10 can further include a color film layer provided on the light emitting side of the plurality of sub-pixels 9. For example, the plurality of sub-pixels 9 emit white light, red light, green light or blue light, etc. In this case, the color light emitted by the sub-pixel 9 remains the same color light after passing through the color film layer, or is converted into other color light, so that the display panel 10 can realize multi-color light emission when the plurality of sub-pixels 9 emit light of the same color.

[0101] Alternatively, the plurality of sub-pixels 9 in the display area AA of the display panel 10 emit light of different colors, for example, the plurality of sub-pixels 9 include red sub-pixels emitting red light, green sub-pixels emitting green light, and blue sub-pixels emitting blue light, thereby realizing multi-color light emission of the display panel 10.

[0102] Exemplarily, please continue to refer to FIG. 3, the plurality of sub-pixels 9 in the display area AA of the display panel 10 can be arranged in an array.

[0103] For example, please continue to refer to FIG. 3, the plurality of sub-pixels 9 in the display area AA of the display panel 10 can be arranged at intervals along the first direction Y and the second direction X, respectively.

[0104] The sub-pixel 9 is described in detail as follows.

[0105] In some embodiments, referring to FIG. 2, the sub-pixel 9 in the display panel 10 includes a light-emitting device F.

[0106] Exemplarily, referring to FIG. 2, when the display device 100 is an organic light-emitting diode (OLED) display device, the display panel 10 in the display device 100 is an organic light-emitting diode (OLED) display panel, and the light-emitting device F in the display panel 10 can include a first electrode 311, a light-emitting part 331, and a second electrode 321. The first electrode 311, the light-emitting part 331, and the second electrode 321 are sequentially stacked in the third direction Z (i.e., the thickness direction of the display device 100).

[0107] Exemplarily, one of the first electrode 311 and the second electrode 321 can serve as an anode of the light-emitting device F, and the other can serve as a cathode of the light-emitting device F.

[0108] For example, the first electrode 311 can serve as an anode of the light-emitting device F. The first electrode 311 is configured to inject holes into the light-emitting part 331. The second electrode 321 can serve as a cathode of the light-emitting device F. The second electrode 321 is configured to inject electrons into the light-emitting part 331. In some examples, when the second electrode 321 serves as a cathode of the light-emitting device F, the second electrodes 321 of the plurality of light-emitting devices F can be interconnected to form a film layer structure.

[0109] The following is a schematic description of some embodiments of the present disclosure, taking the first electrode 311 as an anode of the light-emitting device F and the second electrode 321 as a cathode of the light-emitting device F as an example.

[0110] Exemplarily, the material used to form the first electrode 311 can include a metal material, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0111] The material used to form the first electrode 311 can also include an alloy material of the above-mentioned metal materials, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb).

[0112] Exemplarily, the first electrode 311 can be a single-layer structure.

[0113] Alternatively, the first electrode 311 can also be a multi-layer composite structure. For example, the first electrode 311 can be a Ti / Al / Ti structure or the like. For another example, the first electrode 311 can be a stack structure formed by a metal material and a transparent conductive material, such as ITO / Ag / ITO, Mo / AlNd / ITO or the like.

[0114] Illustratively, the material used to form the second electrode 321 can include any one or several of magnesium (Mg), silver (Ag), aluminum (Al) or the like.

[0115] The material used to form the second electrode 321 can also include an alloy made of any one or several of magnesium (Mg), silver (Ag), aluminum (Al) or the like.

[0116] The material used to form the second electrode 321 can also include a transparent conductive material, for example, indium tin oxide (ITO).

[0117] In some embodiments, as shown in FIG. 4, which is an equivalent circuit schematic diagram of a pixel circuit 9a according to some embodiments, a sub-pixel 9 within the display panel 10 further includes the pixel circuit 9a. The pixel circuit 9a within the sub-pixel 9 is electrically connected with the light emitting device F within the sub-pixel 9, and the pixel circuit 9a can generate a driving signal (for example, a driving current), and the light emitting device F can emit light under the driving action of the driving signal generated by the pixel circuit 9a.

[0118] Illustratively, one pixel circuit 9a can be electrically connected with one light emitting device F; alternatively, one pixel circuit 9a can also be electrically connected with multiple light emitting devices F.

[0119] Illustratively, please continue to refer to FIG. 3, and in combination with FIG. 4, since the sub-pixel 9 within the display area AA of the display panel 10 includes the pixel circuit 9a, in the case that multiple sub-pixels 9 within the display area AA of the display panel 10 are arranged in an array manner, multiple pixel circuits 9a within the multiple sub-pixels 9 can also be arranged in an array manner.

[0120] For example, the multiple pixel circuits 9a within the multiple sub-pixels 9 can be arranged at intervals along the first direction Y and the second direction X, respectively.

[0121] It should be noted that in FIG. 4, only the pixel circuit 9a within the sub-pixel 9 is taken as an example of the 8T1C structure for illustration, but the structure of the pixel circuit 9a within the sub-pixel 9 in the present disclosure is not limited thereto, for example, the pixel circuit 9a within the sub-pixel 9 can also be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure or the like. Among them, T represents a transistor, the number in front of T indicates the number of transistors, and C represents a capacitor, the number in front of C indicates the number of capacitors.

[0122] Please continue to refer to FIG. 4, the pixel circuit 9a can include 8 transistors (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) and 1 storage capacitor C.

[0123] Exemplarily, the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) in the pixel circuit 9a can be P-type transistors.

[0124] Alternatively, the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) in the pixel circuit 9a can also be N-type transistors.

[0125] Exemplarily, the types of the transistors in the pixel circuit 9a can be the same. For example, the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) in the pixel circuit 9a can all be P-type transistors, or all be N-type transistors. Using the same type of transistors in the pixel circuit 9a can simplify the process flow, reduce the process difficulty in manufacturing the display panel 10, and improve the yield of the display panel 10.

[0126] Alternatively, the types of the transistors in the pixel circuit 9a can be different. That is, the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) can include P-type transistors and N-type transistors. For example, the transistor T2 (i.e., the threshold compensation transistor T2) is an N-type transistor, and the remaining transistors (i.e., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) are P-type transistors.

[0127] The following takes the transistor T2 in the pixel circuit 9a (i.e., the threshold compensation transistor T2) as an N-type transistor, and the remaining transistors (i.e., the first reset transistor T1, the drive transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) as P-type transistors as an example to schematically illustrate some embodiments of the present disclosure.

[0128] Exemplarily, the transistors T1-T8 in the pixel circuit 9a (i.e., the first reset transistor T1, the threshold compensation transistor T2, the drive transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) can be top-gate transistors, bottom-gate transistors, or dual-gate transistors. The dual-gate transistor includes an active layer pattern and top-gate patterns and bottom-gate patterns arranged on both sides of the active layer pattern, and the active layer pattern is driven by the top-gate patterns and the bottom-gate patterns, which can more easily control the threshold voltage; at the same time, it can also improve the carrier mobility. That is, compared with the top-gate transistor and the bottom-gate transistor, the stability of the dual-gate transistor is higher.

[0129] Exemplarily, the transistors T1-T8 in the pixel circuit 9a (i.e., the first reset transistor T1, the threshold compensation transistor T2, the drive transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) can adopt a low-temperature polysilicon thin-film transistor, or can adopt an oxide thin-film transistor, or can adopt a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor. The active layer of the low-temperature polysilicon thin-film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor adopts oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has the advantages of high mobility and fast charging, and the oxide thin-film transistor has the advantage of low leakage current. Integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on one display panel 10 forms a low-temperature polysilicon oxide (LTPO) display panel, and the advantages of both can be utilized to switch the refresh frequency of the display panel 10 to realize low-frequency driving, which is conducive to reducing power consumption and improving display quality.

[0130] In some embodiments, please continue to refer to FIG. 4, the pixel circuit 9a can further include a first node N1, a second node N2, a third node N3 and a fourth node N4. It should be noted that in the pixel circuit 9a provided in the embodiments of the present disclosure, the nodes are not actual components, but are convergence points of relevant electrical connections in the equivalent circuit schematic diagram of the pixel circuit 9a, that is, the nodes are equivalent nodes formed by the convergence points of the relevant electrical connections in the equivalent circuit schematic diagram of the pixel circuit 9a.

[0131] The first node N1 is connected with the gate of the driving transistor T3, the first plate of the storage capacitor C and the source of the threshold compensation transistor T2 respectively, the second node N2 is connected with the source of the driving transistor T3, the drain of the first light-emitting control transistor T5, the drain of the data writing transistor T4 and the drain of the third reset transistor T8 respectively, the third node N3 is connected with the drain of the first reset transistor T1, the source of the threshold compensation transistor T2, the source of the second light-emitting control transistor T6 and the drain of the driving transistor T3 respectively, and the fourth node N4 is connected with the drain of the second light-emitting control transistor T6, the drain of the second reset transistor T7 and the light-emitting device F respectively.

[0132] The second plate of the storage capacitor C is electrically connected with the first voltage signal line VDD, and the first plate of the storage capacitor C is connected with the first node N1, that is, the first plate of the storage capacitor C is connected with the gate of the driving transistor T3.

[0133] The source of the first reset transistor T1 is configured to be electrically connected with the initialization signal line Vinit to receive an initialization signal, the drain of the first reset transistor T1 is electrically connected with the drain of the driving transistor T3, and the gate of the first reset transistor T1 is configured to be electrically connected with the first reset control signal line Reset1 to receive a reset control signal.

[0134] The source of the threshold compensation transistor T2 is electrically connected with the gate of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected with the drain of the driving transistor T3, and the gate of the threshold compensation transistor T2 is configured to be electrically connected with the first scan signal line Ngate to receive a compensation control signal.

[0135] The gate of the driving transistor T3 is connected with the first plate of the storage capacitor C, the source of the driving transistor T3 is connected with the second node N2, and the drain of the driving transistor T3 is connected with the third node N3. The driving transistor T3 determines the size of the driving current flowing between the first voltage signal line VDD and the second voltage signal line VSS according to the potential difference between the gate and the source thereof.

[0136] The drain of the data writing transistor T4 is electrically connected with the source of the driving transistor T3, the source of the data writing transistor T4 is configured to be electrically connected with a data signal line Data to receive a data signal, and the gate of the data writing transistor T4 is configured to be electrically connected with a second scan signal line Pgate to receive a scan signal.

[0137] The source of the first light emitting control transistor T5 is electrically connected with a first voltage signal line VDD, the drain of the first light emitting control transistor T5 is electrically connected with the source of the driving transistor T3, and the gate of the first light emitting control transistor T5 is configured to be electrically connected with a light emitting control signal line EM to receive a light emitting control signal.

[0138] The source of the second light emitting control transistor T6 is electrically connected with the drain of the driving transistor T3, the drain of the second light emitting control transistor T6 is electrically connected with a first electrode of the light emitting device F, and the gate of the second light emitting control transistor T6 is configured to be electrically connected with the light emitting control signal line EM to receive the light emitting control signal.

[0139] The source of the second reset transistor T7 is configured to be electrically connected with an initialization signal line Vinit to receive an initialization signal, the drain of the second reset transistor T7 is electrically connected with the first electrode of the light emitting device F, and the gate of the second reset transistor T7 is configured to be electrically connected with a second reset control signal line Reset2 to receive a reset control signal.

[0140] The source of the third reset transistor T8 is configured to be electrically connected with the initialization signal line Vinit to receive the initialization signal, the drain of the third reset transistor T8 is electrically connected with the source of the driving transistor T3, and the gate of the third reset transistor T8 is configured to be electrically connected with the second reset control signal line Reset2 to receive the reset control signal.

[0141] The second electrode of the light emitting device F is electrically connected with a second voltage signal line VSS.

[0142] The first scan signal line Ngate is configured to transmit a first scan signal, the second scan signal line Pgate is configured to transmit a second scan signal, the first reset control signal line Reset1 is configured to transmit a first reset control signal, the second reset control signal line Reset2 is configured to transmit a second reset control signal, the first voltage signal line VDD is configured to transmit a first voltage signal, for example, a high voltage direct current signal, the initialization signal line Vinit is configured to transmit an initialization signal, the data signal line Data is configured to transmit a data signal, the light emitting control signal line EM is configured to transmit a light emitting control signal, and the second voltage signal line VSS is configured to transmit a second voltage signal, for example, a low voltage direct current signal.

[0143] In some embodiments, referring to FIG. 4, the driving process of the pixel circuit 9a in the sub-pixel 9 driving the light emitting device F in the sub-pixel 9 to emit light can include a first reset stage t1, a data refresh and compensation stage t2, a second reset stage t3, and a light emitting stage t4.

[0144] In the first reset stage t1, the threshold compensation transistor T2 is turned on under the control of the first scan signal transmitted by the first scan signal line Ngate, and the first reset transistor T1 is turned on under the control of the first reset control signal transmitted by the first reset control signal line Reset1, so that the initialization signal transmitted by the initialization signal line Vinit is written to the first node N1, and the first node N1 is reset.

[0145] At this time, the driving transistor T3 is turned on, the write transistor T4, the first light emitting control transistor T5, and the second light emitting control transistor T6 are all in an off state, and the light emitting device F does not emit light.

[0146] In the data refresh and compensation stage t2, the first reset transistor T1 is turned off under the control of the first reset control signal transmitted by the first reset control signal line Reset1, the threshold compensation transistor T2 remains in the on state, the write transistor T4 is turned on under the control of the second scan signal transmitted by the second scan signal line Pgate, and the driving transistor T3 maintains the on state in the first reset stage t1. Therefore, the data signal transmitted by the data signal line Data can be transmitted to the first node N1 through the write transistor T4, the driving transistor T3, and the threshold compensation transistor T2 in sequence, so that the voltage of the first node N1 changes until the voltage of the first node N1 reaches the sum of the threshold voltage of the driving transistor T3 and the voltage of the data signal line Data, so that the driving transistor T3 is turned off. In the data refresh and compensation stage t2, the threshold voltage of the driving transistor T3 can be written to the first node N1 to compensate for the threshold voltage drift of the driving transistor T3, avoid changes in the driving signal generated by the driving transistor T3, and avoid affecting the light emitting intensity of the light emitting device F. In this stage, the first light emitting control transistor T5 and the second light emitting control transistor T6 are in an off state under the control of the light emitting control signal transmitted by the light emitting control signal line EM.

[0147] In the second reset stage t3, the compensation transistor T2 is turned off under the control of the first scan signal transmitted by the first scan signal line Ngate, the write transistor T4 is turned off under the control of the second scan signal transmitted by the second scan signal line Pgate, the second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal transmitted by the second reset control signal line Reset2, and thus the initialization signal transmitted by the initialization signal line Vinit is written into the second node N2 and the anode of the light emitting device F, and thus the second node N2 and the anode of the light emitting device F (the fourth node N4) are reset.

[0148] In the light emitting stage t4, the second reset transistor T7 and the third reset transistor T8 are turned off under the control of the second reset control signal transmitted by the second reset control signal line Reset2, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal transmitted by the light emitting control signal line EM, and thus the first voltage signal transmitted by the first voltage signal line VDD is written into the first electrode region of the driving transistor T3, the anode voltage of the light emitting device F can be written into the second electrode region of the driving transistor T3, and thus the driving transistor T3 is turned on, so as to form a path between the first voltage signal line VDD and the light emitting device F, and thus the light emitting device F in the sub-pixel 9 emits light.

[0149] The sub-pixel 9 in the display panel 10 (i.e., the light emitting device F and the pixel circuit 9a in the sub-pixel 9) can be arranged in the film layer structure of the display panel 10, and the film layer structure of the display panel 10 will be described in detail below.

[0150] In some embodiments, please continue to refer to FIG. 2, the display panel 10 includes a substrate 1.

[0151] For example, the substrate 1 can be a glass substrate or a Polymethylmethacrylate (PMMA) substrate, etc.

[0152] Alternatively, the substrate 1 can also be a flexible substrate. For example, the substrate 1 can be a Polyethyleneterephthalate (PET) substrate, a Polyethylenenaphthalatetwoformic acid glycolester (PEN) substrate, or a Polyimide (PI) substrate, etc.

[0153] In some embodiments, please refer to FIG. 2, the display panel 10 further comprises a pixel driving layer 2 and a light emitting device layer 3. The pixel driving layer 2 and the light emitting device layer 3 are located on one side of the substrate 1 and are sequentially stacked in a direction away from the substrate 1. The light emitting device layer 3 is configured to set the light emitting device F in each of the plurality of sub-pixels 9 in the display panel 10. The pixel driving layer 2 is configured to set the pixel circuit 9a in each of the plurality of sub-pixels 9 in the display panel 10. The specific structure of the pixel driving layer 2 will be described in detail below.

[0154] Exemplarily, please refer to FIG. 2, the light emitting device layer 3 comprises a first electrode layer 31, a light emitting functional layer 33 and a second electrode layer 32 which are sequentially stacked in a third direction Z (i.e. the thickness direction of the display device 100). The first electrode layer 31 is configured to set the first electrode 311 of the light emitting device F in each of the plurality of sub-pixels 9, the light emitting functional layer 33 is configured to set the light emitting part 331 of the light emitting device F in each of the plurality of sub-pixels 9, and the second electrode layer 32 is configured to set the second electrode 321 of the light emitting device F in each of the plurality of sub-pixels 9.

[0155] The first electrode layer 31 and the second electrode layer 32 can provide carriers such as electrons and holes to the light emitting functional layer 33, so that the light emitting functional layer 33 emits light. Specifically, the first electrode 311 in the first electrode layer 31 and the second electrode 321 in the second electrode layer 32 can provide carriers such as electrons and holes to the light emitting part 331 in the light emitting functional layer 33, so that the light emitting part 331 in the light emitting functional layer 33 emits light.

[0156] Exemplarily, please refer to FIG. 2, the first electrode layer 31 can be closer to the substrate 1 than the second electrode layer 32.

[0157] In some embodiments, please refer to FIG. 2, the display panel 10 further comprises a pixel definition layer (PDL) 4. The pixel definition layer (PDL) 4 is located on the side of the first electrode layer 31 away from the substrate 1. A plurality of pixel openings are formed in the pixel definition layer (PDL) 4, the pixel openings and the first electrodes 311 in the first electrode layer 31 are correspondingly arranged, and each pixel opening exposes at least a partial region of one first electrode 311. The light emitting part 331 in the light emitting functional layer 33 is arranged in the pixel opening and is electrically connected to the first electrode 311 and the second electrode 321, respectively.

[0158] By exposing at least a partial region of one first electrode 311 in each pixel opening, the pixel definition layer (PDL) 4 can effectively define the actual effective region of the first electrode 311 (i.e. the region where the first electrode 311 is directly electrically connected to the light emitting part 331 in the light emitting functional layer 33), and further define the light emitting region and the light emitting area of the light emitting device F.

[0159] In some embodiments, please refer to FIG. 2, the display panel 10 further comprises a packaging structure 5. The packaging structure 5 is located on the side of the light emitting device layer 3 far away from the substrate 1. The packaging structure 5 is used for packaging the light emitting device layer 3, and plays a role of protecting the light emitting device layer 3 from corrosion caused by external water and oxygen.

[0160] Exemplarily, the packaging structure 5 can comprise an inorganic packaging layer and an organic packaging layer. The material of the inorganic packaging layer is inorganic material, which can be used for blocking water and oxygen. The material of the organic packaging layer is organic material, which can play a role of flat interface, covering defects and stress release.

[0161] The structure of the pixel driving layer 2 is described in detail as follows.

[0162] In some embodiments, as shown in FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5M, 5N and 5O, FIG. 5A is a plan structure diagram of a partial region of the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5B is a plan structure diagram of a partial region of the light shielding layer 21 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5C is a plan structure diagram of a partial region of the first semiconductor layer 22 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5D is a plan structure diagram of a partial region of the first gate layer 23 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5E is a plan structure diagram of a partial region of the light shielding layer 21, the first semiconductor layer 22 and the first gate layer 23 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIGS. 5F, 5G and 5H are all plan structure diagrams of a partial region of the second gate layer 24 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5I is a plan structure diagram of a partial region of the second semiconductor layer 25 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5J is a plan structure diagram of a partial region of the third gate layer 26 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5K is a plan structure diagram of a partial region of the interlayer dielectric layer 27 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5L is a plan structure diagram of a partial region of the first source-drain conductive layer 28 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5M is a plan structure diagram of a partial region of the third gate layer 26 and the first source-drain conductive layer 28 in the pixel driving layer 2 within the display panel 10 according to some embodiments, FIG. 5N is a plan structure diagram of a partial region of the first gate layer 23, the third gate layer 26 and the first source-drain conductive layer 28 in the pixel driving layer 2 within the display panel 10 according to some embodiments, and FIG. 5O is a plan structure diagram of a partial region of the second gate layer 24 and the first source-drain conductive layer 28 in the pixel driving layer 2 within the display panel 10 according to some embodiments.

[0163] It should be noted that, in order to expose the part of the pixel driving layer 2 in the display panel 10 located on the side of the first source-drain conductive layer 28 close to the substrate 1 (for example, the light shielding layer 21, the first semiconductor layer 22, the first gate layer 23, the second gate layer 24, the second semiconductor layer 25, the third gate layer 26, and the interlayer dielectric layer 27, etc.), the respective film layers in the pixel driving layer 2 in the display panel 10 are transparentized in FIG. 5A, the first semiconductor layer 22 and the first gate layer 23 in the pixel driving layer 2 in the display panel 10 are transparentized in FIG. 5E, the first source-drain conductive layer 28 in the pixel driving layer 2 in the display panel 10 is transparentized in FIG. 5M and FIG. 5O, and the third gate layer 26 and the first source-drain conductive layer 28 in the pixel driving layer 2 in the display panel 10 are transparentized in FIG. 5N.

[0164] The pixel driving layer 2 in the display panel 10 includes the light shielding layer 21, the first semiconductor layer 22, the first gate layer 23, the second gate layer 24, the second semiconductor layer 25, the third gate layer 26, the interlayer dielectric layer 27, and the first source-drain conductive layer 28. The light shielding layer 21, the first semiconductor layer 22, the first gate layer 23, the second gate layer 24, the second semiconductor layer 25, the third gate layer 26, the interlayer dielectric layer 27, and the first source-drain conductive layer 28 are sequentially stacked in the direction away from the substrate 1. That is, the light shielding layer 21 is closer to the substrate 1 than the first source-drain conductive layer 28.

[0165] It should be noted that, in FIG. 5A, only the light shielding layer 21, the first semiconductor layer 22, the first gate layer 23, the second gate layer 24, the second semiconductor layer 25, the third gate layer 26, the interlayer dielectric layer 27, and the first source-drain conductive layer 28 in the pixel driving layer 2 are shown, and other film layers in the pixel driving layer 2 are omitted, for example, the gate insulating layer between the first semiconductor layer 22 and the first gate layer 23, the gate insulating layer between the first gate layer 23 and the second gate layer 24, the gate insulating layer between the second gate layer 24 and the second semiconductor layer 25, and the second source-drain conductive layer on the side of the first source-drain conductive layer 28 away from the substrate 1, etc.

[0166] In some embodiments, please continue to refer to FIG. 5B, and in combination with FIG. 2, since the pixel driving layer 2 is located on one side of the substrate 1, the light shielding layer 21 (i.e., the Bottom Shelter Metal (BSM) layer) in the pixel driving layer 2 is also located on one side of the substrate 1.

[0167] Exemplarily, the material of the light shielding layer 21 in the pixel driving layer 2 can include metal. For example, the material of the light shielding layer 21 in the pixel driving layer 2 can include metal materials such as molybdenum (Mo) and the like.

[0168] Please continue to refer to FIG. 5B, the light shielding layer 21 in the pixel driving layer 2 can include a plurality of first signal lines 211. The first signal lines 211 extend along the first direction Y.

[0169] Exemplarily, the first signal lines 211 in the light shielding layer 21 can be configured to transmit direct current signals.

[0170] For example, the first signal lines 211 in the light shielding layer 21 can be configured to transmit one of the direct current signals such as a VDD voltage signal, a VSS voltage signal, and an initialization signal.

[0171] Please continue to refer to FIG. 5B, the light shielding layer 21 in the pixel driving layer 2 can also include a plurality of third signal lines 212. The third signal lines 212 extend along the second direction X.

[0172] The third signal lines 212 can include a plurality of light shielding patterns 212a and a plurality of first connection portions 212b, and two adjacent light shielding patterns 212a in the third signal lines 212 are connected through the first connection portions 212b.

[0173] Exemplarily, please continue to refer to FIG. 5B, the plurality of third signal lines 212 in the light shielding layer 21 and the plurality of first signal lines 211 in the light shielding layer 21 are connected to each other.

[0174] For example, the plurality of light shielding patterns 212a in the plurality of third signal lines 212 in the light shielding layer 21 can be connected to the plurality of first signal lines 211 in the light shielding layer 21.

[0175] It can be understood that, in the case that the plurality of third signal lines 212 in the light shielding layer 21 and the plurality of first signal lines 211 in the light shielding layer 21 are connected to each other, the signals transmitted by the third signal lines 212 in the light shielding layer 21 are the same as the signals transmitted by the first signal lines 211 in the light shielding layer 21. That is, when the first signal lines 211 in the light shielding layer 21 are configured to transmit direct current signals (for example, VDD voltage signals, VSS voltage signals, or initialization signals, and the like), the third signal lines 212 in the light shielding layer 21 are configured to transmit direct current signals (for example, VDD voltage signals, VSS voltage signals, or initialization signals, and the like).

[0176] By connecting the plurality of third signal lines 212 in the light shielding layer 21 and the plurality of first signal lines 211 in the light shielding layer 21 to each other, the signal lines (i.e., the third signal lines 212 and the first signal lines 211) in the light shielding layer 21 are arranged in a grid shape, and the first signal lines 211 and the third signal lines 212 in the light shielding layer 21 are both configured to transmit direct current signals (for example, VDD voltage signals, VSS voltage signals, or initialization signals, and the like), which can shield external electromagnetic interference and prevent the pixel circuit 9a from being damaged by electrostatic discharge.

[0177] In some embodiments, referring to FIG. 5C, the first semiconductor layer 22 in the pixel driving layer 2 can be used to set the active layer pattern of at least part of the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the pixel circuit 9a.

[0178] The active layer pattern of the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the pixel circuit 9a can each include a source region, a drain region, and a channel region between the source region and the drain region.

[0179] Illustratively, referring to FIG. 5C, the first semiconductor layer 22 can be provided with the active layer pattern T11 of the first reset transistor T1, the active layer pattern T31 of the driving transistor T3, the active layer pattern T41 of the data writing transistor T4, the active layer pattern T51 of the first light emitting control transistor T5, the active layer pattern T61 of the second light emitting control transistor T6, the active layer pattern T71 of the second reset transistor T7, and the active layer pattern T81 of the third reset transistor T8.

[0180] Referring to FIG. 5C, the active layer pattern T31 of the driving transistor T3 is taken as an example, the active layer pattern T31 of the driving transistor T3 can include a source region T31a, a drain region T31b, and a channel region T31c between the source region T31a and the drain region T31b.

[0181] Illustratively, the material of the first semiconductor layer 22 can be low-temperature polysilicon.

[0182] Alternatively, the material of the first semiconductor layer 22 can also be any one of indium gallium zinc oxide (IGZO) and low-temperature polysilicon oxide. For example, the material of the first semiconductor layer 22 can be indium gallium zinc oxide (IGZO). For another example, the material of the first semiconductor layer 22 can be indium gallium zinc tin oxide (IGZTO).

[0183] It can be understood that when the material of the first semiconductor layer 22 is low-temperature polysilicon, the transistors (e.g., the first reset transistor T1, the driving transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the active layer pattern located in the first semiconductor layer 22 are low-temperature polysilicon thin film transistors.

[0184] When the material of the first semiconductor layer 22 is any one of indium gallium zinc oxide and low-temperature polycrystalline oxide, the transistors (e.g., the first reset transistor T1, the driving transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the active layer pattern located in the first semiconductor layer 22 are oxide thin film transistors.

[0185] Hereinafter, some embodiments of the present disclosure are schematically described by taking the material of the first semiconductor layer 22 as low-temperature polysilicon, and the transistors (e.g., the first reset transistor T1, the driving transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the active layer pattern located in the first semiconductor layer 22 as low-temperature polysilicon thin film transistors as examples.

[0186] Exemplarily, the first semiconductor layer 22 can be obtained by a quasi-molecular laser annealing process.

[0187] Alternatively, the first semiconductor layer 22 can also be obtained by a physical vapor deposition (PVD) process.

[0188] In some embodiments, please continue to refer to FIG. 5D, and in combination with FIG. 5A, the first gate layer 23 in the pixel driving layer 2 is located between the light shielding layer 21 in the pixel driving layer 2 and the first source-drain conductive layer 28 in the pixel driving layer 2.

[0189] Exemplarily, the first gate layer 23 can be obtained by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) by a PVD process.

[0190] Please continue to refer to FIG. 5D, the first gate layer 23 in the pixel driving layer 2 can be used to set the gate pattern of at least part of the transistors in the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the pixel circuit 9a, the storage capacitor C, and the signal line, etc.

[0191] Exemplarily, please continue to refer to FIG. 5D, the first gate layer 23 can be provided with the gate pattern T12 of the first reset transistor T1, the gate pattern T32 of the driving transistor T3, the gate pattern T42 of the data writing transistor T4, the gate pattern T52 of the first light emitting control transistor T5, the gate pattern T62 of the second light emitting control transistor T6, the gate pattern T72 of the second reset transistor T7, and the gate pattern T82 of the third reset transistor T8.

[0192] Please continue to refer to FIG. 5D, and in combination with FIG. 5E, it can be understood that the gate patterns of the transistors (i.e., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the first gate layer 23 correspond to the channel regions of the active layer patterns of the transistors (i.e., the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the first semiconductor layer 22.

[0193] Taking the driving transistor T3 as an example, the gate pattern T32 of the driving transistor T3 in the first gate layer 23 and the channel region T31c in the active layer pattern T31 of the driving transistor T3 in the first semiconductor layer 22 correspond to each other, that is, the normal projection of the gate pattern T32 of the driving transistor T3 on the substrate 1 and the normal projection of the channel region T31c in the active layer pattern T31 of the driving transistor T3 on the substrate 1 coincide.

[0194] Exemplarily, please continue to refer to FIG. 5D, the first gate layer 23 can be further provided with the second scan signal line Pgate, the first reset control signal line Reset1, the second reset control signal line Reset2, and the light emitting control signal line EM, etc.

[0195] For example, in the case where the first gate layer 23 is provided with the second scan signal line Pgate, the first reset control signal line Reset1, the second reset control signal line Reset2, and the light emitting control signal line EM, the second scan signal line Pgate, the first reset control signal line Reset1, the second reset control signal line Reset2, and the light emitting control signal line EM in the first gate layer 23 can all extend along the second direction X.

[0196] Exemplarily, please continue to refer to FIG. 5D, the first gate layer 23 can be further provided with the first plate C1 of the storage capacitor C. In some examples, the gate pattern T32 of the driving transistor T3 simultaneously serves as the first plate C1 of the storage capacitor C.

[0197] Exemplarily, please continue to refer to FIG. 5E, the orthographic projection of the first plate C1 of the storage capacitor C on the substrate 1 and the orthographic projection of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 on the substrate 1 at least partially coincide.

[0198] It should be noted that, in FIG. 5E, only the case that the orthographic projection of the first plate C1 of the storage capacitor C on the substrate 1 and the orthographic projection of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 on the substrate 1 completely coincide is exemplarily used to schematically describe some embodiments of the present disclosure. However, the relative positional relationship between the first plate C1 of the storage capacitor C and the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 in the present disclosure includes but is not limited to this, for example, the orthographic projection of the first plate C1 of the storage capacitor C on the substrate 1 and the orthographic projection of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 on the substrate 1 can partially coincide. For another example, the orthographic projection of the first plate C1 of the storage capacitor C on the substrate 1 can be located within the range of the orthographic projection of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 on the substrate 1.

[0199] By making the orthographic projection of the first plate C1 of the storage capacitor C on the substrate 1 and the orthographic projection of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 on the substrate 1 at least partially coincide, on the one hand, in the case that the gate pattern T32 of the driving transistor T3 simultaneously serves as the first plate C1 of the storage capacitor C, when the orthographic projection of the first plate C1 of the storage capacitor C on the substrate 1 and the orthographic projection of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 on the substrate 1 at least partially coincide, the orthographic projection of the gate pattern T32 of the driving transistor T3 on the substrate 1 and the orthographic projection of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 on the substrate 1 also at least partially coincide.

[0200] Since the orthogonal projection of the gate pattern T32 of the driving transistor T3 on the substrate 1 and the orthogonal projection of the channel region T31c within the active layer pattern T31 of the driving transistor T3 on the substrate 1 coincide, the orthogonal projection of the channel region T31c within the active layer pattern T31 of the driving transistor T3 on the substrate 1 and the orthogonal projection of the light-shielding pattern 212a within the third signal line 212 within the light-shielding layer 21 on the substrate 1 at least partially coincide, so that the light-shielding pattern 212a within the third signal line 212 within the light-shielding layer 21 can shield the light rays of external illumination from the channel region T31c within the active layer pattern T31 of the driving transistor T3, so that it is difficult for the light rays to illuminate the channel region T31c within the active layer pattern T31 of the driving transistor T3, avoiding the performance change of the driving transistor T3 due to light illumination, preventing the degradation and leakage current of the driving transistor T3 due to light illumination, ensuring the normal work of the driving transistor T3, and further ensuring the normal display of the display panel 10.

[0201] On the other hand, the first plate C1 of the storage capacitor C and the light-shielding pattern 212a within the third signal line 212 within the light-shielding layer 21 can also form a storage capacitor, which can increase the storage capacitance within the pixel circuit 9a, and further ensure the voltage of the pixel circuit 9a to be stable, which is beneficial to reduce the risk of flicker and the probability of crosstalk of the display panel 10.

[0202] In some embodiments, please continue to refer to FIG. 5F, and combine with FIG. 5A, the second gate layer 24 within the pixel driving layer 2 is located between the light-shielding layer 21 and the first source-drain conductive layer 28 within the pixel driving layer 2.

[0203] For example, the second gate layer 24 can be deposited by a PVD process to obtain a metal material such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper).

[0204] Please continue to refer to FIG. 5F, the second gate layer 24 within the pixel driving layer 2 can be used to set the storage capacitor C in the pixel circuit 9a, and the signal line and the like.

[0205] For example, please continue to refer to FIG. 5F, the second gate layer 24 can be provided with the first scanning signal line Ngate.

[0206] For example, in the case that the second gate layer 24 is provided with the first scanning signal line Ngate, the first scanning signal line Ngate within the second gate layer 24 can extend along the second direction X.

[0207] For example, please continue to refer to FIG. 5F, the second gate layer 24 can also be provided with the second plate C2 of the storage capacitor C.

[0208] Exemplarily, please continue to refer to FIG. 5G and FIG. 5H, the second gate layer 24 in the pixel driving layer 2 further comprises a third connecting part 241. The third connecting part 241 is connected between the second plates C2 of the storage capacitors C in two pixel circuits 9a adjacent in the second direction X.

[0209] For example, please continue to refer to FIG. 5G, the second plates C2 of the storage capacitors C in the plurality of pixel circuits 9a arranged in the second direction X comprise a plurality of second plate pairs CD, one second plate pair CD comprises two adjacent second plates C2. The two second plates C2 belonging to one second plate pair CD are connected through the third connecting part 241 in the second gate layer 24, and the two second plates C2 belonging to different second plate pairs CD and adjacent in the second direction X are arranged at intervals. That is, among the second plates C2 of the storage capacitors C in the plurality of pixel circuits 9a arranged in the second direction X, there are two adjacent second plates C2 that are not connected through the third connecting part 241 in the second gate layer 24.

[0210] For another example, please continue to refer to FIG. 5H, among the second plates C2 of the storage capacitors C in the plurality of pixel circuits 9a arranged in the second direction X, any two adjacent second plates C2 are connected through the third connecting part 241 in the second gate layer 24. That is, among the second plates C2 of the storage capacitors C in the plurality of pixel circuits 9a arranged in the second direction X, there are no two adjacent second plates C2 arranged at intervals.

[0211] In some embodiments, please continue to refer to FIG. 5I, the second semiconductor layer 25 in the pixel driving layer 2 can be used to set the active layer pattern of at least part of the transistors T1-T8 (i.e. the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) in the pixel circuit 9a.

[0212] Exemplarily, please continue to refer to FIG. 5I, the second semiconductor layer 25 can be provided with the active layer pattern T21 of the threshold compensation transistor T2. The active layer pattern T21 of the threshold compensation transistor T2 comprises a source region T21a, a drain region T21b, and a channel region T21c between the source region T21a and the drain region T21b.

[0213] Exemplarily, the material of the second semiconductor layer 25 can be low-temperature polysilicon.

[0214] Alternatively, the material of the second semiconductor layer 25 can also be any one of indium gallium zinc oxide and low temperature polycrystalline oxide. For example, the material of the second semiconductor layer 25 can be indium gallium zinc oxide (IGZO). For another example, the material of the second semiconductor layer 25 can be indium gallium zinc tin oxide (IGZTO).

[0215] It can be understood that when the material of the second semiconductor layer 25 is low temperature polycrystalline silicon, the transistor (for example, the threshold compensation transistor T2) of the active layer pattern located in the second semiconductor layer 25 is a low temperature polycrystalline silicon thin film transistor.

[0216] When the material of the second semiconductor layer 25 is any one of indium gallium zinc oxide and low temperature polycrystalline oxide, the transistor (for example, the threshold compensation transistor T2) of the active layer pattern located in the second semiconductor layer 25 is an oxide thin film transistor.

[0217] Hereinafter, some embodiments of the present disclosure are schematically described with the material of the second semiconductor layer 25 being any one of indium gallium zinc oxide and low temperature polycrystalline oxide, and the transistor (for example, the threshold compensation transistor T2) of the active layer pattern located in the second semiconductor layer 25 being an oxide thin film transistor as an example.

[0218] It can be understood that, please continue to refer to FIGS. 5C and 5I, when the material of the first semiconductor layer 22 is low temperature polycrystalline silicon, the transistor (for example, the first reset transistor T1, the driving transistor T3, the data write transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8) of the active layer pattern located in the first semiconductor layer 22 is a low temperature polycrystalline silicon thin film transistor, and the material of the second semiconductor layer 25 is any one of indium gallium zinc oxide and low temperature polycrystalline oxide, the transistor (for example, the threshold compensation transistor T2) of the active layer pattern located in the second semiconductor layer 25 is an oxide thin film transistor, the pixel circuit 9a in the display panel 10 simultaneously includes a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor, and a low temperature polycrystalline oxide (LTPO) display panel can be formed.

[0219] Exemplarily, the second semiconductor layer 25 can be obtained by a quasi-molecular laser annealing process.

[0220] Alternatively, the second semiconductor layer 25 can also be obtained by a physical vapor deposition (PVD) process.

[0221] In some embodiments, please refer to FIG. 5J, and in combination with FIG. 5A, the third gate layer 26 in the pixel driving layer 2 is located between the light shielding layer 21 and the first source-drain conductive layer 28 in the pixel driving layer 2.

[0222] Exemplarily, the third gate layer 26 can be deposited by a physical vapor deposition (PVD) process to obtain a metal material such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper).

[0223] Please refer to FIG. 5J, the third gate layer 26 in the pixel driving layer 2 can be used to set the gate pattern of at least part of the transistors T1-T8 (i.e., the first reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8) in the pixel circuit 9a, and a signal line, etc.

[0224] Exemplarily, please refer to FIG. 5H, the third gate layer 26 can be provided with the gate pattern T22 of the threshold compensation transistor T2.

[0225] The third gate layer 26 can also be provided with an initialization signal line Vinit.

[0226] Exemplarily, please refer to FIG. 5J, in the case that the third gate layer 26 is provided with the initialization signal line Vinit, the initialization signal line Vinit in the third gate layer 26 can extend along the second direction X.

[0227] In some embodiments, please refer to FIG. 5K, the interlayer dielectric layer 27 in the pixel driving layer 2 can be provided with a plurality of vias K. Along the third direction Z (i.e., the thickness direction of the display device 100), the conductive layers (e.g., the third gate layer 26 and the first source-drain conductive layer 28, etc.) located on the opposite sides of the interlayer dielectric layer 27 in the pixel driving layer 2 can be electrically connected through the vias K in the interlayer dielectric layer 27.

[0228] Exemplarily, the material of the interlayer dielectric layer 27 can be any one of silicon nitride, silicon oxide, or silicon oxynitride, or a combination of any of the materials, which can be deposited by a PECVD process.

[0229] In some embodiments, please refer to FIG. 5L, and in combination with FIG. 5A, the first source-drain conductive layer 28 in the pixel driving layer 2 is located on the side of the light shielding layer 21 in the pixel driving layer 2 away from the substrate 1.

[0230] Exemplarily, the first source-drain conductive layer 28 can be deposited by a PVD (Physical Vapor Deposition) process to obtain a metal material such as MO / Ti / Al / Cu.

[0231] Please continue to refer to FIG. 5L, the first source-drain conductive layer 28 includes a plurality of second signal lines 281, and the second signal lines 281 can extend along the first direction Y.

[0232] Exemplarily, the second signal lines 281 in the first source-drain conductive layer 28 can be configured to transmit a direct current signal.

[0233] For example, the second signal lines 281 in the first source-drain conductive layer 28 can be configured to transmit one of a VDD voltage signal, a VSS voltage signal, and an initialization signal.

[0234] Please continue to refer to FIG. 5M, and combine FIG. 5H and FIG. 5J, in the case that the second signal lines 281 in the first source-drain conductive layer 28 are configured to transmit an initialization signal, since the plurality of initialization signal lines Vinit in the third gate layer 26 are also configured to transmit an initialization signal, that is, the second signal lines 281 in the first source-drain conductive layer 28 and the plurality of initialization signal lines Vinit in the third gate layer 26 are both configured to transmit an initialization signal, the plurality of second signal lines 281 in the first source-drain conductive layer 28 can be connected with the plurality of initialization signal lines Vinit in the third gate layer 26, so that the plurality of second signal lines 281 in the first source-drain conductive layer 28 extending along the first direction Y and the plurality of initialization signal lines Vinit in the third gate layer 26 extending along the second direction X form a mesh connection structure.

[0235] By making the plurality of second signal lines 281 in the first source-drain conductive layer 28 and the plurality of initialization signal lines Vinit in the third gate layer 26 form a mesh connection structure, and the initialization signal is dispersedly transmitted through the mesh connection structure, the pressure drop of the initialization signal on the transmission path can be reduced, the uniformity of the initialization signal is improved, so as to further improve the display uniformity, and avoid the display panel 10 from generating display defects such as horizontal lines.

[0236] Exemplarily, please continue to refer to FIG. 5L, the first source-drain conductive layer 28 in the pixel driving layer 2 further includes a second connection part 282.

[0237] Please continue to refer to FIG. 5N, the source or drain of the threshold compensation transistor T2 in the pixel circuit 9a is connected with the first plate C1 of the storage capacitor C through the second connection part 282 in the first source-drain conductive layer 28.

[0238] It can be understood that when the threshold compensation transistor T2 is an N-type transistor, the source of the threshold compensation transistor T2 in the pixel circuit 9a is connected with the first plate C1 of the storage capacitor C through the second connecting portion 282 in the first source-drain conductive layer 28, specifically, the source region T21a of the active layer pattern T21 of the threshold compensation transistor T2 in the second semiconductor layer 25 is connected with the first plate C1 of the storage capacitor C through the second connecting portion 282 in the first source-drain conductive layer 28 (Fig. 5N shows this case).

[0239] When the threshold compensation transistor T2 is a P-type transistor, the drain of the threshold compensation transistor T2 in the pixel circuit 9a is connected with the first plate C1 of the storage capacitor C through the second connecting portion 282 in the first source-drain conductive layer 28. Specifically, the drain region T21b of the active layer pattern T21 of the threshold compensation transistor T2 in the second semiconductor layer 25 is connected with the first plate C1 of the storage capacitor C through the second connecting portion 282 in the first source-drain conductive layer 28.

[0240] Exemplarily, please continue to refer to Fig. 5L, the first source-drain conductive layer 28 in the pixel driving layer 2 further comprises a plurality of fourth connecting portions 283.

[0241] Please continue to refer to Fig. 5O, the second plate C2 of the storage capacitor C in the pixel circuit 9a and the first voltage signal line VDD (not shown in the figure) can be connected through the fourth connecting portion 283 in the first source-drain conductive layer 28.

[0242] For example, in the case that the second gate layer 24 in the pixel driving layer 2 comprises a plurality of third connecting portions 241, and the third connecting portions 241 are connected between the second plates C2 of the storage capacitors C in two pixel circuits 9a adjacent in the second direction X, the first voltage signal line VDD is first connected through the fourth connecting portion 283 in the first source-drain conductive layer 28 and the third connecting portion 241 in the second gate layer 24, and then the third connecting portion 241 in the second gate layer 24 is connected to the second plate C2 of the storage capacitor C in the pixel circuit 9a, so as to realize the electrical connection between the first voltage signal line VDD and the second plate C2 of the storage capacitor C in the pixel circuit 9a.

[0243] The first voltage signal line VDD can be arranged in the second source-drain conductive layer (not shown in the figure) in the pixel driving layer 2.

[0244] In some embodiments, please refer to FIG. 5A and FIG. 2, and combine FIG. 5B, FIG. 5C, FIG. 5D, FIG. 5E, FIG. 5F, FIG. 5G, FIG. 5H, FIG. 5I, FIG. 5J, FIG. 5K, FIG. 5L, FIG. M, FIG. 5N and FIG. 5O, when the optical element 20 (e.g., a camera, an under-screen fingerprint identification sensor or the like) in the display device 100 is working, external light needs to pass through the display panel 10 to irradiate on the optical element 20 (e.g., a camera, an under-screen fingerprint identification sensor or the like), the external light is easily blocked by the light shielding layer 21 in the pixel driving layer 2 and other conductive film layers (e.g., the first gate layer 23, the second gate layer 24, the third gate layer 26 and the first source-drain conductive layer 28, etc.) in the pixel driving layer 2 in the display panel 10, the loss of the external light is large, the light transmittance of the display panel 10 (i.e., the light transmittance) is low, the light collection amount of the optical element 20 (e.g., a camera, an under-screen fingerprint identification sensor or the like) is small, and the performance of the optical element 20 (e.g., a camera, an under-screen fingerprint identification sensor or the like) is easily affected. For example, when the optical element 20 is a camera, the photographing quality of the camera may be reduced. For another example, when the optical element 20 is a fingerprint identification sensor, the accuracy of the fingerprint identification of the fingerprint identification sensor may be reduced.

[0245] Based on this, in some embodiments, as shown in FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D and FIG. 6E, FIG. 6A is a planar structural view of a partial region of the pixel driving layer 2 in the display panel 10 according to some embodiments, FIG. 6B is a planar structural view of a partial region of the light shielding layer 21 in the pixel driving layer 2 in the display panel 10 according to some embodiments, and FIG. 6C, FIG. 6D and FIG. 6E are planar structural views of a partial region of the light shielding layer 21 and the first source-drain conductive layer 28 in the pixel driving layer 2 in the display panel 10 according to some embodiments. It should be noted that in order to expose the partial film layers (e.g., the light shielding layer 21, the first semiconductor layer 22, the first gate layer 23, the second gate layer 24, the second semiconductor layer 25, the third gate layer 26 and the interlayer dielectric layer 27, etc.) in the pixel driving layer 2 in the display panel 10 which are located on the side of the first source-drain conductive layer 28 close to the substrate 1, the transparent treatment is performed on each film layer in the pixel driving layer 2 in the display panel 10 in FIG. 6A, and the transparent treatment is performed on the first source-drain conductive layer 28 in the pixel driving layer 2 in the display panel 10 in FIG. 6C, FIG. 6D and FIG. 6E.

[0246] In the display area AA of the display panel 10, the orthogonal projection of the first signal line 211 in the light shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 at least partially overlap.

[0247] By making the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 at least partially coincide, that is, the second signal line 281 in the first source-drain conductive layer 28 at least covers part of the first signal line 211 in the light-shielding layer 21, in the orthogonal projection facing the substrate 1, the total area ratio of the light-shielding layer 21 in the pixel driving layer 2 and the first source-drain conductive layer 28 in the pixel driving layer 2 can be reduced, and thus the blocking of the light-shielding layer 21 in the pixel driving layer 2 and the first source-drain conductive layer 28 in the pixel driving layer 2 to external light can be weakened, that is, in the orthogonal projection facing the substrate 1, the area ratio of the light-shielding area of the display panel 10 can be reduced, and the area ratio of the light-transmitting area of the display panel 10 can be increased, and thus the light transmittance (i.e., light transmissivity) of the display panel 10 can be improved.

[0248] Please continue to refer to FIGS. 6A, 6C, 6D and 6E, and combine FIG. 2. By improving the light transmittance (i.e., light transmissivity) of the display panel 10, when the optical element 20 (e.g., a camera, an under-screen fingerprint recognition sensor, or the like) in the display device 100 is working, the amount of loss of external light can be reduced when the external light transmits through the display panel 10 and irradiates on the optical element 20 (e.g., a camera, an under-screen fingerprint recognition sensor, or the like), so that the amount of loss of external light is relatively small, and thus the amount of light collection of the optical element 20 (e.g., a camera, an under-screen fingerprint recognition sensor, or the like) is relatively large, which is beneficial to optimizing the performance of the optical element 20 (e.g., a camera, an under-screen fingerprint recognition sensor, or the like). For example, when the optical element 20 is a camera, the photographing quality of the camera can be improved. For another example, when the optical element 20 is a fingerprint recognition sensor, the accuracy of fingerprint recognition of the fingerprint recognition sensor can be improved.

[0249] Exemplarily, please continue to refer to FIG. 6C. In the display area AA of the display panel 10, the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 partially coincide.

[0250] By partially overlapping the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1, that is, by covering the first signal line 211 in the light-shielding layer 21 by the second signal line 281 in the first source-drain conductive layer 28, the area ratio of the light-shielding layer 21 in the pixel driving layer 2 and the first source-drain conductive layer 28 in the pixel driving layer 2 can be reduced in the orthogonal projection facing the substrate 1, and the blocking of external light by the light-shielding layer 21 in the pixel driving layer 2 and the first source-drain conductive layer 28 in the pixel driving layer 2 can be weakened, that is, the area ratio of the light-shielding area of the display panel 10 can be reduced and the area ratio of the light-transmitting area of the display panel 10 can be increased in the orthogonal projection facing the substrate 1, and the light transmittance (i.e., the light transmission rate) of the display panel 10 can be improved.

[0251] Alternatively, please continue to refer to FIG. 6D. In the display area AA of the display panel 10, the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 completely overlap. That is, the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 overlap, and the size h1 of the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 along the second direction X is the same as the size h2 of the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 along the second direction X.

[0252] Alternatively, please continue to refer to FIG. 6E. In the display area AA of the display panel 10, the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 is located within the range of the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1. That is, the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 overlap, and the size h1 of the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 along the second direction X is smaller than the size h2 of the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 along the second direction X.

[0253] By making the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 completely coincide, or making the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 be located in the range of the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1, that is, the second signal line 281 in the first source-drain conductive layer 28 completely covers the first signal line 211 in the light-shielding layer 21, in the orthogonal projection facing the substrate 1, the area ratio of the light-shielding layer 21 in the pixel driving layer 2 and the first source-drain conductive layer 28 in the pixel driving layer 2 can be further reduced, and the blocking of the light-shielding layer 21 in the pixel driving layer 2 and the first source-drain conductive layer 28 in the pixel driving layer 2 to external light can be further weakened, that is, in the orthogonal projection facing the substrate 1, the area ratio of the light-shielding area of the display panel 10 can be further reduced, and the area ratio of the light-transmitting area of the display panel 10 can be further increased, and the light transmittance (i.e., the light transmittance) of the display panel 10 can be further improved.

[0254] It should be noted that the embodiment shown in FIG. 6A corresponds to the embodiment shown in FIG. 6D, and only the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 in the display area AA of the display panel 10 are taken as examples to illustrate the planar structure diagram of the partial region of the pixel driving layer 2 in the display panel 10 in some embodiments of the present disclosure.

[0255] Exemplarily, please continue to refer to FIGS. 6A, 6C, 6D and 6E, since the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 at least partially coincide in the display area AA of the display panel 10, that is, the second signal line 281 in the first source-drain conductive layer 28 at least covers part of the first signal line 211 in the light-shielding layer 21, when transmitting signals, the second signal line 281 in the first source-drain conductive layer 28 and the first signal line 211 in the light-shielding layer 21 are easy to affect each other, resulting in voltage jump of the second signal line 281 in the first source-drain conductive layer 28 and / or the first signal line 211 in the light-shielding layer 21, which is easy to affect the normal display of the display panel 10.

[0256] Based on this, in the case that the first signal line 211 in the light-shielding layer 21 and the second signal line 281 in the first source-drain conductive layer 28 are both configured to transmit direct-current signals (for example, VDD voltage signals, VSS voltage signals, or initialization signals, etc.), the mutual influence between the second signal line 281 in the first source-drain conductive layer 28 and the first signal line 211 in the light-shielding layer 21 can be reduced, the voltage jumps of the first signal line 211 in the light-shielding layer 21 and the second signal line 281 in the first source-drain conductive layer 28 are avoided as much as possible, the stability of the signals transmitted by the first signal line 211 in the light-shielding layer 21 and the second signal line 281 in the first source-drain conductive layer 28 is improved, and the normal display of the display panel 10 is ensured.

[0257] For example, the first signal line 211 in the light-shielding layer 21 can be configured to transmit VDD voltage signals, and the second signal line 281 in the first source-drain conductive layer 28 can be configured to transmit initialization signals.

[0258] For example, the first signal line 211 in the light-shielding layer 21 can be configured to transmit VDD voltage signals, and the second signal line 281 in the first source-drain conductive layer 28 can be configured to transmit initialization signals.

[0259] In some embodiments, as shown in FIGS. 7 and 8, both FIGS. 7 and 8 are planar structure diagrams of a partial region of the light-shielding layer 21 in the pixel driving layer 2 in the display panel 10 according to some embodiments. It should be noted that the region outlined by the dashed line in FIGS. 7 and 8 is a region of the light-shielding layer 21 corresponding to one pixel circuit 9a.

[0260] Along the second direction X, at least two pixel circuits 9a are arranged between the adjacent two first signal lines 211 in the light-shielding layer 21.

[0261] By arranging at least two pixel circuits 9a between the adjacent two first signal lines 211 in the light-shielding layer 21 along the second direction X, compared with the one-to-one arrangement of the first signal line 211 in the light-shielding layer 21 and the pixel circuit 9a in the embodiment shown in FIG. 5B, the number of the first signal lines 211 in the light-shielding layer 21 along the second direction X can be reduced, the area ratio of the light-shielding layer 21 in the pixel driving layer 2 in the orthographic projection facing the substrate 1 can be reduced, and the blocking of the light-shielding layer 21 in the pixel driving layer 2 to external light can be weakened, that is, in the orthographic projection facing the substrate 1, the area ratio of the light-shielding region of the display panel 10 can be reduced, and the area ratio of the light-transmitting region of the display panel 10 can be increased, and thus the light transmittance (i.e., the light transmission rate) of the display panel 10 is improved.

[0262] For example, along the second direction X, two pixel circuits 9a can be arranged between the adjacent two first signal lines 211 in the light-shielding layer 21.

[0263] Alternatively, along the second direction X, three pixel circuits 9a can be provided between any two adjacent first signal lines 211 within the light-shielding layer 21.

[0264] Alternatively, along the second direction X, four pixel circuits 9a can be provided between any two adjacent first signal lines 211 within the light-shielding layer 21, as shown in FIGS. 7 and 8.

[0265] Alternatively, along the second direction X, five pixel circuits 9a can be provided between any two adjacent first signal lines 211 within the light-shielding layer 21.

[0266] Alternatively, along the second direction X, six pixel circuits 9a can be provided between any two adjacent first signal lines 211 within the light-shielding layer 21.

[0267] Exemplarily, along the second direction X, the number of pixel circuits 9a between any two adjacent first signal lines 211 within the light-shielding layer 21 can be the same.

[0268] For example, along the second direction X, the number of pixel circuits 9a between any two adjacent first signal lines 211 within the light-shielding layer 21 can be two.

[0269] For another example, along the second direction X, the number of pixel circuits 9a between any two adjacent first signal lines 211 within the light-shielding layer 21 can be three.

[0270] For another example, along the second direction X, the number of pixel circuits 9a between any two adjacent first signal lines 211 within the light-shielding layer 21 can be four, as shown in FIGS. 7 and 8.

[0271] For another example, along the second direction X, the number of pixel circuits 9a between any two adjacent first signal lines 211 within the light-shielding layer 21 can be five.

[0272] For another example, along the second direction X, the number of pixel circuits 9a between any two adjacent first signal lines 211 within the light-shielding layer 21 can be six.

[0273] In some embodiments, referring to FIG. 7, the display panel 10 includes a plurality of columns of pixel circuits 9a, each column of pixel circuits 9a including a plurality of pixel circuits 9a arranged at intervals along the first direction Y. That is, the first direction Y is the column direction of the plurality of pixel circuits 9a.

[0274] Along the second direction X, at least two columns of pixel circuits 9a are provided between any two adjacent first signal lines 211 within the light-shielding layer 21.

[0275] It can be understood that, in the case that at least two columns of pixel circuits 9a are arranged between every two adjacent first signal lines 211 in the light-shield layer 21 along the second direction X, the plurality of first signal lines 211 in the light-shield layer 21 extend along the first direction Y and the plurality of third signal lines 212 in the light-shield layer 21 extend along the second direction X, so the plurality of first signal lines 211 in the light-shield layer 21 and the plurality of third signal lines 212 in the light-shield layer 21 cross and connect with each other.

[0276] Exemplarily, two columns of pixel circuits 9a can be arranged between every two adjacent first signal lines 211 in the light-shield layer 21 along the second direction X.

[0277] Alternatively, three columns of pixel circuits 9a can be arranged between every two adjacent first signal lines 211 in the light-shield layer 21 along the second direction X.

[0278] Alternatively, please continue to refer to FIG. 7, four columns of pixel circuits 9a can be arranged between every two adjacent first signal lines 211 in the light-shield layer 21 along the second direction X.

[0279] Alternatively, five columns of pixel circuits 9a can be arranged between every two adjacent first signal lines 211 in the light-shield layer 21 along the second direction X.

[0280] Alternatively, six columns of pixel circuits 9a can be arranged between every two adjacent first signal lines 211 in the light-shield layer 21 along the second direction X.

[0281] In other embodiments, please continue to refer to FIG. 8, the plurality of first signal lines 211 in the light-shield layer 21 in the pixel driving layer 2 are connected between every two adjacent third signal lines 212.

[0282] The plurality of first signal lines 211 in the light-shield layer 21 in the pixel driving layer 2 connected to the same third signal line 212 can be alternatively arranged on both sides of the third signal line 212.

[0283] By alternately arranging the plurality of first signal lines 211 connected to the same third signal line 212 in the light-shielding layer 21 on both sides of the third signal line 212, that is, by staggered arranging the plurality of first signal lines 211 connected to the same third signal line 212 in the light-shielding layer 21 on both sides of the third signal line 212, it is beneficial for the direct current signal (for example, the VDD voltage signal, the VSS voltage signal, or the initialization signal, and the like) to be dispersedly transmitted in the plurality of first signal lines 211 and the plurality of third signal lines 212 in the light-shielding layer 21, which can further reduce the voltage drop of the direct current signal (for example, the VDD voltage signal, the VSS voltage signal, or the initialization signal, and the like) on the transmission path, improve the uniformity of the direct current signal (for example, the VDD voltage signal, the VSS voltage signal, or the initialization signal, and the like), and further shield external electromagnetic interference, further prevent the pixel circuit 9a from being damaged by electrostatic discharge, ensure the normal display of the display panel 10, and improve the display uniformity of the display panel 10.

[0284] Exemplarily, please continue to refer to FIG. 8, the plurality of first signal lines in the light-shielding layer 21 are arranged in alignment along the first direction Y, and among the plurality of first signal lines 211 arranged in alignment in the light-shielding layer 21, every two adjacent first signal lines 211 are arranged in a spaced manner. That is, among the plurality of first signal lines 211 arranged in alignment in the light-shielding layer 21, every two adjacent first signal lines 211 are not connected.

[0285] In some embodiments, as shown in FIGS. 9A and 9B, and in combination with FIGS. 5G and 5H, FIG. 9A is a planar structural view of a partial region of the light-shielding layer 21, the first semiconductor layer 22, and the second gate layer 24 in the pixel driving layer 2 in the display panel 10 according to some embodiments, and FIG. 9B is a planar structural view of a partial region of the light-shielding layer 21 and the second gate layer 24 in the pixel driving layer 2 in the display panel 10 according to some embodiments. It should be noted that, in order to facilitate the description of the embodiments shown in FIGS. 9A and 9B, the first semiconductor layer 22 and the second gate layer 24 in FIG. 9A are transparentized, and the second gate layer 24 in FIG. 9B is transparentized to expose the light-shielding layer 21 in the pixel driving layer 2 in the display panel 10.

[0286] In the case where the second gate layer 24 comprises the third connection part 241, the orthogonal projection of the at least one first connection part 212b in the third signal line 212 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the at least one third connection part 241 in the second gate layer 24 on the substrate 1 at least partially overlap.

[0287] By at least partially overlapping the orthographic projection of the at least one first connection portion 212b in the third signal line 212 in the light-shielding layer 21 on the substrate 1 and the orthographic projection of the at least one third connection portion 241 in the second gate layer 24 on the substrate 1, that is, the at least one third connection portion 241 in the second gate layer 24 covers at least a partial region of the at least one first connection portion 212b in the third signal line 212 in the light-shielding layer 21, in the orthographic projection facing the substrate 1, the total area ratio of the light-shielding layer 21 in the pixel driving layer 2 and the second gate layer 24 in the pixel driving layer 2 can be reduced, and thus the blocking of external light by the light-shielding layer 21 in the pixel driving layer 2 and the second gate layer 24 in the pixel driving layer 2 can be weakened, that is, in the orthographic projection facing the substrate 1, the area ratio of the light-shielding region of the display panel 10 can be reduced, and the area ratio of the light-transmitting region of the display panel 10 can be increased, and thus the light transmittance (i.e., the light transmission rate) of the display panel 10 can be improved.

[0288] Please continue to refer to FIGS. 9A and 9B, and combine FIG. 2. By improving the light transmittance (i.e., the light transmission rate) of the display panel 10, when the optical element 20 (for example, a camera, an under-screen fingerprint recognition sensor, or the like) in the display device 100 is working, the loss amount of external light can be reduced when the external light transmits through the display panel 10 and irradiates on the optical element 20 (for example, a camera, an under-screen fingerprint recognition sensor, or the like), so that the loss amount of external light is relatively small, and thus the light collection amount of the optical element 20 (for example, a camera, an under-screen fingerprint recognition sensor, or the like) is relatively large, which is beneficial to optimizing the performance of the optical element 20 (for example, a camera, an under-screen fingerprint recognition sensor, or the like). For example, when the optical element 20 is a camera, the photographing quality of the camera can be improved. For another example, when the optical element 20 is a fingerprint recognition sensor, the accuracy of the fingerprint recognition of the fingerprint recognition sensor can be improved.

[0289] It should be noted that in the case where the orthographic projection of the at least one first connection portion 212b in the third signal line 212 in the light-shielding layer 21 on the substrate 1 and the orthographic projection of the at least one third connection portion 241 in the second gate layer 24 on the substrate 1 overlap, only the orthographic projection of the at least one first connection portion 212b in the third signal line 212 in the light-shielding layer 21 on the substrate 1 is located in the range of the orthographic projection of the at least one third connection portion 241 in the second gate layer 24 on the substrate 1 in FIGS. 9A and 9B is taken as an example for illustratively describing some embodiments of the present disclosure. However, the positional relationship between the orthographic projection of the at least one first connection portion 212b in the third signal line 212 in the light-shielding layer 21 on the substrate 1 and the orthographic projection of the at least one third connection portion 241 in the second gate layer 24 on the substrate 1 in the present disclosure is not limited thereto.

[0290] For example, the orthogonal projection of at least one first connection portion 212b in the third signal line 212 in the light-blocking layer 21 on the substrate 1 and the orthogonal projection of at least one third connection portion 241 in the second gate layer 24 on the substrate 1 can partially coincide.

[0291] For another example, the orthogonal projection of at least one first connection portion 212b in the third signal line 212 in the light-blocking layer 21 on the substrate 1 and the orthogonal projection of at least one third connection portion 241 in the second gate layer 24 on the substrate 1 can also completely coincide.

[0292] In some embodiments, please refer to FIG. 9A, in the second plate C2 of the storage capacitor C in the plurality of pixel circuits 9a arranged along the second direction X, in the case that the two second plates C2 belonging to one second plate pair CD are connected by the third connection portion 241 in the second gate layer 24, and the two second plates C2 belonging to different second plate pairs CD and adjacent in the second direction X are arranged at intervals, the plurality of first connection portions 212b in the plurality of third signal lines 212 in the light-blocking layer 21 include first type first connection portions B1 and second type first connection portions B2. In the orthogonal projection on the substrate 1, the first type first connection portion B1 is located between the two second plates C2 belonging to one second plate pair CD in the second gate layer 24, and the first type first connection portion B1 in the light-blocking layer 21 and the third connection portion 241 in the second gate layer 24 at least partially coincide.

[0293] The second type first connection portion B2 can be located between the two second plates C2 belonging to different second plate pairs CD and adjacent in the second direction X in the second gate layer 24, and the second type first connection portion B2 and the active layer pattern of the transistor in the pixel circuit 9a at least partially coincide. That is, the second type first connection portion B2 in the light-blocking layer 21 and the third connection portion 241 in the second gate layer 24 do not coincide.

[0294] Exemplarily, please refer to FIG. 9A, the orthogonal projection of at least one first connection portion 212b (i.e. the second type first connection portion B2) in the third signal line 212 in the light-blocking layer 21 on the substrate 1 can at least partially coincide with the orthogonal projection of the active layer pattern T61 of the second light-emitting control transistor T6 (the active layer pattern T61 of the second light-emitting control transistor T6 is located in the first semiconductor layer 22) in the pixel circuit 9a on the substrate 1.

[0295] In other embodiments, referring also to FIG. 9B, in the second plate C2 of the storage capacitor C in the plurality of pixel circuits 9a arranged in the second direction X, each first connection portion 212b in the third signal line 212 in the light-shielding layer 21 and the orthogonal projection of one third connection portion 241 in the second gate layer 24 on the substrate 1 at least partially overlap in the orthogonal projection on the substrate 1.

[0296] In some embodiments, as shown in FIG. 10, which is a planar structural diagram of a partial region of the light-shielding layer 21 in the pixel driving layer 2 in the display panel 10 according to some embodiments, the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 includes a main body portion A1 and an extension portion A2 connected to one side of the main body portion A1.

[0297] As shown in FIG. 11 and FIG. 12, FIG. 11 is a planar structural diagram of a partial region of the pixel driving layer 2 in the display panel 10 according to some embodiments, and FIG. 12 is a planar structural diagram of a partial region of the light-shielding layer 21, the first gate layer 23, and the first source-drain conductive layer 28 in the pixel driving layer 2 in the display panel 10 according to some embodiments. In the orthogonal projection on the substrate 1, the main body portion A1 of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 and the first plate C1 of the storage capacitor C in the pixel circuit 9a overlap, and the extension portion A2 of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 and the first plate C1 of the storage capacitor C in the pixel circuit 9a do not overlap.

[0298] The second connection portion 282 in the first source-drain conductive layer 28 (the second connection portion 282 is used to connect the first plate C1 of the storage capacitor C in the pixel circuit 9a and the source or the drain of the threshold compensation transistor T2 in the pixel circuit 9a) and the extension portion A2 of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 overlap.

[0299] By setting the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 to include the main body portion A1 and the extension portion A2 connected to one side of the main body portion A1, and the extension portion A2 of the light-shielding pattern 212a and the second connection portion 282 in the first source-drain conductive layer 28 (the second connection portion 282 is used to connect the first plate C1 of the storage capacitor C in the pixel circuit 9a and the source or drain of the threshold compensation transistor T2 in the pixel circuit 9a) overlap, the overlapping area of the extension portion A2 of the light-shielding pattern 212a and the second connection portion 282 in the first source-drain conductive layer 28 (the second connection portion 282 is used to connect the first plate C1 of the storage capacitor C in the pixel circuit 9a and the source or drain of the threshold compensation transistor T2 in the pixel circuit 9a) can form a storage capacitor, which can increase the storage capacitance in the pixel circuit 9a, and further ensure that the voltage of the pixel circuit 9a remains stable, which is beneficial to reduce the risk of flicker and the probability of crosstalk of the display panel 10.

[0300] In particular, with the continuous development of the display panel 10, large-size, ultra-high-definition display screens are favored by more and more users. From 720P to 1080P, from 2K to 4K to 8K, the resolution of the display panel 10 is constantly upgraded. PPI (pixels per inch) is the unit of image resolution, which represents the number of pixels per inch. Therefore, the higher the PPI value, the higher the density of the display screen that can display images. The higher the display density, the higher the fidelity, so as to achieve high-definition, ultra-high-definition display.

[0301] Since the higher the PPI value of the display panel 10, the more the number of pixels per inch, the area of each pixel circuit 9a in the display panel 10 is reduced, and it is difficult to set the storage capacitor C in the pixel circuit 9a. By setting the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 to include the main body portion A1 and the extension portion A2 connected to one side of the main body portion A1, and the extension portion A2 of the light-shielding pattern 212a and the second connection portion 282 in the first source-drain conductive layer 28 (the second connection portion 282 is used to connect the first plate C1 of the storage capacitor C in the pixel circuit 9a and the source or drain of the threshold compensation transistor T2 in the pixel circuit 9a) overlap, the overlapping area of the extension portion A2 of the light-shielding pattern 212a and the second connection portion 282 in the first source-drain conductive layer 28 (the second connection portion 282 is used to connect the first plate C1 of the storage capacitor C in the pixel circuit 9a and the source or drain of the threshold compensation transistor T2 in the pixel circuit 9a) can form a storage capacitor, which can ensure the storage capacitance of the pixel circuit 9a, and further enable the voltage of the pixel circuit 9a to remain stable, which is beneficial to reduce the risk of flicker and the probability of crosstalk of the display panel 10.

[0302] Exemplarily, as shown in FIG. 13, FIG. 13 is a planar structural diagram of a partial region of the light-shielding layer 21, the first gate layer 23, the second gate layer 24 and the first source-drain conductive layer 28 in the pixel driving layer 2 in the display panel 10 according to some embodiments. The first scan signal line Ngate in the second gate layer 24 and the first plate C1 of the storage capacitor C are adjacently and spacedly arranged. That is, the first scan signal line Ngate in the second gate layer 24 and the first plate C1 of the storage capacitor C located in the second gate layer 24 are not connected.

[0303] The second connection part 282 in the first source-drain conductive layer 28 (the second connection part 282 is used to connect the first plate C1 of the storage capacitor C in the pixel circuit 9a and the source or drain of the threshold compensation transistor T2 in the pixel circuit 9a) and the first scan signal line Ngate in the second gate layer 24 are cross-arranged, and the extension part A2 of the light-shielding pattern 212a is located in the interval region between the first scan signal line Ngate in the second gate layer 24 and the first plate C1 of the storage capacitor C located in the second gate layer 24.

[0304] In the orthographic projection onto the substrate 1, the extension part A2 of the light-shielding pattern 212a and the first scan signal line Ngate in the second gate layer 24 do not overlap.

[0305] Exemplarily, as shown in FIG. 13, in the orthographic projection onto the substrate 1, the extension part A2 of the light-shielding pattern 212a and the fourth connection part 283 in the first source-drain conductive layer 28 (the fourth connection part 283 in the first source-drain conductive layer 28 is used to connect the second plate C2 of the storage capacitor C in the pixel circuit 9a and the first voltage signal line VDD) do not overlap.

[0306] Although some embodiments of the present application about the positional relationship between the orthographic projection of the first signal line 211 in the light-shielding layer 21 onto the substrate 1 and the orthographic projection of the second signal line 281 in the first source-drain conductive layer 28 onto the substrate 1, the corresponding relationship between the number of the adjacent two first signal lines 211 in the light-shielding layer 21 and the pixel circuit 9a, the positional relationship between the orthographic projection of at least one first connection part 212b in the third signal line 212 in the light-shielding layer 21 onto the substrate 1 and the orthographic projection of at least one third connection part 241 in the second gate layer 24 onto the substrate 1, and the structure of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 are described herein in combination with FIG. 6A to FIG. 13. However, the description of some embodiments of the present application in combination with FIG. 6A to FIG. 13 is exemplary and not exhaustive, and thus is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope of the above embodiments.

[0307] Specifically, the positional relationship between the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1, the correspondence relationship between the adjacent two first signal lines 211 in the light-shielding layer 21 and the number of the pixel circuits 9a, the positional relationship between the orthogonal projection of at least one first connecting portion 212b in the third signal line 212 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of at least one third connecting portion 241 in the second gate layer 24 on the substrate 1, and the structure of the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21, and the like in the embodiments shown in FIGS. 6A to 13 can be arbitrarily combined, and any combination of the above-mentioned embodiments is within the scope of the present disclosure.

[0308] For example, please continue to refer to FIG. 12, while making the orthogonal projection of the first signal line 211 in the light-shielding layer 21 on the substrate 1 and the orthogonal projection of the second signal line 281 in the first source-drain conductive layer 28 on the substrate 1 at least partially coincide, the light-shielding pattern 212a in the third signal line 212 in the light-shielding layer 21 can also be set to include a main body portion A1 and an extension portion A2 connected to one side of the main body portion A1, and the extension portion A2 of the light-shielding pattern 212a and the second connecting portion 282 in the first source-drain conductive layer 28 (the second connecting portion 282 is used to connect the first plate C1 of the storage capacitor C in the pixel circuit 9a and the source or drain of the threshold compensation transistor T2 in the pixel circuit 9a) overlap. This makes it possible to increase the storage capacity of the pixel circuit 9a in the display panel 10 while improving the light transmittance (i.e., the light transmission rate) of the display panel 10, and reduce the risk of flicker and the probability of crosstalk of the display panel 10.

[0309] The above merely describes specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art who conceives changes or substitutions within the technical scope disclosed in the present disclosure should be covered within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be subject to the scope of protection of the claims.

Claims

1. A display panel, comprising: a substrate; a light shielding layer located on one side of the substrate; the light shielding layer comprises a plurality of first signal lines extending along a first direction; a first source-drain conductive layer located on a side of the light shielding layer away from the substrate; the first source-drain conductive layer comprises a plurality of second signal lines extending along the first direction; wherein, in a display area of the display panel, a projection of the first signal lines on the substrate and a projection of the second signal lines on the substrate at least partially overlap.

2. The display panel of claim 1, wherein, in the display area, the projection of the first signal lines on the substrate and the projection of the second signal lines on the substrate completely overlap; or, in the display area, the projection of the first signal lines on the substrate is located within the range of the projection of the second signal lines on the substrate.

3. The display panel of claim 1, wherein, the first signal lines and the second signal lines are configured to transmit direct current signals.

4. The display panel of claim 3, wherein, the first signal lines are configured to transmit one of a VDD voltage signal, a VSS voltage signal and an initialization signal, and the second signal lines are configured to transmit one of a VDD voltage signal, a VSS voltage signal and an initialization signal.

5. The display panel of claim 1, wherein, the display panel further comprises a plurality of pixel circuits arranged in an array; in a second direction, at least two pixel circuits are arranged between any two adjacent first signal lines; the second direction and the first direction intersect.

6. The display panel of claim 5, wherein, in the second direction, the number of pixel circuits between any two adjacent first signal lines is the same.

7. The display panel of claim 5, wherein, the light shielding layer further comprises a plurality of third signal lines extending along the second direction; a plurality of first signal lines are connected between any two adjacent third signal lines.

8. The display panel of claim 7, wherein, in the second direction, a plurality of first signal lines connected to the same third signal line are alternately arranged on both sides of the third signal line.

9. The display panel of claim 8, wherein, a plurality of first signal lines are arranged in alignment along the first direction, and among the plurality of first signal lines arranged in alignment, any two adjacent first signal lines are arranged apart from each other.

10. The display panel of claim 5, wherein, the light shielding layer further comprises a plurality of third signal lines extending along the second direction; in the second direction, at least two columns of pixel circuits are arranged between any two adjacent first signal lines, and the plurality of third signal lines and the plurality of first signal lines intersect and connect with each other.

11. The display panel of claim 1, wherein, the display panel further comprises a first gate layer located between the light shielding layer and the first source-drain conductive layer; the pixel circuit of the display panel comprises a storage capacitor, and the storage capacitor comprises a first plate located on the first gate layer; the third signal lines in the light shielding layer comprise a plurality of light shielding patterns and a plurality of first connecting portions, and any two adjacent light shielding patterns are connected by the first connecting portion; a projection of the first plate on the substrate and a projection of the light shielding pattern on the substrate at least partially overlap; the first signal lines and the first connecting portions are connected.

12. The display panel of claim 11, wherein, the first source-drain conductive layer further comprises a second connecting portion; The pixel circuit further comprises a threshold compensation transistor, a source or a drain of the threshold compensation transistor is connected with the first plate through the second connecting part; The light shielding pattern comprises a main body part and an extension part connected to one side of the main body part, in the orthographic projection onto the substrate, the main body part and the first plate overlap, the extension part and the first plate do not overlap, and the second connecting part and the extension part overlap.

13. The display panel of claim 12, wherein, The display panel further comprises a first scan signal line extending along a second direction, a gate of the threshold compensation transistor is connected with the first scan signal line; In the orthographic projection onto the substrate, the first scan signal line and the first plate are adjacent and spaced apart; the second connecting part and the first scan signal line are cross arranged, and the extension part is located in the spacing region between the first scan signal line and the first plate.

14. The display panel of claim 13, wherein, The display panel further comprises a second gate layer between the light shielding layer and the first source-drain conductive layer; the storage capacitor of the pixel circuit of the display panel further comprises a second plate in the second gate layer; The display panel further comprises a first voltage signal line; The first source-drain conductive layer comprises a plurality of fourth connecting parts, and the first voltage signal line and the second plate are connected through the fourth connecting parts; In the orthographic projection onto the substrate, the extension part and the fourth connecting part do not overlap; and / or, In the orthographic projection onto the substrate, the extension part and the first scan signal line do not overlap.

15. The display panel of claim 1, wherein, The display panel further comprises a second gate layer between the light shielding layer and the first source-drain conductive layer; the storage capacitor of the pixel circuit of the display panel further comprises a second plate in the second gate layer; The second gate layer further comprises a third connecting part, the third connecting part is connected between the second plates of the storage capacitors of two pixel circuits adjacent in a second direction; the second direction and the first direction intersect; The orthographic projection of at least one first connecting part on the substrate and the orthographic projection of at least one third connecting part on the substrate at least partially overlap.

16. The display panel of claim 15, wherein, The display panel further comprises a first semiconductor layer between the light shielding layer and the second gate layer; The pixel circuit comprises a plurality of transistors, and the transistors comprise an active layer pattern in the semiconductor layer; The orthographic projection of at least one first connecting part on the substrate and the orthographic projection of at least one active layer pattern of the transistors on the substrate at least partially overlap.

17. The display panel of claim 16, wherein, The plurality of transistors comprises a second light-emitting control transistor; The orthographic projection of at least one first connecting part on the substrate and the orthographic projection of an active layer pattern of the second light-emitting control transistor on the substrate at least partially overlap.

18. The display panel of claim 16, wherein, The second plates of the storage capacitors of a plurality of pixel circuits arranged in a second direction comprise a plurality of second plate pairs, and one second plate pair comprises two adjacent second plates; The two second plates belonging to one second plate pair are connected through the third connecting part, and two second plates belonging to different second plate pairs and adjacent in the second direction are spaced apart; The orthographic projection of at least one first connecting part on the substrate and the orthographic projection of at least one active layer pattern of the transistors on the substrate at least partially overlap. The first connection portions include first connection portions of a first type and first connection portions of a second type. In a normal projection onto the substrate, the first connection portions of the first type are located between two second plates belonging to one second plate pair, and the first connection portions of the first type and the third connection portions at least partially overlap. The first connection portions of the second type are located between two second plates belonging to different second plate pairs and adjacent in the second direction, and the first connection portions of the second type and the active layer pattern of the transistors at least partially overlap.

19. The display panel of claim 15, wherein, Among the second plates of the storage capacitors of the pixel circuits arranged in the second direction, any two adjacent second plates are connected by the third connection portions; The normal projection of each first connection portion onto the substrate and the normal projection of one third connection portion onto the substrate at least partially overlap.

20. A display device, comprising: The display panel according to any one of claims 1 to 19; An optical element located on a non-light-emitting side of the display panel.

Images