CXL switch board and CXL memory allocation system, method and apparatus

Abstract

The present application relates to the technical field of computers, and provides a CXL switch board and a CXL memory allocation system, method and apparatus. The CXL switch board is provided with a CXL switch unit and a micro-control unit; the CXL switch unit comprises at least one first port and at least one second port, the first port being used for connecting to a CPU, and the second port being used for connecting to a CXL memory board; after the CXL switch unit is powered on, the micro-control unit is used for acquiring the memory capacity of a local memory corresponding to the CPU; the micro-control unit or the CXL switch unit is used for calculating a CXL memory starting address on the basis of the memory capacity; the CXL switch unit is used for writing the CXL memory starting address into a register of the first port corresponding to the CPU, and using the CXL memory starting address as a base address of a CXL memory to allocate the CPU the CXL memory in the CXL memory board.

Description

CXL switch board card, CXL memory allocation system, allocation method and device

[0001] Cross-reference to related applications

[0002] This application claims priority to the Chinese patent application No. 202410635709.2, filed on May 22, 2024, and entitled "CXL switch board card, CXL memory allocation system, allocation method and device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of computer technology, and in particular to a CXL switch board card, a CXL memory allocation system, an allocation method and a device. BACKGROUND

[0004] With the development of artificial intelligence and high-performance computing, the complexity of artificial intelligence models and the amount of data calculation have also increased substantially, and thus the demand for memory resources has increased exponentially. In order to meet the growth demand of memory resources, the existing related technical solution is to allocate CXL (Compute Express Link) memory resources to CPUs in a server system.

[0005] In the above solution, the memory capacity of the local memory corresponding to each CPU needs to be determined manually, and then the starting address of the CXL memory to be allocated is calculated according to the memory capacity of the local memory, and finally the CXL memory allocation is completed. Since the CXL memory allocation requires a large amount of manual input, the CXL memory allocation efficiency is low, and additional labor costs are also increased. Moreover, manual calculation is prone to errors, which may result in failure of CXL memory allocation. SUMMARY

[0006] The present application provides a CXL switch board card, which is provided with a CXL switching unit and a micro control unit connected with the CXL switching unit. The CXL switching unit includes at least one first port and at least one second port. The first port is used to connect a CPU, and the second port is used to connect a CXL memory board card to obtain CXL memory in the CXL memory board card.

[0007] The micro control unit is used to obtain the memory capacity of the local memory corresponding to the CPU after the CXL switching unit is powered on. The micro control unit or the CXL switching unit is used to calculate the starting address of the CXL memory according to the memory capacity.

[0008] The CXL switching unit is used to write the starting address of the CXL memory into the register of the first port corresponding to the CPU, and use the starting address of the CXL memory as the first address of the CXL memory to allocate the CXL memory in the CXL memory board card to the CPU.

[0009] According to the CXL exchange board provided in the application, the CXL exchange board is further provided with a first voltage regulator and a first power-on controller, the first power-on controller is connected with the micro control unit and the first voltage regulator, the first voltage regulator is connected with the CXL exchange unit, the first power-on controller is used to control the first voltage regulator to supply power to the CXL exchange unit, and the first voltage regulator feeds back the power-on completion signal of the CXL exchange unit to the first power-on controller after the CXL exchange unit is powered on, and the first power-on controller feeds back the power-on completion signal of the CXL exchange unit to the micro control unit.

[0010] According to the CXL exchange board provided in the application, the micro control unit is used to control the CXL memory board to be powered on after the power-on completion signal of the CXL exchange unit is received, and the memory capacity of the local memory corresponding to the CPU is obtained.

[0011] According to the CXL exchange board provided in the application, the CXL exchange unit is further used to send a write completion signal to the micro control unit after the CXL memory start address is written into the register of the first port corresponding to the CPU, and the micro control unit is further used to control the CPU to be powered on after the write completion signal is received, and the CXL exchange unit allocates the CXL memory in the CXL memory board to the CPU as the first address of the CXL memory with the CXL memory start address as the first address of the CXL memory after the CPU is powered on.

[0012] The application further provides a CXL memory allocation system, which comprises a host board, a CXL exchange board and a CXL memory board, the host board is provided with at least one CPU and local memory corresponding to the CPU respectively, the CXL exchange board is provided with a CXL exchange unit and a micro control unit connected with the CXL exchange unit, the CXL exchange unit comprises at least one first port and at least one second port, each CPU is connected with the first port respectively, one first port is connected with only one CPU, and the CXL exchange unit is connected with the CXL memory board through the second port to obtain the CXL memory in the CXL memory board.

[0013] The micro control unit is used to obtain the memory capacity of the local memory corresponding to the CPU after the CXL exchange unit is powered on, and the micro control unit or the CXL exchange unit is used to calculate the CXL memory start address according to the memory capacity.

[0014] The CXL exchange unit is used to write the CXL memory start address into the register of the first port corresponding to the CPU, and the CXL exchange unit allocates the CXL memory in the CXL memory board to the CPU as the first address of the CXL memory with the CXL memory start address as the first address of the CXL memory.

[0015] According to the CXL memory allocation system provided in the application, the CXL switch board card is further provided with a first voltage regulator and a first power-on controller, the first power-on controller is connected with the micro control unit and the first voltage regulator, the first voltage regulator is connected with the CXL switch unit, the first power-on controller is used for controlling the first voltage regulator to supply power for the CXL switch unit, and the first voltage regulator feeds back a CXL switch unit power-on completion signal to the first power-on controller after the CXL switch unit is powered on.

[0016] According to the CXL memory allocation system provided in the application, the CXL memory board card is provided with at least one CXL memory, a memory controller corresponding to the CXL memory and a second voltage regulator, the memory controller is connected with the corresponding CXL memory and the second voltage regulator, the micro control unit is connected with the second voltage regulator, and the micro control unit is further used for controlling the second voltage regulator to supply power for the corresponding memory controller after the CXL switch unit is powered on, and receiving a memory controller power-on completion signal fed back by the second voltage regulator.

[0017] The second port is connected with the memory controller, one memory controller is connected with one second port, and the CXL switch unit is used for establishing a communication link based on the second port and the memory controller after the memory controller is powered on, and feeding back a communication link completion signal to the micro control unit, and the CXL switch unit is used for acquiring the CXL memory through the second port after the communication link is established.

[0018] According to the CXL memory allocation system provided in the application, the at least one second port is connected with a plurality of memory controllers.

[0019] According to the CXL memory allocation system provided in the application, the host board card is further provided with a baseboard controller, and the baseboard controller is connected with the micro control unit and the local memory.

[0020] The micro control unit is used for sending a memory capacity reading instruction to the baseboard controller after the CXL memory board card is powered on, and the baseboard controller is used for acquiring the memory capacity of the local memory corresponding to the CPU after receiving the memory capacity reading instruction, and sending the memory capacity to the micro control unit.

[0021] According to the CXL memory allocation system provided in the application, the host board card is further provided with an I3C hub, and in the case that there are a plurality of CPUs on the host board card, the baseboard controller is connected with the local memories corresponding to the plurality of CPUs through the I3C hub.

[0022] According to the CXL memory allocation system provided in the application, the local memory comprises a serial detection chip, and the baseboard controller is connected with the serial detection chip and is used for reading the memory capacity acquired by the serial detection chip.

[0023] According to the CXL memory allocation system provided in the application, the host board card is further provided with a second power-on controller and a third voltage regulator corresponding to the CPU, the second power-on controller is connected with the baseboard controller and the third voltage regulator;

[0024] The CXL switching unit is further configured to send a write completion signal to the micro control unit after the CXL memory start address is written into the register of the first port corresponding to the CPU;

[0025] The micro control unit is further configured to send a host power-on instruction to the baseboard controller after receiving the write completion signal, the baseboard controller is further configured to send the host power-on instruction to the second power-on controller, and the second power-on controller is configured to control the third voltage regulator to power on the corresponding CPU after receiving the host power-on instruction, the CPU establishes a communication link with the first port after being powered on, and the third voltage regulator sends a host power-on completion signal to the micro control unit through the second power-on controller and the baseboard controller after completing power-on.

[0026] According to the CXL memory allocation system provided in the application, at least one CPU is connected with a plurality of first ports.

[0027] According to the CXL memory allocation system provided in the application, the micro control unit is further configured to acquire the memory capacity of the local memory corresponding to the CPU and acquire the local memory identifier at the same time, and send the local memory identifier to the CXL switching unit, and the CXL switching unit is configured to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table, and the identifier mapping table records the mapping relationship between the first port identifier and the local memory identifier.

[0028] The application further provides a CXL memory allocation method, which is realized based on the CXL memory allocation system of any one of the above and applied to the micro control unit, and the method comprises the following steps:

[0029] After the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is acquired; and

[0030] The memory capacity is sent to the CXL switching unit, the memory capacity is used to instruct the CXL switching unit to calculate the CXL memory start address according to the memory capacity, and the CXL memory start address is written into the register of the first port corresponding to the CPU, so that the CXL memory start address is used as the first address of the CXL memory, and the CXL memory in the CXL memory board card is allocated to the CPU, or the CXL memory start address is calculated according to the memory capacity, and the CXL memory start address is sent to the CXL switching unit, and the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, so that the CXL memory start address is used as the first address of the CXL memory, and the CXL memory in the CXL memory board card is allocated to the CPU.

[0031] According to the CXL memory allocation method provided in the application, after the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is obtained, including:

[0032] After the CXL switching unit is powered on, the CXL memory board card is powered on; and

[0033] After the CXL memory board card is powered on, the memory capacity of the local memory corresponding to the CPU is obtained.

[0034] According to the CXL memory allocation method provided in the application, the method further comprises:

[0035] The write completion signal sent by the CXL switching unit is received, and the CPU in the host board card is powered on, so that after the CPU is powered on, the CXL switching unit allocates the CXL memory in the CXL memory board card to the CPU with the CXL memory start address as the first address of the CXL memory;

[0036] The write completion signal is sent by the CXL switching unit after the CXL memory start address is written into the register of the first port corresponding to the CPU.

[0037] According to the CXL memory allocation method provided in the application, the method further comprises: while obtaining the memory capacity of the local memory corresponding to the CPU, obtaining the local memory identifier, and sending the local memory identifier to the CXL switching unit, the CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to the preset identifier mapping table, and the mapping relationship between the first port identifier and the local memory identifier is recorded in the identifier mapping table.

[0038] The application also provides one or more non-volatile computer readable storage media storing computer readable instructions, which are executed by one or more processors to make the one or more processors execute the steps of a CXL memory allocation method according to any one of the above embodiments.

[0039] The application also provides a microcontroller, comprising a memory and one or more processors, the memory storing computer readable instructions, the computer readable instructions being executed by the one or more processors to enable the one or more processors to perform the CXL memory allocation method provided by any of the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the application or the prior art, the drawings required to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0041] Fig. 1 is a schematic diagram of the framework structure of the CXL memory allocation system provided by one or more embodiments of the application;

[0042] Fig. 2 is a schematic diagram of the specific structure of the CXL memory allocation system provided by one or more embodiments of the application;

[0043] Fig. 3 is a schematic diagram of one of the CXL memory allocation method flowcharts provided by one or more embodiments of the application;

[0044] Fig. 4 is a schematic diagram of another of the CXL memory allocation method flowcharts provided by one or more embodiments of the application;

[0045] Fig. 5 is a schematic diagram of the structure of the CXL memory allocation device provided by one or more embodiments of the application. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the application more clear, the technical solutions in the application will be clearly and completely described below in combination with the drawings in the application. Obviously, the described embodiments are some of the embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application.

[0047] In order to facilitate understanding of the embodiments of the application, the related English abbreviations in the embodiments of the application are explained as follows:

[0048] CXL: Compute Express Link, a high-speed interconnection technology designed to improve the communication efficiency between processors, memory devices, accelerators (such as GPUs, FPGAs, etc.) in data centers and high-performance computing environments.

[0049] DIMM: Dual-Inline-Memory-Modules, dual in-line memory modules.

[0050] CPLD: Complex Programmable Logic Device, complex programmable logic device.

[0051] SPD: Serial Presence Detect, serial presence detect.

[0052] VR: Voltage Regulated, voltage regulated.

[0053] BMC: Baseboard Management Controller, baseboard management controller.

[0054] MCU: Microcontroller Unit, microcontroller unit.

[0055] USP: upstream port, upstream port.

[0056] DSP: downstream port, downstream port.

[0057] I2C: Inter-Integrated Circuit, inter-integrated circuit.

[0058] I3C: Improved Inter Integrated Circuit, improved inter integrated circuit.

[0059] The CXL switch board card of the first embodiment of the present application is shown in FIGS. 1 and 2, and the CXL switch board card is provided with a CXL switching unit CXL SW and a micro control unit MCU connected with the CXL switching unit CXL SW. The CXL switching unit CXL SW includes at least one first port and at least one second port. In the present embodiment, the first port is a USP port (upstream port), and the second port is a DSP port (downstream port). Two first ports USP_0 and USP_1 and two second ports DSP_0 and DSP_1 are shown in FIG. 2. The first port is used to connect a CPU, and the second port is used to connect a CXL memory board card to obtain a CXL memory in the CXL memory board card. The CPU is located in an upstream motherboard card, and each CPU corresponds to a local memory. The CXL memory board card is provided with at least one CXL memory.

[0060] In the embodiment, the micro control unit MCU is configured to obtain the memory capacity of the local memory corresponding to the CPU after the CXL switch unit CXL SW is powered on, and the micro control unit MCU or the CXL switch unit CXL SW is configured to calculate the CXL memory start address according to the memory capacity. For example, in a simple calculation, the capacity of the local memory of the CPU is 64 GB, and the logical address of the last byte in the 64 GB + 1 is used as the CXL memory start address.

[0061] The CXL switch unit CXL SW is configured to write the CXL memory start address into the register of the first port corresponding to the CPU, and use the CXL memory start address as the first address of the CXL memory to allocate the CXL memory in the CXL memory board to the CPU, thereby realizing the function of automatically allocating the CXL memory to the CPU.

[0062] In the CXL switch board of the embodiment, the micro control unit MCU automatically obtains the memory capacity of the local memory corresponding to the CPU after the CXL switch unit is powered on, and the micro control unit or the CXL switch unit calculates the CXL memory start address according to the memory capacity. The CXL switch unit automatically writes the CXL memory start address into the register of the first port, thereby realizing the CXL memory allocation to the CPU, and without the need of manually obtaining the memory capacity of the local memory corresponding to the CPU or manually calculating the register of the first port, the labor cost is reduced, the manual allocation error is avoided, and the memory allocation efficiency of the entire CXL memory allocation system is improved.

[0063] In the embodiment, the CXL switch board further comprises a first voltage regulator VR_SW and a first power-on controller CPLD_1. The first power-on controller CPLD_1 is connected to the micro control unit MCU and the first voltage regulator VR_SW, and the first voltage regulator VR_SW is connected to the CXL switch unit CXL SW. The first power-on controller CPLD_1 is configured to control the first voltage regulator VR_SW to supply power to the CXL switch unit CXL SW. After the CXL switch unit CXL SW is powered on, the first voltage regulator VR_SW feeds back a CXL switch unit power-on completion signal to the first power-on controller CPLD_1, and the first power-on controller CPLD_1 feeds back the CXL switch unit power-on completion signal to the micro control unit MCU.

[0064] Specifically, the micro control unit MCU connects the first power-on controller CPLD_1 through UART, the micro control unit MCU and the CXL switch unit CXL SW are connected through I2C, and the micro control unit MCU sends the memory capacity or the CXL memory start address to the CXL switch unit CXL SW through I2C. Of course, the CXL switch board further has a power supply (Power Supply) switch button PWR_button, and the PWR_button is connected to the first power-on controller CPLD_1. After pressing the PWR_button, the first power-on controller CPLD_1 receives the power-on signal and sends the power-on enable signal PWREN_SW to the first voltage regulator VR_SW. The first voltage regulator VR_SW outputs a voltage to the CXL switch unit CXL SW, the CXL switch unit CXL SW completes its own initialization and enables the first port and the second port, and the first voltage regulator VR_SW sends the CXL switch unit power-on completion signal PWRGD_SW to the first power-on controller CPLD_1. The first power-on controller CPLD_1 transmits the CXL switch unit power-on completion signal to the micro control unit MCU through the UART interface.

[0065] The micro control unit MCU is used to control the power-on of the CXL memory board after receiving the CXL switch unit power-on completion signal, and obtain the memory capacity of the local memory corresponding to the CPU.

[0066] In the embodiment, the first power-on controller CPLD_1 controls the power-on of the CXL switch unit CXL SW and feeds back the CXL switch unit power-on completion signal to the micro control unit MCU, which is conducive to the control of the micro control unit MCU on the power-on timing of the CXL memory board, that is, the micro control unit MCU controls the power-on of the CXL memory board after the power-on of the CXL switch unit CXL SW. Moreover, the memory capacity of the local memory corresponding to the CPU is obtained after the power-on of the CXL memory board. The problem of CXL memory allocation failure caused by the unsuccessful power-on of the CXL memory board after obtaining the memory capacity is avoided.

[0067] In this embodiment, the CXL switching unit CXL SW is also configured to send a write completion signal to the micro control unit MCU after writing the CXL memory start address into the register of the first port corresponding to the CPU, and specifically, the write completion signal is sent to the micro control unit MCU through I2C. The micro control unit MCU is also configured to control the power-on of the CPU after receiving the write completion signal, and after the power-on of the CPU, the CXL switching unit allocates the CXL memory in the CXL memory board to the CPU with the CXL memory start address as the first address of the CXL memory. That is, the power-on of the CPU is controlled after the successful writing of the CXL memory start address, so as to avoid the problem of the failure of the allocation of the CXL memory due to the fact that the CXL memory start address is not written into the corresponding first port after the power-on of the CPU.

[0068] The CXL memory allocation system of the second embodiment of the present application, as shown in FIGS. 1 and 2, comprises a host board, a CXL switching board and a CXL memory board.

[0069] The host board is provided with at least one CPU and local memory corresponding to the CPU, and two CPUs, CPU_0 and CPU_1, in one host board are shown in FIG. 2. The CPU_0 and CPU_1 are connected to local memories DIMM_0 and DIMM_1 through a DDR5 bus respectively. The CXL switching board can be the CXL switching board of the above-mentioned embodiments. The CXL switching board is provided with a CXL switching unit CXL SW and a micro control unit MCU connected to the CXL switching unit CXL SW. The CXL switching unit CXL SW comprises at least one first port and at least one second port. Each CPU is connected to a first port, and one first port is connected to only one CPU (if a plurality of CPUs are connected, the CXL memory start addresses corresponding to the plurality of CPUs will be written into the register of the first port, and a conflict will occur during the allocation of the CXL memory). The CXL switching unit CXL SW is connected to the CXL memory board through the second port to obtain the CXL memory in the CXL memory board. Specifically, the CPU and the first port are connected through a CXL bus (MCIO cable), and the second port and the CXL memory board are also connected through a CXL bus (MCIO cable).

[0070] The micro control unit MCU is configured to obtain the memory capacity of the local memory corresponding to the CPU after the power-on of the CXL switching unit CXL SW, and the micro control unit MCU or the CXL switching unit CXL SW is configured to calculate the CXL memory start address according to the memory capacity.

[0071] The CXL switching unit CXL SW is configured to write the CXL memory start address into the register of the first port corresponding to the CPU, and allocate the CXL memory in the CXL memory board to the CPU with the CXL memory start address as the first address of the CXL memory.

[0072] In the CXL memory allocation system of the embodiment, the micro control unit MCU automatically acquires the memory capacity of the local memory corresponding to the CPU after the CXL switch unit is powered on, and the micro control unit or the CXL switch unit calculates the CXL memory starting address according to the memory capacity, the CXL switch unit automatically writes the CXL memory starting address to the register of the first port, thereby realizing automatic allocation of the CXL memory to the CPU, without the need for manual acquisition of the memory capacity of the local memory corresponding to the CPU, or manual calculation of the register of the first port, reducing the labor cost, avoiding manual allocation errors, and improving the memory allocation efficiency of the entire CXL memory allocation system.

[0073] In the embodiment, the CXL switch board card is further provided with a first voltage regulator VR_SW and a first power-on controller CPLD_1, the first power-on controller CPLD_1 is connected to the micro control unit MCU and the first voltage regulator VR_SW, the first voltage regulator VR_SW is connected to the CXL switch unit CXL SW, the first power-on controller CPLD_1 is used to control the first voltage regulator VR_SW to supply power to the CXL switch unit CXL SW, the first voltage regulator VR_SW feeds back a CXL switch unit power-on completion signal to the first power-on controller CPLD_1 after the CXL switch unit CXL SW is powered on, and the first power-on controller CPLD_1 feeds back the CXL switch unit power-on completion signal to the micro control unit MCU. The internal specific structure of the CXL switch board card is shown in the first embodiment described above, and will not be described here.

[0074] In the embodiment, the CXL memory board card is provided with at least one CXL memory (DIMM in FIGS. 1 and 2) and a memory controller and a second voltage regulator corresponding to the CXL memory, two CXL memories, two memory controllers MXC_0 and MXC_1 corresponding thereto, and two second voltage regulators VR_MXC_0 and VR_MXC_1 corresponding to the two memory controllers MXC_0 and MXC_1, respectively, are shown in FIG. 2. The memory controller is connected to the corresponding CXL memory and the second voltage regulator, the micro control unit MCU is connected to the second voltage regulator, and is further used to control the second voltage regulator to supply power to the corresponding memory controller after the CXL switch unit CXL SW is powered on, and receive the memory controller power-on completion signal fed back by the second voltage regulator.

[0075] The second port is connected with a memory controller, one memory controller is connected with one second port, and the CXL switching unit CXL SW is configured to establish a communication link (i.e., a CXL bus communication protocol link) with the memory controller based on the second port after the memory controller is powered on, and feed back a communication link completion signal to the micro control unit MCU, and the CXL switching unit CXL SW is configured to obtain the CXL memory through the second port after the communication link is established. In the embodiment, the second voltage regulator feeds back a memory controller power-on completion signal to the micro control unit MCU, and the CXL switching unit CXL SW feeds back a communication link completion signal to the micro control unit MCU, so that the micro control unit MCU performs timing control, and obtains the memory capacity of the local memory corresponding to the CPU after the CXL memory board card is powered on and the CXL switching unit CXL SW establishes a communication link with the CXL memory board card, thereby avoiding the case that the CXL memory allocation fails due to the power-on failure of the CXL memory board card or the failure of establishing the communication link.

[0076] Specifically, as shown in FIG. 2, the micro control unit MCU is connected with two second voltage regulators VR_MXC_0 and VR_MXC_1 through a low-speed cable, and the memory controller is connected with the corresponding CXL memory through a DDR5 bus. The micro control unit MCU sends PWREN_MXC0 and PWREN_MXC1 power-on enable signals to VR_MXC_0 and VR_MXC_1 respectively, so that VR_MXC_0 and VR_MXC_1 power on two memory controllers MXC_0 and MXC_1 respectively. After MXC_0 and MXC_1 are powered on and complete self-initialization, the DIMM memory resources are obtained through the DDR5 bus, and meanwhile, the two second ports DSP_0 and DSP_1 of the CXL switching unit CXL SW establish communication links with MXC_0 and MXC_1 respectively, so as to obtain the CXL memory resources. The CXL switching unit CXL SW sends a communication link completion signal to the micro control unit MCU through I2C, and meanwhile, the micro control unit MCU receives the memory controller power-on completion signals PWRGD_MXC0 and PWRGD_MXC1 sent by VR_MXC_0 and VR_MXC_1 respectively.

[0077] In the embodiment, at least one second port is connected with multiple memory controllers, and one second port is connected with multiple memory controllers, so that the second port resources can be maximized to connect more CXL memories and maximize the performance of the CXL bus.

[0078] In the embodiment, the host board card is further provided with a baseboard management controller BMC, and the baseboard management controller BMC is connected with the micro control unit MCU and the local memory.

[0079] The micro control unit MCU is configured to send a memory capacity reading instruction to the baseboard management controller BMC after the CXL memory board card is powered on. Specifically, the micro control unit MCU sends the memory capacity reading instruction to the baseboard management controller BMC through a network (Eth, i.e., Ethereum) after the memory controller is powered on and the communication link between the second port and the memory controller is established.

[0080] The baseboard management controller BMC is configured to obtain the memory capacity of the local memory corresponding to the CPU after receiving the memory capacity reading instruction, and send the memory capacity to the micro control unit MCU. Specifically, the baseboard management controller BMC is connected to the local memory of the CPU through I3C, and obtains the memory capacity of the local memory through I3C.

[0081] In the embodiment, the host board card is also provided with an I3C hub. In the case that the host board card has multiple CPUs, the baseboard management controller BMC is connected to the local memories corresponding to the multiple CPUs through the I3C hub. The I3C hub reduces the interface occupation of the baseboard management controller BMC, and is not limited by the interfaces of the baseboard management controller BMC, so that the reading requirement of the memory capacity of the local memories corresponding to the multiple CPUs on the host board card can be met.

[0082] In the embodiment, the local memory includes a serial detection chip SPD, and the baseboard management controller BMC is connected to the serial detection chip SPD, and is configured to read the memory capacity obtained by the serial detection chip SPD. Specifically, the baseboard management controller BMC is connected to the serial detection chip SPD through I3C.

[0083] In the embodiment, the host board card is also provided with a second power-on controller CPLD_2 and a third voltage regulator corresponding to the CPU, and the second power-on controller CPLD_2 is connected to the baseboard management controller BMC and the third voltage regulator. In FIG. 2, the third voltage regulators VR_0 and VR_1 corresponding to the two CPUs CPU_0 and CPU_1 are shown, and the baseboard management controller BMC is connected to the second power-on controller CPLD_2 through I2C.

[0084] The CXL switch unit CXL SW is also configured to send a write completion signal to the micro control unit MCU after the CXL memory starting address is written into the register of the first port corresponding to the CPU. Specifically, the write completion signal is sent through I2C between the micro control unit MCU and the CXL switch unit CXL SW.

[0085] The micro control unit MCU is also configured to send a host power-on instruction to the baseboard management controller BMC after receiving the write completion signal, and the baseboard management controller BMC is also configured to send the host power-on instruction to the second power-on controller CPLD_2, and the second power-on controller CPLD_2 is configured to control the third voltage regulator to power on the corresponding CPU after receiving the host power-on instruction, and the CPU is powered on and establishes a communication link with the first port. The third voltage regulator sends a host power-on completion signal to the micro control unit MCU through the second power-on controller CPLD_2 and the baseboard management controller BMC after the power-on is completed.

[0086] Specifically, the micro control unit MCU sends a host node power-on signal to the baseboard management controller BMC through Eth, the BMC transmits the host power-on signal to the second power-on controller CPLD_2 through I2C, the second power-on controller CPLD_2 sends corresponding PWREN_0 and PWREN_1 to the third voltage regulator VR_0 and VR_1, the VR_0 and VR_1 output voltages to the CPU_0 and CPU_1 to complete initialization, the CPU_0 and CPU_1 establish a communication link with the first port USP_0 and USP_1 in the CXL switch unit CXL SW through the CXL bus, and then access the CXL memory. At the same time, the VR_0 and VR_1 output host power-on completion signals PWRGD_0 and PWRGD_1 to the second power-on controller CPLD_2, and the second power-on controller CPLD_2 forwards the power-on completion signal to the BMC through the I2C bus. The BMC forwards the host power-on completion signal to the MCU through Eth.

[0087] The micro control unit MCU is also connected with an indicator light, and the micro control unit MCU turns on the indicator light or changes the indicator light from red to green after receiving the host power-on completion signal, reminding the user that the CXL memory allocation has been completed.

[0088] In the embodiment, at least one CPU is connected with multiple first ports, and in the case that one CPU is connected with multiple first ports, multiple CXL memories can be accessed at the same time, the access efficiency of the CXL memory is improved, and the data processing bandwidth of the CPU is improved.

[0089] In this embodiment, the micro control unit MCU is further configured to acquire the local memory identifier while acquiring the memory capacity of the local memory corresponding to the CPU, and send (through I2C) the local memory identifier to the CXL switch unit CXL SW. The CXL switch unit CXL SW is configured to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table. The identifier mapping table records the mapping relationship between the first port identifier and the local memory identifier. Since the CPU corresponds to the local memory and the CPU is connected to the first port, the local memory identifier also corresponds to the first port identifier. By pre-setting the identifier mapping table in the CXL switch unit CXL SW, the CXL memory start address can be written into the register of the corresponding first port quickly and accurately without manually specifying the write port after the CXL memory start address is calculated.

[0090] The CXL switch unit CXL SW performs CXL memory allocation according to the built-in CXL memory allocation mechanism. To realize on-demand allocation, the CXL switch unit CXL SW pre-stores a first relationship table of the CPU identifier and the first port identifier, and a second relationship table of the CXL memory identifier and the second port identifier. The CXL switch unit CXL SW is further configured to acquire the CXL memory identifier and the remaining capacity in real time after the memory controller is powered on, and send the CXL memory identifier and the remaining capacity to the micro control unit MCU. The micro control unit MCU is further configured to acquire the CPU memory expansion demand and the CPU identifier in real time after the CPU is powered on, select a target CXL memory identifier corresponding to the remaining capacity with the smallest difference from the CPU memory expansion demand, and send the CPU identifier and the target CXL memory identifier to the CXL switch unit CXL SW. The CXL switch unit CXL SW is further configured to determine the target first port according to the CPU identifier and the first relationship table, determine the target second port according to the target CXL memory identifier and the second relationship table, and establish a data path between the CPU target first port and the target second port (as shown in FIG. 2, the physical connection between the first port and the second port in the CXL switch unit CXL SW is usually in a full connection form, and each first port and any second port can form a data path), thereby realizing on-demand allocation of CXL memory for the CPU, avoiding the problem that a small capacity needs to occupy a CXL memory with a large remaining capacity, and causing the single CXL memory usage rate and the memory fragmentation to be high.

[0091] In a case that the CPU memory expansion demand is greater than the remaining capacity of all the CXL memories, the micro control unit MCU is further configured to select a minimum number of target CXL memory identifiers, the sum of the remaining capacities of the CXL memories corresponding to the target CXL memory identifiers is greater than the CPU memory expansion demand, and send the CPU identifier and the corresponding target CXL memory identifiers to the CXL switch unit CXL SW. The CXL switch unit CXL SW determines the target first port and the target second ports according to the CPU identifier and the corresponding target CXL memory identifiers, the first relationship table and the second relationship table, and establishes a data path between the target first port and the target second ports. The minimum number of target CXL memory identifiers enables the CPU with a greater memory demand to allocate sufficient memory space from a smaller number of CXL memories, and the CPU accesses a smaller number of CXL memories, thereby improving the access efficiency of the CPU.

[0092] The CXL memory allocation method provided by the third embodiment of the present application is implemented based on the CXL memory allocation system described above, and is applied to a micro control unit MCU, as shown in FIG. 3, and the method comprises the following steps:

[0093] In step S310, the memory capacity of the local memory corresponding to the CPU is obtained after the CXL switch unit is powered on.

[0094] In step S320, the memory capacity is sent to the CXL switch unit, the memory capacity is used to instruct the CXL switch unit to calculate the CXL memory start address according to the memory capacity, and write the CXL memory start address into the register of the first port corresponding to the CPU, so as to take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board card to the CPU, or calculate the CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switch unit, the CXL memory start address is used to instruct the CXL switch unit to write the CXL memory start address into the register of the first port corresponding to the CPU, so as to take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board card to the CPU.

[0095] In this embodiment, step S310 specifically comprises:

[0096] After the CXL switch unit is powered on, the CXL memory board card is powered on.

[0097] After the CXL memory board card is powered on, the memory capacity of the local memory corresponding to the CPU is obtained. That is, after the CXL switch unit and the CXL memory board card are both powered on, the memory capacity of the local memory corresponding to the CPU is obtained again, so as to ensure the correctness of the CXL memory allocation timing and avoid the problem of CXL memory allocation failure caused by the unsuccessful power-on of the CXL memory board card after the memory capacity is obtained.

[0098] The CXL memory allocation method of the embodiment further includes: receiving a write completion signal sent by the CXL switch unit, and controlling the power-on of the CPU in the host board card, so that after the CPU is powered on, the CXL switch unit allocates the CXL memory in the CXL memory board card to the CPU with the CXL memory start address as the first address of the CXL memory. The write completion signal is sent by the CXL switch unit after the CXL memory start address is written into the register of the first port corresponding to the CPU. In the embodiment, the CPU is powered on after the CXL memory start address is written successfully, avoiding the problem of CXL memory allocation failure caused by the CXL memory start address not being written into the corresponding first port after the CPU is powered on.

[0099] Taking the CXL memory allocation system shown in FIG. 2 as an example, the CXL memory allocation method is explained from the perspective of the interaction between the host board card, the CXL switch board card and the CXL memory board card, and the CXL memory start address is calculated by the micro control unit MCU, as shown in FIG. 4, which includes:

[0100] Step S410: The user presses the power-on button PWR_button, and the first power-on controller CPLD_1 controls the first voltage regulator VR_SW to power on the CXL switch unit CXL SW. After the CXL switch unit CXL SW is powered on, the power-on completion signal is returned to the micro control unit MCU.

[0101] Step S420: The micro control unit MCU sends a memory controller power-on instruction, and the second voltage regulator is powered on after receiving the power-on instruction. The micro control unit MCU receives the memory controller power-on completion signal. Specifically, the two second voltage regulators VR_MXC_0 and VR_MXC_1 power on the two memory controllers MXC_0 and MXC_1 respectively, and receive the memory controller power-on completion signal returned by the second voltage regulators VR_MXC_0 and VR_MXC_1.

[0102] Step S430: The micro control unit MCU sends a memory capacity reading instruction to the baseboard controller BMC, and the BMC reads the SPD of the CPU local memory through I3C to obtain the memory capacity, and sends the memory capacity to the MCU. The MCU calculates the CXL memory start address according to the memory capacity, and sends the CXL memory start address to the CXL switch unit CXL SW. Specifically, the BMC reads the SPD of the CPU local memory through the I3C hub, and sends the memory capacity to the micro control unit MCU through the network. The micro control unit MCU sends the CXL memory start address to the CXL switch unit CXL SW through I2C.

[0103] Step S440: The CXL switch unit CXL SW writes the CXL memory start address into the register of the first port corresponding to the CPU, and sends a write completion signal to the micro control unit MCU. Specifically, the CXL switch unit CXL SW sends the write completion signal to the micro control unit MCU through I2C.

[0104] Step S450: The micro control unit MCU sends a CPU power-on instruction to the baseboard controller BMC, the baseboard controller BMC controls the CPU to power on, and sends a CPU power-on completion signal to the micro control unit MCU.

[0105] The CXL memory allocation method provided by the third embodiment of the present application further includes the steps that the micro control unit MCU acquires the local memory identifier while acquiring the memory capacity of the local memory corresponding to the CPU, and sends the local memory identifier to the CXL switch unit, and the CXL switch unit is configured to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table, and the identifier mapping table records the mapping relationship between the first port identifier and the local memory identifier.

[0106] Through the above process, the CXL memory allocation for the CPU is realized, and manual acquisition of the memory capacity of the local memory corresponding to the CPU is not required, and manual calculation of the register of the first port is not required, thereby reducing the labor cost, avoiding manual allocation errors, and improving the memory allocation efficiency of the entire CXL memory allocation system.

[0107] The CXL memory allocation device provided by the present application will be described below, and the CXL memory allocation device described below can be mutually referred to the CXL memory allocation method described above.

[0108] The CXL memory allocation device provided by the fourth embodiment of the present application is realized based on the CXL memory allocation system of the above-mentioned embodiments, and is applied to a micro control unit, as shown in FIG. 5, and the device includes:

[0109] The memory capacity acquisition module 510 is configured to acquire the memory capacity of the local memory corresponding to the CPU after the CXL switch unit is powered on.

[0110] The memory capacity processing module 520 is configured to send the memory capacity to the CXL switching unit, and the memory capacity is used to instruct the CXL switching unit to calculate the CXL memory start address according to the memory capacity, and write the CXL memory start address into the register of the first port corresponding to the CPU, so as to take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board card to the CPU, or calculate the CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switching unit, and the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, so as to take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board card to the CPU.

[0111] In the CXL memory allocation device, after the CXL switching unit is powered on, the micro control unit automatically acquires the memory capacity of the local memory corresponding to the CPU, and the micro control unit or the CXL switching unit calculates the CXL memory start address according to the memory capacity, and the CXL switching unit automatically writes the CXL memory start address into the register of the first port, so as to realize automatic allocation of the CXL memory to the CPU, and manual acquisition of the memory capacity of the local memory corresponding to the CPU is not required, and manual calculation of the register of the first port is not required, labor cost is reduced, manual allocation errors are avoided, and memory allocation efficiency of the entire CXL memory allocation system is improved.

[0112] Optionally, the memory capacity acquisition module 510 is specifically configured to control the CXL memory board card to be powered on after the CXL switching unit is powered on; and acquire the memory capacity of the local memory corresponding to the CPU after the CXL memory board card is powered on.

[0113] Optionally, the CXL memory allocation device further comprises:

[0114] The host power-on control module is configured to receive a write completion signal sent by the CXL switching unit, and control the CPU in the host board card to be powered on, so that, after the CPU is powered on, the CXL switching unit allocates the CXL memory in the CXL memory board card to the CPU by taking the CXL memory start address as the first address of the CXL memory; and the write completion signal is sent by the CXL switching unit after the CXL memory start address is written into the register of the first port corresponding to the CPU.

[0115] In another aspect, the present application also provides a computer readable instruction product, which comprises computer readable instructions, the computer readable instructions can be stored on a non-transient computer readable storage medium, and the computer readable instructions can be executed by a processor to enable the computer to perform the CXL memory allocation method provided by each method, and the method comprises the following steps of:

[0116] After the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is acquired.

[0117] The memory capacity is sent to the CXL switching unit, and the memory capacity is used to instruct the CXL switching unit to calculate the CXL memory start address according to the memory capacity, and write the CXL memory start address into the register of the first port corresponding to the CPU, and take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board to the CPU, or calculate the CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switching unit, and the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board to the CPU.

[0118] In another aspect, the application also provides one or more non-volatile computer readable storage media storing computer readable instructions, which are executed by one or more processors to make the one or more processors execute the CXL memory allocation method provided by the above-mentioned methods, and the method comprises:

[0119] After the CXL switching unit is powered on, the memory capacity of the local memory corresponding to the CPU is acquired.

[0120] The memory capacity is sent to the CXL switching unit, and the memory capacity is used to instruct the CXL switching unit to calculate the CXL memory start address according to the memory capacity, and write the CXL memory start address into the register of the first port corresponding to the CPU, and take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board to the CPU, or calculate the CXL memory start address according to the memory capacity, and send the CXL memory start address to the CXL switching unit, and the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, and take the CXL memory start address as the first address of the CXL memory, and allocate the CXL memory in the CXL memory board to the CPU.

[0121] In yet another aspect, the present application provides a microcontroller comprising a memory and one or more processors, the memory storing computer readable instructions which, when executed by the one or more processors, cause the one or more processors to perform the CXL memory allocation method provided by any of the above embodiments. The apparatus embodiments described above are merely exemplary, in which the units as shown can or can not be physical units, and the units as shown can or can not be the physical units, that is, they can be located in one place or distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art can understand and implement it without creative labor.

[0122] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary general hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in the sense of contribution to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of the various embodiments or some parts of the methods.

[0123] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

A CXL switch board card characterized by, The CXL exchange card is provided with a CXL exchange unit and a micro control unit connected with the CXL exchange unit, the CXL exchange unit comprises at least one first port and at least one second port, the first port is used for connecting a CPU, and the second port is used for connecting a CXL memory card to obtain CXL memory in the CXL memory card; The micro control unit is used for obtaining the memory capacity of the local memory corresponding to the CPU after the CXL exchange unit is powered on, and the micro control unit or the CXL exchange unit is used for calculating a CXL memory start address according to the memory capacity; The CXL exchange unit is used for writing the CXL memory start address into a register of the first port corresponding to the CPU, and allocating CXL memory in the CXL memory card to the CPU as the first address of the CXL memory. The CXL switch board card of claim 1, wherein, The CXL exchange card is further provided with a first voltage regulator and a first power-on controller, the first power-on controller is connected with the micro control unit and the first voltage regulator, the first voltage regulator is connected with the CXL exchange unit, the first power-on controller is used for controlling the first voltage regulator to supply power to the CXL exchange unit, and the first voltage regulator feeds back a CXL exchange unit power-on completion signal to the first power-on controller after the CXL exchange unit is powered on, and the first power-on controller feeds back the CXL exchange unit power-on completion signal to the micro control unit. The CXL switch card of claim 2, wherein, The micro control unit is used for controlling the CXL memory card to be powered on after receiving the CXL exchange unit power-on completion signal, and obtaining the memory capacity of the local memory corresponding to the CPU. The CXL switch board card according to any one of claims 1 to 3, characterized in that, The CXL exchange unit is further used for sending a write completion signal to the micro control unit after writing the CXL memory start address into the register of the first port corresponding to the CPU, and the micro control unit is further used for controlling the CPU to be powered on after receiving the write completion signal, and the CXL exchange unit allocates CXL memory in the CXL memory card to the CPU as the first address of the CXL memory after the CPU is powered on. A CXL memory allocation system, characterized by, Comprise: A host card, a CXL exchange card and a CXL memory card, the host card is provided with at least one CPU and local memory corresponding to the CPU respectively, the CXL exchange card is provided with a CXL exchange unit and a micro control unit connected with the CXL exchange unit, the CXL exchange unit comprises at least one first port and at least one second port, each CPU is connected with the first port respectively, one first port is connected with only one CPU, and the CXL exchange unit is connected with the CXL memory card through the second port to obtain CXL memory in the CXL memory card; The micro control unit is used for obtaining the memory capacity of the local memory corresponding to the CPU after the CXL exchange unit is powered on, and the micro control unit or the CXL exchange unit is used for calculating a CXL memory start address according to the memory capacity; The CXL exchange unit is used for writing the CXL memory start address into a register of the first port corresponding to the CPU, and allocating CXL memory in the CXL memory card to the CPU as the first address of the CXL memory. The CXL switching unit is configured to write the CXL memory start address into a register of a first port corresponding to the CPU, so as to allocate CXL memory in a CXL memory board to the CPU as a starting address of CXL memory. The CXL memory allocation system of claim 5, wherein, The CXL switching board further comprises a first voltage regulator and a first power-on controller, the first power-on controller is connected to the micro control unit and the first voltage regulator, the first voltage regulator is connected to the CXL switching unit, the first power-on controller is configured to control the first voltage regulator to supply power to the CXL switching unit, and the first voltage regulator feeds back a CXL switching unit power-on completion signal to the first power-on controller after the CXL switching unit is powered on, and the first power-on controller feeds back the CXL switching unit power-on completion signal to the micro control unit. The CXL memory allocation system of claim 5, wherein, The CXL memory board further comprises at least one CXL memory, a memory controller corresponding to the CXL memory, and a second voltage regulator, the memory controller is connected to the corresponding CXL memory and the second voltage regulator, and the micro control unit is connected to the second voltage regulator. The second port is connected to the memory controller, one memory controller is connected to one second port, and the CXL switching unit is configured to establish a communication link based on the second port and the memory controller after the memory controller is powered on, and feed back a communication link completion signal to the micro control unit, and the CXL switching unit is configured to obtain the CXL memory through the second port after the communication link is established. The CXL memory allocation system of claim 7, wherein, At least one second port is connected to a plurality of memory controllers. The CXL memory allocation system of claim 5, wherein, The host board further comprises a baseboard controller connected to the micro control unit and the local memory. The micro control unit is configured to send a memory capacity reading instruction to the baseboard controller after the CXL memory board is powered on, and the baseboard controller is configured to obtain the memory capacity of the local memory corresponding to the CPU after receiving the memory capacity reading instruction, and send the memory capacity to the micro control unit. The CXL memory allocation system of claim 9, wherein, The host board further comprises an I3C hub, and the baseboard controller is connected to the local memories corresponding to the plurality of CPUs through the I3C hub. The CXL memory allocation system of claim 9, wherein, The local memory comprises a serial detection chip, and the baseboard controller is connected to the serial detection chip and configured to read the memory capacity obtained by the serial detection chip. The CXL memory allocation system of claim 9, wherein, The host board further comprises a second power-on controller and a third voltage regulator corresponding to the CPU, and the second power-on controller is connected to the baseboard controller and the third voltage regulator. The CXL switching unit is further configured to send a write completion signal to the micro control unit after writing the CXL memory start address into the register of the first port corresponding to the CPU. The micro control unit is also used to send a host power-on instruction to the substrate controller after receiving the write completion signal, the substrate controller is also used to send the host power-on instruction to the second power-on controller, the second power-on controller is used to control the third voltage regulator to power on the corresponding CPU after receiving the host power-on instruction, the CPU is powered on and establishes a communication link with the first port, and the third voltage regulator sends a host power-on completion signal to the micro control unit through the second power-on controller and the substrate controller after the power-on is completed. The CXL memory allocation system of claim 5, wherein, At least one of the CPUs is connected to a plurality of the first ports. The CXL memory allocation system of any of claims 5-13, wherein, The micro control unit is also used to obtain a local memory identifier while obtaining the memory capacity of the local memory corresponding to the CPU, and send the local memory identifier to the CXL switching unit, and the CXL switching unit is used to write the CXL memory start address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table, and the identifier mapping table records the mapping relationship between the first port identifier and the local memory identifier. A CXL memory allocation method, characterized in that, The CXL memory allocation system implementation based on any one of claims 5 to 14 is applied to the micro control unit, and the method comprises: After the CXL switching unit is powered on, obtaining the memory capacity of the local memory corresponding to the CPU; and The memory capacity is sent to the CXL switching unit, the memory capacity is used to instruct the CXL switching unit to calculate a CXL memory start address according to the memory capacity, and write the CXL memory start address into the register of the first port corresponding to the CPU, so that the CXL memory start address is used as the first address of the CXL memory, and the CXL memory in the CXL memory board is allocated to the CPU, or the CXL memory start address is calculated according to the memory capacity and sent to the CXL switching unit, the CXL memory start address is used to instruct the CXL switching unit to write the CXL memory start address into the register of the first port corresponding to the CPU, so that the CXL memory start address is used as the first address of the CXL memory, and the CXL memory in the CXL memory board is allocated to the CPU. The CXL memory allocation method of claim 15, wherein, After the CXL switching unit is powered on, obtaining the memory capacity of the local memory corresponding to the CPU, comprises: After the CXL switching unit is powered on, controlling the CXL memory board to be powered on; and After the CXL memory board is powered on, obtaining the memory capacity of the local memory corresponding to the CPU. The CXL memory allocation method of claim 15, wherein, Further comprising: Receiving the write completion signal sent by the CXL switching unit, controlling the CPU in the host board to be powered on, so that after the CPU is powered on, the CXL switching unit allocates the CXL memory in the CXL memory board to the CPU with the CXL memory start address as the first address of the CXL memory; The write completion signal is sent by the CXL switching unit after the CXL memory start address is written into the register of the first port corresponding to the CPU. The CXL memory allocation method of claim 15, wherein, Further comprising: When the memory capacity of the local memory corresponding to the CPU is acquired, a local memory identifier is acquired and sent to the CXL switching unit, and the CXL switching unit is used to write the CXL memory starting address into the register of the first port corresponding to the local memory identifier according to a preset identifier mapping table, and the identifier mapping table records the mapping relationship between the first port identifier and the local memory identifier. [Rule 91 amendment 13.08.2025] One or more non-transitory computer-readable storage media storing computer-readable instructions, wherein the instructions, when executed by one or more computer processors, cause the one or more computer processors to perform any of the methods described herein, The computer readable instructions, when executed by one or more processors, cause the one or more processors to perform the steps of the method of any one of claims 15 to 17. A microcontroller, characterized by A computer readable medium having stored the computer readable instructions, the computer readable instructions, when executed by one or more processors, cause the one or more processors to perform the steps of the method of any one of claims 15 to 17.

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