Semiconductor device

Abstract

Provided is a semiconductor device that includes a transistor having a large ON-state current. The semiconductor device includes: a semiconductor layer; a first conductive layer; a second conductive layer; and a first insulative layer. The first insulative layer is positioned above the first conductive layer. The second conductive layer is positioned above the first insulative layer. The first insulative layer and the second conductive layer include an opening reaching the first conductive layer. The semiconductor layer includes: a first region adjoining the first conductive layer in the opening; a second region adjoining a lateral surface of the first insulative layer in the opening; and a third region adjoining the second conductive layer. The semiconductor layer includes crystal grains. The crystal grains have regions located in the first region, the second region, and the third region. The semiconductor layer preferably has indium and oxygen.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a semiconductor device including a transistor.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, there has been a demand for high-definition display devices. Devices requiring high-definition display devices, such as devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), have been actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also referred to as light-emitting devices). Examples of light-emitting elements include organic electroluminescence (EL) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using organic EL elements.

[0006] Technologies related to transistors using semiconductor thin films have been attracting attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention.

[0007] Examples of oxide semiconductors that can be used in transistors include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin film transistor using hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization.

[0008] International Publication No. 2016 / 038508

[0009] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a manufacturing method of the above-described transistor, semiconductor device, or display device. Another object is to provide a highly productive manufacturing method of a transistor, semiconductor device, or display device. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer have openings that reach the first conductive layer. The semiconductor layer has a first region that contacts the first conductive layer in the opening, a second region that contacts a side surface of the first insulating layer in the opening, and a third region that contacts the second conductive layer. The semiconductor layer has crystal grains. The crystal grains have regions located in the first region, the second region, and the third region.

[0013] In the above-described semiconductor device, the semiconductor layer preferably contains indium and oxygen. The first conductive layer is preferably polycrystalline. The first conductive layer preferably contains indium, tin, and oxygen. The second conductive layer is preferably amorphous. The second conductive layer preferably contains indium, tin, silicon, and oxygen.

[0014] In the above-described semiconductor device, the semiconductor layer preferably contains indium and oxygen. The first conductive layer is preferably amorphous. The first conductive layer preferably contains indium, tin, silicon, and oxygen. The second conductive layer is preferably polycrystalline. The second conductive layer preferably contains indium, tin, and oxygen.

[0015] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer have an opening that reaches the first conductive layer. The semiconductor layer has a first region that contacts the first conductive layer in the opening, a second region that contacts a side surface of the first insulating layer in the opening, and a third region that contacts the second conductive layer. The semiconductor layer has a first crystal grain and a second crystal grain. The first crystal grain has a region located in the first region and the second region. The second crystal grain has a region located in the second region and the third region. The grain boundary between the first crystal grain and the second crystal grain has a region located in the second region.

[0016] In the semiconductor device, the semiconductor layer preferably contains indium and oxygen. The first conductive layer and the second conductive layer are preferably polycrystalline. The first conductive layer and the second conductive layer preferably contain indium, tin, and oxygen.

[0017] The aforementioned semiconductor device preferably includes a second insulating layer. The second insulating layer preferably has a region in contact with the lower surface of the first conductive layer. The first insulating layer preferably includes a third insulating layer and a fourth insulating layer on the third insulating layer. The second insulating layer preferably includes silicon, nitrogen, and hydrogen. The third insulating layer preferably includes silicon and nitrogen. The fourth insulating layer preferably includes silicon and oxygen. The second insulating layer preferably includes a region having a higher hydrogen content than the third insulating layer.

[0018] In the semiconductor device described above, the first insulating layer preferably includes a fifth insulating layer on the fourth insulating layer, and the fifth insulating layer preferably includes silicon and nitrogen.

[0019] In the semiconductor device described above, the first insulating layer preferably includes a fifth insulating layer on the fourth insulating layer, and the fifth insulating layer preferably includes aluminum and oxygen.

[0020] According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a manufacturing method for the above-described transistor, semiconductor device, or display device can be provided. Alternatively, a highly productive manufacturing method for a transistor, semiconductor device, or display device can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0022] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIG. 3A is a cross-sectional view showing an example of a semiconductor device. FIGS. 3B and 3C are perspective views showing an example of a semiconductor device. FIGS. 4A to 4C are cross-sectional and perspective views showing an example of a method for manufacturing a semiconductor device. FIGS. 5A to 5C are cross-sectional and perspective views showing an example of a method for manufacturing a semiconductor device. FIGS. 6A and 6B are perspective views showing an example of a semiconductor device. FIGS. 7A to 7C are cross-sectional and perspective views showing an example of a method for manufacturing a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIG. 9A is a top view showing an example of a semiconductor device. FIG. 9B is a cross-sectional view showing an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are equivalent circuit diagrams of a semiconductor device. FIG. 11C is a top view showing an example of a semiconductor device. FIG. 12 is a cross-sectional view showing an example of a semiconductor device. FIG. 13 is a perspective view showing an example of a semiconductor device. FIGS. 14A to 14D are perspective views showing an example of a semiconductor device. FIGS. 15A to 15E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 16A to 16D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 17A to 17D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 18A and 18B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 18C is a cross-sectional view illustrating an indium oxide film. FIG. 19A is a perspective view showing an example of a display device. FIG. 19B is a block diagram showing an example of a display device. FIGS. 20A to 20E are circuit diagrams of pixel circuits. FIGS. 21A and 21B are circuit diagrams of pixel circuits. FIGS. 22A and 22B are circuit diagrams of pixel circuits. FIGS. 23A and 23B are cross-sectional views showing an example of a display device. FIG. 24 is a cross-sectional view showing an example of a display device. FIG. 25 is a cross-sectional view showing an example of a display device. FIGS. 26A to 26C are cross-sectional views showing an example of a display device. 27A and 27B are cross-sectional views showing an example of a display device, Fig. 28 is a cross-sectional view showing an example of a display device, and Fig. 29 is a cross-sectional view showing an example of a display device.FIG. 30 is a cross-sectional view showing an example of a display device. FIGS. 31A to 31D are views showing an example of an electronic device. FIGS. 32A to 32F are views showing an example of an electronic device. FIGS. 33A to 33G are views showing an example of an electronic device. FIGS. 34A to 34D are TEM images of a sample according to an example. FIG. 35A is a TEM image of a sample according to an example. FIGS. 35B to 35D are TEM images and electron diffraction patterns of a sample according to an example. FIG. 36A is a TEM image of a sample according to an example. FIGS. 36B to 36D are TEM images and electron diffraction patterns of a sample according to an example. FIG. 37A is a TEM image of a sample according to an example. FIGS. 37B to 37D are TEM images and electron diffraction patterns of a sample according to an example. FIGS. 38A and 38C are TEM images of a sample according to an example. FIGS. 38B and 38D are TEM images and electron diffraction patterns of a sample according to an example. Fig. 39A is a TEM image of a sample according to an example. Figs. 39B to 39D are TEM images and electron diffraction patterns of a sample according to an example. Fig. 40A is a TEM image of a sample according to an example. Figs. 40B to 40D are TEM images and electron diffraction patterns of a sample according to an example. Fig. 41A is a TEM image of a sample according to an example. Figs. 41B to 41D are TEM images and electron diffraction patterns of a sample according to an example.

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0025] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0026] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between the components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0027] In this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m, n]" may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which an identification numeral is added, or when it is not necessary to distinguish between them, the elements may be described without the identification numeral.

[0028] The words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0029] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0030] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0031] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0032] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0033] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0034] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0035] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0036] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and the source (also referred to as gate voltage, Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0037] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0038] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0039] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0040] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0041] In this specification, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as a taper angle.

[0042] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0043] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer is physically separated from the adjacent metal oxide layer.

[0044] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0045] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0046] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element has a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer functioning as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0047] In this specification and the like, flexibility refers to the property of an object being soft and bendable, i.e., the property of an object being able to deform in response to an external force applied to the object, regardless of whether or not the object has elasticity or the ability to return to its original shape before deformation.

[0048] For example, a flexible electronic device can deform in response to an external force. A flexible electronic device can be used while fixed in a deformed state, or can be used after repeatedly deforming. A flexible display device (also referred to as a flexible display device, flexible display device, flexible display, etc.) can deform in response to an external force. A flexible display device can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible battery (also referred to as a flexible battery, flexible battery, flexible battery, etc.) can deform in response to an external force. A flexible battery can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible substrate (also referred to as a flexible substrate, flexible substrate, etc.) can deform in response to an external force. A flexible substrate can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. Note that the above phrase "deform in response to an external force" refers to deformation by an average adult's hand without requiring excessive force. Flexibility can be evaluated using a testing machine capable of performing stress-strain measurements (such as a tensile testing machine or a compression testing machine). In stress-strain measurements, an external force is applied to an object, and the strain of the object caused by the resulting stress is measured, thereby making it possible to quantify the flexibility of the object.

[0049] In this specification, when an object is described as having flexibility, it means that at least a part of the object has flexibility. In other words, a flexible object may have a non-flexible part (also called a hard part).

[0050] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0051] 1A to 17D , a semiconductor device according to one embodiment of the present invention can be suitably used for, for example, one or both of a pixel circuit and a driver circuit of a display device.

[0052] <Configuration Example 1> A top view (also referred to as a plan view) of a semiconductor device 10 is shown in FIG. 1A. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view of a cut surface taken along dashed dotted line B1-B2. Note that some components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some components are also omitted in the top views of the semiconductor device in the subsequent drawings. FIGS. 2A to 2D show perspective views of the semiconductor device 10. FIG. 2B shows a cross-sectional view taken along dashed dotted line C1-C2 in FIG. 2A. In FIG. 2C, the insulating layer shown in FIG. 2A is shown transparently, with its outline indicated by a dashed line. Similarly, in FIG. 2D, the insulating layer shown in FIG. 2B is shown transparently, with its outline indicated by a dashed line.

[0053] The semiconductor device 10 includes a transistor 100 and an insulating layer 110. The semiconductor device 10 is provided on an insulating surface. FIG. 1B and other figures show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film.

[0054] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. In the semiconductor layer 108, a region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region. In the semiconductor layer 108, the channel formation region is located between the source region and the drain region.

[0055] A conductive layer 112a is provided on a substrate 102, an insulating layer 110 is provided on the conductive layer 112a, and a conductive layer 112b is provided on the insulating layer 110. The insulating layer 110 is in contact with the conductive layer 112a and the conductive layer 112b and has a region sandwiched between them. The conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141. The conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141. Note that in FIG. 1A and other drawings, the opening 141 in the insulating layer 110 and the opening 143 in the conductive layer 112b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 112b have openings that reach the conductive layer 112a.

[0056] The semiconductor layer 108 is provided to cover the openings 141 and 143. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a and the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.

[0057] The insulating layer 106, which functions as a gate insulating layer of the transistor 100, is provided to cover the openings 141 and 143. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the top surface of the insulating layer 110, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 108, and the top surface of the conductive layer 112a.

[0058] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106.

[0059] In the transistor 100, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor 100 is formed, and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows vertically in the transistor 100. Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like. The conductive layer 112a can be called a lower electrode of the transistor, and the conductive layer 112b can be called an upper electrode. Since the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner in the VFET, the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0060] The semiconductor layer 108 is preferably formed using a metal oxide (also referred to as an oxide semiconductor (OS)) that exhibits semiconductor characteristics. A transistor using an oxide semiconductor for a channel formation region (hereinafter also referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. In addition, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device. Note that a transistor using silicon for a channel formation region may be referred to as a Si transistor.

[0061] The semiconductor layer 108 preferably has crystallinity. That is, the semiconductor layer 108 preferably has crystal grains. Examples of films having crystal grains include a single crystal film, a polycrystalline film, and an amorphous film containing crystal grains. Note that a single crystal film can be said to be a film having one crystal grain. It is preferable to use a crystalline oxide semiconductor for the semiconductor layer 108 because this can suppress deterioration of transistor characteristics. The semiconductor layer 108 preferably has high crystallinity, and is preferably a polycrystalline film or a single crystal film. It is more preferable that the semiconductor layer 108 be a single crystal film.

[0062] A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities and insulating oxides) that hinder carrier flow tend to segregate at grain boundaries, resulting in uneven distribution of the impurities. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, resulting in a transistor with high field-effect mobility. Furthermore, variations in transistor characteristics due to grain boundaries can be suppressed.

[0063] A polycrystalline film can reduce impurity scattering compared to a microcrystalline film and an amorphous film, resulting in a transistor with high field-effect mobility. When a polycrystalline film is used for the semiconductor layer 108, the grain size of the crystal grains contained in the semiconductor layer 108 is preferably large. Using a polycrystalline film with large grain size can reduce the number of grain boundaries located in the channel formation region and shorten the length of the grain boundaries located in the channel formation region, resulting in a transistor with high field-effect mobility. Furthermore, it is preferable that the number of grain boundaries intersecting the direction of the drain current flow (also referred to as the channel length direction) in the channel formation region be small. Reducing the number of grain boundaries across the current path between the source and drain regions can result in a transistor with high field-effect mobility. Even in the case of a polycrystalline film, if no grain boundaries are located in the channel formation region, the channel formation region is located within a single-crystal region included in the polycrystalline film, thereby achieving the same effect as when a single-crystal film is used for the semiconductor layer. The crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0064] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film.Furthermore, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0065] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0066] The crystal grains contained in the semiconductor layer 108 can be confirmed by, for example, a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), or an electron backscatter diffraction pattern (EBSD or EBSP). Alternatively, analysis can be performed by combining a plurality of these techniques. The crystal grain boundaries can sometimes be confirmed by, for example, a high-resolution TEM. That is, crystal grains and crystal grain boundaries can sometimes be confirmed in a high-resolution TEM image. The magnification in TEM observation is preferably 2 million times or more, and more preferably 4 million times or more. The grain size of a crystal grain can be, for example, the average value of the grain sizes of a plurality of crystal grains. The grain size of a crystal grain can also be, for example, the diameter of a circle having the same area as the area of ​​the crystal grain. The diameter in this case is sometimes called the circle equivalent diameter.

[0067] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a TEM image, if the crystal orientations of the two crystal grains are identical or approximately identical, the boundary may not be called a grain boundary. Furthermore, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same crystal grain.

[0068] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). In addition, space group numbers in the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be assigned. Crystal planes and crystal directions are also expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal directions are expressed with a bar above the number. However, due to formatting restrictions, in this specification, instead of a bar above the number, a minus sign (-) may be placed before the number. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent directions with < >, individual planes indicating crystal planes with ( ), and collective planes with equivalent symmetry with {}. Even if the space group number is the same, the space group notation may differ depending on how the crystal axes are arranged.

[0069] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of a substrate. For example, a crystal with a <100> crystal orientation is said to be a crystal with its (100) plane parallel to the surface of the substrate.

[0070] The semiconductor layer 108 preferably contains indium and oxygen. The semiconductor layer 108 preferably contains indium oxide. By using an oxide semiconductor with a high indium content for the semiconductor layer of a transistor, the transistor can have high field-effect mobility. Therefore, the transistor can have a large on-state current. A polycrystalline indium oxide film is preferably used for the semiconductor layer 108, and a single-crystalline indium oxide film is more preferably used.

[0071] In addition, cubic In ２ O ３ The crystal structure of this compound belongs to space group Ia-3 (space group number 206). In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal or a cubic structure. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0072] The crystal grains contained in the semiconductor layer 108 can be observed, for example, with an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating unevenness on the surface of the semiconductor layer 108 using an etchant whose etching rate varies depending on the crystal plane or crystallinity, the crystal grains can be easily observed with an optical microscope or a scanning electron microscope (SEM). When an indium oxide film is used as the semiconductor layer 108, the crystal grains of the indium oxide can be easily observed by using an etchant containing an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid. Note that if the etching rate is too fast, part of the semiconductor layer 108 may be lost, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by adjusting the concentration, temperature, and treatment time of the etchant so that the semiconductor layer 108 is thinned without being lost (also referred to as half etching). By performing half etching, the crystal grains can be easily observed.

[0073] 3A shows a cross-sectional view of the semiconductor device 10. 3B and 3C show perspective views of the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, the insulating layer 110, and the substrate 102. 3C shows a cross section taken along the dashed dotted line D1-D2 shown in FIG. 3B.

[0074] As shown in FIG. 3A , the semiconductor layer 108 has a region 108P that is in contact with the conductive layer 112a in the opening 141, a region 108Q that is in contact with the insulating layer 110 in the opening 141, and a region 108R that is in contact with the conductive layer 112b. In the transistor 100, the region 108P functions as one of the source region and the drain region, and the region 108R functions as the other of the source region and the drain region. The channel formation region of the transistor 100 is located in the region 108Q. Note that although the cross-sectional views such as FIG. 3A show two regions of the semiconductor layer 108 that are in contact with the insulating layer 110 in the opening 141, these regions are actually connected to one another. Similarly, in the opening 143, the region of the semiconductor layer 108 that is in contact with the conductive layer 112b is also connected to one another.

[0075] 3B and 3C show an example in which the semiconductor layer 108 has multiple crystal grains 103. One crystal grain 103 has a portion located in region 108P, a portion located in region 108Q, and a portion located in region 108R. It can be said that one crystal grain 103 spans regions 108P, 108Q, and 108R. The grain boundary 105 between two crystal grains 103 extends in region 108Q from region 108P toward region 108R (or from region 108R toward region 108P). This reduces the number of grain boundaries 105 intersecting the channel length direction in the channel formation region.

[0076] Note that the size, shape, and position of the crystal grains 103 and the shape and position of the crystal grain boundaries 105 shown in FIGS. 3B and 3C are merely examples, and one embodiment of the present invention is not limited to these.

[0077] The conductive layer 112a or the conductive layer 112b preferably has crystallinity. That is, the conductive layer 112a or the conductive layer 112b preferably has crystal grains. A microcrystalline film, a polycrystalline film, or a single crystalline film can be used as the conductive layer 112a or the conductive layer 112b, and a polycrystalline film or a single crystalline film is more preferable. The conductive layer 112a or the conductive layer 112b functions as a seed crystal that increases the crystallinity of the semiconductor layer 108 during the formation of the semiconductor layer 108. Note that in this specification and the like, a layer that functions as a seed crystal may be referred to as a seed crystal layer.

[0078] The seed crystal layer is preferably made of, for example, a metal oxide containing the same metal element as the semiconductor layer 108 .

[0079] Examples of the seed crystal layer include indium oxide, tin oxide, In—Sn oxide (indium tin oxide, also referred to as ITO), In—Zn oxide, In—Ga oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (silicon-containing ITO, also referred to as ITSO), and In—Ga—Zn oxide (IGZO). Oxide conductors containing indium are preferred due to their high conductivity. For example, ITO is highly conductive and can easily be used as a polycrystalline or single-crystalline film for the seed crystal layer. When the seed crystal layer has a stacked structure, it is preferable to use a material that functions as a seed crystal for at least the layer in contact with the semiconductor layer 108.

[0080] When one of the conductive layers 112a and 112b functions as a seed crystal, the other of the conductive layers 112a and 112b preferably has lower crystallinity than the other of the conductive layers 112a and 112b. The lower the crystallinity of the other of the conductive layers 112a and 112b, the more preferable it is, and an amorphous film can be suitably used as the other of the conductive layers 112a and 112b.

[0081] Compared to ITO, ITSO has lower crystallinity and is therefore suitable for use as the other of the conductive layers 112a and 112b. The silicon content in ITSO is preferably 1 atomic % to 20 atomic %, more preferably 3 atomic % to 20 atomic %, even more preferably 3 atomic % to 15 atomic %, and even more preferably 5 atomic % to 15 atomic %. Typically, metal oxides with an atomic ratio of In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. If the silicon content is too low, the ITSO may have high crystallinity, while if the silicon content is too high, the ITSO may have low conductivity. By setting the silicon content in ITSO within the aforementioned range, high conductivity and low crystallinity (e.g., amorphous) can be achieved. The silicon content in ITSO is not limited to the above range. Here, the silicon content is defined as the ratio of the number of silicon atoms to the sum of the numbers of indium, tin, and silicon atoms in ITSO.

[0082] When one of the conductive layers 112a and 112b functions as a seed crystal, the silicon content in the other of the conductive layers 112a and 112b is preferably higher than the silicon content in one of the conductive layers 112a and 112b. For example, polycrystalline ITO can be used for one of the conductive layers 112a and 112b, and amorphous ITSO can be used for the other of the conductive layers 112a and 112b.

[0083] By using a polycrystalline film or a single-crystalline film as one of the conductive layers 112a and 112b and an amorphous film as the other of the conductive layers 112a and 112b, crystallization in the layer that will become the semiconductor layer 108 progresses from a region in contact with one of the conductive layers 112a and 112b to a region in contact with the other. This allows crystal grains 103 to be formed across the regions 108P, 108Q, and 108R. Therefore, the generation of crystal grain boundaries 105 that intersect with the channel length direction in the channel formation region can be suppressed. Furthermore, the generation of crystal nuclei (hereinafter also referred to as natural nuclei) not resulting from the seed crystal layer can be suppressed in the region in contact with the other of the conductive layers 112a and 112b in the layer that will become the semiconductor layer 108, thereby suppressing the inclusion of crystal grains resulting from natural nuclei in the region. It is preferable that the semiconductor layer 108 contains crystal grains 103 that extend across the regions 108P, 108Q, and 108R, and the semiconductor layer 108 may also contain crystal grains resulting from natural nuclei.

[0084] The seed crystal layer is preferably made of a material containing crystals with a small difference in lattice constant (also referred to as lattice mismatch) with the material constituting the semiconductor layer 108. This makes it easier for epitaxial growth to occur in the layer that will become the semiconductor layer 108 when the layer is formed over the seed crystal layer, and makes it easier for the layer to be crystallized.

[0085] One method for evaluating the degree of lattice mismatch is the lattice mismatch ratio. The lattice mismatch ratio Δa [%] of the crystals of the formed film to the crystals of the film to be formed is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film (here, the layer that will become the semiconductor layer 108), and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the film to be formed (here, the seed crystal layer).

[0086] The smaller the absolute value of the lattice mismatch Δa between the seed crystal layer and the semiconductor layer 108, the more preferable, and it is most preferably 0. For example, the lattice mismatch Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0087] When indium oxide having a cubic crystal structure is used for the semiconductor layer 108, the crystal structure of the seed crystal layer is preferably, for example, a cubic crystal structure, a hexagonal crystal structure, or a trigonal crystal structure. Note that the crystal structure of the seed crystal layer is not particularly limited.

[0088] An amorphous film is preferably used as the insulating layer 110. This can prevent crystal nuclei not resulting from the seed crystal layer from being generated in a region of the layer to be the semiconductor layer 108 that is in contact with the insulating layer 110.

[0089] 4A to 4C, the formation of the semiconductor layer 108 will be described. Cross-sectional views are shown on the left side of each of FIGS. 4A to 4C, and perspective views are shown on the right side. Here, a structure in which a polycrystalline film is used for the conductive layer 112b and an amorphous film is used for the conductive layer 112a will be described as an example.

[0090] As shown in FIG. 4A, a metal oxide layer 108F that will become the semiconductor layer 108 is formed on the conductive layer 112a, the conductive layer 112b, and the insulating layer 110.

[0091] The metal oxide layer 108F can be formed by depositing a metal oxide film that will become the semiconductor layer 108 and processing the metal oxide film. The metal oxide film is preferably deposited by a sputtering method using a metal target or a metal oxide target. Alternatively, the metal oxide film is preferably deposited by an atomic layer deposition (ALD) method. By using the ALD method, a metal oxide film can be deposited with high coverage on the side surfaces of the insulating layer 110 and the conductive layer 112b. Furthermore, the ALD method allows easy control of the deposition rate, allowing thin films to be deposited with high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Alternatively, a chemical vapor deposition (CVD) method can be used to deposit the metal oxide film.

[0092] When forming a metal oxide film, an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used, or a mixture of oxygen gas and an inert gas can be used.

[0093] The metal oxide film is preferably formed under conditions that result in low crystallinity of the metal oxide film. The ratio of the flow rate of oxygen gas to the total film-forming gas (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber of the film-forming apparatus when forming the metal oxide film is preferably low. For example, the oxygen flow rate ratio in forming the metal oxide film is preferably 0% or more and 10% or less, more preferably 0% or more and 5% or less, and even more preferably 0% or more and 3% or less. When a reactive sputtering method using a metal target (e.g., an indium target) is used to form the metal oxide film, the oxygen flow rate ratio is preferably more than 0% and 10% or less, more preferably more than 0% and 5% or less, and even more preferably more than 0% and 3% or less.

[0094] By using oxygen gas when forming the metal oxide film (i.e., by increasing the oxygen flow rate ratio to more than 0%), it is possible to suppress the occurrence of oxygen vacancies in the metal oxide film. Furthermore, oxygen can be supplied into the insulating layer 110 when forming the metal oxide film. As a result, oxygen is supplied to the semiconductor layer 108 in a later step, and oxygen vacancies in the semiconductor layer 108 and defects in which hydrogen has entered the oxygen vacancies (hereinafter referred to as V Ｏ H) can be reduced.

[0095] It is preferable to use hydrogen gas when forming a metal oxide film. This can reduce the number of natural nuclei generated in the metal oxide film, resulting in a metal oxide film with low crystallinity. For example, the ratio of the flow rate of hydrogen gas to the total film-forming gas when forming a metal oxide film (hereinafter also referred to as the hydrogen flow rate ratio) is preferably greater than 0% and less than 20%, more preferably greater than 0% and less than 15%, and even more preferably greater than 0% and less than 10%.

[0096] Oxygen gas, hydrogen gas, and argon gas can be suitably used as the deposition gas for the metal oxide film. The oxygen flow rate ratio and the hydrogen flow rate ratio are preferably set in the above-mentioned ranges. This allows the deposition of a metal oxide film with low crystallinity, and also prevents oxygen deficiency and V. Ｏ The semiconductor layer 108 can have a small amount of H. Note that the oxygen flow rate ratio and the hydrogen flow rate ratio in the formation of the metal oxide film are not limited to the above ranges.

[0097] The substrate temperature during deposition of the metal oxide film is preferably low. This can reduce the crystallinity of the metal oxide film. The substrate temperature during deposition of the metal oxide film is preferably from room temperature (e.g., 25°C) to 150°C, more preferably from room temperature to 100°C, even more preferably from room temperature to 80°C, and even more preferably from room temperature to 50°C. In particular, it is preferable to deposit the metal oxide film at room temperature or without heating the substrate. Note that the substrate temperature during deposition of the metal oxide film is not limited to the above-mentioned range.

[0098] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0099] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0100] For example, when forming an indium oxide film, a precursor containing indium can be used, such as triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]indium.

[0101] Oxidizing agents include, for example, ozone, oxygen, hydrogen peroxide, and water.

[0102] The metal oxide layer 108F has a crystalline portion 107c. For example, when a metal oxide film is formed, the crystalline portion 107c is generated in the region 108R. The crystalline portion 107c has crystal grains generated by using the conductive layer 112b as a seed crystal. The crystalline portion 107c has a crystal orientation that reflects the crystal orientation of the conductive layer 112b. On the other hand, the crystallinity of regions other than the region 108R (e.g., the region 108P and the region 108Q) is low. Note that, to avoid cluttering the illustration, the crystal grain boundaries are omitted in FIG. 4A. Similarly, the crystal grain boundaries may also be omitted in FIGS. 4B and 4C.

[0103] Next, a heat treatment is performed. The heat treatment promotes crystal growth of the crystal grains generated in the seed crystal layer, and the crystal portion 107c spreads from the region 108R toward the region 108Q. Figure 4B shows the growth of the crystal portion 107c from the region 108R toward the region 108Q. The direction in which the crystal growth progresses (here, from top to bottom) is indicated by an outline arrow.

[0104] The crystal growth of the crystal grains generated by the seed crystal layer further progresses, and the crystalline portion 107c spreads from the region 108Q toward the region 108P. As a result, the semiconductor layer 108 can be obtained as shown in FIG. 4C. It is preferable that at least the crystal grains 103 reach the region 108P. Note that if the heat treatment is insufficient, amorphous portions may remain in the region 108P.

[0105] As described above, the crystal grains 103 can be formed across the regions 108P, 108Q, and 108R. This reduces the number of crystal grain boundaries across the current path of the transistor, resulting in a transistor with high field-effect mobility.

[0106] Note that although the structure in which the metal oxide layer 108F has the crystalline portion 107c before the heat treatment is described here, one embodiment of the present invention is not limited to this. There is a case in which the metal oxide layer 108F does not have the crystalline portion 107c before the heat treatment and the crystalline portion 107c is generated by the heat treatment.

[0107] The temperature of the heat treatment is preferably 100° C. or higher and 450° C. or lower, more preferably 100° C. or higher and 350° C. or lower, further preferably 150° C. or higher and 350° C. or lower, further preferably 170° C. or higher and 350° C. or lower, and further preferably 200° C. or higher and 350° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. By using an atmosphere with as low a content of hydrogen, water, and the like as possible, it is possible to prevent hydrogen, water, and the like from being taken into the semiconductor layer 108 as much as possible. The heat treatment can be performed, for example, in an oven.

[0108] If the heat treatment temperature is too high, natural nuclei are likely to occur and the crystal growth of the natural nuclei is also likely to proceed. On the other hand, if the heat treatment temperature is too low, the rate of crystal growth of the crystal grains 103 resulting from the seed crystals may be slowed, which may result in reduced productivity of the semiconductor device. By setting the heat treatment temperature within the above-mentioned range, it is possible to suppress the occurrence of natural nuclei and the crystal growth of the natural nuclei and to increase the rate of crystal growth of the crystal grains 103.

[0109] A rapid thermal annealing (RTA) apparatus can be used for the heat treatment. The use of an RTA apparatus can shorten the heat treatment time. When an RTA apparatus is used, the short heat treatment time makes it difficult for natural nuclei to occur even at high temperatures. Furthermore, because the heat treatment time is short, crystal growth of natural nuclei is less likely to proceed compared to crystal growth of the crystal grains 103 resulting from seed crystals. Therefore, when an RTA apparatus is used, the heat treatment temperature can be increased. The heat treatment temperature is preferably 100°C or higher and 750°C or lower, more preferably 200°C or higher and 700°C or lower, even more preferably 300°C or higher and 700°C or lower, still more preferably 400°C or higher and 700°C or lower, and even more preferably 500°C or higher and 700°C or lower. The treatment time is preferably 1 minute or higher and 10 minutes or lower, more preferably 3 minutes or higher and 10 minutes or lower, and even more preferably 5 minutes or higher and 10 minutes or lower.

[0110] As described above, the semiconductor layer 108 can be formed by forming a metal oxide film with low crystallinity, processing the metal oxide film into an island shape, and then crystallizing the metal oxide film by heat treatment. This allows the metal oxide film to be processed at a low crystallinity stage, which facilitates processing and improves the productivity of semiconductor devices. Note that one embodiment of the present invention is not limited thereto. The semiconductor layer 108 can also be formed by forming a metal oxide film with low crystallinity, crystallizing the metal oxide film by heat treatment, and then processing the metal oxide film into an island shape.

[0111] 5A to 5C, a method for forming the semiconductor layer 108 using a polycrystalline film for the conductive layer 112a and an amorphous film for the conductive layer 112b will be described. In each of FIGS. 5A to 5C, a cross-sectional view is shown on the left side, and a perspective view is shown on the right side.

[0112] As shown in FIG. 5A , a metal oxide layer 108F that will become the semiconductor layer 108 is formed on the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. When the metal oxide film that will become the metal oxide layer 108F is formed, a crystalline portion 107c is generated in the region 108P. The crystalline portion 107c has crystal grains that use the conductive layer 112a as a seed crystal. The crystalline portion 107c also has a crystal orientation that reflects the crystal orientation of the conductive layer 112a. On the other hand, the crystallinity of regions other than the region 108P (e.g., the region 108R and the region 108Q) is low. For details about the formation of the metal oxide film, please refer to the above description. Note that, to avoid cluttering the illustration, grain boundaries are omitted in FIG. 5A . Similarly, grain boundaries may also be omitted in FIGS. 5B and 5C .

[0113] Next, a heat treatment is performed. The heat treatment promotes crystal growth of the crystal grains generated in the seed crystal layer, and the crystal portion 107c spreads from the region 108P toward the region 108Q. Fig. 5B shows the state in which the crystal portion 107c grows from the region 108P toward the region 108Q. The direction in which the crystal growth progresses (here, from bottom to top) is indicated by an outline arrow.

[0114] The crystal growth of the crystal grains generated by the seed crystal layer further progresses, and the crystalline portion 107c spreads from the region 108Q toward the region 108R. As a result, the semiconductor layer 108 can be obtained as shown in FIG. 5C. It is preferable that at least the crystal grains 103 reach the region 108R. Note that if the heat treatment is insufficient, an amorphous region may remain in the region 108R. For details about the heat treatment, please refer to the above description.

[0115] As described above, the crystal grains 103 can be formed across the regions 108P, 108Q, and 108R. This reduces the number of crystal grain boundaries across the current path of the transistor, resulting in a transistor with high field-effect mobility.

[0116] Both the conductive layer 112a and the conductive layer 112b can function as seed crystals. Each of the conductive layer 112a and the conductive layer 112b can be a single crystal film or a polycrystalline film.

[0117] A structure in which polycrystalline films are used for the conductive layers 112a and 112b will be described with reference to Figures 6A to 7C. Figures 6A and 6B are perspective views of the semiconductor layer 108, the conductive layers 112a and 112b, the insulating layer 110, and the substrate 102. Figure 6B shows a cross section taken along the dashed dotted line D1-D2 shown in Figure 6A.

[0118] The semiconductor layer 108 has a crystal grain 103a that straddles the region 108P and the region 108Q, and a crystal grain 103b that straddles the region 108R and the region 108Q. FIGS. 6A and 6B show a plurality of crystal grains 103a and a plurality of crystal grains 103b. One crystal grain 103a has a region located in the region 108P and a region located in the region 108Q. It can also be said that one crystal grain 103a straddles the region 108P and the region 108Q. One crystal grain 103b has a region located in the region 108R and a region located in the region 108Q. It can also be said that one crystal grain 103b straddles the region 108R and the region 108Q. The crystal grain boundary 105 between the crystal grain 103a and the crystal grain 103b is located in the region 108Q.

[0119] Note that the size, shape, and position of the crystal grains 103a and 103b and the shape and position of the grain boundary 105 shown in FIGS. 6A and 6B are merely examples, and one embodiment of the present invention is not limited to these.

[0120] A method for forming the semiconductor layer 108 using polycrystalline films for the conductive layers 112a and 112b will be described with reference to Figures 7A to 7C. In each of Figures 7A to 7C, a cross-sectional view is shown on the left side, and a perspective view is shown on the right side.

[0121] As shown in FIG. 7A , a metal oxide layer 108F that will become the semiconductor layer 108 is formed on the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. When forming the metal oxide film that will become the metal oxide layer 108F, a crystalline portion 107cp is generated in the region 108P, and a crystalline portion 107cr is generated in the region 108R. The crystalline portion 107cp has crystal grains that use the conductive layer 112a as a seed crystal. The crystalline portion 107cp also has a crystal orientation that reflects the crystal orientation of the conductive layer 112a. Similarly, the crystalline portion 107cr has crystal grains that use the conductive layer 112b as a seed crystal. The crystalline portion 107cr also has a crystal orientation that reflects the crystal orientation of the conductive layer 112b. Meanwhile, regions other than the region 108P and the region 108R (e.g., the region 108Q) have low crystallinity. The above description can be referred to for the formation of a metal oxide film. To avoid cluttering the drawing, grain boundaries are omitted in Fig. 7A. Similarly, grain boundaries may be omitted in Fig. 7B and Fig. 7C.

[0122] Next, a heat treatment is performed. The heat treatment causes crystal growth of the crystal grains generated by the seed crystal layer, and the crystal portion 107cp spreads from the region 108P toward the region 108Q, while the crystal portion 107cr spreads from the region 108R toward the region 108Q. Figure 7B shows how the crystal portion 107cp grows from the region 108P toward the region 108Q, and how the crystal portion 107cr grows from the region 108R toward the region 108Q. The directions in which the crystal growth progresses (here, the bottom-to-top direction and the top-to-bottom direction) are indicated by hollow arrows.

[0123] The crystal growth of the crystal grains generated by the seed crystal layer continues, and the crystal portion 107cp and the crystal portion 107cr come into contact with each other, whereby the crystal growth stops. As a result, the semiconductor layer 108 can be obtained, as shown in FIG. 7C . The crystal grain boundary 105 between the crystal grain 103a included in the crystal portion 107cp and the crystal grain 103b included in the crystal portion 107cr is located in the region 108Q.

[0124] Since both the conductive layer 112a and the conductive layer 112b function as seed crystals, crystal growth proceeds from both the region 108P and the region 108R, which shortens the time required to crystallize the entire semiconductor layer 108. Therefore, productivity of the semiconductor device can be improved.

[0125] The semiconductor layer 108 can be crystallized using one or both of the upper electrode and the lower electrode of the VFET according to one embodiment of the present invention as seed crystals. Compared to forming the semiconductor layer 108 by crystal growth caused by natural nuclei, forming the semiconductor layer 108 by crystal growth from each of the regions 108P and 108R can reduce the number of grain boundaries 105 located in the channel formation region. This can reduce the number of grain boundaries across the current path of the transistor, resulting in a transistor with high field-effect mobility.

[0126] By using indium oxide with few crystal grain boundaries for the semiconductor layer 108, a transistor with large on-state current can be obtained. Therefore, a semiconductor device that operates at high speed can be provided. When the semiconductor device of one embodiment of the present invention is applied to a display device, the display device can operate at high speed and have high display quality. Furthermore, a transistor using indium oxide for a semiconductor layer has high field-effect mobility, and thus can obtain a large on-state current even with a small channel width. Therefore, the area occupied by the transistor can be reduced, and the area occupied by the semiconductor device can be reduced. When the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame.

[0127] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0128] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0129] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.

[0130] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ ), and VＯ H can be reduced.

[0131] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high precision. Furthermore, the variation in characteristics among the plurality of transistors 100 is also reduced. This stabilizes the operation of the semiconductor device 10, thereby improving its reliability. Furthermore, the reduced variation in transistor characteristics increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device to be lowered. Therefore, the power consumption of the semiconductor device can be reduced.

[0132] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the area occupied by the transistor 100 and the wirings can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided. Furthermore, when the semiconductor device is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be provided. Furthermore, for example, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be provided.

[0133] 1B and the like show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143; however, one embodiment of the present invention is not limited to this. A step may be formed between the insulating layer 110, the conductive layer 112b, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.

[0134] [Semiconductor Layer 108] As described above, the semiconductor layer 108 preferably uses indium oxide. Examples of metal oxides that can be used for the semiconductor layer 108 include gallium oxide (also referred to as gallium oxide) and zinc oxide (also referred to as zinc oxide). The metal oxide preferably contains at least indium. The metal oxide preferably contains one or both of indium and zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, such as a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0135] The semiconductor layer 108 may be formed of, for example, indium oxide (also referred to as indium oxide, In-O, or IO), indium zinc oxide (also referred to as In-Zn oxide, or IZO (registered trademark)), ITO, indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, or IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, or IGTO), gallium zinc oxide (Ga-Zn oxide, or GZO), or aluminum zinc oxide (Al-Zn Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, ITSO, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide) can be used.

[0136] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0137] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0138] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0139] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When multiple elements are contained as element M, the sum of the ratios of the number of atoms of element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of element M.

[0140] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0141] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage (Vg) is 0 V can be reduced, and a normally-off transistor can be obtained. In addition, a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0142] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0143] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0144] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0145] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0146] By using a material with a high indium content for the semiconductor layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or thereabouts. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide having a ratio of In:Sn:Zn=40:1:10 or thereabouts can be suitably used. Alternatively, a metal oxide having a ratio of In:Al:Zn=40:1:10 or thereabouts can be suitably used.

[0147] A metal oxide not containing element M can be used for the semiconductor layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0148] The composition of the semiconductor layer 108 can be analyzed by, for example, Energy Dispersive X-ray Spectrometry (EDX), X-ray Photoelectron Spectroscopy (XPS), or Electron Spectrometry for Chemical Analysis (ESCA), Inductively Coupled Plasma-Mass Spectrometry (ICP-MS), or Inductively Coupled Plasma-Atomic Emission Spectroscopy (ICP-AES). Spectrometry) can be used. Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0149] The metal oxide film can be preferably formed by sputtering or atomic layer deposition (ALD). When a metal oxide film is formed by sputtering, the composition of the formed metal oxide film may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide film may decrease to about 50% of that in the sputtering target.

[0150] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0151] The semiconductor layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0152] The CAAC-OS has multiple layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 is formed. The semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b and layered crystals parallel to or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel to or approximately parallel to the side surface of the insulating layer 110 where the semiconductor layer 108 is formed. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel to or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0153] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0154] The higher the substrate temperature during deposition of a metal oxide film, the higher the crystallinity of the resulting metal oxide film. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for deposition or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide film.

[0155] When a metal oxide is used for the semiconductor layer 108, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the ＯBy using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0156] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0157] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0158] The semiconductor layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0159] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0160] The semiconductor layer 108 can have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the two or more metal oxide layers included in the semiconductor layer 108 have the same or substantially the same composition, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0161] [Insulating Layer 110] The insulating layer 110 preferably has a stacked structure. In Fig. 1A and other figures, the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can each be made of the materials listed for the insulating layer 110.

[0162] A region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region. The insulating layer 110b preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. Specifically, the insulating layer 110b can be made of silicon oxide, silicon oxynitride, or both.

[0163] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0164] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. Then, the film can be removed.

[0165] The insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a PECVD method. In particular, when the insulating layer 110b is formed by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, the film can have an extremely low hydrogen content. The sputtering method is particularly suitable for forming the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0166] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., water and hydrogen) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0167] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting favorable electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layer 112a from increasing. Similarly, the conductive layer 112b can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of the conductive layer 112b from increasing. Therefore, a transistor with a large on-state current can be obtained.

[0168] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering).

[0169] The insulating layers 110a and 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layers 110a and 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Note that the insulating layers 110a and 110c can be made of the same material. Alternatively, the insulating layers 110a and 110c can be made of different materials.

[0170] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) when the insulating layer 110c (or the insulating film that will become the insulating layer 110c) is formed.

[0171] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0172] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0173] When the insulating layer 110c has a stacked structure, the layers constituting the insulating layer 110c can be made of the materials listed for the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have, for example, a stacked structure of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0174] 8A is a cross-sectional view of a semiconductor device 10A according to one embodiment of the present invention. For a top view of the semiconductor device 10A, see FIG. 1A. FIG. 8A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A, and FIG. 8B is a cross-sectional view of the cut surface taken along dashed line A1-A2.

[0175] The semiconductor device 10A includes a transistor 100 and an insulating layer 110. The semiconductor device 10A differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 110e.

[0176] The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c.

[0177] The insulating layer 110d is provided between the conductive layer 112a and the insulating layer 110a. The insulating layer 110d is provided so as to cover the conductive layer 112a. The insulating layer 110d has regions in contact with the top surface and side surfaces of the conductive layer 112a, the top surface of the substrate 102, and the side surfaces of the semiconductor layer 108.

[0178] The insulating layer 110e is provided between the conductive layer 112b and the insulating layer 110c. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, and the side surface of the semiconductor layer .

[0179] It is more preferable that the insulating layer 110d and the insulating layer 110e each be made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. Impurities are released from the insulating layer 110d and diffuse into a region of the semiconductor layer 108 that is in contact with the insulating layer 110d. This allows the region of the semiconductor layer 108 that is in contact with the insulating layer 110d to contain impurities and become a low-resistance region. The semiconductor layer 108 can have a low-resistance region between a region that is in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110e, impurities are released from the insulating layer 110e and diffuse into a region of the semiconductor layer 108 that is in contact with the insulating layer 110e. The region of the semiconductor layer 108 that is in contact with the insulating layer 110e contains impurities and becomes a low-resistance region. The semiconductor layer 108 may have a low-resistance region between a region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance region can function as a buffer region for reducing the drain electric field. Note that these low-resistance regions may function as the source or drain region.

[0180] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. For example, when the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. When the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor.

[0181] When the region of the semiconductor layer 108 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be made more uniform, thereby making the electric field of the gate electrode applied to the channel formation region more uniform.

[0182] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released from the insulating layers 110d and 110e include hydrogen. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen atoms (V Ｏ H) functions as a donor, generating electrons as carriers. This increases the carrier concentration in the region of the semiconductor layer 108 that is in contact with the insulating layer 110d and the region that is in contact with the insulating layer 110e, thereby reducing the electrical resistance.

[0183] The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0184] The amount of released hydrogen can be adjusted by differentiating the film formation conditions between the insulating layer 110d and the insulating layer 110a. Specifically, it is preferable to make one or more of the film formation power (film formation power density), film formation pressure, film formation gas type, film formation gas flow rate ratio, film formation temperature, and distance between the substrate and the electrode different between the insulating layer 110d and the insulating layer 110a. For example, by making the film formation power density of the insulating layer 110d lower than the film formation power density of the insulating layer 110a, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0185] The hydrogen content in the deposition gas used to deposit the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to deposit the insulating layer 110a. Specifically, when silicon nitride films or silicon nitride oxide films are deposited as the insulating layer 110d and the insulating layer 110a by a PECVD method, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to deposit the insulating layer 110d (hereinafter also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow rate of the deposition gas used to deposit the insulating layer 110a. By depositing the insulating layer 110d under conditions with a high ammonia flow ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased.

[0186] It is more preferable that the film density of the insulating layer 110a be higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker transmission electron (TE) image, whereas a low film density results in a lighter transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear darker than the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0187] The insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layers 110c and 110e, the descriptions of the insulating layers 110a and 110d can be referred to.

[0188] Here, the insulating layer 110 is shown to have a stacked structure of three or five layers, but one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b. A structure without one or more of the insulating layer 110d, the insulating layer 110a, the insulating layer 110c, and the insulating layer 110e is also possible. The insulating layer 110 can have a stacked structure of two, four, or six or more layers. Alternatively, the insulating layer 110 can have a single-layer structure.

[0189] The configuration of the insulating layer 110 can be applied to other configuration examples.

[0190] [Opening 141, Opening 143] The top surface shapes of openings 141 and 143 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shapes of openings 141 and 143 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other documents, "circular" does not necessarily mean a perfect circle.

[0191] In this specification and the like, the top surface shape of the opening 141 refers to the shape of the top surface end portion of the insulating layer 110 on the opening 141 side. Also, the top surface shape of the opening 143 refers to the shape of the bottom surface end portion of the conductive layer 112b on the opening 143 side.

[0192] As shown in FIG. 1A and other figures, the top shapes of the openings 141 and 143 can be identical or substantially identical to each other. In this case, as shown in FIGS. 1B and 1C and other figures, it is preferable that the bottom edge of the conductive layer 112b on the opening 143 side be identical or substantially identical to the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side. The top shapes of the openings 141 and 143 can also be configured to not be identical to each other. When the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 can also be concentric. Alternatively, the openings 141 and 143 can be configured not to be concentric.

[0193] 9A and 9B, the channel length and the channel width of the transistor 100 will be described. Here, a region of the semiconductor layer 108 in contact with the insulating layer 110b is described as a channel formation region.

[0194] In FIG. 9B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110 of the insulating layer 110b and the angle θ110 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0195] The channel length L100 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0196] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0197] The channel length L100 can be controlled by adjusting the thickness T110 and angle θ110 of the insulating layer 110b.

[0198] The thickness T110 of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0199] When the angle θ110 is 90 degrees or less, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0200] 9B and the like, the angle θ110 is shown as being less than 90 degrees; however, one embodiment of the present invention is not limited to this. The angle θ110 can be set to 90 degrees. This can shorten the channel length L100 of the transistor 100.

[0201] In the layer that becomes the semiconductor layer 108, crystal growth progresses from a region in contact with the seed crystal layer toward the channel formation region. Therefore, a shorter channel length L100 is preferable because it allows the crystal growth distance to be shortened. On the other hand, when the channel length L100 is long, the channel formation region may contain crystal grains resulting from the seed crystal and crystal grains resulting from natural nuclei. Even in this case, the channel formation region may contain crystal grains resulting from the seed crystal, thereby reducing the number of crystal grain boundaries located in the channel formation region.

[0202] 1B and the like show a structure in which the shape of the side surface of the insulating layer 110 on the opening 141 side is straight in a cross-sectional view, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side can be curved. Alternatively, a structure having both a straight region and a curved region in the shape of the side surface is also possible.

[0203] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141 or that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view).

[0204] 9A and 9B, the width D141 of the opening 141 is indicated by a two-dot chain line with a double arrow. FIG. 9A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the length of the circumference of the circle. In other words, the channel width W100 is π×D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0205] The width D141 of the opening 141 may vary in the depth direction. For example, the width D141 of the opening 141 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view. Alternatively, the diameter of the opening 141 may be any of the diameter at the highest point, the diameter at the lowest point, or the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view.

[0206] When the opening 141 is formed using lithography, the width D141 of the opening 141 is equal to or greater than the minimum exposure dimension of the exposure device. The width D141 can be, for example, 20 nm or greater, 50 nm or greater, 100 nm or greater, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and can be less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0207] Note that although the example in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region has been described here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region in contact with the insulating layer 110c may also function as a channel formation region.

[0208] [Insulating Layer 106] The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be formed using the materials listed for the insulating layer 110.

[0209] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0210] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0211] 1B and the like, the insulating layer 106 has a single-layer structure; however, one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers. When the insulating layer 106 has a stacked structure, the insulating layer on the semiconductor layer 108 side preferably contains oxide or oxynitride. The insulating layer on the semiconductor layer 108 side can preferably be made of, for example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0212] It is preferable to use a material that is difficult for substances to permeate for at least one of the layers constituting the insulating layer 106. The layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100 from diffusing into the semiconductor layer 108 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the semiconductor layer 108 from diffusing into the conductive layer 104 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ ) can be suppressed. In addition, the conductive layer 104 can be prevented from being oxidized by oxygen contained in the semiconductor layer 108, which can prevent the electrical resistance of the conductive layer 104 from increasing. As a result, a transistor with good electrical characteristics and high reliability can be obtained. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of oxides and oxynitrides can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0213] The insulating layer 106 can have, for example, a stacked structure of a silicon oxynitride film and a silicon nitride film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of a silicon oxynitride film and an aluminum oxide film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon oxynitride film over the aluminum oxide film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0214] Although the insulating layer 106 has a two-layer structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three-layer or more layer structure.

[0215] The configuration of the insulating layer 106 shown here can also be applied to other configuration examples.

[0216] [Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 104] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0217] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be formed using a conductive metal oxide (also referred to as an oxide conductor (OC)).

[0218] Examples of oxide conductors include indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, ITSO, zinc oxide doped with gallium, and In—Ga—Zn oxide. Oxide conductors containing indium are particularly preferred because of their high conductivity.

[0219] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0220] The conductive layers 112a, 112b, and 104 can each have a stacked-layer structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0221] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied to each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0222] Note that the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can be formed using the same material, or at least one of them can be formed using a different material.

[0223] The conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, for the conductive layer 112a and the conductive layer 112b, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material.

[0224] For the conductive layer 112a and the conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108.

[0225] The conductive layer 112 a and the conductive layer 112 b can each be formed using any of the above-described oxide conductors, such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, ITSO, and zinc oxide doped with gallium.

[0226] The conductive layer 112a and the conductive layer 112b may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104 may also be made of any of the nitride conductors described above.

[0227] As described above, one or both of the conductive layers 112a and 112b can be used as a seed crystal layer. The above description can be referred to for materials that can be used for the seed crystal layer.

[0228] [Substrate 102] The material of the substrate 102 is not particularly limited, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited, and can be, for example, circular or rectangular.

[0229] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0230] [Insulating Layer 218] An insulating layer 218 is provided over the transistor 100. The insulating layer 218 functions as a protective layer for the transistor. The insulating layer 218 can be formed using the same material as that used for the insulating layer 110. The insulating layer 218 preferably includes one or more inorganic insulating layers. Note that the insulating layer 218 is omitted from the perspective views shown in FIGS. 2A to 2D.

[0231] The insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 218 to function as a barrier film. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device. The above description of the barrier film can be referred to.

[0232] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0233] 10A and 10B are cross-sectional views of a semiconductor device 10B according to one embodiment of the present invention. For a top view of the semiconductor device 10B, see FIG. 1A. FIG. 10A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 10B is a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG. 1A.

[0234] The semiconductor device 10B includes a transistor 100, an insulating layer 110, and an insulating layer 109. The semiconductor device 10B differs from the semiconductor device 10 shown in FIG.

[0235] The insulating layer 109 is located between the substrate 102 and the conductive layer 112a. The insulating layer 109 is provided on the substrate 102, the conductive layer 112a is provided on the insulating layer 109, and the insulating layer 110 is provided on the conductive layer 112a. The insulating layer 109 has regions in contact with the bottom surface of the conductive layer 112a and the bottom surface of the insulating layer 110. The conductive layer 112a has regions in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. The insulating layer 110 has regions in contact with the top and side surfaces of the conductive layer 112a, the top surface of the insulating layer 109, the side surface of the semiconductor layer 108, the bottom surface of the conductive layer 112b, and the bottom surface of the insulating layer 106.

[0236] The insulating layer 109 preferably has a barrier property. The insulating layer 109 is preferably made of a material through which impurities (e.g., water and hydrogen) contained in the substrate 102 do not easily diffuse. This can prevent impurities from diffusing from the substrate 102 to the transistor 100.

[0237] The description of the barrier film can be referred to for the insulating layer 109. For example, the insulating layer 109 can be formed using one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, for example, the insulating layer 109 can be formed using one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0238] The insulating layer 109 is preferably formed using a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. The insulating layer 109 can be formed using the same material as that used for the insulating layer 110d and the insulating layer 110e. For example, the insulating layer 109 can preferably be formed using silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

[0239] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a also diffuse into a region of the semiconductor layer 108 that is in contact with the conductive layer 112a. This reduces the electrical resistance of the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, that is, one of the source region and the drain region. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be obtained.

[0240] When a metal oxide is used for the semiconductor layer 108, the impurities released from the insulating layer 109 preferably contain hydrogen. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 108 through the conductive layer 112a increases the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a, thereby reducing the electrical resistance of one of the source and drain regions.

[0241] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112a. This can reduce the electrical resistance of the conductive layer 112a. For example, when a metal oxide is used for the conductive layer 112a, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layer 112a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a can function as a wiring, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 108.

[0242] The materials that can be used for the conductive layer 112a are as described above. Note that the conductive layer 112a preferably easily transmits impurities and more preferably does not easily adsorb impurities.

[0243] The insulating layer 110a has a region in contact with the top surface of the insulating layer 109 and the top surface and side surfaces of the conductive layer 112a, which can suppress diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel formation region of the semiconductor layer 108 through the insulating layer 110b.

[0244] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For the insulating layer 109, the descriptions of the insulating layers 110d and 110e can be referred to.

[0245] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0246] 10A and other drawings show the insulating layer 110 having a four-layer structure including insulating layers 110a, 110b, 110c, and 110e, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 can have a five-layer structure including insulating layers 110d, 110a, 110b, 110c, and 110e. Alternatively, the insulating layer 110 can have a three-layer structure including insulating layers 110a, 110b, and 110c.

[0247] The structure of the insulating layer 109 shown here can also be applied to other structure examples.

[0248] 11A illustrates an equivalent circuit diagram of a semiconductor device 10C according to one embodiment of the present invention. The semiconductor device 10C includes transistors 100_1 to 100_q (q is an integer of 2 or greater). The transistors 100_1 to 100_q are connected in series. The transistors 100_1 to 100_q share a gate, and the semiconductor device 10C can be regarded as a single transistor.

[0249] 11A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_q may be p-channel transistors.

[0250] A specific description will be given taking the case where q is 4 as an example. FIG. 11B shows an equivalent circuit diagram of a semiconductor device 10C according to one embodiment of the present invention. FIG. 11C shows a top view of the semiconductor device 10C. FIG. 12 shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6 in FIG. 11C. FIG. 13 shows a perspective view of the semiconductor device 10C.

[0251] The semiconductor device 10C includes transistors 100_1 to 100_4. The transistors 100_1 to 100_4 can each have the same structure as the transistor 100. Note that although the example in which the insulating layer 110 has a three-layer structure is described, one embodiment of the present invention is not limited to this.

[0252] 11C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0253] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100_1, and the conductive layer 112b functions as the other electrode.

[0254] The transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c. The conductive layer 112a serves as one of a source electrode and a drain electrode of the transistor 100_2, and the conductive layer 112c serves as the other electrode. The conductive layer 112a is shared by the transistor 100_1 and the transistor 100_2.

[0255] The transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. The conductive layer 112c serves as one of a source electrode and a drain electrode of the transistor 100_3, and the conductive layer 112d serves as the other electrode. The conductive layer 112c is shared by the transistors 100_2 and 100_3.

[0256] The transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. The conductive layer 112d functions as one of a source electrode and a drain electrode of the transistor 100_4, and the conductive layer 112e functions as the other. The conductive layer 112d is shared by the transistors 100_3 and 100_4. The conductive layer 104 is shared by the transistors 100_1 to 100_4.

[0257] 14A is a perspective view showing the conductive layer 112a and the conductive layer 112d. The conductive layer 112a and the conductive layer 112d can be formed in the same process.

[0258] 14B is a perspective view illustrating the conductive layers 112a, 112b, 112c, 112d, and 112e, the openings 141_1 to 141_4, and the openings 143_1 to 143_4. The conductive layers 112a to 112e can be formed in the same process. The conductive layer 112b has an opening 143_1, the conductive layer 112c has openings 143_2 and 143_3, and the conductive layer 112e has an opening 143_4.

[0259] 14C is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the semiconductor layers 108_1 to 108_4. The semiconductor layers 108_1 to 108_4 can be formed in the same process.

[0260] 14D is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the conductive layer 104. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4.

[0261] One of a source electrode and a drain electrode of the transistor 100_1 is connected to one of a source electrode and a drain electrode of the transistor 100_2. The other of the source electrode and the drain electrode of the transistor 100_2 is connected to one of a source electrode and a drain electrode of the transistor 100_3. The other of the source electrode and the drain electrode of the transistor 100_3 is connected to one of a source electrode and a drain electrode of the transistor 100_4.

[0262] To avoid complicating the drawings, the insulating layer 109 is not shown with hatching patterns in FIGS. 13 to 14D.

[0263] When the semiconductor device 10C is considered as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is defined as L100, the semiconductor device 10C can be considered as a transistor having a channel length of "L100×4" (see FIG. 9B). The semiconductor device 10C, which is configured with q transistors, can be considered as a transistor having a channel length of "L100×q". Note that the semiconductor device 10C can be considered as a transistor having a channel width W100 (see FIGS. 9A and 9B). By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel lengths can be varied by adjusting the number (q) of transistors connected in series. The number (q) of transistors connected in series can be determined so as to achieve a desired saturation.

[0264] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0265] The configuration of the semiconductor device 10C shown here can be applied to other configuration examples. Also, a configuration can be adopted in which a group of series-connected transistors are further connected in parallel (hereinafter also referred to as series-parallel connection).

[0266] 15A to 17D, a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 shown in FIG.

[0267] Here, an example in which the conductive layer 112a functions as a seed crystal is described.

[0268] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0269] Next, a conductive film that will become the conductive layer 112a is formed on the insulating layer 109 and then processed to form the conductive layer 112a ( FIG. 15A ). The conductive film can be preferably formed by sputtering. The conductive layer 112a that functions as a seed crystal preferably has high crystallinity. A polycrystalline ITO film can be preferably used as the conductive layer 112a.

[0270] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a (FIG. 15B).

[0271] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, it is preferable to form the insulating film 110bf continuously using the same device after forming the insulating film 110af.

[0272] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating films 110af and 110bf within the above-described range, the amount of impurities (e.g., water and hydrogen) released from the insulating films 110af and 110bf can be reduced, and the diffusion of the impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0273] Since the insulating films 110af and 110bf are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to heat applied when the insulating films 110af and 110bf are formed.

[0274] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0275] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. Examples of methods for supplying oxygen include ion implantation, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ The plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, carbon monoxide, and carbon dioxide. The amount of oxygen supplied can be adjusted by, for example, the power and treatment time in the plasma treatment.

[0276] After the insulating film 110bf is formed, nitrogen can be supplied to the insulating film 110bf. The nitrogen supply method can be referred to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO ２ The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0277] In the insulating layer (here, the insulating film 110bf or the later insulating layer 110b), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ , X is a real number greater than 0). ２ O, NO and NO ２ In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level at which the charge of the indium oxide changes between a 0 state and a -1 state is located within the band gap of indium oxide. Therefore, when nitrogen oxide diffuses to the interface between the insulating layer and the semiconductor layer having the metal oxide or near the interface, the level traps electrons. As a result, the trapped electrons remain at the interface between the insulating layer and the semiconductor layer or near the interface, and the threshold voltage of the transistor can be increased in the positive direction. This allows a normally-off transistor to be obtained, resulting in a semiconductor device with low power consumption.

[0278] Increasing the amount of nitrogen oxide can increase the threshold voltage to the positive side. However, if the amount of nitrogen oxide is too large, the threshold voltage may fluctuate greatly when a positive potential (positive bias) is applied to the gate of the transistor, which may result in reduced reliability. Therefore, it is preferable to use a nitrogen oxide amount within a range that does not affect reliability.

[0279] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of desorption in thermal desorption spectrometry (TDS) or the amount of electron spin in electron spin resonance (ESR). In TDS, NO (m / z (also referred to as mass-to-charge ratio) = 30), N ２ O (m / z=44), and NO ２ The amount of NO (m / z = 46) desorbed can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２ Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２ Since the molecule has a lone electron, it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４ The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0280] The order of the treatment for supplying oxygen and the treatment for supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same treatment. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N ２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0281] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0282] Next, a film 139 is preferably formed on the insulating film 110bf ( FIG. 15D ). The film 139 can be formed by a sputtering method. By forming the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf. FIG. 15C schematically shows the supply of oxygen to the insulating film 110bf using solid arrows.

[0283] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, ITO, or ITSO can be used as the film 139.

[0284] The film 139 is preferably formed using an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108.

[0285] When forming the film 139, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the processing chamber of the film formation apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0286] In this way, by forming the film 139 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 139, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be confined in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0287] Heat treatment may be performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf.

[0288] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, further preferably 250°C or higher and 450°C or lower, further preferably 300°C or higher and 450°C or lower, further preferably 300°C or higher and 400°C or lower, and further preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being incorporated into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed in an oven, a rapid thermal annealing (RTA) apparatus, or the like. By using an RTA device, the heat treatment time can be shortened.

[0289] After the film 139 is formed or after the heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 139. Oxygen can be supplied by, for example, ion implantation, plasma immersion ion implantation, or plasma treatment. The above description of the plasma treatment can be referred to, and therefore, detailed description thereof will be omitted.

[0290] Next, the film 139 is removed ( FIG. 15E ). Although there is no particular limitation on the method for removing the film 139, a wet etching method can be suitably used. By using the wet etching method, etching of the insulating film 110bf can be suppressed when the film 139 is removed. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0291] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0292] Next, an insulating film 110cf that will become the insulating layer 110c and an insulating film 110ef that will become the insulating layer 110e are formed on the insulating film 110bf (FIG. 16A). The formation of the insulating film 110cf and the insulating film 110ef can be referred to in the description of the formation of the insulating film 110af and the insulating layer 109, and therefore detailed description thereof will be omitted.

[0293] Next, a conductive film 112bf to be the conductive layer 112b is formed over the insulating film 110ef (FIG. 16B). The conductive film 112bf can be formed by a sputtering method. The conductive layer 112b preferably has low crystallinity. An amorphous ITSO film can be preferably used as the conductive layer 112b.

[0294] Next, the conductive film 112bf is processed to form a conductive layer 112B (FIG. 16C). The conductive layer 112B will later become the conductive layer 112b. The conductive layer 112B can be formed by, for example, wet etching.

[0295] Subsequently, a part of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143. The conductive layer 112b can be preferably formed by wet etching.

[0296] Subsequently, parts of the insulating films 110af, 110bf, and 110cf are removed to form the insulating layer 110 having an opening 141 ( FIG. 16D ). The opening 141 is provided in a region overlapping with the opening 143. The formation of the opening 141 exposes the conductive layer 112a. The insulating layer 110 can be preferably formed by dry etching.

[0297] The opening 141 can be formed using, for example, the resist mask used to form the opening 143. Specifically, a resist mask is formed over the conductive layer 112B, part of the conductive layer 112B is removed using the resist mask to form the opening 143, and part of the insulating films 110af, 110bf, and 110cf is removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the resist mask used to form the opening 143.

[0298] Next, a metal oxide film 108f to be the semiconductor layer 108 is formed so as to cover the openings 141 and 143 ( FIG. 17A ). The metal oxide film 108f is provided in contact with the upper and side surfaces of the conductive layer 112b, the upper and side surfaces of the insulating layer 110, and the upper surface of the conductive layer 112a. During the formation of the metal oxide film 108f, a region of the metal oxide film 108f in contact with the conductive layer 112a crystallizes using the conductive layer 112a as a seed crystal. As a result, a crystalline portion 107c is formed in the region of the metal oxide film 108f in contact with the conductive layer 112a. The above description can be referred to for the formation of the metal oxide film 108f.

[0299] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment in an atmosphere containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0300] Next, the metal oxide film 108f is processed into an island shape to form the metal oxide layer 108F (FIG. 17B). The metal oxide layer 108F can be preferably formed by wet etching.

[0301] Subsequently, heat treatment is performed. The heat treatment crystallizes the metal oxide layer 108F, thereby obtaining the semiconductor layer 108 ( FIG. 17C ). Alternatively, heat treatment is performed after the metal oxide film 108f is formed and before the metal oxide film 108f is processed into an island shape. The metal oxide film crystallized by the heat treatment is processed into an island shape, thereby obtaining the semiconductor layer 108. The above-described description can be referred to for the heat treatment and crystallization.

[0302] The heat treatment can remove hydrogen and water contained in or adsorbed to the surface of the metal oxide film 108f or the semiconductor layer 108. Furthermore, the heat treatment can also supply oxygen from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108.

[0303] Note that the heat treatment is not performed here, and can be performed in the same manner as a heat treatment performed in a later step. In addition, a process in which heat is applied in a later step (for example, a film formation step) may also serve as the heat treatment.

[0304] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110 (FIG. 17D). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0305] When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 has a function of suppressing oxygen diffusion, which suppresses oxygen from being released from the semiconductor layer 108 and prevents oxygen vacancies (V Ｏ ) can be suppressed from increasing. Furthermore, oxygen contained in the semiconductor layer 108 is prevented from diffusing into the conductive layer 104 through the insulating layer 106, and the conductive layer 104 can be prevented from being oxidized. As a result, a transistor with good electrical characteristics and high reliability can be obtained.

[0306] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108, causing oxygen vacancies and V in the semiconductor layer 108. ＯH may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0307] Before forming the insulating layer 106, plasma treatment can be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0308] Subsequently, the conductive layer 104 is formed over the insulating layer 106 (FIGS. 10A and 10B). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0309] Subsequently, an insulating layer 218 is formed. The insulating layer 218 can be preferably formed by a PECVD method.

[0310] Through the above steps, the semiconductor device 10B of one embodiment of the present invention can be manufactured.

[0311] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0312] Embodiment 2 In this embodiment, an indium oxide film that can be used for the semiconductor layer 108 of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0313] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0314] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (IGZO) and zinc oxide.

[0315] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 18A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 18B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0316] As shown by the arrows in Figure 18B, IGZO tends to have higher hole mobility as the carrier concentration increases. On the other hand, as shown by the arrows in Figure 18A, indium oxide tends to have higher hole mobility as the carrier concentration decreases (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 18A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 18A.

[0317] 18A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0318] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the electrical resistivity can be increased to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0319] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, aluminum, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, and magnesium. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0320] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 18A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived. By using this technical concept, a transistor that has high mobility, a small off-state current, and is capable of being normally off can be realized.

[0321] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 18B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the semiconductor may no longer function as a transistor. On the other hand, in indium oxide, as shown in FIG. 18A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0322] Note that "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. The normally off state can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to the state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from the two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0323] In a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef=Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. With this film structure, a semiconductor device with high reliability and Ef=Ei can be obtained.

[0324] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0325] The above film configuration can also be considered as a stacked configuration of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Furthermore, hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0326] The indium oxide film in the channel formation region preferably has a low impurity concentration. Impurities in the indium oxide film in the channel formation region can serve as a scattering source for carriers, thereby reducing the field-effect mobility. These impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include gallium, zinc, boron, aluminum, and silicon. The concentrations of these impurities in the indium oxide film are preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities. Because impurities can inhibit the crystal growth of a metal oxide film, a low impurity concentration is preferable. Reducing the impurity concentration can sometimes promote the crystal growth of a metal oxide film. Incidentally, ppm is an abbreviation for "parts per million," and 1 ppm is 1 x 10 −６ is.

[0327] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0328] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 18C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and are released as water molecules (H ２ O) may be released in the film. ＯIn the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0329] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0330] As shown in FIG. 18C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or, as mentioned above, reacts with oxygen contained in the film and is released as water molecules.

[0331] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0332] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0333]

[0334] For the layer or substrate (hereinafter collectively referred to as the "film") that forms the surface on which the crystalline indium oxide film is to be formed, it is preferable to use a material containing crystals that has a small difference in lattice constant from that of indium oxide (also referred to as lattice mismatch), which can improve the crystallinity of the indium oxide film.

[0335] Here, the crystal of indium oxide has a cubic structure (bixbyite type), and YSZ (Zr ０．９ Y ０．１ O １．９５ The crystals of indium oxide have a cubic crystal structure (fluorite type). The lattice mismatch between indium oxide and YSZ is −1.74%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0336] It should be noted that the crystal structure of the film to be formed and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the film to be formed to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ There are various types of structures, including modified structures.

[0337] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0338] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0339] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0340] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0341] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0342] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0343] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0344] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0345] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0346] <Configuration Example 1 of Display Device> FIG. 19A shows a perspective view of a display device 50A.

[0347] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 19A, the substrate 152 is indicated by a dashed line.

[0348] The display device 50A includes a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 19A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 19A can also be said to be a display module including the display device 50A, an IC, and an FPC.

[0349] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 19A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0350] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0351] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0352] 19A shows an example in which an IC 173 is provided on a substrate 151 by a COG method. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0353] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0354] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0355] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 19A shows an enlarged view of one pixel 201.

[0356] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0357] 19A includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the number of sub-pixels included in one pixel is not particularly limited.

[0358] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0359] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0360] Examples of quantum dot materials used in the color conversion layer include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of an element belonging to Groups 4 to 14 and a Group 16 element, compounds of a Group 2 element and a Group 16 element, compounds of a Group 13 element and a Group 15 element, compounds of a Group 13 element and a Group 17 element, compounds of a Group 14 element and a Group 15 element, compounds of a Group 11 element and a Group 17 element, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0361] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, telluride Indium, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, calcium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tungsten oxide Examples of the quantum dots include tantalum, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, a compound of selenium, zinc, and cadmium, a compound of indium, arsenic, and phosphorus, a compound of cadmium, selenium, and sulfur, a compound of cadmium, selenium, and tellurium, a compound of indium, gallium, and arsenic, a compound of indium, gallium, and selenium, a compound of indium, selenium, and sulfur, a compound of copper, indium, and sulfur, and combinations thereof. Also, so-called alloy-type quantum dots, whose composition is expressed in any ratio, may be used.

[0362] Examples of quantum dot structures include core, core-shell, and core-multishell types. Furthermore, quantum dots have a high proportion of surface atoms, making them highly reactive and prone to aggregation. Therefore, to prevent quantum dot aggregation and improve their dispersibility in a dispersion medium, it is preferable that a protective agent be attached to the surface of the quantum dots or that protective groups be provided. This can reduce reactivity and improve electrical stability.

[0363] Since the band gap of quantum dots increases as their size decreases, their size can be adjusted appropriately to obtain light of the desired wavelength. As the size decreases, the emission of quantum dots shifts toward the blue side, i.e., toward higher energy, so by changing the size of the quantum dots, the emission wavelength can be adjusted across the wavelength ranges of the ultraviolet, visible, and infrared spectrums. The size (diameter) of the quantum dots is, for example, 0.5 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less. Furthermore, the narrower the size distribution of the quantum dots, the narrower the emission spectrum, and the more excellent the color purity of the light emitted. Furthermore, the shape of the quantum dots is not particularly limited and may be spherical, rod-shaped, disc-shaped, or other shapes. Quantum rods, which are rod-shaped quantum dots, have the function of emitting directional light.

[0364] The color conversion layer can be formed by a droplet ejection method (for example, an inkjet method), a coating method, an imprint method, various printing methods (screen printing, offset printing), etc. A color conversion film such as a quantum dot film may also be used.

[0365] When processing a film to be used as a color conversion layer, it is preferable to use a photolithography method. Photolithography methods include a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed, and a method in which a photosensitive thin film is formed, and then the thin film is processed into a desired shape by exposure and development. For example, an island-shaped color conversion layer can be formed by forming a thin film using a material in which quantum dots are mixed into a photoresist, and processing the thin film using a photolithography method.

[0366] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0367] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0368] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0369] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0370] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0371] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0372] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0373] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0374] 19B is a block diagram illustrating a display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or greater). The circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.

[0375] The circuit included in the first driver circuit unit 231 functions as, for example, a scanning line driver circuit (also referred to as a gate line driver circuit, gate driver, scan driver, or row driver). The circuit included in the second driver circuit unit 232 functions as, for example, a signal line driver circuit (also referred to as a source line driver circuit, source driver, data driver, or column driver). Note that some kind of circuit may be provided at a position facing the first driver circuit unit 231 across the display unit 162. Some kind of circuit may be provided at a position facing the second driver circuit unit 232 across the display unit 162.

[0376] The circuit portion 164 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. A transistor, a capacitor, or the like can be used for the circuit portion 164. The transistors included in the circuit portion 164 can be formed in the same process as the transistors included in the pixel 230.

[0377] The display device 50A has wirings 236 that are arranged parallel or approximately parallel to each other and whose potentials are controlled by a circuit included in a first drive circuit unit 231, and wirings 238 that are arranged parallel or approximately parallel to each other and whose potentials are controlled by a circuit included in a second drive circuit unit 232. Note that Fig. 19B shows an example in which wirings 236 and 238 are connected to pixel 230. However, wirings 236 and 238 are just an example, and wirings connected to pixel 230 are not limited to wirings 236 and 238.

[0378] 19B , the direction in which the wiring 236 extends may be referred to as the row direction, and the direction in which the wiring 238 extends may be referred to as the column direction. Note that although the horizontal direction in the drawing is the row direction and the vertical direction is the column direction, this is not limiting, and the row direction and the column direction may be interchanged.

[0379] The semiconductor device of one embodiment of the present invention includes a vertical transistor (VFET) having a submicron channel length and a large on-state current. An oxide semiconductor (OS) can be preferably used for a channel formation region of the transistor, thereby enabling the transistor to have a small off-state current. The semiconductor device of one embodiment of the present invention can be preferably used for one or both of the display portion 162 and the circuit portion 164. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device, it is possible to reduce manufacturing costs.

[0380] 20A shows an example of the configuration of a pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

[0381] The pixel circuit 51 includes a transistor 52A, a transistor 52B, and a capacitor 53. The pixel circuit 51 is a 2Tr1C pixel circuit including two transistors and one capacitor. Note that there is no particular limitation on the pixel circuit that can be applied to the display device of one embodiment of the present invention.

[0382] The anode of the light-emitting device 61 is connected to one of the source and drain of the transistor 52B and one electrode of the capacitor 53. The other of the source and drain of the transistor 52B is connected to a wiring ANO. The gate of the transistor 52B is connected to one of the source and drain of the transistor 52A and the other electrode of the capacitor 53. The other of the source and drain of the transistor 52A is connected to a wiring SL. The gate of the transistor 52A is connected to a wiring GL. The cathode of the light-emitting device 61 is connected to a wiring VCOM.

[0383] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting device 61. The transistor 52A has a function of controlling the conduction or non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0384] In this specification and the like, a high power supply potential VDD (also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. Also, a low power supply potential VSS (also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. Also, a ground potential GND (also simply referred to as "GND") can be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0385] The transistor 52A functions as a selection transistor for controlling the selection state of the pixel 230. The transistor 52B functions as a drive transistor for controlling the amount of current flowing through the light-emitting device 61. The capacitance element 53 has a function of maintaining the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting device 61 is controlled in accordance with an image signal supplied to the gate of the transistor 52B.

[0386] The above-described semiconductor device can be used for the pixel circuit 51. This allows the area occupied by the pixel circuit 51 to be reduced, resulting in a high-definition display device. In addition, the display device can operate at high speed.

[0387] By using a plurality of transistors and capacitors in a pixel circuit, a high-performance display device can be provided. By applying the semiconductor device of one embodiment of the present invention, the occupied area can be reduced even when the number of transistors and capacitors is increased, and a high-performance and high-resolution display device can be provided. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be provided.

[0388] Since the occupation area of ​​the semiconductor device according to one embodiment of the present invention can be reduced, the aperture ratio of a pixel in a bottom-emission display device can be increased. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0389] In this specification and the like, the aperture ratio refers to the ratio of the area of ​​the region through which light is emitted to the area of ​​the pixel.

[0390] 20B shows an example of a configuration different from that of the pixel 230 shown in FIG.

[0391] The pixel circuit 51A differs from the pixel circuit 51 shown in FIG. 20A mainly in that the anode of the light-emitting device 61 is connected to the line ANO.

[0392] One of the source and drain of the transistor 52B and one electrode of the capacitor 53 are connected to the wiring VCOM. The cathode of the light-emitting device 61 is connected to the other of the source and drain of the transistor 52B.

[0393] In the pixel circuit 51A, the source potential of the transistor 52B functioning as a driving transistor is the potential of the wiring VCOM, so that fluctuations in the voltage (Vgs) between the gate and source of the transistor 52B can be suppressed, thereby reducing variations in luminance.

[0394] 20C shows an example of a configuration different from that of the pixel 230 shown in FIG.

[0395] 20A in that the pixel circuit 51B includes a transistor 52C. The pixel circuit 51B includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51B is a 3Tr1C type pixel circuit including three transistors and one capacitor.

[0396] One of the source and drain of the transistor 52C is connected to one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52C is connected to a wiring V0. For example, a reference potential is supplied to the wiring V0. The gate of the transistor 52C is connected to a wiring GL.

[0397] The transistor 52C has a function of controlling conduction or non-conduction between the wiring V0 and one of the source electrode and the drain electrode of the transistor 52B based on the potential of the wiring GL. The reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source potential of the transistor 52B.

[0398] The wiring V0 can be used to obtain a current value that can be used to set pixel parameters. Specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.

[0399] A backgate can be provided for some or all of the transistors included in the pixel circuit 51. A pixel circuit 51C shown in FIG. 20D illustrates a configuration in which the transistor 52B in the pixel circuit 51 shown in FIG. 20A has a backgate connected to one of the source and drain of the transistor 52B. A pixel circuit 51D shown in FIG. 20E illustrates a configuration in which the transistor 52B in the pixel circuit 51B shown in FIG. 20C has a backgate connected to one of the source and drain of the transistor 52B. This can improve reliability. Note that the backgate of the transistor 52B can also be connected to the gate of the transistor 52B. This can increase the on-state current of the transistor 52B.

[0400] 21A shows an example of a configuration different from the above-described pixel 230. The pixel 230 has a pixel circuit 51E and a light-emitting device 61.

[0401] The pixel circuit 51E includes transistors M21, M22, and M23, and a capacitor C21. The pixel circuit 51E is a 3Tr1C pixel circuit having three transistors and one capacitor. One of the source and drain of the transistor M21 is connected to a wiring SL. One of the source and drain of the transistor M22 is connected to a wiring ANO. One of the source and drain of the transistor M23 is connected to a wiring V0. The other of the source and drain of the transistor M21 is connected to the gate of the transistor M22 and one electrode of the capacitor C21. The other of the source and drain of the transistor M22 is connected to the other of the source and drain of the transistor M23, the other electrode of the capacitor C21, and the anode of the light-emitting device 61. The cathode of the light-emitting device 61 is connected to a wiring VCOM.

[0402] The gate of the transistor M21 is connected to the wiring GL11. The gate of the transistor M23 is connected to the wiring GL12. By connecting the gate of the transistor M21 to a wiring different from the wiring to which the gate of the transistor M23 is connected, potentials of different magnitudes can be applied to the gate of the transistor M21 and the gate of the transistor M23, respectively, and these transistors can operate independently.

[0403] The transistor M21 functions as a selection transistor, the transistor M22 functions as a drive transistor, and the capacitive element C21 has a function of holding the gate potential of the transistor M22. The intensity of light emitted by the light-emitting device 61 is controlled in accordance with an image signal supplied to the gate of the transistor M22. For the transistor M23, the description of the transistor 52C can be referred to.

[0404] 21B shows an example of a configuration different from the above-described pixel 230. The pixel 230 has a pixel circuit 51F and a light-emitting device 61.

[0405] The pixel circuit 51F includes a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a capacitor C11, and a capacitor C12. The pixel circuit 51F is a 6Tr2C type pixel circuit including six transistors and two capacitors.

[0406] The anode of the light-emitting device 61 is connected to one of the source and drain of the transistor M15. The cathode of the light-emitting device 61 is connected to the wiring VCOM. The other of the source and drain of the transistor M15 is connected to one of the source and drain of the transistor M12, one of the source and drain of the transistor M13, one of the source and drain of the transistor M16, one electrode of the capacitance element C11, and one electrode of the capacitance element C12. The gate of the transistor M12 is connected to one of the source and drain of the transistor M11, the other of the source and drain of the transistor M13, and the other electrode of the capacitance element C11. The back gate of the transistor M12 is connected to one of the source and drain of the transistor M14 and the other electrode of the capacitance element C12.

[0407] The other of the source and drain of transistor M11 is connected to wiring SL. The other of the source and drain of transistor M12 is connected to wiring ANO. The other of the source and drain of transistor M14 is connected to wiring V0. The other of the source and drain of transistor M16 is connected to wiring V1. For example, a constant potential is supplied to wiring V1. The gates of transistors M11 and M16 are connected to wiring GL1. The gates of transistors M13 and M14 are connected to wiring GL2. The gate of transistor M15 is connected to wiring GL3.

[0408] The transistor M11 functions as a selection transistor that controls the conductive state or non-conductive state between the gate of the transistor M12 and the wiring SL. The transistor M12 functions as a drive transistor that controls the current flowing through the light-emitting device 61. The transistor M14 changes the potential supplied from the wiring V0 to a potential corresponding to the threshold voltage of the transistor M12 and supplies the changed potential to the back gate of the transistor M12. The threshold voltage can be controlled by supplying a constant potential to the back gate of the transistor M12. The capacitor C11 maintains the gate potential (potential difference between the gate and source) of the transistor M12. The capacitor C12 maintains the back gate potential (potential difference between the back gate and source) of the transistor M12. The pixel circuit 51F has a so-called internal threshold voltage correction function that corrects the threshold voltage of the transistor M12 using the back gate. Specifically, the capacitor C12 maintains a back gate potential such that the threshold voltage of the transistor M12 becomes 0 V. This makes it possible to correct the threshold voltage of the transistor M12 to a constant value of 0 V or near 0 V, regardless of variations in the threshold voltage of the transistor and deterioration over time.

[0409] 22A shows an example of a configuration different from the above-described pixel 230. The pixel 230 includes a pixel circuit 51G and a liquid crystal device 62.

[0410] The pixel circuit 51G includes a transistor 52A and a capacitor 53. One of the source and drain of the transistor 52A is connected to a wiring SL, and the gate of the transistor 52A is connected to a wiring GL. The other of the source and drain of the transistor 52A is connected to one electrode of the capacitor 53 and the liquid crystal device 62. The other electrode of the capacitor 53 is connected to a wiring VCOM.

[0411] A transistor 52A may have a back gate, as in a pixel circuit 51H shown in Fig. 22B, in which the back gate of the transistor 52A is connected to the gate.

[0412] Figure 23A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0413] 23A includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0414] The display device 50A employs a side-by-side (SBS) structure, in which light-emitting layers are created for light-emitting elements (light-emitting devices) with different emission wavelengths. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the freedom in material and configuration selection and facilitating improvements in brightness and reliability.

[0415] The display device 50A is a top emission type, which allows transistors and the like to be arranged so as to overlap the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0416] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured in the same process. Note that the transistors 205D, the transistor 205R, the transistor 205G, and the transistor 205B may have different structures.

[0417] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B is shown. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0418] Specifically, the transistors 205D, 205R, 205G, and 205B each include a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, a conductive layer 112a and a conductive layer 112b that function as a source and a drain, a semiconductor layer 108 containing metal oxide, and an insulating layer 110. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0419] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0420] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0421] The display device of this embodiment may have a Si transistor.

[0422] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0423] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0424] In terms of the saturation of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the change in the source-drain current is small even when the source-drain voltage is changed, and therefore the light-emitting luminance of the light-emitting element can be stabilized.

[0425] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0426] All the transistors included in the display portion 162 may be OS transistors, or all the transistors included in the display portion 162 may be Si transistors. Alternatively, some of the transistors included in the display portion 162 may be OS transistors and the rest may be Si transistors. Silicon may be single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS). A transistor using LTPS in a channel formation region (hereinafter also referred to as an LTPS transistor) has high field-effect mobility and can operate at high speed.

[0427] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0428] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0429] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly low (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0430] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218. The above description of the insulating layer 218 can be referred to.

[0431] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Note that the pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrodes 111.

[0432] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0433] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 23A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0434] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 23A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0435] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 23A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0436] 23A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited thereto. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length increases the intensity of the light emitted by each layer. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element to be improved.

[0437] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0438] Ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the materials that can be used for the insulating layer 218 and the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0439] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may be provided up to the edge of the display device 50A.

[0440] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0441] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0442] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0443] Materials for forming the pair of electrodes of a light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these metals in combination. Other examples of such materials include ITO, ITSO, indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum alloys, such as an aluminum-nickel-lanthanum alloy (Al-Ni-La), and silver-magnesium alloys and silver-palladium-copper alloys (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0444] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0445] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10−２ Preferably, it is Ωcm or less.

[0446] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 23A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 23A , but this is not limited to this. In other words, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap but are spaced apart.

[0447] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0448] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0449] Quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Quantum dot materials containing elements from groups 2 and 16, 13 and 15, 13 and 17, 11 and 17, or 14 and 15 can also be used. Quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can also be used.

[0450] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and hole-transport properties) or a TADF material can be used.

[0451] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth and light emission can be achieved efficiently. This configuration allows for high efficiency, low-voltage operation, and a long lifetime of the light-emitting element.

[0452] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0453] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0454] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0455] In Figure 23A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0456] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 23A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0457] The protective layer 131 is preferably provided in at least the display portion 162 and is provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162 but also the connection portion 140 and the circuit portion 164. The protective layer 131 is also preferably provided up to the edge of the display device 50A. Meanwhile, in the connection portion 197, a region where the protective layer 131 is not provided is generated in order to connect the FPC 172 and the conductive layer 166.

[0458] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0459] The protective layer 131 can have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0460] The protective layer 131 has an inorganic film, which can prevent the common electrode 115 from being oxidized, suppress impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0461] The protective layer 131 preferably includes one or more inorganic insulating layers. The protective layer 131 can be made of a material that can be used for the insulating layer 110. In particular, the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.

[0462] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0463] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0464] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0465] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0466] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. FIG. 23A shows an example in which the conductive layer 165 is a conductive layer obtained by processing the same conductive film as the conductive layer 112b. An example in which the conductive layer 166 is a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B is shown. The connection portion between the conductive layer 165 and the conductive layer 166 can have the same structure as the connection portion between the pixel electrode 111 and the conductive layer 112b. Specifically, FIG. 23A shows an example in which an opening is provided above the conductive layer 165, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 through the opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be connected via the connection layer 242 .

[0467] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0468] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, and the like.

[0469] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0470] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.

[0471] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0472] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0473] Substrate 151 and substrate 152 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrate 151 and substrate 152 can be made of glass having a thickness sufficient to provide flexibility.

[0474] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0475] The adhesive layer 142 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0476] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0477] <Configuration Example 2 of Display Device> Figure 23B shows an example of a cross section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each subpixel of each color. The configuration shown in Figure 23B can be combined with the region including the FPC 172, the circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the end portion configuration shown in Figure 23A. Note that in the following description of the display device, descriptions of parts similar to those of the display device described above may be omitted.

[0478] A display device 50B shown in FIG. 23B includes light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0479] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0480] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0481] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0482] The light-emitting elements 130R, 130G, and 130B each share the EL layer 113 and the common electrode 115. The configuration in which the subpixels of each color are provided with a common EL layer 113 can reduce the number of manufacturing steps compared to the configuration in which the subpixels of each color are provided with different EL layers.

[0483] 23B emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0484] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers can be selected such that the emission colors of the two light-emitting layers have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer have a complementary color relationship, a configuration in which the light-emitting element as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0485] The EL layer 113 preferably includes, for example, a light-emitting layer having a light-emitting substance that emits blue light and a light-emitting layer having a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0486] A tandem structure is preferably used for the light-emitting element emitting white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and red light, and a light-emitting unit that emits blue light, in this order, or the like can be applied. For example, the number of stacked light-emitting units and the order of colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of stacked light-emitting layers in light-emitting unit X and the order of colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0487] By applying a microcavity structure, a light emitting element configured to emit white light may emit light of a specific wavelength such as red, green, or blue that is intensified.

[0488] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 23B emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or light-emitting element 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or light-emitting element 130G into light with a longer wavelength, thereby extracting red or green light. The above-mentioned description of the color conversion layer can be referred to. Specifically, the color conversion layer can be formed using the various quantum dot materials described above. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A portion of the light emitted by the light-emitting element may be transmitted directly without being converted by the color conversion layer. By extracting the light that has transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0489] <Configuration Example 3 of Display Device> A display device 50C shown in FIG. 24 is different from the display device 50A mainly in that it includes a conductive layer 234p, a conductive layer 234a, a conductive layer 234b, and an insulating layer 239.

[0490] An insulating layer 239 is provided over the insulating layer 235, and the light-emitting elements 130R, 130G, and 130B are provided over the insulating layer 239.

[0491] The conductive layer 234p is provided to cover the openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. The conductive layer 234p is in contact with the conductive layer 112b included in the transistor 205R in the openings and is connected to the conductive layer 112b.

[0492] An insulating layer 239 is provided over the conductive layer 234p and the insulating layer 235. The insulating layer 239 can be formed using any of the materials listed for the insulating layer 235.

[0493] The pixel electrode 111R is provided so as to cover an opening provided in the insulating layer 239. The pixel electrode 111R is in contact with the conductive layer 234p in the opening and is connected to the conductive layer 234p. In other words, the pixel electrode 111R is connected to the conductive layer 112b via the conductive layer 234p. The same applies to the pixel electrodes 111G and 111B.

[0494] The conductive layer 234a is provided to cover the openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. The conductive layer 234a is in contact with and connected to the conductive layer 165 in the openings.

[0495] The conductive layer 166 is provided to cover the opening provided in the insulating layer 239. The conductive layer 166 is in contact with and connected to the conductive layer 234a in the opening. That is, the conductive layer 166 is connected to the conductive layer 165 through the conductive layer 234a.

[0496] 24 shows a structure in which the circuit portion 164 includes a conductive layer 234b. Note that the conductive layer 234b can be connected to the transistor 205D.

[0497] The conductive layer 234p, the conductive layer 234a, and the conductive layer 234b each function as a wiring. The conductive layer 234p, the conductive layer 234a, and the conductive layer 234b are provided in a layer different from the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. Therefore, wiring can be arranged in each layer, which increases the degree of freedom in layout and enables the area occupied by the circuit to be reduced.

[0498] The conductive layer 234p, the conductive layer 234a, and the conductive layer 234b can be formed using the same materials as those for the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. The conductive layer 234p, the conductive layer 234a, and the conductive layer 234b can be formed in the same process. For example, the conductive layer 234p, the conductive layer 234a, and the conductive layer 234b can be formed by forming a conductive film and processing the conductive film.

[0499] <Configuration Example 4 of Display Device> A display device 50F shown in FIG. 25 differs from the display device 50B mainly in that it is a bottom-emission display device.

[0500] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0501] 25 shows an example in which the light-shielding layer 117 is provided over the substrate 151, the insulating layer 153 is provided over the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided over the insulating layer 153. In addition, the coloring layers 132R, 132G, and 132B are provided over the insulating layer 218, and the insulating layer 235 is provided over the coloring layers 132R, 132G, and 132B.

[0502] The light emitting element 130R overlapping the colored layer 132R includes a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0503] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0504] The light emitting element 130B overlapping the colored layer 132B has a pixel electrode 111B, an EL layer 113 and a common electrode 115.

[0505] The pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal or the like with low electrical resistivity can be used for the common electrode 115, which can suppress voltage drops caused by the electrical resistance of the common electrode 115 and achieve high display quality.

[0506] The transistor of one embodiment of the present invention is miniaturized and can occupy a small area; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the size of the pixel can be reduced.

[0507] <Configuration Example 5 of Display Device> A display device 50G shown in FIG. 26A differs from the display device 50A mainly in that it includes a light receiving element 130S.

[0508] The display device 50G has a light-emitting element and a light-receiving element in each pixel. In the display device 50G, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element.

[0509] In the display device 50G, in which pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so that the contact or proximity of an object can be detected while displaying an image. Therefore, the display unit 162 has one or both of an imaging function and a sensing function in addition to the image display function. For example, in addition to displaying an image using all of the sub-pixels of the display device 50G, some of the sub-pixels can emit light as a light source, other sub-pixels can perform light detection, and the remaining sub-pixels can display an image.

[0510] Therefore, there is no need to provide a light receiving unit and a light source separately from the display device 50G, and the number of components in the electronic device can be reduced. For example, there is no need to provide a separate biometric authentication device or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50G, it is possible to provide an electronic device with reduced manufacturing costs.

[0511] When a light receiving element is used as an image sensor, the display device 50G can capture an image using the light receiving element. For example, the image sensor can capture an image for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, or the like.

[0512] The light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor). A touch sensor can detect an object (such as a finger, hand, or pen) when the object comes into direct contact with the display device. A non-contact sensor can detect an object without the object touching the display device.

[0513] The light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50G.

[0514] The pixel electrode 111S is connected to a conductive layer 112b of the transistor 205S in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.

[0515] The end of the pixel electrode 111S is covered with an insulating layer 237.

[0516] The common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B. The common electrode 115 shared by the light emitting element and the light receiving element is connected to a conductive layer 123 provided in the connection portion 140.

[0517] The functional layer 113S has at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors including organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer is shown. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), allowing the use of a common manufacturing device.

[0518] The functional layer 113S may further include a layer containing a substance with high hole transporting properties, a substance with high electron transporting properties, a bipolar substance, or the like, as a layer other than the active layer. Furthermore, without being limited to the above, the functional layer 113S may further include a layer containing a substance with high hole injection properties, a hole blocking material, a substance with high electron injection properties, an electron blocking material, or the like. For example, the materials that can be used for the light-emitting element described above can be used for the functional layer 113S.

[0519] The light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0520] A display device 50G shown in FIGS. 26B and 26C has, between a substrate 151 and a substrate 152, a layer 353 having a light receiving element, a circuit layer 355, and a layer 357 having a light emitting element.

[0521] The layer 353 includes, for example, the light receiving element 130S. The layer 357 includes, for example, the light emitting elements 130R, 130G, and 130B.

[0522] The circuit layer 355 includes a circuit for driving the light receiving element and a circuit for driving the light emitting element. The circuit layer 355 includes, for example, transistors 205R, 205G, and 205B. In addition, the circuit layer 355 may include one or more of a switch, a capacitor, a resistor, a wiring, a terminal, and the like.

[0523] 26B shows an example in which the light receiving element 130S is used as a touch sensor. As shown in FIG. 26B, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that touches the display device 50G, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has touched the display device 50G.

[0524] 26C shows an example in which the light receiving element 130S is used as a non-contact sensor. As shown in FIG. 26C, light emitted by a light emitting element in a layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50G, and the light receiving element in a layer 353 detects the reflected light.

[0525] 27A is an example of a display device to which an MML (metal maskless) structure is applied. That is, the display device 50H has light-emitting elements fabricated without using a fine metal mask.

[0526] The island-shaped light-emitting layers in the light-emitting elements of a display device employing the MML structure are formed by depositing a light-emitting layer on one surface and then processing it using lithography. This allows for the realization of high-definition display devices or display devices with a high aperture ratio, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be created separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized. For example, if a display device is composed of three types of light-emitting elements, namely, light-emitting elements that emit blue light, light-emitting elements that emit green light, and light-emitting elements that emit red light, the three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0527] Because MML structure devices can be manufactured without using a metal mask, they can exceed the upper limit of resolution imposed by the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the metal mask cleaning process are unnecessary. Furthermore, since the same or similar equipment as that used for manufacturing transistors can be used for lithography processing, there is no need to introduce special equipment for manufacturing MML structure devices. As such, the MML structure allows for low manufacturing costs, making it suitable for mass production of devices.

[0528] In a display device to which the MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, and therefore it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) using a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.

[0529] By providing a sacrificial layer over the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0530] By employing a film formation step using an area mask and a processing step using a resist mask, a light-emitting element can be manufactured through a relatively simple process.

[0531] The layered structure from the substrate 151 to the insulating layer 235 and the layered structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, and therefore will not be described here.

[0532] In FIG. 27A, light emitting elements 130 R, 130 G, and 130 B are provided on an insulating layer 235 .

[0533] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in FIG. 27A emits red light (R). The layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 114 can be collectively referred to as an EL layer. One or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

[0534] The light-emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in FIG. 27A emits green light (G). The layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 114 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0535] The light-emitting element 130B includes a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in FIG. 27A emits blue light (B). The layer 133B includes a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 114 can be collectively referred to as an EL layer. One or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

[0536] In this specification and the like, among the EL layers included in the light-emitting elements, layers provided in an island shape for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 114. Note that in this specification and the like, the layers 133R, 133G, and 133B may be referred to as island-shaped EL layers or EL layers formed in an island shape, without including the common layer 114. Furthermore, a light-emitting element manufactured without using a metal mask may not have a common layer, and all layers constituting the EL layer may be formed in an island shape.

[0537] The layers 133R, 133G, and 133B are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.

[0538] 27A, the layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limitative and the layers 133R, 133G, and 133B may have different thicknesses.

[0539] The conductive layer 124R is connected to the conductive layer 112b of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the conductive layer 124G is connected to the conductive layer 112b of the transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of the transistor 205B.

[0540] The conductive layers 124R, 124G, and 124B are formed so as to cover the openings provided in the insulating layer 235. A layer 128 is buried in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0541] The layer 128 has a function of planarizing the recesses of the conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B connected to the conductive layers 124R, 124G, and 124B are provided on the conductive layers 124R, 124G, and 124B and the layer 128. Therefore, the regions overlapping with the recesses of the conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixel. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layers 124R and 126R.

[0542] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 237 described above can be used for the layer 128.

[0543] 27A shows an example in which the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0544] The height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.

[0545] The end of the conductive layer 126R may be flush with the end of the conductive layer 124R, or may cover the side surface of the end of the conductive layer 124R. The end of each of the conductive layers 124R and 126R preferably has a tapered shape. Specifically, the end of each of the conductive layers 124R and 126R preferably has a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By tapering the side surface of the pixel electrode, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0546] The conductive layers 124G, 126G and the conductive layers 124B, 126B are similar to the conductive layers 124R, 126R, and therefore detailed description thereof will be omitted.

[0547] The upper surface and side surfaces of the conductive layer 126R are covered with the layer 133R. Similarly, the upper surface and side surfaces of the conductive layer 126G are covered with the layer 133G, and the upper surface and side surfaces of the conductive layer 126B are covered with the layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0548] Part of the top surface and side surfaces of each of the layers 133R, 133G, and 133B are covered with insulating layers 125 and 127. A common layer 114 is provided on the layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to a plurality of light-emitting elements.

[0549] In FIG. 27A , the insulating layer 237 shown in FIG. 23A and other figures is not provided between the conductive layer 126R and the layer 133R. Similarly, the insulating layer 237 is not provided between the conductive layer 126G and the layer 133G, and between the conductive layer 126B and the layer 133B. That is, the display device 50H does not have an insulating layer (also referred to as a partition wall, bank, spacer, or the like) that is in contact with the pixel electrode and covers the upper end of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This allows a high-definition or high-resolution display device to be obtained. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0550] As described above, the layers 133R, 133G, and 133B each have a light-emitting layer. The layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer). Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer). Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer, a carrier block layer, and a carrier transport layer on the carrier block layer. It is more preferable that the carrier transport layer be provided on the light-emitting layer. It is more preferable that the carrier block layer be provided on the light-emitting layer. When the surfaces of the layers 133R, 133G, and 133B are exposed to the atmosphere during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the light-emitting layer prevents the light-emitting layer from being exposed to the outermost surface, thereby preventing the light-emitting layer from being exposed to the atmosphere, thereby reducing damage to the light-emitting layer and improving the reliability of the light-emitting element.

[0551] The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.

[0552] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B with the insulating layer 125 interposed therebetween.

[0553] The side surfaces (and even part of the upper surfaces) of the layers 133R, 133G, and 133B are covered with at least one of the insulating layer 125 and the insulating layer 127, which prevents the common layer 114 (or the common electrode 115) from coming into contact with the pixel electrodes and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements, thereby improving the reliability of the light-emitting elements.

[0554] The insulating layer 125 preferably has a region in contact with each side surface of the layer 133R, the layer 133G, and the layer 133B. By configuring the insulating layer 125 to be in contact with the layer 133R, the layer 133G, and the layer 133B, peeling of the layer 133R, the layer 133G, and the layer 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0555] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0556] By providing the insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, which reduces large unevenness in height on the surface on which layers (e.g., a carrier injection layer, a common electrode, etc.) are formed on the island-shaped layers, thereby making the surface flatter, thereby improving the coverage of the carrier injection layer, the common electrode, etc.

[0557] The common layer 114 and the common electrode 115 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting elements). In the display device of one embodiment of the present invention, the insulating layer 125 and the insulating layer 127 can flatten the step, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection due to disconnection can be suppressed. Furthermore, the step can suppress an increase in electrical resistance due to a local thinning of the common electrode 115.

[0558] The upper surface of the insulating layer 127 preferably has a highly flat shape. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a convex curved shape with a large radius of curvature.

[0559] The insulating layer 125 can have a single-layer structure or a stacked structure of two or more layers. The insulating layer 125 preferably has one or more inorganic insulating layers. The insulating layer 125 can be formed using a material that can be used for the insulating layer 110. Aluminum oxide is particularly preferable because it has a high etching selectivity with respect to the EL layer and has a function of protecting the EL layer during the formation of the insulating layer 127. By using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 125, the insulating layer 125 can be formed with few pinholes and excellent protection of the EL layer. The insulating layer 125 may also have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulating layer 125 may have a stacked structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0560] The insulating layer 125 preferably functions as a barrier film against at least one of water and oxygen, and preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 also preferably has a function of capturing or fixing (gettering) at least one of water and oxygen.

[0561] The insulating layer 125 functions as a barrier film, which can prevent impurities (typically, at least one of water and oxygen) from diffusing from the outside into each light-emitting element. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.

[0562] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. Furthermore, by reducing the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both of them.

[0563] The insulating layer 127 provided on the insulating layer 125 has a function of flattening large unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.

[0564] An insulating layer containing an organic material can be suitably used as the insulating layer 127. It is preferable to use a photosensitive resin as the organic material, and for example, it is preferable to use a photosensitive resin composition containing an acrylic resin. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0565] The insulating layer 127 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins. Alternatively, the insulating layer 127 may be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. Alternatively, a photoresist may be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive resin.

[0566] The insulating layer 127 may be made of a material that absorbs visible light. The insulating layer 127 absorbs light emitted from the light-emitting element, thereby suppressing leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lightweight and thin.

[0567] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to form a black or nearly black resin layer.

[0568] <Configuration Example 7 of Display Device> Figure 27B shows an example of a cross section of the display unit 162 of the display device 50I. The display device 50I differs from the display device 50H mainly in that a colored layer (such as a color filter) is provided in each subpixel of each color. The configuration shown in Figure 27B can be combined with the region including the FPC 172, the circuit unit 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection unit 140, and the configuration of the end portion shown in Figure 27A.

[0569] A display device 50I shown in FIG. 27B includes light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0570] The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50I through the colored layer 132R. Similarly, the light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50I through the colored layer 132G. The light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50I through the colored layer 132B.

[0571] Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed using the same material and in the same process. Furthermore, these three layers 133 are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.

[0572] 27B emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0573] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 27B emit blue light. In this case, the layer 133 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or the light-emitting element 130G into light with a longer wavelength, thereby allowing red or green light to be extracted. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0574] <Configuration Example 8 of Display Device> A display device 50J shown in FIG. 28 differs from the display device 50I mainly in that it is a bottom-emission type display device.

[0575] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substr...

Claims

a semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a first region in contact with the first conductive layer in the opening, a second region in contact with a side surface of the first insulating layer in the opening, and a third region in contact with the second conductive layer; the semiconductor layer has crystal grains, The crystal grain has regions located in the first region, the second region, and the third region. 　 In claim 1, the semiconductor layer comprises indium and oxygen; the first conductive layer is polycrystalline; the first conductive layer comprises indium, tin, and oxygen; the second conductive layer is amorphous, The semiconductor device, wherein the second conductive layer contains indium, tin, silicon, and oxygen. 　 In claim 1, the semiconductor layer comprises indium and oxygen; the first conductive layer is amorphous, the first conductive layer comprises indium, tin, silicon, and oxygen; the second conductive layer is polycrystalline; The semiconductor device, wherein the second conductive layer contains indium, tin, and oxygen. 　 a semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a first region in contact with the first conductive layer in the opening, a second region in contact with a side surface of the first insulating layer in the opening, and a third region in contact with the second conductive layer; the semiconductor layer has first crystal grains and second crystal grains; the first crystal grain has a region located in the first region and the second region, the second crystal grain has a region located in the second region and the third region, a grain boundary between the first crystal grain and the second crystal grain has a region located in the second region. 　 In claim 4, the semiconductor layer comprises indium and oxygen; the first conductive layer and the second conductive layer are each polycrystalline; The semiconductor device, wherein the first conductive layer and the second conductive layer each contain indium, tin, and oxygen. 　 In any one of claims 1 to 5, a second insulating layer; the second insulating layer has a region in contact with a lower surface of the first conductive layer; the first insulating layer has a third insulating layer and a fourth insulating layer on the third insulating layer; the second insulating layer comprises silicon, nitrogen, and hydrogen; the third insulating layer comprises silicon and nitrogen; the fourth insulating layer includes silicon and oxygen; The semiconductor device, wherein the second insulating layer has a region having a higher hydrogen content than the third insulating layer. 　 In claim 6, the first insulating layer has a fifth insulating layer on the fourth insulating layer; The semiconductor device, wherein the fifth insulating layer includes silicon and nitrogen. 　 In claim 6, the first insulating layer has a fifth insulating layer on the fourth insulating layer; The semiconductor device, wherein the fifth insulating layer contains aluminum and oxygen.

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