Semiconductor device and method for manufacturing semiconductor device

Abstract

A bonding layer (15) is disposed directly on a diamond substrate (16) and comprises an amorphous material. A silicon crystal layer (11) is bonded to the diamond substrate (16) with at least the bonding layer (15) therebetween. A buffer layer (12) comprises a nitride containing an aluminum atom, and is disposed on the bonding layer (15) with at least the silicon crystal layer (11) therebetween. A nitride semiconductor layer (13) is disposed directly on the buffer layer (12) and has a composition different from the composition of the buffer layer (12).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a semiconductor layer made of nitride and a method for manufacturing the same.

[0002] According to Japanese Patent Laid-Open Publication No. 2019-036566 (Patent Document 1), using diamond as a heat spreader or heat sink is effective for improving the heat dissipation of semiconductor devices, because diamond has high thermal conductivity. The publication also mentions a method for bonding diamond to a semiconductor substrate of a semiconductor device using a surface activated bonding method. Because diamond has extremely high rigidity during bonding, it does not deform, and many voids are likely to occur between the semiconductor substrate and the diamond. In particular, many voids are likely to occur when a SiC substrate is used as the semiconductor substrate. These voids cause a decrease in heat dissipation.

[0003] Taking this problem into consideration, the semiconductor device according to the invention described in the above publication comprises a substrate, a semiconductor chip including an element region on the substrate, a diamond heat conductor, and a metal layer between the semiconductor chip and the heat conductor, and the substrate has an amorphous region on its back surface. The amorphous region and the metal layer are bonded to each other. The metal layer and the heat conductor are bonded to each other. The element region may include a high electron mobility transistor (HEMT). According to what is claimed in the above publication, by including a substrate including an amorphous region, a heat conductor, and a metal layer, the semiconductor device can achieve excellent heat dissipation.

[0004] Furthermore, according to the method for manufacturing a semiconductor device described in the above publication, first, a semiconductor chip and a structure having a heat conductor are prepared separately. The method for preparing the semiconductor chip involves polishing the back surface of a semiconductor chip having an element region formed on the surface of a substrate. This thins the substrate. Meanwhile, the method for preparing the structure having a heat conductor involves polishing the surface of a diamond heat conductor. A metal layer is formed on this surface. Next, a rare gas beam is irradiated onto the back surface of the semiconductor chip and the surface of the metal layer. As a result, an amorphous region is formed on the back surface of the semiconductor chip. Furthermore, the back surface of the semiconductor chip and the surface of the metal layer are activated. Next, the back surface of the semiconductor chip and the surface of the metal layer are brought into close contact with each other, thereby bonding them.

[0005] International Publication No. 2023 / 048160 (Patent Document 2) discloses a semiconductor device including a HEMT. In this semiconductor device, a bonding layer, a SiC layer, and a nitride semiconductor layer are stacked in this order on a primary surface of a diamond substrate. A source electrode, a drain electrode, and a gate electrode are formed on the primary surface of the nitride semiconductor layer at intervals.

[0006] The semiconductor device manufacturing method described in the International Publication may include the following steps: First, a SiC layer and a nitride semiconductor layer are sequentially formed on a Si substrate. Next, a HEMT is formed on the nitride semiconductor layer. Next, the entire Si substrate is removed by etching. A diamond substrate is bonded to the exposed SiC layer. According to the International Publication, the bonding is preferably performed using a surface activated bonding method. In this case, first, energetic particles (e.g., Ar particles) are irradiated onto the diamond substrate and the SiC layer in a reduced pressure and room temperature atmosphere, thereby removing adsorbed materials from the diamond substrate and the SiC layer. The irradiation of the energetic particles results in the appearance of an amorphous layer primarily composed of C on the diamond substrate, and an amorphous layer primarily composed of C and Si on the SiC layer. These paired amorphous layers are brought into contact with each other, thereby bonding the diamond substrate and the SiC layer via a bonding layer including the paired amorphous layers.

[0007] JP 2019-036566 A International Publication No. 2023 / 048160

[0008] In the semiconductor device according to the invention described in the above-mentioned Japanese Patent Application Laid-Open No. 2019-036566, a metal layer is provided between the semiconductor chip and the heat transfer body. This metal layer increases the parasitic capacitance in the semiconductor device. Furthermore, in the manufacturing method according to the invention, the back surface of the semiconductor chip is polished. As a result, damage caused by polishing is likely to occur to the back surface of the portion of the semiconductor device related to the operation of the HEMT, i.e., the back surface of the nitride semiconductor layer. This damage to the back surface can increase current collapse in the HEMT. In this way, damage to the back surface of the nitride semiconductor layer can degrade the performance of the semiconductor device.

[0009] According to the above-mentioned International Publication No. 2023 / 048160, a nitride semiconductor layer is formed by homoepitaxial growth on a SiC layer provided directly on a Si substrate. However, unlike the invention described in this International Publication, a silicon crystal layer may be preferable to a SiC layer as an underlayer for homoepitaxial growth. For example, when high in-plane uniformity of the underlayer thickness is required, a silicon crystal layer is more likely to meet such a requirement than a SiC layer. Specifically, by using a silicon-on-insulator (SOI) substrate having a structure in which an insulating layer and a silicon crystal layer serving as an underlayer are sequentially stacked on a Si substrate, a silicon crystal layer suitable for the underlayer can be easily prepared. Furthermore, when a semiconductor device is manufactured using the above-mentioned SOI substrate, it is also easy to remove the Si substrate, which is ultimately unnecessary. In contrast, according to WO 2023 / 048160, when the entire Si substrate is etched away, the surface where the etching stops is the SiC layer, so it may be difficult to stop the etching precisely at a desired position, which may result in damage to the back surface of the nitride semiconductor layer, resulting in a deterioration in the performance of the semiconductor device.

[0010] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress degradation of the performance of the semiconductor device due to damage to the back surface of the nitride semiconductor layer.

[0011] The semiconductor device according to the present disclosure comprises a diamond substrate, a bonding layer made of an amorphous material and disposed directly on the diamond substrate, a silicon crystal layer bonded to the diamond substrate at least via the bonding layer, a buffer layer made of a nitride containing aluminum atoms and disposed on the bonding layer at least via the silicon crystal layer, and a nitride semiconductor layer disposed directly on the buffer layer and having a composition different from that of the buffer layer.

[0012] A method for manufacturing a semiconductor device according to the present disclosure includes: a) a step of directly or indirectly forming a buffer layer made of a nitride containing aluminum atoms on a silicon crystal layer, the silicon crystal layer being disposed directly on an oxide layer, the oxide layer being disposed on a support substrate; b) a step of forming a nitride semiconductor layer on the buffer layer, the nitride semiconductor layer having a composition different from that of the buffer layer; c) a step of forming a semiconductor element structure on the nitride semiconductor layer; d) a step of providing a protective substrate on the semiconductor element structure via an adhesive layer; e) a step of removing the support substrate after d); f) a step of bonding the silicon crystal layer and the polished surface of a diamond substrate to each other via at least a bonding layer, the bonding layer being disposed directly on the polished surface of the diamond substrate, and on the silicon crystal layer directly or via the oxide layer; and g) a step of removing the adhesive layer and the protective substrate.

[0013] According to the semiconductor device of the present disclosure, in the semiconductor device, the buffer layer is disposed on the bonding layer via at least a silicon crystal layer. Therefore, in the manufacturing of the semiconductor device, the silicon crystal layer can continue to protect the buffer layer until the structure including the nitride semiconductor layer is completely bonded to the diamond substrate using the bonding layer. This allows the buffer layer to continue to protect the back surface of the nitride semiconductor layer from damage caused by any manufacturing process. Therefore, it is possible to suppress degradation of the performance of the semiconductor device due to damage to the back surface of the nitride semiconductor layer.

[0014] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0015] 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a first embodiment. FIG. 2 is a top view schematically showing the configuration of the semiconductor device of FIG. 1. FIG. 3 is a flow diagram schematically showing a method for manufacturing the semiconductor device according to FIG. 1. FIG. 4 is a cross-sectional view schematically showing a first step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 5 is a top view schematically showing the first step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 6 is a cross-sectional view schematically showing a second step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 7 is a cross-sectional view schematically showing a third step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 8 is a cross-sectional view schematically showing a fourth step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 9 is a cross-sectional view schematically showing a fifth step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 10 is a cross-sectional view schematically showing a sixth step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 11 is a cross-sectional view schematically showing a seventh step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 12 is a cross-sectional view schematically showing an eighth step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 13 is a cross-sectional view schematically showing a ninth step in the method for manufacturing the semiconductor device according to FIG. 1. FIG. 14 is a cross-sectional view schematically showing a tenth step in the method for manufacturing the semiconductor device according to FIG. 1. 19 is a graph showing a relationship between an applied power P and a temperature rise ΔT of a current-carrying region in a semiconductor device. FIG. 20 is a graph showing a relationship between a thickness of a silicon crystal layer in a semiconductor device and a temperature rise rate Rth. FIG. 21 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. FIG. 23 is a flow chart showing a method for manufacturing the semiconductor device according to FIG. 19. FIG. 24 is a cross-sectional view showing a process in the method for manufacturing the semiconductor device according to FIG. 19.

[0016] Hereinafter, embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and their description will not be repeated. The size of each element in the drawings may differ from the actual size in order to make the drawings easier to see.

[0017] 1 and 2 are a cross-sectional view and a top view, respectively, that schematically show the configuration of a semiconductor device 100 according to the present embodiment 1. In the top view of Fig. 2, the surface electrodes 14 are given a dotted pattern to make them easier to identify.

[0018] The semiconductor device 100 has a diamond substrate 16, a bonding layer 15, a silicon crystal layer 11, a buffer layer 12, and a nitride semiconductor layer 13. The diamond substrate 16, the bonding layer 15, the silicon crystal layer 11, the buffer layer 12, and the nitride semiconductor layer 13 may be stacked in this order as shown in FIG. 1 . A semiconductor device structure ES is provided on a main surface FM1 of the nitride semiconductor layer 13. The semiconductor device structure ES may include a surface electrode 14. In the first embodiment, the semiconductor device structure ES has a HEMT structure, and the surface electrode 14 includes a plurality of electrode portions, namely, a gate electrode portion 14a, a source electrode portion 14b, and a drain electrode portion 14c. The semiconductor device structure ES may have an insulating film in addition to the surface electrode 14. The semiconductor device structure ES may also have a protective film that protects its surface. The insulating film may be made of, for example, SiN, Al ２ O ３ , or SiO ２ The protective film is made of, for example, polyimide.

[0019] The diamond substrate 16 is made of a single crystal diamond, a mosaic diamond, or a polycrystalline diamond. A mosaic diamond is made up of multiple single crystal diamonds bonded together in the in-plane direction (the lateral direction in FIG. 1). The diamond substrate 16 may have a thickness of 50 μm or more and 600 μm or less.

[0020] The bonding layer 15 is disposed directly on the diamond substrate 16 and is made of an amorphous material. The material of the bonding layer 15 may be a single-layer material or a laminated material. The bonding layer 15 may include an amorphous carbon layer disposed directly on the diamond substrate 16. The amorphous carbon layer may have a thickness of 1 nm or less. The bonding layer 15 may include a silicon-containing layer. The silicon-containing layer may be laminated on the amorphous carbon layer. The silicon-containing layer is a layer containing silicon atoms. The silicon-containing layer may further contain carbon atoms and / or oxygen atoms. Therefore, the material of the silicon-containing layer may be, for example, Si, SiO Ｘ (X>0), SiC, or SiC Ｘ O Ｙ (X>0, Y>0).

[0021] The thickness of the bonding layer 15 is preferably 1 nm or more and 10 nm or less, more preferably 1 nm or more and 5 nm or less. The bonding layer 15 has a first interface IF1 in contact with the diamond substrate 16 and a second interface IF2 opposite the first interface IF1. In the first embodiment, the second interface IF2 is the interface between the bonding layer 15 and the silicon crystal layer 11. The first interface IF1 may have an arithmetic mean roughness of 0.5 nm or less. In other words, the upper surface of the diamond substrate 16 in FIG. 1 (corresponding to the main surface FM3 in FIG. 12) may have an arithmetic mean roughness of 0.5 nm or less. The second interface IF2 may have an arithmetic mean roughness of 0.5 nm or less. In other words, the back surface FB2 of the silicon crystal layer 11 may have an arithmetic mean roughness of 0.5 nm or less.

[0022] The silicon crystal layer 11 is bonded to the diamond substrate 16 via at least a bonding layer 15. In the first embodiment, the silicon crystal layer 11 is directly bonded to the bonding layer 15. The silicon crystal layer 11 may be a single-crystal Si layer. The silicon crystal layer 11 serves as an underlayer, in other words, a growth substrate, when the buffer layer 12 and the nitride semiconductor layer 13 are grown in sequence. The thickness of the silicon crystal layer 11 is preferably 0.5 μm or more and 20.0 μm or less, and more preferably 0.5 μm or more and 5.0 μm or less. The silicon crystal layer 11 may have a resistivity of 5000 Ω cm or less.

[0023] The buffer layer 12 is disposed on the bonding layer 15 with at least the silicon crystal layer 11 interposed therebetween. In the first embodiment, the buffer layer 12 is disposed directly on the silicon crystal layer 11. The thickness of the buffer layer 12 is preferably 2 μm or less. The buffer layer 12 is made of a nitride containing aluminum atoms. The nitride may also contain gallium atoms. The material of the buffer layer 12 may be a single-layer material or a laminated material in which multiple materials with different compositions are applied. Specifically, the material of the buffer layer 12 is, for example, AlGaN or AlN. The component ratio of Al atoms in the composition of the buffer layer 12 may be different from the component ratio of Al atoms in the composition of the nitride semiconductor layer 13.

[0024] The nitride semiconductor layer 13 is disposed directly on the buffer layer 12. Taking into consideration the influence on heat dissipation performance, the thickness of the nitride semiconductor layer 13 is preferably 10 μm or less. The nitride semiconductor layer 13 has a composition different from that of the buffer layer 12. The material of the nitride semiconductor layer 13 may contain aluminum atoms, but does not necessarily contain them. The material of the nitride semiconductor layer 13 may be a single-layer material or a multi-layer material. The single-layer material may be SiN, GaN, AlGaN, InAlN, or AlN, and may be doped with impurities such as Fe and / or C. The multi-layer material may include two or more of the above-mentioned materials.

[0025] The material of the surface electrode 14 may be a single metal element or an alloy. The single metal element may be one element selected from the group consisting of Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, and Mo. The alloy may be AlSi, AlCu, AuGe, AuGa, or AuSn. The material of the surface electrode 14 may be a laminate of two or more of the above-mentioned materials. When the surface electrode 14 includes multiple electrode portions, the materials of the multiple electrode portions may be the same or different.

[0026] Fig. 3 is a flow diagram schematically showing a manufacturing method MM1 of the semiconductor device 100 (Fig. 1). Figs. 4 and 5 are a cross-sectional view and a top view, respectively, schematically showing a first step in the manufacturing method of the semiconductor device 100. Figs. 6 to 14 are cross-sectional views schematically showing second to tenth steps in the manufacturing method of the semiconductor device 100, respectively.

[0027] 4 and 5, first, an SOI substrate 10 is formed. The SOI substrate 10 is composed of a silicon crystal layer 11, an oxide layer 19, and a support substrate 20. The oxide layer 19 is disposed on the support substrate 20. The silicon crystal layer 11 is disposed directly on the oxide layer 19. In the SOI substrate 10, the thickness of the support substrate 20 is preferably 500 μm or more and 700 μm or less. The thickness of the oxide layer 19 is preferably 0.1 μm or more and 2.0 μm or less. The support substrate 20 is typically a Si substrate.

[0028] In the SOI substrate 10, the silicon crystal layer 11 preferably has an in-plane uniformity within 10%. Preferably, such in-plane uniformity is achieved in an SOI substrate 10 (wafer) having a diameter of approximately 50 millimeters (2 inches) or more. The in-plane uniformity of the silicon crystal layer 11 may be calculated based on the thickness at nine measurement points PM ( FIG. 5 ) shown in FIG. 5 , for example. One of the measurement points may be approximately the center of the wafer. The other eight measurement points may be selected at approximately equiangular intervals (in other words, at approximately 45° intervals) on the boundary between the ineffective area at the outer edge of the wafer and the effective area inside it. Using the maximum, minimum, and average thickness values ​​at these measurement points, the in-plane uniformity may be calculated using the following formula: In-plane uniformity (%) = (maximum value - minimum value) / (average value × 2) × 100.

[0029] To obtain the SOI substrate 10, for example, a silicon crystal layer 11 is bonded to a support substrate 20 via an oxide layer 19, and then the silicon crystal layer 11 is given a desired thickness and in-plane uniformity by grinding and polishing. The silicon crystal layer 11 may be deposited on the oxide layer 19 instead of being bonded thereto. At this time, a dopant such as boron or phosphorus may be added to adjust the resistivity. Alternatively, a technique called SIMOX (separation by implanted oxygen) method may be used. That is, the silicon crystal layer 11 and the oxide layer 19 may be formed on the surface of the support substrate 20 by implanting a high concentration of oxygen ions into a single-crystal silicon substrate and then performing a high-temperature heat treatment. In the following description of the manufacturing method, a case where the support substrate 20 is a single-crystal Si substrate and the oxide layer is a silicon oxide film will be exemplified.

[0030] 6, in step ST10 (FIG. 3), a buffer layer 12 made of nitride is formed directly or indirectly on the silicon crystal layer 11 of the SOI substrate 10. In the first embodiment, the buffer layer 12 is formed directly on the silicon crystal layer 11. Next, in step ST20 (FIG. 3), a nitride semiconductor layer 13 having a composition different from that of the buffer layer 12 is formed on the buffer layer 12. These are formed by, for example, a metal organic chemical vapor deposition (MOCVD) method or the like. Next, with reference to FIG. 7, in step ST30 (FIG. 3), a semiconductor element structure ES is formed on the main surface FM1 of the nitride semiconductor layer 13.

[0031] 8, in step ST40 (FIG. 3), a protective substrate 18 is provided on the main surface FM1 (FIG. 7) on which the semiconductor element structure ES is provided, via an adhesive layer 17. The adhesive layer 17 may be made of an adhesive material containing resin. The protective substrate 18 is provided temporarily to protect the semiconductor element structure ES. The thickness of the protective substrate 18 is, for example, 500 μm or more. The material of the protective substrate 18 is preferably one having high strength, and is preferably transparent when light irradiation is used to harden the adhesive layer 17. The material of the protective substrate 18 is, for example, sapphire, quartz, or SiC.

[0032] Next, in step ST50 ( FIG. 3 ), the support substrate 20 ( FIG. 8 ) is removed as shown in FIG. 9 . This removal process is performed by starting from the main surface FM4 ( FIG. 8 ) of the support substrate 20 and stopping on the oxide layer 19. This exposes the main surface FM5 of the oxide layer 19. This removal process may be performed by grinding, dry etching, or wet etching. It is easy to ensure a sufficient etching selectivity of the support substrate 20, such as a single-crystal Si substrate, to the oxide layer 19, such as a silicon oxide film. Therefore, it is easy to remove the support substrate 20 by etching without significantly sacrificing the oxide layer 19. For wet etching, an alkaline solution such as KOH, NaOH, or ammonia is used.

[0033] Next, in this first embodiment, in step ST61 ( FIG. 3 ), wet etching is performed, which has a higher etching rate for the material of the oxide layer 19 than for the material of the silicon crystal layer 11. As a result, the oxide layer 19 ( FIG. 9 ) is removed while leaving the silicon crystal layer 11, as shown in FIG. 10 . This exposes the back surface FB2 of the silicon crystal layer 11. It is very easy to ensure the etching selectivity of the silicon crystal layer 11 relative to the oxide layer 19, such as a silicon oxide film. Therefore, it is sufficiently easy to remove the oxide layer 19 by etching without sacrificing much of the silicon crystal layer 11. It is preferable to use hydrofluoric acid or buffered hydrofluoric acid for this wet etching. Because the selectivity is very easy to ensure as described above, the surface roughness of the back surface FB2 of the silicon crystal layer 11 after the oxide layer 19 is removed corresponds approximately to the surface roughness of the back surface FB2 of the silicon crystal layer 11 before the oxide layer 19 is removed ( FIG. 4 ). These surface roughnesses preferably have an arithmetic mean roughness of 0.5 nm or less.

[0034] Next, an activation process may be performed on the back surface FB2 of the silicon crystal layer 11. Specifically, the back surface FB2 is irradiated with an ion beam of a rare gas element (e.g., He, Ar, Xe, or Ne). This removes impurities and deposits on the back surface FB2 and exposes dangling bonds on the irradiated surface.

[0035] 11, a diamond substrate 16 having a main surface FM3 is prepared. The diamond substrate 16 is preferably fabricated by chemical vapor deposition (CVD). Referring further to FIG. 12, the main surface FM3 of the diamond substrate 16 is polished. This polishing is preferably performed so that the main surface FM3 has an arithmetic mean roughness of 0.5 nm or less.

[0036] 13, the bonding layer 15 is formed on the main surface FM3 (FIG. 12) of the diamond substrate 16. Therefore, the bonding layer 15 is disposed directly on the main surface FM3 (FIG. 12) of the diamond substrate 16, i.e., on the polished surface of the diamond substrate 16. Preferably, the main surface FM3 (FIG. 12) of the diamond substrate 16 is first activated. Specifically, the main surface FM3 of the diamond substrate 16 is irradiated with an ion beam of a rare gas element (e.g., He, Ar, Xe, or Ne). This removes impurities and deposits on the main surface FM3, and exposes dangling bonds on the irradiated surface. At the same time, the vicinity of the main surface FM3 of the diamond substrate 16 is amorphized, thereby forming an amorphous carbon layer on the diamond substrate 16 as at least a part of the bonding layer 15. The bonding layer 15 may then be further formed by deposition on the amorphous carbon layer. This deposition may be performed using, for example, Si, SiO ２ Alternatively, it is performed by a sputtering method using SiC as a target material.

[0037] Referring to FIG. 14 , in step ST71 ( FIG. 3 ), the silicon crystal layer 11 and the main surface FM3 ( FIG. 12 ), which is the polished surface of the diamond substrate 16, are bonded to each other via at least the bonding layer 15. In the first embodiment, the bonding layer 15 is disposed directly on the silicon crystal layer 11. This allows the structure including the diamond substrate 16 ( FIG. 13 ) and the structure including the silicon crystal layer 11 ( FIG. 10 ) to be bonded to each other via the bonding layer 15. This bonding is preferably performed by room-temperature pressure bonding. In the case of room-temperature pressure bonding, the bonded surfaces preferably have atomic-level smoothness. Specifically, the arithmetic mean roughness of the bonded surfaces is preferably 0.5 nm or less. Furthermore, while partial delamination is generally a concern in room-temperature pressure bonding, the bonding layer 15 functions to prevent this. Furthermore, since room-temperature pressure bonding does not require heating for bonding, warping due to thermal stress can be avoided.

[0038] Next, in step ST80 (FIG. 3), adhesive layer 17 and protective substrate 18 are removed (FIG. 1). Specifically, adhesive layer 17 is peeled off, so that adhesive layer 17 and protective substrate 18 are separated from the portion that will become semiconductor device 100 (FIG. 1). In this way, semiconductor device 100 is obtained.

[0039] FIG. 15 is a graph showing the relationship between the drain voltage Vds and the drain current Ids in a semiconductor device 100 having a HEMT structure. In the figure, the solid line indicates the characteristics without pulse application, and the dashed line indicates the characteristics with pulse application. The decrease in the drain current Ids (see the arrow in the figure) is related to current collapse due to carrier trapping on the back surface of the nitride semiconductor layer 13, in other words, back surface collapse. According to the first embodiment, the silicon crystal layer 11 is left in place until the semiconductor device 100 is completed, thereby reliably protecting the back surface of the nitride semiconductor layer 13. This suppresses back surface collapse. This suppresses the decrease in the drain current Ids. On the other hand, since the silicon crystal layer 11 is located between the semiconductor element structure ES and the diamond substrate 16, heat dissipation characteristics are somewhat sacrificed.

[0040] FIG. 16 is a graph showing the relationship between the applied power P (= Ids × Vds) and the temperature rise ΔT of the current-carrying region in a semiconductor device. The dashed line in the figure corresponds to a device in which the diamond substrate 16 is omitted from the semiconductor device 100 ( FIG. 1 ). In this device, the heat dissipation enhancement provided by the diamond substrate 16 is not achieved, resulting in a very large temperature rise ΔT. On the other hand, the lower of the two solid lines in the figure corresponds to a device in which the silicon crystal layer 11 is omitted from the semiconductor device 100 ( FIG. 1 ). In this device, the heat dissipation enhancement provided by the diamond substrate 16 is achieved without being hindered by the silicon crystal layer 11, resulting in a significant suppression of the temperature rise ΔT. The upper of the two solid lines in the figure corresponds to a semiconductor device having both the diamond substrate 16 and the silicon crystal layer 11. In this device, the thicker the silicon crystal layer 11, the larger the temperature rise ΔT. In other words, the heat dissipation characteristics deteriorate. However, since the heat dissipation enhancement effect of the diamond substrate 16 is very significant, this heat dissipation enhancement effect can be fully enjoyed as long as the silicon crystal layer 11 is not excessively thick. The bonding layer 15 is very thin and has little effect on heat dissipation, so reference to the bonding layer 15 is omitted in the above description.

[0041] 17 is a graph schematically illustrating the relationship between the thickness of the silicon crystal layer 11 of the semiconductor device 100 and the rate of temperature rise Rth per 1 W / mm in the semiconductor device 100. As shown in this figure, if the thickness of the silicon crystal layer 11 is 20.0 μm or less, excessive sacrifice of heat dissipation characteristics due to the silicon crystal layer 11 can be avoided. On the other hand, in order to fully obtain the effect of suppressing current collapse by the silicon crystal layer 11, its thickness is preferably 0.5 μm or more. Therefore, in order to fully obtain the effect of suppressing current collapse by the silicon crystal layer 11 while fully suppressing the influence of the silicon crystal layer 11 on deterioration of heat dissipation characteristics, its thickness is preferably 0.5 μm or more and 20.0 μm or less.

[0042] If the silicon crystal layer 11 is removed by etching and / or grinding the bottom of the structure shown in FIG. 10 and the removal process can be stopped when the back surface of the buffer layer 12 is exposed, and a diamond substrate 16 is bonded to the back surface via a bonding layer 15, a semiconductor device without the silicon crystal layer 11 can be obtained. In this semiconductor device, the silicon crystal layer 11 is prevented from impeding heat dissipation. However, because the buffer layer 12 is typically very thin, it is very difficult to control the removal process to stop when the buffer layer 12 is exposed. Especially in mass production, the buffer layer 12 is easily lost, exposing the back surface of the silicon crystal layer 11. To bond the diamond substrate 16 to this back surface via the bonding layer 15 with sufficient strength, the back surface must have a high degree of smoothness. To achieve such a back surface, a process such as polishing or dry etching is usually required. Such a process directly physically damages the back surface of the nitride semiconductor layer 13, resulting in worsening back surface collapse. Furthermore, even if the buffer layer 12 is lost and the back surface of the nitride semiconductor layer 13 is exposed, this may lead to an increase in back surface collapse.

[0043] According to the first embodiment, referring to FIG. 1 , the buffer layer 12 is disposed on the bonding layer 15 via at least the silicon crystal layer 11. Therefore, in the manufacturing process of the semiconductor device 100, the silicon crystal layer 11 can continue to protect the buffer layer 12 until the configuration shown in FIG. 14 is obtained in step ST71 ( FIG. 3 ), in other words, until the structure including the nitride semiconductor layer 13 is bonded to the diamond substrate 16 using the bonding layer 15. This allows the buffer layer 12 to continue to protect the rear surface of the nitride semiconductor layer 13 from damage caused by any manufacturing process. Specifically, the rear surface of the nitride semiconductor layer 13 can continue to be protected from damage caused by a polishing process for smoothing or an ion beam irradiation process for activation. This prevents performance degradation of the semiconductor device 100 caused by damage to the rear surface of the nitride semiconductor layer 13.

[0044] The bonding layer 15 is made of an amorphous material. This alleviates the reduction in bonding strength due to lattice mismatch at the bonding interface. From this perspective, it is particularly preferable that the bonding layer 15 includes an amorphous carbon layer that is in direct contact with the diamond substrate 16.

[0045] In the present embodiment 1, the silicon crystal layer 11 is directly bonded to the bonding layer 15. This prevents a decrease in heat dissipation caused by a member disposed between the silicon crystal layer 11 and the bonding layer 15, unlike when any member is disposed between the silicon crystal layer 11 and the bonding layer 15.

[0046] By making the thickness of the silicon crystal layer 11 0.5 μm or more, the buffer layer 12 can be more reliably protected during the manufacture of the semiconductor device 100. This makes it possible to more reliably suppress a decrease in performance of the semiconductor device 100, specifically, current collapse, caused by damage to the back surface of the nitride semiconductor layer 13. By making the thickness of the silicon crystal layer 11 20.0 μm or less, preferably 5.0 μm or less, it is possible to prevent the silicon crystal layer 11 from having an excessively adverse effect on heat dissipation from the nitride semiconductor layer 13 to the diamond substrate 16.

[0047] Furthermore, by making the silicon crystal layer 11 20.0 μm or less, the rigidity of the silicon crystal layer 11 can be reduced. As a result, even if the diamond substrate 16 has a slight warp, the silicon crystal layer 11 can be easily bonded along the warp. This bonding process is usually performed by bonding the SOI substrate 10, including the portion that will become the silicon crystal layer 11 of the semiconductor device 100, to the diamond substrate 16. It is preferable that the in-plane thickness uniformity of the silicon crystal layer 11 on the SOI substrate 10 be within 10%.

[0048] In the first embodiment, the buffer layer 12 is disposed directly on the silicon crystal layer 11. This prevents a decrease in heat dissipation caused by a member disposed between the buffer layer 12 and the silicon crystal layer 11.

[0049] The silicon crystal layer 11 may have a resistivity of 5000 Ω·cm or less. In this case, the occurrence of current collapse in the silicon crystal layer 11 can be suppressed.

[0050] The bonding layer 15 may include an amorphous carbon layer disposed directly on the diamond substrate 16. The amorphous carbon layer may be formed incidentally by activating the surface of the diamond substrate 16.

[0051] The bonding layer 15 may include a silicon-containing layer. The silicon-containing layer may be, for example, Si or SiO ２ and a Si layer formed by sputtering using ２ The silicon-containing layer may be any one of the layers or a stack thereof. The silicon-containing layer does not need to be a semiconductor layer to which a dopant is added, and therefore can have high resistivity, which can suppress leakage current in the semiconductor device 100.

[0052] When the thickness of the bonding layer 15 is 1 nm or more, it becomes easier to ensure sufficient bonding strength by the bonding layer 15. When the thickness of the bonding layer 15 is 10 nm or less, it becomes possible to prevent the bonding layer 15 from having an excessively adverse effect on the heat dissipation from the nitride semiconductor layer 13 to the diamond substrate 16.

[0053] The diamond substrate 16 is made of single crystal diamond, mosaic diamond, or polycrystalline diamond. Although single crystal diamond, mosaic diamond, and polycrystalline diamond have different grain boundary configurations, they all have high thermal conductivity. Therefore, all of these are suitable materials for the diamond substrate 16. In particular, the thermal conductivity of single crystal diamond and mosaic diamond is the highest among natural solids.

[0054] The diamond substrate 16 may have a thickness of 50 μm to 600 μm, which is suitable for obtaining high heat dissipation properties from the diamond substrate 16.

[0055] The arithmetic mean roughness of each of the first interface IF1 and the second interface IF2 of the bonding layer 15 may be 0.5 nm or less. By using such atomically smooth surfaces, voids or defects are less likely to occur at the first interface IF1 and the second interface IF2. This makes it possible to make bonding failures of the bonding layer 15 less likely to occur.

[0056] 9 to 10, i.e., the process of removing the oxide layer 19 while leaving the silicon crystal layer 11, is performed by wet etching. This can suppress the occurrence of damage compared to physical methods such as polishing. Furthermore, wet etching, which removes the oxide layer 19 while leaving the silicon crystal layer 11, can be performed with a high selectivity. As a result, the surface roughness of the interface between the silicon crystal layer 11 and the oxide layer 19 roughly corresponds to the surface roughness of the interface between the silicon crystal layer 11 and the adhesive layer 17. Therefore, if the former is sufficiently small, the latter can be sufficiently small. In this case, there is no need to perform a smoothing process such as polishing after wet etching.

[0057] Furthermore, when an SOI substrate 10 (FIG. 4) is used, the in-plane thickness uniformity of the silicon crystal layer 11 included therein can be easily set to within 10%. In the semiconductor device 100 obtained using the SOI substrate 10 having such high in-plane uniformity, the variation in the influence of the silicon crystal layer 11 on the heat dissipation characteristics can be sufficiently suppressed.

[0058] Second Embodiment Figure 18 is a cross-sectional view schematically showing the configuration of a semiconductor device 101 according to a second embodiment. The semiconductor device 101 differs from the semiconductor device 100 (Figure 1: first embodiment) in that the semiconductor device 101 has a silicon compound layer 21 between the silicon crystal layer 11 and the buffer layer 12. Therefore, in the second embodiment, the buffer layer 12 is indirectly disposed on the silicon crystal layer 11 via the silicon compound layer 21. The silicon compound layer 21 may be any one of a silicon carbide layer, a silicon oxide layer, and a silicon nitride layer. Alternatively, the silicon compound layer 21 may be a layer formed by stacking two or more of these layers.

[0059] Note that the configuration other than that described above is substantially the same as that of the first embodiment, and therefore the same or corresponding elements are given the same reference numerals and their description will not be repeated.

[0060] According to the second embodiment, the crystal growth of the buffer layer 12 and the nitride semiconductor layer 13 can be performed on the silicon compound layer 21. By selecting the silicon compound layer 21 suitable for the crystal growth of the buffer layer 12, it is possible to further reduce lattice defects during the crystal growth.

[0061] <Third Embodiment> Figure 19 is a cross-sectional view showing a schematic configuration of a semiconductor device 102 according to a third embodiment. The semiconductor device 102 differs from the semiconductor device 100 (Figure 1: first embodiment) in that it has an oxide layer 19. The oxide layer 19 is disposed between the silicon crystal layer 11 and the bonding layer 15. The oxide layer 19 is in direct contact with the silicon crystal layer 11 and is also directly bonded to the bonding layer 15. Therefore, the silicon crystal layer 11 is indirectly bonded to the bonding layer 15 via the oxide layer 19. The silicon crystal layer 11 is also bonded to the diamond substrate 16 via the oxide layer 19 and the bonding layer 15. The oxide layer 19 is made of SiO ２ The oxide layer 19 may have a thickness of 0.1 μm or more and 1.0 μm or less.

[0062] In the case of the semiconductor device 102 ( FIG. 19 ), the second interface IF2 of the bonding layer 15 is the interface with the oxide layer 19, unlike the semiconductor device 100 ( FIG. 1 : Embodiment 1). In the case of the semiconductor device 102, as in the case of the semiconductor device 100, the arithmetic mean roughness of the second interface IF2 is preferably 0.5 nm or less. This can increase the bonding strength between the bonding layer 15 and the oxide layer 19.

[0063] FIG. 20 is a flow diagram schematically illustrating a manufacturing method MM2 of the semiconductor device 102 ( FIG. 19 ). First, similarly to the manufacturing method MM1 ( FIG. 3 : Embodiment 1), steps up to step S50 are performed to form the configuration shown in FIG. 9 . Next, in step S62 ( FIG. 20 ), the main surface FM5 of the oxide layer 19 is polished. This results in the main surface FM5 being a polished surface. In other words, a polished surface is formed as the main surface FM5 of the oxide layer 19. This polishing is preferably precision polishing using chemical mechanical polishing (CMP). Furthermore, this polished surface preferably has an arithmetic mean roughness of 0.5 nm or less. Furthermore, this polishing is preferably controlled so that the thickness of the oxide layer 19 after polishing is 0.1 μm or more and 1.0 μm or less.

[0064] 21 , next, in step ST72 ( FIG. 20 ), bonding layer 15 is disposed on silicon crystal layer 11 with oxide layer 19 interposed therebetween, and is disposed directly on the polished surface serving as main surface FM5 of oxide layer 19. Thus, bonding layer 15 is disposed on silicon crystal layer 11 with oxide layer 19 interposed therebetween. Thereafter, step S80 is performed in the same manner as in the above-described manufacturing method MM1 ( FIG. 3 : first embodiment), thereby forming semiconductor device 102 ( FIG. 19 ).

[0065] Since the configuration other than the above is substantially the same as that of the first embodiment, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated. As a modification of the third embodiment, the silicon compound layer 21 (FIG. 18) described in the second embodiment may be applied to the semiconductor device 102 (FIG. 19).

[0066] According to the semiconductor device 102 of the third embodiment, the buffer layer 12 is disposed on the bonding layer 15 via not only the silicon crystal layer 11 but also the oxide layer 19. Therefore, in the manufacture of the semiconductor device 102, until the configuration shown in FIG. 21 is obtained, in other words, until the structure including the nitride semiconductor layer 13 is bonded to the diamond substrate 16 using the bonding layer 15, not only the silicon crystal layer 11 but also the oxide layer 19 can continue to protect the buffer layer 12. This allows the buffer layer 12 to continue to protect the back surface of the nitride semiconductor layer 13 from damage caused by any manufacturing process. Therefore, degradation of the performance of the semiconductor device 102 due to damage to the back surface of the nitride semiconductor layer 13 can be suppressed. In particular, when ion beam processing is performed immediately before bonding to the structure including the diamond substrate 16, damage to the nitride semiconductor layer 13 caused by the ion beam can be suppressed not only by the buffer layer 12 and the silicon crystal layer 11 but also by the oxide layer 19.

[0067] In the third embodiment, the bonding layer 15 is bonded to the oxide layer 19. The bonding layer 15 made of an amorphous material is more likely to have a better lattice match with the oxide layer 19 than with the silicon crystal layer 11. Therefore, the bonding strength can be increased compared to when the bonding layer 15 is bonded to the silicon crystal layer 11.

[0068] The oxide layer 19 of the semiconductor device 102 is made of SiO.sub.2 having a thickness of 0.1 .mu.m or more. ２ It may be a layer of SiO ２ Although the thermal conductivity of the oxide layer 19 is relatively low, if the thickness is not made excessively large and is set to 1.0 μm or less, it is possible to avoid a significant decrease in heat dissipation caused by the oxide layer 19 being interposed between the nitride semiconductor layer 13 and the diamond substrate 16.

[0069] According to the manufacturing method of the semiconductor device 102 according to the third embodiment, a polishing step for forming a polished surface is performed, but this step is performed on the oxide layer 19. This makes it possible to suppress damage to the nitride semiconductor layer 13 caused by the polishing step.

[0070] It should be noted that the embodiments can be freely combined, and the embodiments can be appropriately modified or omitted. Although the present disclosure has been described in detail, the above description is illustrative in all aspects and is not intended to be limiting. It is understood that countless variations not illustrated can be envisioned from the present disclosure.

[0071] 10 SOI substrate (silicon-on-insulator substrate), 11 silicon crystal layer, 12 buffer layer, 13 nitride semiconductor layer, 14 surface electrode, 15 bonding layer, 16 diamond substrate, 17 adhesion layer, 18 protective substrate, 19 oxide layer, 20 support substrate, 21 silicon compound layer, 100-102 semiconductor device, ES semiconductor element structure, IF1 first interface, IF2 second interface.

Claims

1. A semiconductor device comprising: a diamond substrate; a bonding layer made of an amorphous material and disposed directly on the diamond substrate; a silicon crystal layer bonded to the diamond substrate at least via the bonding layer; a buffer layer made of a nitride containing aluminum atoms and disposed on the bonding layer at least via the silicon crystal layer; and a nitride semiconductor layer disposed directly on the buffer layer and having a composition different from that of the buffer layer.

2. The semiconductor device according to claim 1, wherein said silicon crystal layer is directly bonded to said bonding layer.

3. The semiconductor device according to claim 1, further comprising an oxide layer disposed between said silicon crystal layer and said bonding layer, in direct contact with said silicon crystal layer, and directly bonded to said bonding layer.

4. The oxide layer is SiO ２ 4. The semiconductor device according to claim 3, wherein the semiconductor device comprises a metal layer and has a thickness of 0.1 μm or more and 1.0 μm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein the silicon crystal layer has a thickness of 0.5 µm or more and 20.0 µm or less.

6. The semiconductor device according to any one of claims 1 to 5, wherein the buffer layer is disposed directly on the silicon crystal layer.

7. The semiconductor device according to claim 1, further comprising a silicon compound layer between the silicon crystal layer and the buffer layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein the silicon crystal layer has a resistivity of 5000 Ω·cm or less.

9. The semiconductor device according to any one of claims 1 to 8, wherein the bonding layer comprises an amorphous carbon layer disposed directly on the diamond substrate.

10. The semiconductor device according to any one of claims 1 to 9, wherein the bonding layer includes a silicon-containing layer.

11. The semiconductor device according to any one of claims 1 to 10, wherein the bonding layer has a thickness of 1 nm or more and 10 nm or less.

12. The semiconductor device according to any one of claims 1 to 11, wherein the diamond substrate is made of single crystal diamond, mosaic diamond, or polycrystalline diamond.

13. The semiconductor device according to any one of claims 1 to 12, wherein the diamond substrate has a thickness of 50 μm or more and 600 μm or less.

14. The semiconductor device according to any one of claims 1 to 13, wherein the bonding layer has a first interface in contact with the diamond substrate and a second interface opposite to the first interface, and each of the first interface and the second interface has an arithmetic mean roughness of 0.5 nm or less.

15. A method for manufacturing a semiconductor device comprising: a) a step of directly or indirectly forming a buffer layer made of a nitride containing aluminum atoms on a silicon crystal layer, the silicon crystal layer being disposed directly on an oxide layer, the oxide layer being disposed on a support substrate; b) a step of forming a nitride semiconductor layer on the buffer layer, the nitride semiconductor layer having a composition different from that of the buffer layer; c) a step of forming a semiconductor element structure on the nitride semiconductor layer; d) a step of providing a protective substrate on the semiconductor element structure via an adhesive layer; e) a step of removing the support substrate after d); f) a step of bonding the silicon crystal layer and a polished surface of a diamond substrate to each other via at least a bonding layer, the bonding layer being disposed directly on the polished surface of the diamond substrate, and on the silicon crystal layer directly or via the oxide layer; and g) a step of removing the adhesive layer and the protective substrate.

16. The method for manufacturing a semiconductor device according to claim 15, further comprising, after e) and before f), a step of removing the oxide layer while leaving the silicon crystal layer by wet etching having a higher etching rate for the material of the oxide layer than for the material of the silicon crystal layer, wherein in f), the bonding layer is disposed directly on the silicon crystal layer.

17. The method for manufacturing a semiconductor device according to claim 15, further comprising the step of forming a polished surface of the oxide layer by polishing the oxide layer after e) and before f), wherein in f), the bonding layer is disposed on the silicon crystal layer via the oxide layer and is disposed directly on the polished surface of the oxide layer.

18. A method for manufacturing a semiconductor device according to any one of claims 15 to 17, wherein in a), the silicon crystal layer, the oxide layer, and the support substrate constitute a silicon-on-insulator substrate, and the silicon crystal layer in the silicon-on-insulator substrate has an in-plane uniformity of within 10%.

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