Semiconductor device

Abstract

Disclosed is a semiconductor device applicable to a 2.xD structure. A semiconductor device 1 includes: a substrate 2; a semiconductor chip 31 mounted on the substrate 2; and a stiffener 4 arranged on the substrate 2 and extending so as to surround the semiconductor chip 31. The stiffener 4 is formed of, for example, SUS430 or an organic material. In the semiconductor device 1, the difference obtained by subtracting an average thermal expansion coefficient of the substrate 2 at 30°C-245°C inclusive from an average thermal expansion coefficient of the stiffener 4 at 30°C-245°C inclusive is -4 ppm / °C to 4 ppm / °C inclusive. The width of the stiffener 4 is larger than 20 mm.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] In recent years, with the rapid advancement in functionality of electronic devices, such as AI and HPC, semiconductor packages have become larger and denser. These package structures go beyond surface mounting to include inorganic (silicon) or organic interposer (Bridge die / RDL) technology, 2.xD mounting using these, and 3D mounting (HBM / Chiplet) technology utilizing TSV. For example, Resonac Inc., based at its Packaging Solutions Center, is developing next-generation semiconductor packaging process technology from the perspective of its customers (semiconductor manufacturers), combining mounting processes and materials.

[0003] As a technology in the field of semiconductor packaging, a semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and a stiffener as a reinforcing member disposed on the substrate is known (see, for example, Patent Document 1). Such a semiconductor device is mounted on, for example, a motherboard for use.

[0004] Japanese Patent Application Laid-Open No. 2017-126668

[0005] In the semiconductor device described above, warping of the substrate may occur due to temperature changes accompanying the reflow process during mounting, for example. In recent years, substrates on which semiconductor chips are mounted have become larger due to demands for higher functionality, etc. In particular, the amount of warping becomes large in large substrates, which may make it difficult to properly mount the semiconductor device.

[0006] An object of the present disclosure is to provide a semiconductor device capable of suppressing warpage.

[0007] [1] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a semiconductor chip mounted on a main surface of the substrate, and a stiffener disposed on the main surface and extending along at least a portion of a region of the main surface that surrounds the semiconductor chip when viewed in the thickness direction of the substrate, wherein the difference between the average thermal expansion coefficient of the stiffener at 30°C or higher and 245°C or lower minus the average thermal expansion coefficient of the substrate at 30°C or higher and 245°C or lower is -4 ppm / °C or higher and 4 ppm / °C or lower, and the width of the stiffener is greater than 20 mm.

[0008] In this semiconductor device, the difference between the average thermal expansion coefficient of the stiffener at temperatures between 30°C and 245°C and the average thermal expansion coefficient of the substrate at temperatures between 30°C and 245°C is between -4 ppm / °C and 4 ppm / °C. Therefore, even if a temperature change occurs in the semiconductor device due to a reflow process when mounting the semiconductor device on another device (e.g., a motherboard), the difference between the average thermal expansion coefficient of the substrate and the average thermal expansion coefficient of the stiffener is small, so stress caused by the difference in thermal expansion coefficients can be reduced. Furthermore, in this semiconductor device, the width of the stiffener is greater than 20 mm. Therefore, the reinforcing strength of the stiffener on the substrate is improved, and deformation of the substrate is suppressed. Therefore, this semiconductor device can suppress warpage.

[0009] [2] In the semiconductor device of [1] above, when viewed in the thickness direction of the substrate, the ratio of the area of ​​the stiffener to the total area of ​​the main surface may be 60% or more and 85% or less. When the area ratio of the stiffener is 60% or more, the reinforcing strength of the substrate provided by the stiffener is improved, and deformation of the substrate is suppressed. This makes it possible to further suppress warpage of the semiconductor device. Furthermore, when the area ratio of the stiffener is 85% or less, a wide mounting area for semiconductor chips or other components (discrete components, etc.) can be secured on the main surface of the substrate.

[0010] [3] In the semiconductor device of [1] or [2] above, the width of the stiffener may be 50 mm or less. If the width of the stiffener is too large, the semiconductor device is more likely to warp at its edges due to temperature changes. However, by setting the width of the stiffener to 50 mm or less, such warping at its edges can be suppressed. Furthermore, by setting the width of the stiffener to 50 mm or less, a wide mounting area for semiconductor chips or other components (discrete components, etc.) can be secured on the main surface of the substrate.

[0011] [4] In the semiconductor device of any one of [1] to [3] above, when viewed in the thickness direction of the substrate, the stiffener may extend in a frame shape so as to surround the semiconductor chip. In this case, the reinforcing strength of the substrate provided by the stiffener is improved, and deformation of the substrate is suppressed. This makes it possible to further suppress warpage of the semiconductor device.

[0012] [5] In any of the semiconductor devices [1] to [4] above, the stiffener is formed in a rectangular frame shape including a pair of first portions each extending along a first direction and a pair of second portions each extending along a second direction intersecting the first direction, and the width of each of the pair of first portions may be different from the width of each of the pair of second portions. In this case, even if the width of the semiconductor chip along the first direction and the width along the second direction are different, the semiconductor chip and the stiffener can be spaced apart at an appropriate distance.

[0013] [6] In any of the semiconductor devices [1] to [5] above, the substrate may have a rectangular shape with each side longer than 100 mm when viewed in the thickness direction of the substrate. When a substrate with each side longer than 100 mm (a large substrate) is used, warping of the semiconductor device is likely to occur. However, even when a large substrate is used, warping of the semiconductor device can be suppressed for the reasons described above.

[0014] [7] In any of the semiconductor devices [1] to [6] above, the material of the stiffener may contain an organic material. In this case, for example, electrical insulation between the wiring of the substrate and the stiffener can be easily ensured. In addition, the weight of the semiconductor device can be reduced.

[0015] [8] A semiconductor device according to one aspect of the present disclosure includes a substrate, a semiconductor chip mounted on a main surface of the substrate, and a stiffener disposed on the main surface and extending along at least a portion of a region of the main surface that surrounds the semiconductor chip when viewed in the thickness direction of the substrate, wherein the difference between the average thermal expansion coefficient of the stiffener at 30°C or higher and 245°C or lower minus the average thermal expansion coefficient of the substrate at 30°C or higher and 245°C or lower is -4 ppm / °C or higher and 4 ppm / °C or lower, and the material of the stiffener includes an organic material.

[0016] In this semiconductor device, the difference between the average thermal expansion coefficient of the stiffener at temperatures between 30°C and 245°C and the average thermal expansion coefficient of the substrate at temperatures between 30°C and 245°C is between -4 ppm / °C and 4 ppm / °C. Therefore, even if a temperature change occurs in the semiconductor device due to a reflow process when mounting the semiconductor device on another device (such as a motherboard), the difference between the average thermal expansion coefficient of the substrate and the average thermal expansion coefficient of the stiffener is small, so stress caused by the difference in thermal expansion coefficients can be reduced. Therefore, this semiconductor device can suppress warping.

[0017] [9] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a semiconductor chip mounted on a main surface of the substrate, and a stiffener disposed on the main surface and extending along at least a portion of a region of the main surface that surrounds the semiconductor chip when viewed in the thickness direction of the substrate, wherein the difference between the average thermal expansion coefficient of the stiffener at 30°C or higher and 245°C or lower minus the average thermal expansion coefficient of the substrate at 30°C or higher and 245°C or lower is -4 ppm / °C or higher and 4 ppm / °C or lower.

[0018] In this semiconductor device, the difference between the average thermal expansion coefficient of the stiffener at temperatures between 30°C and 245°C and the average thermal expansion coefficient of the substrate at temperatures between 30°C and 245°C is between -4 ppm / °C and 4 ppm / °C. Therefore, even if a temperature change occurs in the semiconductor device due to a reflow process when mounting the semiconductor device on another device (such as a motherboard), the difference between the average thermal expansion coefficient of the substrate and the average thermal expansion coefficient of the stiffener is small, so stress caused by the difference in thermal expansion coefficients can be reduced. Therefore, this semiconductor device can suppress warping.

[0019] According to one aspect of the present disclosure, warpage of a semiconductor device can be suppressed.

[0020] Fig. 1 is a plan view showing a semiconductor device according to one embodiment. Fig. 2 is a cross-sectional view of the semiconductor device taken along line II-II shown in Fig. 1. Fig. 3 is a graph showing the relationship between the diagonal position of a substrate in a semiconductor device and the amount of warpage.

[0021] Hereinafter, several embodiments of the present disclosure will be described in detail, with reference to the drawings as necessary. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicate explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0022] In the present specification, numerical ranges indicated using "to" include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In the numerical ranges described in stages in the present specification, the upper or lower limit value described in one numerical range may be replaced with the upper or lower limit value of another numerical range described in stages. Furthermore, in the numerical ranges described in the present specification, the upper or lower limit value of that numerical range may be replaced with a value shown in the examples.

[0023] [Configuration of Semiconductor Device] Fig. 1 is a plan view showing a semiconductor device 1 according to one embodiment. Fig. 2 is a cross-sectional view of the semiconductor device 1 taken along line II-II shown in Fig. 1. In this example, the semiconductor device 1 is mounted on a motherboard 101. The motherboard 101 may be, for example, a PCB substrate. The semiconductor device 1 is electrically connected to the motherboard 101 via a plurality of bumps 102. The device on which the semiconductor device 1 is mounted is not limited to the motherboard 101 and may be another device.

[0024] In this embodiment, the semiconductor device 1 has a 2.5-dimensional (2.5D) package structure. The semiconductor device 1 is not limited to a 2.5D structure and may have other 2.xD structures, such as 2.1D or 2.3D. In the semiconductor device 1, for example, multiple semiconductor chips (dies) are arranged on a common interposer, and the semiconductor chips are connected to each other via wiring formed on the interposer. The semiconductor device 1 includes a substrate 2, a semiconductor package 3, and a stiffener 4. Hereinafter, the thickness direction of the substrate 2 is referred to as the Z-axis direction, a direction intersecting the Z-axis direction is referred to as the X-axis direction (first direction), and a direction intersecting the Z-axis direction and the X-axis direction is referred to as the Y-axis direction (second direction). In this example, the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0025] The substrate 2 is a substrate that supports the semiconductor package 3. In this example, the substrate 2 is formed in a rectangular plate shape. The substrate 2 has a main surface 2a and a main surface 2b. When viewed from the Z-axis direction, the outer edges of the main surfaces 2a and 2b have a rectangular shape. The main surface 2b is located on the opposite side of the main surface 2a in the Z-axis direction. The semiconductor device 1 is placed on the motherboard 101 so that the main surface 2b is located closer to the motherboard 101 than the main surface 2a (so that it faces the main surface of the motherboard 101). A plurality of bumps 102 are placed between the main surface 2b and the motherboard 101.

[0026] The substrate 2 has an insulating layer 21 and wiring 22 formed on the insulating layer 21. In this example, the insulating layer 21 is formed from multiple layers, each containing an organic material. Each layer constituting the insulating layer 21 may be, for example, a cured resin film or a prepreg. The prepreg can be obtained by impregnating or coating a substrate with a thermosetting resin composition and semi-curing (B-staging) it by heating or other methods. The thermosetting resin contained in the prepreg is not particularly limited, but examples include epoxy resin, phenolic resin, unsaturated imide resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resin, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, silicone resin, triazine resin, and melamine resin. These may be used alone or in combination of two or more types. Among these, epoxy resin and cyanate resin are preferred in terms of moldability and electrical insulation.

[0027] To these thermosetting resins, modified silicone compounds described in WO 2012 / 099133, curing agents, curing accelerators, inorganic fillers, thermoplastic resins, elastomers, organic fillers, flame retardants, ultraviolet absorbers, antioxidants, photopolymerization initiators, fluorescent brightening agents, adhesion improvers, and the like can be added as needed.

[0028] The prepreg substrate can be any well-known material used in various electrical insulating laminates. Examples of suitable materials include inorganic fibers such as E-glass, D-glass, S-glass, and Q-glass; organic fibers such as polyimide, polyester, and tetrafluoroethylene; and mixtures thereof. These substrates can take various forms, such as woven fabric, nonwoven fabric, roving, chopped strand mat, and surfacing mat. The material and shape are selected based on the intended application and performance of the molded product. If necessary, a single material or a combination of two or more materials and shapes can be used. For example, a thickness of approximately 0.03 to 0.5 mm can be used. Those surface-treated with a silane coupling agent or mechanically opened are preferred in terms of heat resistance, moisture resistance, and processability. The type of resin composition is not particularly limited, and examples include thermosetting resin compositions and photosensitive resin compositions. Examples of thermosetting resin compositions include epoxy resins. Resin compositions containing silica (SiO ２ ) may contain fillers such as

[0029] The wiring 22 is a metal wiring electrically connected to the semiconductor package 3 and the motherboard 101. The wiring 22 may include a plurality of metal layers (metal foils) formed on the surfaces of the layers that make up the insulating layer 21. The material of the wiring 22 may be, for example, at least one of copper, gold, silver, nickel, platinum, molybdenum, ruthenium, aluminum, tungsten, iron, titanium, and chromium, or may be an alloy containing at least one of these metal elements.

[0030] The semiconductor package 3 is disposed in the center of the main surface 2a of the substrate 2. The semiconductor package 3 has a plurality of semiconductor chips 31, a plurality of bumps 32, an interposer 33, a plurality of bumps 34, and a sealing member 35. The plurality of bumps 34, the interposer 33, the plurality of bumps 32, and the plurality of semiconductor chips 31 are disposed in this order on the main surface 2a of the substrate 2.

[0031] The plurality of semiconductor chips 31 are arranged on the main surface 2a of the substrate 2 via an interposer 33. The plurality of semiconductor chips 31 are arranged side by side in a plane along the X-axis direction and the Y-axis direction. The semiconductor chip 31 is a die formed using a semiconductor material such as silicon. The semiconductor chip 31 is manufactured by, for example, cutting (dicing) a wafer on the surface of which electronic components such as transistors, diodes, and resistors are formed into individual chips. The semiconductor chip 31 functions as, for example, a processor or a memory. The processor may be, for example, a processor unit such as a GPU (Graphics Processing Unit) or a CPU (Central Processing Unit). The memory may be, for example, a memory unit such as an HBM (High Bandwidth Memory).

[0032] The plurality of bumps 32 are disposed between the plurality of semiconductor chips 31 and the interposer 33. The bumps 32 are formed of a metal material such as solder. The bumps 32 electrically connect the semiconductor chips 31 and the interposer 33.

[0033] The interposer 33 supports the plurality of semiconductor chips 31. The interposer 33 electrically connects the plurality of semiconductor chips 31 to each other and also electrically connects the plurality of semiconductor chips 31 to the substrate 2. The interposer 33 may be, for example, a silicon interposer including a silicon substrate and wiring.

[0034] The plurality of bumps 34 are disposed between the interposer 33 and the substrate 2. The bumps 34 are formed of a metal material such as solder. The bumps 34 electrically connect the wiring of the interposer 33 to the wiring 22 of the substrate 2. The plurality of semiconductor chips 31 are electrically connected to the wiring 22 of the substrate 2 via the plurality of bumps 32, the interposer 33, and the plurality of bumps 34.

[0035] The sealing member 35 seals the semiconductor chip 31 and the interposer 33. The sealing member 35 covers the surfaces of the semiconductor chips 31 except for the surface of each semiconductor chip 31 opposite the interposer 33. The surface of each semiconductor chip 31 opposite the interposer 33 is exposed from the sealing member 35. The sealing member 35 covers the bumps 32, the interposer 33, and the bumps 34. The sealing member 35 is formed of, for example, a resin. The material of the sealing member 35 may include, for example, an epoxy resin. The sealing member 35 may also be an epoxy molding compound (EMC).

[0036] The material of the sealing member 35 may be an epoxy resin composition. The epoxy resin composition of this embodiment is prepared in powder, granule, film, or liquid form. The resin composition of this embodiment can be prepared using any method that can uniformly disperse and mix the various components. A typical method involves thoroughly mixing the components in predetermined amounts using a mixer or the like, melt-kneading them using a mixing roll or extruder, and then cooling and pulverizing them. For example, the resin composition can be obtained by uniformly stirring and mixing the predetermined amounts of the components described above, kneading them using a kneader, roll, extruder, or the like that has been preheated to 70 to 140°C, cooling, and pulverizing them. For ease of use, the resin composition can be formed into tablets with dimensions and mass that match the molding conditions.

[0037] (Epoxy Resin) The epoxy resin of this embodiment is preferably a compound having two or more epoxy groups. The epoxy resin used here is not limited to those commonly used in epoxy resin compositions, and examples include epoxidized novolac resins obtained by condensing or co-condensing phenols such as phenol, cresol, bisphenol, biphenol, thiodiphenol, aminophenol, and naphthol, including epoxy resins having a triphenylmethane skeleton, with compounds having aldehyde groups such as formaldehyde and acetaldehyde. One of these may be used alone, or two or more may be used in combination. Among these, from the viewpoint of achieving both fluidity and curability, biphenyl-type epoxy resins, which are diglycidyl ethers of alkyl-substituted, aromatic-ring-substituted, or unsubstituted biphenols, are preferred. From the viewpoint of curability, novolac-type epoxy resins are preferred, while naphthalene-type epoxy resins and / or triphenylmethane-type epoxy resins are preferred from the viewpoints of heat resistance and low warpage.

[0038] (Curing Agent) The epoxy resin composition of this embodiment may contain a curing agent. The curing agent used here is not limited to any curing agent commonly used in epoxy resin compositions. Examples include novolac-type phenolic resins obtained by condensing or co-condensing phenols such as phenol, cresol, bisphenol, biphenol, thiodiphenol, aminophenol, or naphthol with compounds having an aldehyde group such as formaldehyde or acetaldehyde; phenol aralkyl resins synthesized from phenols and dimethoxy-para-xylene or bis(methoxymethyl)biphenyl; aralkyl-type phenolic resins such as naphthol-aralkyl resins; copolymerized phenol aralkyl resins in which phenol novolac structures and phenol aralkyl structures are repeated randomly, in blocks, or alternately; cyclopentadiene-modified phenolic resins; and polycyclic aromatic ring-modified phenolic resins. These curing agents may be used alone or in combination of two or more.

[0039] (Silane Compound) The epoxy resin composition of the present embodiment may contain a silane compound. The silane compound is a silane-based compound such as an epoxy silane, a mercapto silane, an amino silane, an alkyl silane, a ureido silane, or a vinyl silane. One of these compounds may be used alone, or two or more of these compounds may be used in combination. In addition to the silane compound, titanates, aluminum chelates, and the like may be used alone, or two or more of these compounds may be used in combination.

[0040] (Curing Accelerator) The epoxy resin composition of this embodiment may contain a curing accelerator. The curing accelerator used in this embodiment is not particularly limited and may be one that is commonly used in encapsulated epoxy resin compositions, and examples thereof include cycloamidine compounds such as 1,5-diazabicyclo[4.3.0]nonene-5,5,6-dibutylamino-1,8-diazabicyclo[5.4.0]undecene-7; tertiary amines such as tris(dimethylaminomethyl)phenol and derivatives thereof; imidazoles such as 2-phenyl-4-methylimidazole and derivatives thereof; organic phosphines such as phenylphosphine and derivatives thereof; and tetraphenylboron salts such as N-methylmorpholine tetraphenylborate and derivatives thereof. These may be used alone or in combination of two or more.

[0041] (Filler, Inorganic Filler) The epoxy resin composition of this embodiment may contain a filler. The filler used in this embodiment is not particularly limited and is any filler commonly used in encapsulating epoxy resin compositions, but is preferably an inorganic filler. For example, an inorganic filler containing at least one inorganic material selected from the group consisting of aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, aluminum nitride, aluminum borate whisker, boron nitride, crystalline silica, amorphous silica, and antimony oxide is preferred. Among these, alumina, aluminum nitride, boron nitride, crystalline silica, and amorphous silica are preferred for improving thermal conductivity. For the purpose of adjusting melt viscosity or imparting thixotropy, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, crystalline silica, and amorphous silica are preferred. Furthermore, alumina, silica, aluminum hydroxide, and antimony oxide are preferred for improving moisture resistance. These may be used alone or in combination of two or more.

[0042] In this example, when viewed from the Z-axis direction, the outer edge 3e of the semiconductor package 3 has a rectangular shape. The width of the semiconductor package 3 along the X-axis direction is smaller than the width of the semiconductor package 3 along the Y-axis direction.

[0043] The stiffener 4 is a reinforcing member disposed on the main surface 2 a of the substrate 2. The stiffener 4, for example, reinforces the mechanical strength of the substrate 2 and suppresses warpage of the substrate 2. When viewed from the Z-axis direction, the stiffener 4 extends along at least a portion of the region of the main surface 2 a that surrounds the multiple semiconductor chips 31 (semiconductor packages 3). The region surrounding the semiconductor chips 31 is an annular region located outside the semiconductor chips 31 when viewed from the Z-axis direction, and is a region located between the outer edge 3 e of the semiconductor chips 31 and the outer edge 2 e of the substrate 2. In this example, when viewed from the Z-axis direction, the stiffener 4 extends continuously in a frame shape so as to surround the multiple semiconductor chips 31. The stiffener 4 is formed in a rectangular frame shape.

[0044] The stiffener 4 has a top surface 4a and a bottom surface 4b located on the opposite side of the top surface 4a in the Z-axis direction. The top surface 4a and the bottom surface 4b extend along the X-axis direction and the Y-axis direction. The bottom surface 4b is bonded to the main surface 2a of the substrate 2 by, for example, an adhesive.

[0045] When viewed from the Z-axis direction, the stiffener 4 has an inner edge 4e and an outer edge 4f. When viewed from the Z-axis direction, the inner edge 4e and the outer edge 4f each have a rectangular shape. The stiffener 4 is disposed away from the semiconductor package 3 so that the inner edge 4e does not come into contact with the semiconductor package 3. When viewed from the Z-axis direction, the outer edge 4f overlaps with the outer edge 2e of the substrate 2. In other words, when viewed from the Z-axis direction, the outer edge 4f has the same shape as the outer edge 2e.

[0046] The stiffener 4 is composed of a pair of first portions 41 each extending along the X-axis direction and a pair of second portions 42 each extending along the Y-axis direction. The pair of first portions 41 and the pair of second portions 42 are formed integrally with each other. The pair of first portions 41 are positioned so as to sandwich the semiconductor package 3 in the Y-axis direction. The pair of second portions 42 are positioned so as to sandwich the semiconductor package 3 in the X-axis direction.

[0047] The material of the stiffener 4 may include a metal. In this case, the stiffener 4 may be made of, for example, stainless steel (such as SUS430), copper, or nickel-plated copper. The material of the stiffener 4 may include an organic material. In this case, the stiffener 4 may be made of, for example, a resin containing a filler. The filler may be, for example, silica. The resin may be, for example, an epoxy resin. The material of the stiffener 4 may be ceramic.

[0048] [Size of Substrate and Stiffener] Next, the sizes of the substrate 2 and the stiffener 4 will be described. When viewed from the Z-axis direction, the substrate 2 has a rectangular shape with each side longer than 100 mm. When viewed from the Z-axis direction, the outer edge 2e of the substrate 2 has a pair of sides extending along the X-axis direction and a pair of sides extending along the Y-axis direction. The width W21 of the substrate 2 along the X-axis direction (the length of the side extending along the X-axis direction) is greater than 100 mm. The width W21 may be 110 mm or greater, 120 mm or greater, or 130 mm or greater. The width W22 of the substrate 2 along the Y-axis direction (the length of the side extending along the Y-axis direction) is greater than 100 mm. The width W22 may be 110 mm or greater, 120 mm or greater, or 130 mm or greater. The substrate 2 has a maximum width W13. In this example, the maximum width W13 is the length of the diagonal of the substrate 2.

[0049] The stiffener 4 has a width W. The width W of the stiffener 4 is the width along a direction perpendicular to the extension direction of the stiffener 4 when viewed from the Z-axis direction. Specifically, the first portion 41 extending along the X-axis direction has a width W11 along the Y-axis direction, and the second portion 42 extending along the Y-axis direction has a width W12 along the X-axis direction. The width W of the stiffener 4 (widths W11, W12) is greater than 20 mm. The width W of the stiffener 4 (widths W11, W12) may be 25 mm or more, 30 mm or more, 35 mm or more, 40 mm or more, or 45 mm or more. The width W of the stiffener 4 (widths W11, W12) may be 50 mm or less.

[0050] The width W11 of the stiffener 4 may be 15% or more and 45% or less of the width W21 of the substrate 2. The width W11 may be 25% or more, 30% or more, 35% or more, or 40% or more of the width W21. The width W12 of the stiffener 4 may be 15% or more and 45% or less of the width W22 of the substrate 2. The width W12 may be 25% or more, 30% or more, 35% or more, or 40% or more of the width W22.

[0051] The width W (widths W11, W12) of the stiffener 4 may be 10% or more and 30% or less of the maximum width W13 of the substrate 2. The width W (widths W11, W12) may be 15% or more, 20% or more, or 25% or more of the maximum width W13.

[0052] The width W11 of each of the pair of first portions 41 is different from the width W12 of each of the pair of second portions 42. In this example, the width W11 of the first portion 41 is smaller than the width W12 of the second portion 42. For example, when the width W11 is 23 mm, the width W12 may be 25 mm. When the width W11 is 28 mm, the width W12 may be 30 mm. When the width W11 is 34 mm, the width W12 may be 36 mm. The values ​​of the width W11 and the width W12 may be determined so that the distance between the outer edge 3 e of the semiconductor package 3 and the inner edge 4 e of the stiffener 4 in the X-axis direction (the distance between the semiconductor package 3 and the second portion 42) is equal to the distance between the outer edge 3 e and the inner edge 4 e in the Y-axis direction (the distance between the semiconductor package 3 and the first portion 41).

[0053] When viewed from the Z-axis direction, the ratio of the area of ​​the stiffener 4 to the entire area of ​​the main surface 2a of the substrate 2 is 60% or more and 85% or less. The entire area of ​​the main surface 2a is an area including the area where the semiconductor package 3 and the stiffener 4 are arranged. In this example, the entire area of ​​the main surface 2a is the area of ​​the area surrounded by the outer edge 2e of the substrate 2 when viewed from the Z-axis direction. The area of ​​the stiffener 4 may be the area of ​​the bottom surface 4b of the stiffener 4 to which the substrate 2 is bonded. The ratio of the area of ​​the stiffener 4 to the entire area of ​​the main surface 2a may be 60% or more and 78% or less, 68% or more and 78% or less, or 70% or more and 78% or less.

[0054] The width of the stiffener 4 in the Z-axis direction (the height from the bottom surface 4 b to the top surface 4 a) may be, for example, 2 mm, or may be 1 mm or more and 5 mm or less. The width of the stiffener 4 in the Z-axis direction may be larger than the width of the semiconductor package 3 in the Z-axis direction.

[0055] [Average Coefficient of Thermal Expansion (CTE) of Substrate and Stiffener] The average coefficient of thermal expansion of the substrate 2 at temperatures from 30°C to 245°C is 3 ppm / °C to 17 ppm / °C. The average coefficient of thermal expansion of the substrate 2 may be the average coefficient of thermal expansion of the insulating layer 21 of the substrate 2. The average coefficient of thermal expansion of the substrate 2 at temperatures from 30°C to 245°C may be 4 ppm / °C to 15 ppm / °C, 5 ppm / °C to 14 ppm / °C, 6 ppm / °C to 12 ppm / °C, or 7 ppm / °C to 9 ppm / °C. The average coefficient of thermal expansion of the substrate 2 is measured by a digital image correlation method. The average temperature rise rate during this measurement may be, for example, 0.28°C / second.

[0056] The average thermal expansion coefficient of the stiffener 4 at 30°C or higher and 245°C or lower is 3 ppm / °C or higher and 17 ppm / °C or lower. The average thermal expansion coefficient of the stiffener 4 may be 4 ppm / °C or higher and 15 ppm / °C or lower, 5 ppm / °C or higher and 14 ppm / °C or lower, 6 ppm / °C or higher and 13 ppm / °C or lower, or 6 ppm / °C or higher and 9 ppm / °C or lower. The average thermal expansion coefficient of the stiffener 4 is measured by a digital image correlation method.

[0057] The difference obtained by subtracting the average thermal expansion coefficient of the substrate 2 at 30° C. or higher and 245° C. or lower from the average thermal expansion coefficient of the stiffener 4 at 30° C. or higher and 245° C. or lower is −4 ppm / ° C. or higher and 4 ppm / ° C. or lower. The difference obtained by subtracting the average thermal expansion coefficient of the substrate 2 at 30° C. or higher and 245° C. or lower from the average thermal expansion coefficient of the stiffener 4 at 30° C. or higher and 245° C. or lower may be −2 ppm / ° C. or higher and 2 ppm / ° C. or lower, −1 ppm / ° C. or higher and 1 ppm / ° C. or lower, or −0.5 ppm / ° C. or higher and 0.5 ppm / ° C. or lower.

[0058] In the semiconductor device 1, the difference between the average thermal expansion coefficient of the stiffener 4 at temperatures between 30°C and 245°C and the average thermal expansion coefficient of the substrate 2 at temperatures between 30°C and 245°C is between -4 ppm / °C and 4 ppm / °C. Therefore, even if a temperature change occurs in the semiconductor device 1 due to a reflow process when mounting the semiconductor device 1 on another device (e.g., a motherboard 101), the difference between the average thermal expansion coefficient of the substrate 2 and the average thermal expansion coefficient of the stiffener 4 is small, so stress caused by the difference in thermal expansion coefficients can be reduced. Furthermore, in the semiconductor device 1, the width W of the stiffener 4 is greater than 20 mm. Therefore, the reinforcing strength of the stiffener 4 to the substrate 2 is improved, and deformation of the substrate 2 is suppressed. Therefore, the semiconductor device 1 can suppress warpage.

[0059] When viewed from the Z-axis direction, the ratio of the area of ​​the stiffener 4 to the entire area of ​​the main surface 2a of the substrate 2 is 60% or more and 85% or less. When the area ratio of the stiffener 4 is 60% or more, the reinforcing strength of the substrate 2 provided by the stiffener 4 is improved, and deformation of the substrate 2 is suppressed. This makes it possible to further suppress warping of the semiconductor device 1. Furthermore, when the area ratio of the stiffener 4 is 85% or less, a wide mounting area for the semiconductor chip 31 or other components (discrete components, etc.) can be secured on the main surface 2a of the substrate 2.

[0060] The width W of the stiffener 4 is 50 mm or less. If the width W of the stiffener 4 is too large, warping is likely to occur at the ends of the semiconductor device 1 due to temperature changes, but by setting the width W of the stiffener 4 to 50 mm or less, such warping at the ends can be suppressed. Furthermore, by setting the width W of the stiffener 4 to 50 mm or less, a wide mounting area for the semiconductor chip 31 or other components (discrete components, etc.) can be secured on the main surface 2 a of the substrate 2.

[0061] When viewed from the Z-axis direction, the stiffener 4 extends in a frame shape so as to surround the semiconductor chip 31. This improves the reinforcing strength of the substrate 2 provided by the stiffener 4, and suppresses deformation of the substrate 2. Therefore, warpage of the semiconductor device 1 can be further suppressed.

[0062] The stiffener 4 is formed in a rectangular frame shape including a pair of first portions 41 each extending along the X-axis direction and a pair of second portions 42 each extending along the Y-axis direction. The width W11 of each of the pair of first portions 41 is different from the width W12 of each of the pair of second portions 42. In this case, even if the width of the semiconductor chip 31 along the X-axis direction and the width along the Y-axis direction are different, the semiconductor chip 31 and the stiffener 4 can be spaced apart at an appropriate distance.

[0063] When viewed from the Z-axis direction, the substrate 2 has a rectangular shape with each side longer than 100 mm. If a substrate with each side longer than 100 mm (a large substrate) is used, warping of the semiconductor device 1 is likely to occur. However, even if a large substrate is used, warping of the semiconductor device 1 can be suppressed for the reasons described above.

[0064] The material of the stiffener 4 contains an organic material. In this case, it is possible to easily ensure electrical insulation between the wiring 22 of the substrate 2 and the stiffener 4. Furthermore, it is possible to reduce the weight of the semiconductor device 1.

[0065] [Examples] The present invention will be described in more detail below with reference to examples, although the present invention is not limited to these examples.

[0066] The influence of the difference between the average thermal expansion coefficient of the substrate and the average thermal expansion coefficient of the stiffener on the warpage of the semiconductor device will be described below. The amounts of warpage were measured for semiconductor devices according to Example 1 and Comparative Example 1, which have the same configuration as the semiconductor device 1 according to the above-described embodiment.

[0067] In Example 1 and Comparative Example 1, a substrate having an average thermal expansion coefficient of 11 to 13 ppm / °C at temperatures between 30°C and 245°C was used as the substrate 2. The insulating layer of the substrate was mainly made of epoxy resin, filler, hardener, glass cloth, and copper foil, and the wiring material was plated copper. The substrates in Example 1 and Comparative Example 1 were rectangular substrates measuring 120 mm x 120 mm in plan view.

[0068] In Example 1, a stiffener having an average thermal expansion coefficient of 10 ppm / °C at temperatures from 30°C to 245°C was used as the stiffener 4. The material of the stiffener in Example 1 was stainless steel (SUS430). In Comparative Example 1, a stiffener having an average thermal expansion coefficient of 17 ppm / °C at temperatures from 30°C to 245°C was used as the stiffener 4. The material of the stiffener in Comparative Example 1 was copper. In each example, the width W11 of the stiffener was 28 mm, and the width W12 was 30 mm.

[0069] The semiconductor devices according to each example of Example 1 and Comparative Example 1 were heated from room temperature (28°C) to the reflow temperature (243°C) used when mounting the semiconductor device on a motherboard, and then cooled back down to 150°C. Based on the three-dimensional shape of the semiconductor device, the amount of warpage (μm) at each temperature was calculated. The amount of warpage of the semiconductor device was measured from the back surface of the substrate (the surface opposite to the main surface 2a) using an AXP2.0 (shadow moire) manufactured by Akrometrix. The amount of warpage of the semiconductor device was the difference between the maximum value (highest position) and the minimum value (lowest position) when the position (height) of the back surface of the substrate in the Z-axis direction was measured at each diagonal position of the substrate.

[0070] As shown in Table 1 below, in Example 1, in which the difference between the average thermal expansion coefficient of the substrate and the average thermal expansion coefficient of the stiffener was smaller than in Comparative Example 1, the amount of warpage of the semiconductor device was reduced. In particular, the amount of warpage at high temperatures (near the reflow temperature) was significantly reduced compared to Comparative Example 1. Specifically, in the semiconductor device according to Example 1, the amount of warpage at room temperature of 28°C before heating was 488.8 μm, the amount of warpage at 148°C was 133.6 μm, the amount of warpage at 222°C was 65.1 μm, the amount of warpage at 243°C was −91.3 μm, and after cooling, the amount of warpage at 221°C was 97.9 μm, and the amount of warpage at 150°C was 266.9 μm. In the semiconductor device according to Comparative Example 1, the amount of warpage at room temperature of 28° C. before heating was −335.5 μm, the amount of warpage at 148° C. was 259 μm, the amount of warpage at 222° C. was 644.9 μm, and the amount of warpage at 243° C. was 770.9 μm, and after cooling was 221° C., the amount of warpage was 727.4 μm and the amount of warpage at 150° C. was 473.4 μm. Therefore, by reducing the difference between the average thermal expansion coefficient of the substrate and the average thermal expansion coefficient of the stiffener, warpage of the semiconductor device can be suppressed.

[0071]

[0072] The effect of the stiffener width on warpage of a semiconductor device will be described with reference to FIG. 3. The amounts of warpage were measured for semiconductor devices according to Examples 2 to 5, which have the same configuration as the semiconductor device 1 according to the above-described embodiment. FIG. 3 shows the relationship between the diagonal position of the substrate and the amount of warpage for each of the semiconductor devices according to Examples 2 to 5. In FIG. 3, graph a corresponds to Example 2, graph b corresponds to Example 3, graph c corresponds to Example 4, and graph d corresponds to Example 5. The diagonal position of the substrate is indicated by the distance on the diagonal of the substrate that passes through one corner in a plan view of the substrate, with the corner being set as the reference (0 mm).

[0073] In Examples 2 and 3, a substrate having an average thermal expansion coefficient of 11.97 ppm / °C at temperatures between 30°C and 245°C was used as the substrate 2. The insulating layer of the substrate was made of an insulating material consisting of epoxy resin, filler, glass cloth, and a hardener, and the wiring was made of plated copper and copper foil. In Examples 4 and 5, a substrate having an average thermal expansion coefficient of 12.81 ppm / °C at temperatures between 30°C and 245°C was used as the substrate 2. The insulating layer of the substrate was made of an insulating material consisting of epoxy resin, filler, glass cloth, and a hardener, and the wiring was made of plated copper and copper foil. The substrates in Examples 2 to 5 were rectangular substrates measuring 120 mm x 120 mm in plan view.

[0074] In Examples 2 to 5, a stiffener having an average thermal expansion coefficient of 10 ppm / °C at temperatures equal to or higher than 30°C and equal to or lower than 245°C was used as the stiffener 4. The material of the stiffeners in Examples 2 to 5 was stainless steel (SUS430). In Examples 2 and 4, the width W11 of the stiffener was 28 mm, and the width W12 was 30 mm. In Examples 3 and 5, the width W11 of the stiffener was 34 mm, and the width W12 was 36 mm.

[0075] The semiconductor devices according to Examples 2 to 5 were heated from room temperature (approximately 25°C to 35°C) to the reflow temperature (approximately 245°C) used when mounting the semiconductor device on a motherboard, and then cooled back to room temperature (approximately 25°C to 35°C). Based on the three-dimensional shape of the semiconductor device, the amount of warpage at each position on the diagonal of the substrate was calculated. The amount of warpage of the semiconductor device was measured using AXP2.0 (shadow moire) manufactured by Akrometrix. The amount of warpage is the position in the Z-axis direction of the point to be measured for the amount of warpage, with the position in the Z-axis direction of the center of the main surface of the substrate (the surface corresponding to main surface 2a) being set as the reference (0 mm).

[0076] 3, it can be seen that the amount of warpage of the semiconductor device is reduced in Examples 3 and 5, in which the width W of the stiffener (widths W11 and W12) is larger than in Examples 2 and 4. Therefore, by increasing the width W of the stiffener, it is possible to suppress warpage of the semiconductor device.

[0077] 3, it can be seen that the shape of the semiconductor device (substrate) in a cross section along the diagonal line is approximately M-shaped in Examples 2 and 3, in which the difference between the average thermal expansion coefficient of the substrate and the average thermal expansion coefficient of the stiffener is smaller than in Examples 4 and 5. Therefore, in the semiconductor device according to Examples 2 and 3, when the semiconductor device is placed on another device such as the motherboard 101, the center and edges of the substrate come into contact with the motherboard 101, etc., and the semiconductor device can be mounted in a stable state.

[0078] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments and can be applied to various embodiments. For example, the shape of the substrate 2 when viewed from the Z-axis direction is not limited to a rectangular shape, but may be a circular shape, an elliptical shape, or a polygonal shape other than a rectangular shape. If the shape of the substrate 2 is a circular shape, the maximum width W13 of the substrate 2 is the diameter of the substrate 2. If the shape of the substrate 2 is an elliptical shape, the maximum width W13 of the substrate 2 is the major axis of the substrate 2.

[0079] When viewed from the Z-axis direction, the outer edge 4 f of the stiffener 4 does not have to overlap with the outer edge 2 e of the substrate 2. When viewed from the Z-axis direction, the outer edge 4 f may be located inside or outside the outer edge 2 e.

[0080] The stiffener 4 may extend along only a portion of the area of ​​the main surface 2a that surrounds the multiple semiconductor chips 31 (semiconductor packages 3). For example, the stiffener 4 may have only a pair of first portions 41 and one second portion 42 and be U-shaped when viewed from the Z-axis direction. The stiffener 4 may extend discontinuously. The pair of first portions 41 and the pair of second portions 42 may not be formed integrally with each other. The respective ends of the pair of first portions 41 and the pair of second portions 42 may be discontinuous with each other. The shape of the stiffener 4 is not limited to a rectangular frame. The stiffener 4 may be formed, for example, in the shape of a circular frame, an elliptical frame, or a polygonal frame other than a rectangle.

[0081] When viewed from the Z-axis direction, the ratio of the area of ​​the stiffener 4 to the entire main surface 2a of the substrate 2 may be smaller than 60% or larger than 85%. The width W (widths W11, W12) of the stiffener 4 may be larger than 50 mm. The width W11 of the first portion 41 of the stiffener 4 may be equal to or larger than the width W12 of the second portion 42.

[0082] 1...semiconductor device, 2...substrate, 2a...main surface, 2b...main surface, 2e...outer edge, 3...semiconductor package, 3e...outer edge, 4...stiffener, 4a...top surface, 4b...bottom surface, 4e...inner edge, 4f...outer edge, 21...insulating layer, 22...wiring, 31...semiconductor chip, 32...bump, 33...interposer, 34...bump, 35...sealing member, 41...first part, 42...second part, 101...motherboard, 102...bump.

Claims

1. A semiconductor device comprising: a substrate; a semiconductor chip mounted on a main surface of the substrate; and a stiffener disposed on the main surface and extending along at least a portion of a region of the main surface surrounding the semiconductor chip when viewed in the thickness direction of the substrate, wherein the difference between the average thermal expansion coefficient of the stiffener at temperatures between 30°C and 245°C and the average thermal expansion coefficient of the substrate at temperatures between 30°C and 245°C is between -4 ppm / °C and 4 ppm / °C, and the width of the stiffener is greater than 20 mm.

2. The semiconductor device according to claim 1, wherein the ratio of the area of ​​said stiffener to the total area of ​​said main surface when viewed in the thickness direction of said substrate is 60% or more and 85% or less.

3. The semiconductor device according to claim 1 or 2, wherein the width of the stiffener is 50 mm or less.

4. The semiconductor device according to claim 1 or 2, wherein, when viewed in the thickness direction of the substrate, the stiffener extends in a frame shape so as to surround the semiconductor chip.

5. The semiconductor device according to claim 1 or 2, wherein the stiffener is formed in a rectangular frame shape including a pair of first portions each extending along a first direction and a pair of second portions each extending along a second direction intersecting the first direction, and the width of each of the pair of first portions is different from the width of each of the pair of second portions.

6. The semiconductor device according to claim 1 or 2, wherein the substrate has a rectangular shape with each side longer than 100 mm when viewed in the thickness direction of the substrate.

7. The semiconductor device according to claim 1 or 2, wherein the material of the stiffener includes an organic material.

8. A semiconductor device comprising: a substrate; a semiconductor chip mounted on a main surface of the substrate; and a stiffener disposed on the main surface and extending along at least a part of a region of the main surface surrounding the semiconductor chip when viewed in the thickness direction of the substrate, wherein the difference between the average thermal expansion coefficient of the stiffener at 30°C or higher and 245°C or lower minus the average thermal expansion coefficient of the substrate at 30°C or higher and 245°C or lower is -4 ppm / °C or higher and 4 ppm / °C or lower, and the material of the stiffener includes an organic material.

9. A semiconductor device comprising: a substrate; a semiconductor chip mounted on a main surface of the substrate; and a stiffener disposed on the main surface and extending along at least a portion of an area of ​​the main surface surrounding the semiconductor chip when viewed in the thickness direction of the substrate, wherein the difference between the average thermal expansion coefficient of the stiffener at temperatures between 30°C and 245°C and the average thermal expansion coefficient of the substrate at temperatures between 30°C and 245°C is between -4 ppm / °C and 4 ppm / °C.

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