Semiconductor device

Abstract

This semiconductor device includes an electromagnetic shield and an inductor. The electromagnetic shield has a first slit extending in a first direction and a second slit extending in a second direction different from the first direction and intersecting the first slit, and extends along a first surface including the first direction and the second direction. The inductor faces the electromagnetic shield in a third direction intersecting the first surface.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device with an electromagnetic shield.

[0002] A semiconductor device has been proposed in which an electromagnetic shield is provided between a substrate having an inductor and a circuit board on which a logic circuit is formed (see, for example, Patent Document 1). In this semiconductor device, the electromagnetic shield can prevent electromagnetic noise caused by a magnetic field generated in the logic circuit from affecting the inductor.

[0003] International Publication No. 2017 / 122416

[0004] However, further improvements in quality are being sought for such semiconductor devices.

[0005] Therefore, a semiconductor device with excellent performance is desired.

[0006] A semiconductor device according to an embodiment of the present disclosure includes an electromagnetic shield and an inductor. The electromagnetic shield has a first slit extending in a first direction and a second slit extending in a second direction different from the first direction and intersecting the first slit, and extends along a first plane including the first direction and the second direction. The inductor faces the electromagnetic shield in a third direction intersecting the first plane.

[0007] In a semiconductor device according to an embodiment of the present disclosure, the electromagnetic shield protects the inductor from electromagnetic noise generated inside or outside the semiconductor device, and also attenuates eddy currents generated in the electromagnetic shield, thereby suppressing performance degradation of the inductor.

[0008] FIG. 1 is a block diagram illustrating an example configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a block diagram illustrating an example configuration of a phase-locked loop circuit illustrated in FIG. 1. FIG. 3 is a circuit diagram illustrating an example configuration of a voltage-controlled oscillator illustrated in FIG. 2. FIG. 4 is a perspective view illustrating an example configuration of the semiconductor device illustrated in FIG. 1. FIG. 5 is an enlarged perspective view illustrating some components of the semiconductor device illustrated in FIG. 4. FIG. 6 is a plan view illustrating an example configuration of an electromagnetic shield illustrated in FIG. 5. FIG. 7 is a schematic diagram illustrating an example direction of a current flowing through the inductor illustrated in FIG. 5 and an example of an eddy current induced in the electromagnetic shield illustrated in FIG. 5. FIG. 8 is a perspective view illustrating an example of an electromagnetic shield and an inductor as a reference example. FIG. 9 is a plan view illustrating an example configuration of an electromagnetic shield according to a second embodiment of the present disclosure. FIG. 10 is a plan view illustrating an example configuration of an electromagnetic shield according to a first modified example of the present disclosure. FIG. 11 is a plan view illustrating an example configuration of an electromagnetic shield according to a second modified example of the present disclosure. FIG. 12 is a perspective view illustrating an example configuration of an inductor according to a third modified example of the present disclosure. FIG. 13 is a characteristic diagram showing the relationship between the Q value of the inductor and the frequency of the AC signal in the example.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and the technology according to the present disclosure is not limited to the following aspects. Furthermore, the arrangement, dimensions, dimensional ratios, etc. of each component of the present disclosure are not limited to the aspects shown in the drawings.

[0010] The description will be given in the following order: 1. First embodiment (example of a semiconductor device in which an electromagnetic shield with slits is inserted between an inductor and a circuit) 1.1. Configuration example of a semiconductor device 1.2. Configuration example of a phase locked loop circuit 1.3. Configuration example of a phase locked loop circuit 1.4. Effects and advantages 2. Second embodiment (example of an electromagnetic shield arranged between an inductor and a circuit) 2.1. Configuration example 2.2. Effects and advantages 2.3. Modified example 3. Other modified examples 4. Examples

[0011] 1. First Embodiment 1.1. Configuration Example of Semiconductor Device First, with reference to FIG. 1 , a configuration example of a semiconductor device 100 according to a first embodiment of the present disclosure will be described. FIG. 1 is a block diagram showing one configuration example of the semiconductor device 100. The semiconductor device 100 may be, for example, a device equipped with an imaging element or an LSI (Large Scale Integration). The semiconductor device 100 includes multiple stacked semiconductor chips, such as an upper chip 110 and a lower chip 150. The upper chip 110 includes a logic circuit 111. The lower chip 150 includes a logic circuit 151 and a phase-locked loop 200. While FIG. 1 illustrates an example in which the semiconductor device 100 includes two semiconductor chips (i.e., the upper chip 110 and the lower chip 150), the semiconductor device 100 may include three or more semiconductor chips.

[0012] The logic circuit 111 executes predetermined processing and transmits and receives data to and from a logic circuit 151 provided in the lower chip 150 via a signal line 119. The logic circuit 111 may be, for example, a pixel circuit or a vertical drive circuit that drives the pixel circuit.

[0013] The logic circuit 151 executes predetermined processing in synchronization with the clock signal CLKout from the phase locked loop 200. The logic circuit 151 may be, for example, an AD (Analog to Digital) converter or a horizontal drive circuit that drives the AD converter.

[0014] A clock signal CLKin having a predetermined cycle, which is generated by an external crystal oscillator or the like, is input to the phase locked loop 200. The phase locked loop 200 multiplies the clock signal CLKin by a predetermined multiplication ratio and outputs the result as a clock signal CLKout to the logic circuit 151 via a signal line 209.

[0015] 2 is a block diagram showing an example of the configuration of a phase locked loop circuit 200. The phase locked loop circuit 200 includes a phase comparator 210, a charge pump 220, a frequency divider 230, and a voltage controlled oscillator 240.

[0016] The phase comparator 210 compares the phase of the clock signal CLKin from the crystal oscillator 152 with the phase of the clock signal CLKfb from the frequency divider 230. Based on the comparison result, the phase comparator 210 generates a detection signal UP and a detection signal DN indicating the phase difference between the phase of the clock signal CLKin and the phase of the clock signal CLKfb, and supplies these signals to the charge pump 220. For example, the difference between the pulse width of the detection signal UP and the pulse width of the detection signal DN indicates the phase difference between the phase of the clock signal CLKin and the phase of the clock signal CLKfb.

[0017] The charge pump 220 generates a control signal Vc having a voltage corresponding to the phase difference between the detection signals UP and DN, and supplies the control signal Vc to the voltage-controlled oscillator 240.

[0018] The voltage controlled oscillator 240 generates a clock signal CLKout having a frequency corresponding to the voltage of the control signal Vc, and supplies the clock signal CLKout to the frequency divider 230 and the logic circuit 151. The clock signal CLKout is, for example, a single-ended signal or a differential signal.

[0019] The frequency divider 230 divides the frequency of the clock signal CLKout from the voltage-controlled oscillator 240 by a predetermined division ratio. The frequency divider 230 feeds back the divided signal as the clock signal CLKfb to the phase comparator 210. By feeding back the signal obtained by dividing the frequency of the clock signal CLKout from the voltage-controlled oscillator 240 to the phase comparator 210 in this manner, the phase-locked loop 200 can generate a signal obtained by multiplying the clock signal CLKin.

[0020] 3 is a circuit diagram showing an example of the configuration of the voltage-controlled oscillator 240. The voltage-controlled oscillator 240 includes an amplifier circuit 241, an inductor 250, and a variable capacitor 242. The variable capacitor 242 and the inductor 250 are connected in parallel to the amplifier circuit 241. In addition, an electromagnetic shield 260 is layered above the inductor 250, with the direction from the lower chip 150 toward the upper chip 110 being the upward direction.

[0021] The variable capacitance 242 is a capacitor whose capacitance changes in response to the voltage of the control signal Vc from the charge pump 220. For example, a varicap diode is used as the variable capacitance 242.

[0022] The inductor 250 generates a clock signal by resonating with the variable capacitor 242. The inductor 250 also generates a magnetic field in the upward or downward direction.

[0023] The amplifier circuit 241 amplifies the signal generated by the LC resonant circuit made up of the variable capacitor 242 and the inductor 250, and supplies the amplified signal to the frequency divider 230 and the logic circuit 151 as the clock signal CLKout.

[0024] Electromagnetic shield 260 has a plurality of slits formed in a direction parallel to the substrate plane of each of upper chip 110 and lower chip 150. A predetermined fixed potential (e.g., ground potential) is applied to electromagnetic shield 260. Electromagnetic shield 260 blocks electromagnetic noise caused by the magnetic field generated in logic circuit 111. Thus, inductor 250 is protected from electromagnetic noise resulting from the magnetic field generated in logic circuit 111.

[0025] Although the potential of the electromagnetic shield 260 is set to a fixed potential, it may also be set to a floating potential. In this case, the electromagnetic shield 260 functions as a magnetic field shield that blocks only electromagnetic noise caused by electromagnetic induction. If it is necessary to block electromagnetic noise caused by electrostatic induction as well, a fixed potential is applied to the electromagnetic shield 260.

[0026] Furthermore, although the electromagnetic shield 260 is placed above the inductor 250 in the voltage-controlled oscillator 240, it may also be placed above an inductor provided in a circuit other than the voltage-controlled oscillator 240, such as a buffer circuit or a clock distribution circuit.

[0027] Fig. 4 is a perspective view showing an example of the configuration of the semiconductor device 100. Fig. 5 is a perspective view showing an example of the configuration of the electromagnetic shield 260 and the inductor 250 provided on the lower chip 150 of the semiconductor device 100. Fig. 6 is a plan view showing an example of the configuration of the electromagnetic shield 260.

[0028] As shown in Figure 4, in the semiconductor device 100, the upper chip 110 and the lower chip 150 each extend along an XY plane including the X-axis direction and the Y-axis direction, which are orthogonal to each other. The upper chip 110 and the lower chip 150 are stacked in the Z-axis direction. Note that the X-axis direction, the Y-axis direction, and the Z-axis direction are examples of configurations corresponding to the "first direction," "second direction," and "third direction" as an embodiment of the present disclosure. The XY plane is also an example of configurations corresponding to the "first surface" as an embodiment of the present disclosure.

[0029] As described above, the upper chip 110 is provided with the logic circuit 111. Meanwhile, the lower chip 150 is provided with, in addition to the logic circuit 151, the inductor 250 and the electromagnetic shield 260 that constitute the voltage-controlled oscillator 240. In the lower chip 150, the inductor 250 is provided adjacent to the logic circuit 151 in the XY plane. The electromagnetic shield 260 is also disposed above the inductor 250 so as to overlap with the inductor 250 in the Z-axis direction. Therefore, the logic circuit 111 is disposed on the opposite side of the inductor 250 in the Z-axis direction as viewed from the electromagnetic shield 260. In other words, the electromagnetic shield 260 is inserted between the inductor 250 and the logic circuit 111 of the upper chip 110 in the Z-axis direction. Here, the electromagnetic shield 260, the inductor 250, the logic circuit 111, and the upper chip 110 are each an example configuration corresponding to an "electromagnetic shield," "inductor," "circuit," and "circuit board" according to an embodiment of the present disclosure.

[0030] Although Figure 4 illustrates an example in which the electromagnetic shield 260 is placed between the inductor 250 and the logic circuit 111, the electromagnetic shield 260 may also be placed between the inductor 250 and a circuit other than the logic circuit 111.

[0031] (Electromagnetic Shield) As shown in FIG. 6 , the electromagnetic shield 260 has a plurality of first slits 261 and one second slit 262. Each of the plurality of first slits 261 extends, for example, in the X-axis direction. Therefore, the plurality of first slits 261 extend substantially parallel to one another without intersecting with one another and are aligned in the Y-axis direction. In the example shown in FIG. 6 , the plurality of first slits 261 all have the same length L1 in the X-axis direction and the same width W1 in the Y-axis direction. The plurality of first slits 261 are aligned in the Y-axis direction, for example, at substantially equal intervals D1. The second slit 262 also extends in the Y-axis direction. The second slit 262 intersects with each of the plurality of first slits 261 at their respective centers in the X-axis direction. The portions of the electromagnetic shield 260 other than the first slits 261 and the second slits 262 constitute a shielding portion 269. Therefore, the electromagnetic shield 260 is open except for the shielding portion 269. However, the first slits 261 and the second slits 262 may be filled with a non-magnetic material. The shielding portion 269 may be made of, for example, a metal, specifically, a simple substance such as Cu (copper), Al (aluminum), Ag (silver), or Fe (iron), or an alloy containing these elements. The length L1 of the first slit 261 and the length L2 of the second slit 262 are, for example, 200 μm, the width W1 is, for example, 1 μm, and the distance D1 is, for example, 10 μm.

[0032] (Inductor) Inductor 250 is a spiral coil including a winding portion wound along a plane parallel to the XY plane. As shown in FIG. 5 , first slits 261 and second slits 262 of electromagnetic shield 260 are provided at positions overlapping in the Z-axis direction with inductor 250. Note that region 260R (see FIG. 6 ) in electromagnetic shield 260 where first slits 261 and second slits 262 are formed preferably overlaps with all of inductor 250 in the Z-axis direction. Furthermore, the center position of region 260R in the XY plane preferably substantially coincides with the center position of inductor 250 in the XY plane.

[0033] 7 is a schematic diagram showing an example of the direction of current flowing through inductor 250 and an example of eddy current induced in electromagnetic shield 260. Inductor 250 includes first terminal 501 and second terminal 502. When current I flows through inductor 250 from first terminal 501 to second terminal 502, current I flows through inductor 250 in a clockwise direction as indicated by the arrow in FIG. 7. As a result, as shown in FIG. 7, magnetic flux BF is generated from inductor 250, and eddy current Ie is induced in electromagnetic shield 260 by magnetic flux BF. Eddy current Ie reduces the Q value of inductor 250. However, in semiconductor device 100, electromagnetic shield 260 is provided with second slits 262 in addition to first slits 261, and therefore eddy current Ie can be sufficiently attenuated.

[0034] FIG. 8 is a perspective view showing an electromagnetic shield 1260 as a reference example. The electromagnetic shield 1260 has a plurality of first slits 261 but does not have a second slit 262. Except for this point, the configuration of the electromagnetic shield 1260 is substantially the same as the configuration of the electromagnetic shield 260. When a current I flows through the inductor 250 in FIG. 8 from the first terminal 501 to the second terminal 502, a magnetic flux BF is generated from the inductor 250. As a result, an eddy current Ie is induced in the electromagnetic shield 1260. However, because the electromagnetic shield 1260 does not have the second slits 262, a plurality of eddy currents Iex are induced in the electromagnetic shield 1260, drawing large elliptical loops around each of the plurality of first slits 261.

[0035] 7 further includes second slits 262 extending in the Y-axis direction, which is different from the extension direction of each of the first slits 261. Therefore, instead of a large elliptical eddy current Ie extending in the X-axis direction, an eddy current Ie that forms two small elliptical loops subdivided in the X-axis direction is induced. Therefore, the peak value and integral value of the eddy current Ie induced in the electromagnetic shield 260 are attenuated, and it is possible to prevent the Q value of the inductor 250 from decreasing due to eddy current loss.

[0036] As described above, in the semiconductor device 100, the electromagnetic shield 260 is provided between the inductor 250 and the logic circuit 111 of the upper chip 110 in the Z-axis direction. Therefore, electromagnetic noise caused by the magnetic field generated in the logic circuit 111 is blocked by the electromagnetic shield 260, preventing it from reaching the inductor 250. In other words, the inductor 250 can be protected from electromagnetic noise caused by the magnetic field generated in the logic circuit 111.

[0037] Furthermore, in the semiconductor device 100, the electromagnetic shield 260 is provided with a plurality of first slits 261, so that some of the eddy currents Ie induced in the electromagnetic shield 260 by the magnetic flux BF caused by the inductor 250 cancel each other out. Furthermore, the electromagnetic shield 260 is provided with the second slits 262, so that the eddy current Ie can be subdivided. Therefore, the eddy current Ie can be attenuated, and a decrease in the Q value of the inductor 250 due to eddy current loss can be suppressed.

[0038] Therefore, the semiconductor device 100 of this embodiment can exhibit excellent performance.

[0039] 2. Second Embodiment [2.1. Configuration Example] Next, an electromagnetic shield 270 according to a second embodiment of the present disclosure will be described with reference to Fig. 9. Fig. 9 is a schematic diagram showing a planar configuration example of the electromagnetic shield 270. Note that Fig. 9 corresponds to Fig. 6 which shows one configuration example of the electromagnetic shield 260 of the first embodiment. The electromagnetic shield 270 can be applied to the semiconductor device 100 described in the first embodiment.

[0040] 9 , the electromagnetic shield 270 further has a plurality of third slits 263 in addition to the first slits 261 and the second slits 262. Except for the above points, the configuration of the electromagnetic shield 270 is substantially the same as the configuration of the electromagnetic shield 260. Note that while FIG. 9 illustrates an example in which a plurality of third slits 263 are provided, the present embodiment is not limited to this, and only one third slit 263 may be provided.

[0041] Each of the multiple third slits 263 is disposed between two adjacent first slits 261 in the Y-axis direction, extends in the X-axis direction, and intersects with the second slits 262. The length L3 of the third slit 263 in the X-axis direction is shorter than the length L1 of the first slit 261 in the X-axis direction (L1 > L3). When the length L1 of the first slit 261 is 200 μm, the length L3 of the third slit 263 can be, for example, 100 μm. The widths W3 of the multiple third slits 263 in the Y-axis direction may be equal to or different from each other. Furthermore, the width W3 of the third slit 263 in the Y-axis direction may be the same as or different from the width W1 of the first slit 261 in the Y-axis direction. The widths W1 and W3 can be, for example, 1 μm. In this embodiment, the region 263R ( FIG. 9 ) where the multiple third slits 263 are disposed may overlap the entire inductor 250 in the Z-axis direction.

[0042] [2.2. Effects] As described above, the electromagnetic shield 270 of this embodiment further includes the third slits 263 in addition to the first slits 261 and the second slits 262. This effectively reduces eddy currents while preventing an increase in the aperture ratio. That is, compared to the electromagnetic shield 260 of the first embodiment, which includes multiple first slits 261 each having a length L1 extending in the X-axis direction, the electromagnetic shield 270 includes a mixture of first slits 261 each having a length L1 and third slits 263 each having a length L3 extending in the X-axis direction. This allows for a large area of ​​the shielding portion 269 while attenuating eddy currents. Increasing the area of ​​the shielding portion 269 in the electromagnetic shield 270 increases the mechanical strength of the electromagnetic shield 270. This is advantageous for reducing the thickness of the electromagnetic shield 270. Furthermore, inserting the short third slits 263 is more likely to achieve overall flatness of the electromagnetic shield 270 than forming multiple long first slits 261.

[0043] [2.3. Modifications] (Modification 2-1) An electromagnetic shield 270A according to a first modification (modification 2-1) of the second embodiment of the present disclosure will be described with reference to Fig. 10. Fig. 10 is a schematic diagram showing an example of the planar configuration of the electromagnetic shield 270A. Note that Fig. 10 corresponds to Fig. 6, which shows the example of the planar configuration of the electromagnetic shield 260 according to the first embodiment.

[0044] 10, electromagnetic shield 270A of modified example 2-1 has a plurality of third slits 263 arranged between two adjacent first slits 261 in the Y-axis direction. Note that, although two third slits 263 are arranged between two adjacent first slits 261 in the Y-axis direction in FIG. 10, the number of third slits 263 is not limited to two and can be selected arbitrarily.

[0045] The electromagnetic shield 270A of the modified example 2-1 is also expected to have the same effects as the electromagnetic shield 270 of the second embodiment (FIG. 9).

[0046] 3. Other Modifications The technology according to the present disclosure has been described above using several embodiments and modifications. However, the technology according to the present disclosure is not limited to the above-described embodiments, and various modifications are possible.

[0047] For example, as in an electromagnetic shield 260A shown in FIG. 11, the length of each of the plurality of first slits 261 may be adjusted to form a substantially circular region 260R in accordance with the planar shape of the inductor 250.

[0048] Furthermore, for example, in the first and second embodiments, an inductor having one spiral coil is illustrated, but the inductor of the present disclosure is not limited to this. For example, the inductor of the present disclosure may be a transformer or balun in which two spiral coils C1 and C2 are stacked in the Z-axis direction, as shown in FIG.

[0049] Furthermore, for example, in the first embodiment described above, the inductor 250 constituting the voltage-controlled oscillator 240 has been described, but the inductor of the present disclosure may also be an inductor constituting a circuit such as an LNA (low noise amplifier), a PA (power amplifier), an LC filter, or a power splitter / combiner.

[0050] Furthermore, for example, in the first and second embodiments described above, the first slits and the second slits are perpendicular to each other, but the first slits and the second slits may intersect at an angle other than 90°. Furthermore, the lengths of the first slits may be set arbitrarily, and the lengths of some of the first slits may be different from the lengths of the other first slits. Alternatively, the lengths of all of the first slits may be different from each other. Furthermore, the shapes of the first to third slits are not limited to rectangular, and may be other shapes.

[0051] 4. Examples Here, a comparison was made by simulation between the electromagnetic shield 260 of the first embodiment (FIGS. 4 to 7), the electromagnetic shield 270 of the second embodiment (FIG. 9), and the electromagnetic shield 1260 (FIG. 12) as a reference example. Here, a semiconductor device using the electromagnetic shield 260 is referred to as Example 1, a semiconductor device using the electromagnetic shield 270 as Example 2, and a semiconductor device using the electromagnetic shield 1260 as Reference Example 1. Specifically, the magnitudes of eddy currents induced in the electromagnetic shields 260, 270, and 1260 when a constant current I was passed through the inductor 250 were compared. Furthermore, the Q values ​​(where the AC signal frequency f was 12.6 GHz and the inductance L was 1 nH) of the inductors 250 arranged directly below the electromagnetic shields 260, 270, and 1260 were compared. In Examples 1 and 2 and Reference Example 1, the outer diameter of the inductor 250 was set to 110 μm. Furthermore, the length L1 of the first slits 261 and the length L2 of the second slits 262 of the electromagnetic shields 260 and 270 were both 200 μm. The length L3 of the third slits 263 of the electromagnetic shield 270 was both 100 μm. The widths W1 to W3 were all 1 μm. The spacing D1 was 10 μm. In the electromagnetic shield 270, the spacing between the first slits 261 and the third slits 263 was 4.5 μm. The results are shown in Table 1 and FIG. 13. In FIG. 13, the horizontal axis represents the frequency f [GHz] of the AC signal, and the vertical axis represents the Q value of the inductor 250. In FIG. 13, the curve representing the Q value of Example 1 (electromagnetic shield 260) is represented by a solid line, the curve representing the Q value of Example 2 (electromagnetic shield 270) is represented by a dashed line, and the curve representing the Q value of Reference Example 1 (electromagnetic shield 1260) is represented by a dashed line. Table 1 also shows values ​​normalized by setting the area of ​​the slit, the peak value of the eddy current, and the integral value of the eddy current in Reference Example 1 (electromagnetic shield 1260) to 1.

[0052]

[0053] As shown in Table 1, it was found that in Examples 1 and 2, the peak value of the eddy current was reduced more than in the reference example, while the Q value of the inductor 250 was improved. In particular, in Example 2, the third slit 263 was provided, which made it possible to further improve the Q value of the inductor 250 while further reducing the peak value and integral value of the eddy current.

[0054] Terms used throughout this specification and the appended claims should be interpreted as "open-ended" terms. For example, the terms "including" or "including" should be interpreted as "not limited to the manner described as including." The term "having" should be interpreted as "not limited to the manner described as having."

[0055] The terms used in this specification include terms that are used merely for the convenience of description and are not intended to limit the configuration or operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions in the drawings to which reference is made. Furthermore, the terms "inner" and "outer" merely indicate directions toward and away from the center of a focused element, respectively. The same applies to similar terms and terms of a similar meaning.

[0056] The technology according to the present disclosure may also be configured as follows. A semiconductor device according to the present disclosure having the following configuration can have excellent performance. The effects achieved by the technology according to the present disclosure are not necessarily limited to the effects described herein and may be any of the effects described in the present disclosure. <1> A semiconductor device comprising: an electromagnetic shield having a first slit extending in a first direction and a second slit extending in a second direction different from the first direction and intersecting the first slit, the electromagnetic shield extending along a first plane including the first direction and the second direction; and an inductor facing the electromagnetic shield in a third direction intersecting the first plane. <2> The semiconductor device according to <1> above, further comprising: a circuit board having a circuit arranged on the opposite side of the inductor from the electromagnetic shield in the third direction. <3> The semiconductor device according to <1> or <2> above, wherein the electromagnetic shield has a plurality of the first slits, and the plurality of first slits are aligned in the second direction. <4> The semiconductor device according to <3> above, wherein the plurality of first slits are aligned in the second direction at substantially equal first intervals. <5> The semiconductor device according to <3> above, wherein the electromagnetic shield further includes a third slit provided between two of the first slits adjacent to each other in the second direction, extending in the first direction, and intersecting with the second slit, wherein the length of the third slit in the first direction is shorter than the length of the first slit in the first direction. <6> The semiconductor device according to any one of <1> to <5> above, wherein the inductor is a spiral coil wound along a plane parallel to the first plane. <7> The semiconductor device according to any one of <1> to <6> above, wherein the first slit and the second slit are provided at positions overlapping with the inductor in the third direction. <8> The semiconductor device according to any one of <1> to <7> above, wherein the second slit intersects with the first slit at a center position of the first slit in the first direction.

[0057] This application claims priority based on Japanese Patent Application No. 2024-083539, filed on May 22, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0058] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: an electromagnetic shield having a first slit extending in a first direction and a second slit extending in a second direction different from the first direction and intersecting the first slit, the electromagnetic shield extending along a first plane including the first direction and the second direction; and an inductor facing the electromagnetic shield in a third direction intersecting the first plane.

2. The semiconductor device according to claim 1, further comprising a circuit board having a circuit disposed on the opposite side of said inductor as viewed from said electromagnetic shield in said third direction.

3. The semiconductor device according to claim 1, wherein the electromagnetic shield has a plurality of the first slits, and the plurality of first slits are aligned in the second direction.

4. The semiconductor device according to claim 3, wherein the plurality of first slits are arranged in the second direction at substantially equal first intervals.

5. The semiconductor device according to claim 3, wherein the electromagnetic shield further has a third slit that is provided between two of the first slits that are adjacent in the second direction, extends in the first direction, and intersects with the second slits, and the length of the third slit in the first direction is shorter than the length of the first slit in the first direction.

6. The semiconductor device according to claim 1, wherein the inductor is a spiral coil wound along a plane parallel to the first plane.

7. The semiconductor device according to claim 1, wherein the first slit and the second slit are provided at positions overlapping the inductor in the third direction.

8. The semiconductor device according to claim 1, wherein the second slit intersects with the first slit at the center of the first slit in the first direction.

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