Durable backside layer of a semiconductor substrate
A multilayer stack of silicon oxycarbide and functional layers on semiconductor substrates addresses the durability and resistance issues of conventional backside sealing layers, enhancing chemical resistance and reducing defects, thus improving production efficiency and reducing costs.
WO2025244797A1PCT designated stage Publication Date: 2025-11-27LAM RES CORP
Patent Information
- Application Number
- PCT/US2025/026879
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-05-21
- Filing Date
- 2025-04-29
- Publication Date
- 2025-11-27
Smart Images

Figure US2025026879_27112025_PF_FP_ABST
Abstract
Methods and apparatus for deposition of a backside layer on a semiconductor substrate are provided. In some embodiments, such techniques may include: depositing a first layer of material on a backside of the semiconductor substrate; and depositing a second layer of material over the first layer of material to collectively form a stack of materials on the backside of the semiconductor substrate, the second layer of material comprising a lower tensile stress or a lower compressive stress than that of the first layer of material, the stack of materials comprising a greater chemically resistive property than that of the first layer of material. In some implementations, such techniques may include: depositing a sealing layer on a backside of the semiconductor substrate in a first process chamber; and depositing a silicon oxycarbide (SiOC) layer over the sealing layer to collectively form a stack of materials on the backside.
Need to check novelty before this filing date? Find Prior Art
Citation Information
Patent Citations
Method for improving warping of semiconductor wafer
CN102420176A
Method for manufacturing a back seal epitaxial layer of a wafer concerned with reducing particles on the front of the wafer caused by the back seal while an etching process
KR1019990034019A
Reducing stress in integrated circuits
US20040124452A1
Methods of minimizing wafer backside damage in semiconductor wafer processing
US20190393072A1
Pe-CVD apparatus and method
US20210246555A1