Row address mapping

Abstract

A memory device is operated using a reduced row address space (e.g., 48k rows per bank vs. a full capacity 64k rows per bank). The unused address space (e.g., 16k rows) is used and mapped by the memory device to store information for at least some of the bad rows. In this manner, many more bad rows may be "repaired" at the expense of a reduction in the capacity of the memory device. The translations of external row addresses to internal physical row addresses may include permuting row addresses within groups of row addresses to avoid bad rows within respective groups of row addresses. A linear filter (e.g., Bloom Filter, XOR filter, etc.) may be used to store information for the translations of external row addresses to internal physical row addresses. The information for the translations may be determined and programmed into the memory device once during manufacturing.

Description

ROW ADDRESS MAPPINGBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure l is a block diagram illustrating a memory system.

[0002] Figure 2 is a diagram illustrating an example reduced external range of row addresses mapping to a larger internal physical range of row addresses.

[0003] Figures 3A-3C are notional diagrams illustrating example mappings within row groups to avoid bad rows.

[0004] Figures 4A-4B are diagrams illustrating example processes to map rows within row groups.

[0005] Figure 5 is a block diagram illustrating an example system to map row addresses.

[0006] Figure 6 is a diagram illustrating a first example external to physical row address mapping.

[0007] Figures 7A-7B are diagrams illustrating a second example external row address to physical row address mapping.

[0008] Figure 8 is a diagram illustrating a third example external row address to physical row address mapping.

[0009] Figure 9 is a diagram illustrating an example full external row address range to physical plus repair row address mapping.

[0010] Figure 10 is a block diagram illustrating a weighted matching system to map row addresses.

[0011] Figure 11 is a flowchart illustrating a method of operating a memory device.

[0012] Figure 12 is a flowchart illustrating a method of mapping external row addresses to avoid bad rows.

[0013] Figure 13 is a flowchart illustrating a method of selecting external row address mappings.

[0014] Figure 14 is a flowchart illustrating a method of using a linear filter for external row address to physical address row mapping.

[0015] Figure 15 is a block diagram illustrating a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] When manufacturing memory devices (and dynamic random access memory - DRAM — devices in particular) some rows will have defects or otherwise be considered “bad” (e.g., too slow, stuck bits, etc.) Typically, redundant / spare rows of a memory array (bank) are used to store information in place of the bad rows. However, some manufacturedmemory devices may have too many bad rows to be repaired by the spare rows included in its design.

[0017] In an embodiment, a memory device is operated using a reduced row address space (e.g., 48k rows per bank vs. a full capacity 64k rows per bank). The unused address space (e.g., 16k rows) is used and mapped by the memory device to store information for at least some of the bad rows. In this manner, many more bad rows may be “repaired” at the expense of a reduction in the capacity of the memory device. In an embodiment, “bad” rows are those that may be functional, but don’t meet one or more specifications (e.g., retention time, access delay, etc.). In this situation, the reduced address space mapping may be used to map the reduced address space (e.g., 48k rows per bank) to those rows that can meet a less constraining specification (e.g., reduced retention time, increased access delay, etc.).

[0018] In an embodiment, the translations of external row addresses to internal physical row addresses include permuting row addresses within groups of row addresses to avoid bad rows within respective groups of row addresses. In an embodiment, a Bloom Filter or linear filter (e.g., XOR filter, etc.) may be used to store information for the translations of external row addresses to internal physical row addresses. The information for the translations need only be determined and programmed into the memory device once during manufacturing.

[0019] The descriptions and embodiments disclosed herein are made primarily with references to DRAM devices and DRAM memory arrays. This, however, should be understood to be a first example due at least to the widespread adoption of DRAM technology. It should be understood that other memory technologies may be manufactured with “bad” rows and therefore may also benefit from the methods and / or apparatus described herein. These memory technologies include, but are not limited to static random access memory (SRAM), non-volatile memory (such as flash), conductive bridging random access memory (CBRAM — a.k.a., programmable metallization cell — PMC), resistive random access memory (a.k.a., RRAM or ReRAM), magnetoresistive random-access memory (MRAM), Spin-Torque Transfer (STT-MRAM), phase change memory (PCM), and the like, and / or combinations thereof. Accordingly, it should be understood that in the disclosures and / or descriptions given herein, these aforementioned technologies may be substituted for, included with, and / or encompassed within, the references to DRAM, DRAM devices, and / or DRAM arrays made herein.

[0020] Figure 1 is a block diagram illustrating a memory system. In Figure 1, memory system 100 comprises memory device 110 and memory controller 120. Memory device 110 includes command / address (CA) interface 111, data (DQ) interface 112, row addressmapping 113, primary memory array 130, repair rows 135, row circuitry 131, column circuitry 132, repair content addressable memory (CAM) 115, and control circuitry 118. Row address mapping 113 includes configuration information 114. Configuration information 114 may be or include compressed mapping information such as arithmetic coding, delta-coding, Huffman coding, and / or a linear filter. Control circuitry 118 includes mode circuitry 119. Controller 120 includes CA interface 121, DQ interface 122, and reliability, availability, and serviceability (RAS) circuitry 123 (e.g., error detect and correct — EDC, error correcting code - ECC, chipkill SDDC, memory scrubbing, etc. circuitry).

[0021] Controller 120 and memory device 110 may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 120, manages the flow of data going to and from memory devices and / or memory modules. Memory device 110 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory device 110 may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory device 110 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 120 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0022] CA interface 121 of controller 120 is operatively coupled to CA interface 111 of memory device 110. CA interface 121 is operatively coupled to CA interface 111 to communicate commands and addresses (e.g., row and column addresses) from controller 120 to memory device 110. In an embodiment, the commands communicated from controller 120 to memory device 110 include activate commands and an associated external row address. In an embodiment, when in an operational mode, the external row addresses received from controller 120 are selected from a contiguous range of external row addresses (i.e., contiguous address range).

[0023] Controller 120 is operatively coupled to memory device 110 via DQ interface 122 and DQ interface 112. Controller 120 and memory device 110 are operatively coupled via DQ interface 122 and DQ interface 112 to bidirectionally communicate data. Memory device 110 may store (e.g., in primary memory array 130 and repair rows 135) and retrieve (e.g.,from primary memory array 130 and repair rows 135) data communicated via DQ interface 122 and DQ interface 112.

[0024] CA interface 111 of memory device 110 is operatively coupled to primary array 130. Some row addresses received via CA interface 111 (a.k.a., external row addresses) are operatively coupled to primary memory array 130 via row address mapping 113 and row circuitry 131 (e.g., row address decoders, buffers, etc.) Row addresses corresponding to rows whose functionality has been replaced by rows in repair rows 135 (e.g., external row addresses having an entry in repair CAM 115) are operatively coupled to repair rows 135 via repair CAM 115 and row circuitry 131. Column addresses received via C A interface 111 are operatively coupled to primary memory array 130 and repair rows 135 via column circuitry 132 (e.g., column address decoders, buffers, etc.).

[0025] In an embodiment, memory device 110 receives external row addresses (e.g., associated with an activate command - ACT) via CA interface 111 and provides the external row addresses to row address mapping 113. Based on configuration information 114 (e.g., mode programmed register value, programmed fuses, nonvolatile memory array, etc.), row address mapping 113 maps external row addresses to internal primary memory array 130 row addresses that are provided to row circuitry 131 and repair CAM 115. Row address mapping 113 maps a reduced external range of row addresses (e.g., 48k rows per bank — a.k.a. logical row addresses) to an internal physical range of row addresses that includes the full internal row address range of primary array 130 (e.g., 64k — a.k.a., physical row addresses). The rows not directly addressable by the reduced external range of row addresses (e.g., 16k rows - a.k.a., unused rows) are used and mapped by memory device 110, according to mappings configured by configuration information 114 and mapped by row address mapping 113, to store information for at least some bad rows not already repaired / replaced by repair rows 135 in concert with repair CAM 115.

[0026] Figure 2 is a diagram illustrating an example reduced external range of row addresses mapping to a larger internal physical range of row addresses. In Figure 2, a contiguous reduced external row address range (e.g., 32k, 48k, 56k, etc.) of M number of row addresses is illustrated mapping to a larger contiguous internal physical row address range (e.g., 64k, 128k, etc.) of N number of row addresses. Also illustrated in Figure 2 are row addresses 201-203 within the N number of physical row addresses. In an embodiment, if, for example, physical row address 202 corresponds to a physical row in primary array 130 that is bad, a logical row address corresponding to the row corresponding to physical row address 202 may be mapped by row address mapping 113 to a good row corresponding to a one of,for example, physical row address 201 or physical row address 203. In Figure 2, the reduced external address range of M number of row addresses is illustrated as being a contiguous range. However, in some embodiments, the M number of row addresses may comprise a plurality of non-contiguous address ranges.

[0027] Returning to Figure 1, in an embodiment, the logical -to-physical row address mappings implemented by row address mapping 113 may be stored in, and / or performed by, lookup table circuitry in row address mapping 113 that relates logical row addresses to physical row addresses. The logical -to-physical row address mappings implemented by row address mapping 113 may be stored in, and / or performed by, lookup table circuitry in row address mapping 113 that relates each logical row address in the reduced external row address range to a respective physical row address in a one-to-one manner. This one-to-one manner may include providing one or more values that are arithmetically or logically (e.g., bitwise XOR, rearrange bits, etc.) combined with the logical row address to generate a respective physical row address. The one or more values provided may include a “default” value that, once arithmetically or logically combined with the logical row address generates a physical row address that is equal to the logical row address (e.g., bitwise XOR with all zeros).

[0028] In an embodiment, the mapping of logical -to-physical row addresses may be determined during manufacturing and stored in configuration information 114, and thereafter may not be changed during the operating lifetime of memory device 110. In another embodiment, the mapping of logical -to-physical row addresses may be determined during manufacturing, stored in configuration information 114, and thereafter may be changed if additional bad rows develop and / or are detected (e.g., during a re-manufacturing, update, and / or repair process).

[0029] In an embodiment, row address mapping may be or comprise one or more linear filters. Linear filters can perform a lookup table function. To perform a lookup table function (or lookup table like function), linear filters: (1) based on an input (for example the external row address) determine one or more (e.g., 2 to 4) query values (e.g., the external row address, one or more parts of the external row address, and / or one or more arithmetically and / or logically modified versions of the external row address), to look up in one or more tables. The lookups may be performed into multiple separate tables in parallel (e.g., using SRAM, CAM, etc.); (2) Based on the input, zero or more bits from each lookup table result are selected and XOR’d together; (3) For each bit of linear filter output desired, the above steps (1) and (2) are repeated. In an embodiment, the same query values may be used foreach repetition of steps (1) and (2), but the output bits selected are different. In an embodiment, all of the bits selected in step (2) may: overlap (forming one giant lookup table function); do not overlap (forming logically separate lookup table functions; or a somewhere in between. In an embodiment, linear algebra may be used to determine how to program the values in the one or more tables.

[0030] In an embodiment, row address mapping 113 may group internal physical row addresses into fixed sized groups (e.g., groups of four physical addresses). Of each of the fixed number of physical row addresses in each group, a lesser number (e.g., three physical row addresses) of these physical addresses in each group have a mapping from a logical address that is in the reduced external range of row addresses. In other words, in each group of physical addresses (e.g., 4), one or more of those physical row addresses is either unmapped to a logical row address, or corresponds to a logical row address that is outside of the reduced external range of row addresses, or both. For example, within each grouping of logical row addresses (e.g., four logical row addresses), at least one of those logical row addresses (e.g., one logical row address) is outside of the reduced external range of row addresses and thus, in normal operation, should not be accessed by controller 120. Once grouped, each group of logical row addresses may then have a fixed, arithmetic, and / or algorithmic mapping to a corresponding group of physical row addresses by row address mapping 113. The fixed, arithmetic, and / or algorithmic mapping of groups (a.k.a., sets) of logical row addresses to groups of physical row addresses may be selected to require a relatively small amount of circuitry and / or lookup table entries. Row address mapping 113 may also, in an embodiment, permute or otherwise map respective logical row addresses within each group to respective physical row addresses within the corresponding group of physical row addresses to avoid accessing physical row addresses corresponding to bad rows.

[0031] Figures 3A-3C are notional diagrams illustrating example mappings within row groups to avoid bad rows. In Figures 3A-3C, an external row address range 301 is illustrated as grouped into address groups EAGRP[0]-EAGRP[3], EAGRP[0] includes external row addresses EA0-EA3. EAGRP[1] includes external row addresses EA4-EA7, and so on. Physical row address range 302 is illustrated as grouped into address groups PAGRP[0]- PAGRP[3], PAGRP[0] includes external row addresses PA0-PA3. PAGRP[1] includes external row addresses PA4-PA7, and so on. It should be understood from Figures 3A-3C that the logical row addresses EA0-EA3 in logical row group EAGRP[0] that are used and / or valid will be mapped by row address mapping 113 to physical row group PAGRP[0], logical row addresses EA4-EA7 in logical row group EAGRP[1] that are used and / or valid will bemapped by row address mapping 113 to physical row group PAGRPfl], and so on. This is illustrated in Figures 3A-3C by respective logical address groups EAGRP[0]-EAGRP[3] being aligned horizontally with respective corresponding physical address groups PAGRPfO]- PAGRP[3],

[0032] As discussed herein, row address mapping 113 may also, in an embodiment, permute or otherwise map respective logical row addresses within each group to respective physical row addresses within the corresponding group of physical row addresses to avoid accessing physical row addresses corresponding to bad rows. This is illustrated in Figures 3A-3C by respective intra-group mappings 313 (a.k.a., GRP0-GRP3 maps) illustrated as disposed between a respective logical row group (e.g., EAGRPfl]) and its corresponding physical row group (e.g., PAGRPfl]).

[0033] Figures 3B-3C illustrate by example intra-group mapping to avoid bad rows. In Figure 3B-3C, external row address EA3 is unused (or invalid) in EAGRPfO], External row address EA7 is unused in EAGRPfl], External row address EA11 is unused in EAGRP[2], And external row address EA15 is unused in EAGRP[3], These unused logical addresses are illustrated in Figures 3B-3C by the “prohibition symbol” (i.e., circle with a slash) over EA3, EA7, EA11, and EA15. Also in Figures 3B-3C, physical row addresses PA5 of PAGRPfl], PAI 1 of PAGRP[2], and PA12 and PA14 of PAGRP[3] correspond to bad rows. These addresses that correspond to bad rows are illustrated in Figures 3B-3C by “X”’s over PA5, PA11, PA12, and PA14.

[0034] Figure 3C illustrates example intra-group mappings to avoid bad rows. In Figure 3C, PAGRPfO] is illustrated as having no bad rows. Thus, the intra-group mapping GRP0 selected and stored as configuration information 114 is illustrated implementing, for example, a “null” permutation where EA0 maps to PA0, EA1 maps to PAI, EA2 maps to PA2, and, if implemented, EA3 maps to PA3. This is illustrated in Figure 3C by the solid arrows running from EA0 to PA0, EA1 to PAI, and EA2 to PA2, and the dotted arrow running from unused external address EA3 to PA3.

[0035] PAGRPfl] is illustrated as having PA5 as a bad row. Thus, the intra-group mapping GRP1 selected and stored as configuration information 114 is illustrated implementing, for example, a permutation where EA4 maps to PA6, EA5 maps to PA7, EA6 maps to PA4, and, if implemented, unused logical address EA7 maps to the bad row address PA5. This is illustrated in Figure 3C by the solid arrows running from EA4 to PA6, EA5 to PA7, and EA6 to PA4, and the dotted arrow running from unused external address EA7 to bad row address PA5.

[0036] PAGRP[2] is illustrated as having PAI 1 as a bad row. Thus, the intra-group mapping GRP2 selected and stored as configuration information 114 is illustrated implementing, for example, the “null” permutation where EA8 maps to PA8, EA9 maps to PA9, EA10 maps to PA10, and, if implemented, EA11 maps to bad row address PAI 1. This is illustrated in Figure 3C by the solid arrows running from EA8 to PA8, EA9 to PA9, and EA10 to PA10, and the dotted arrow running from unused external address EA11 to bad row address PA11.

[0037] PAGRP[3] is illustrated as having PA12 and PA14 as bad rows. Thus, the intragroup mapping GRP3 selected and stored as configuration information 114 is illustrated implementing, for example, a permutation where EA12 maps to PA13, EA13 maps to bad row address PA12, EA14 maps to PAI 5, and, if implemented, EA15 maps to bad row address PA14. This is illustrated in Figure 3C by the solid arrows running from EA12 to PA13, EA13 to bad row PA12, and EA14 to PA15, and the dotted arrow running from unused external address EA15 to bad row address PA14. Note that since the GRP3 mapping illustrated in this example was unable to avoid at least one bad row (PA12), the row at physical row address for the bad row PAI 2 may be repaired, for example, by using repair CAM 115 and repair rows 135. In an embodiment, to repair the at least one bad row (e.g., EA13 mapping to PA12) that was unable to be repaired by row address mapping 113, in operation, row address mapping 113 and CAM 115 may be both queried (e.g., concurrently or sequentially) with the unmapped external address (e.g., EA13) and if repair CAM 115 indicates that a repair row is needed even after the remapping by row address mapping 113, the repair row indicated by CAM 115 would be used rather than the row indicated by row address mapping 113.

[0038] Figures 4A-4B are diagrams illustrating example processes to map rows within row groups. Figure 4 A illustrates mapping a 16-bit external row address that ranges over an address space corresponding to 48k contiguous rows to a 16-bit physical row address space that ranges over an address space corresponding to 64k rows and may be configured to avoid a single bad row in physical address groups of four rows. In Figure 4A, external row address (EA) 401 is illustrated having a first field composed of the fourteen (14) least significant bits (EA[13:0]) and a second field composed of the two (2) most significant bits (EA[15:14]). External row address 401 is processed to form an intermediate address 402 by shifting the first field of EA 401 to the fourteen (14) most significant bits of intermediate address 402. These fourteen (14) most significant bits of intermediate address 402 are to be used as a group address that point to (or correspond to) each of 48k four address groups. This isillustrated in Figure 4A by the arrow running from EA[13:0] to group address GA[13:0] of intermediate address 402. External row address 401 is also processed to form intermediate address 402 by shifting the second field of EA 401 to the two (2) least significant bits of intermediate address 402. This is illustrated in Figure 4A by the arrow running from EA[15: 14] to index bits ID[1 :0] of intermediate address 402.

[0039] Group address GA[13 :0] of intermediate address 402 is used as the most significant fourteen bits of physical row address 405 PA[15:2], This is illustrated in Figure 4A by the arrow running from GA[13:0] to the fourteen MSBs PA[15:2] of physical row address 405. The group address GA[13:0] is also used as an index into table function 404a. This is illustrated in Figure 4A by the arrow running from GA[13:0] to table function 404a. Based on the value of the group address GA[13:0], table function provides (outputs) an indicator of a permutation to be applied to index bits ID[ 1 :0] to implement a configured permutation associated with the value of the group address GA[13:0], Based on the indicator of a permutation from table function 404a, permutation circuitry 403a modifies the index bits ID[1 :0] to produce the indicated permutation.

[0040] For example, table function may supply a 2-bit value that is to be exclusive-OR’d (XOR’d)with index bits ID[1 :0] to implement various permutations table function has been configured to indicate in response to respective group address GA[13:0] values. Thus, for example, a 2-bit value of 00b when XOR’d with ID[1 :0] bits would implement the “null” permutation. An example of this type of swapping / permutation is illustrated in Figure 3C by the intra-group mapping GRP0 and the intra-group mapping GRP2. A 2-bit value of 01b when XOR’d with ID[1 :0] bits implements a permutation that swaps the intermediate address with ID[1 :0] bits of 00b with the intermediate address with ID[1 :0] bits of 01b and swaps the intermediate address with ID[1 :0] bits of 10b with the intermediate address with ID[1 :0] bits of 1 lb. An example of this type of swapping / permutation is illustrated in Figure 3C by the intra-group mapping GRP3. A 2-bit value of 10b when XOR’d with ID[1 :0] bits implements a permutation that swaps the intermediate address with ID[1 :0] bits of 00b with the intermediate address with ID[l :0] bits of 10b, swaps the intermediate address with ID[l :0] bits of 01b with the intermediate address with ID[1 :0] bits of 1 lb, swaps the intermediate address with ID[1 :0] bits of 10b with the intermediate address with ID[1 :0] bits of 00b, and swaps the intermediate address with ID[1 :0] bits of 1 lb with the intermediate address with ID[1 :0] bits of 01b. An example of this type of swapping / permutation is illustrated in Figure 3C by the intra-group mapping GRP1.

[0041] After the intermediate address index bits ID[ 1 :0] have been modified to implement an intra-group permutation of external row addresses to physical row addresses, the modified ID[1 :0] bits are used as the least significant 2 -bits of physical row address 405. This is illustrated in Figure 4A by the arrow from ID[ 1 :0] of intermediate address 402 running to permutation circuitry 403a, the arrow from table function 404a to permutation circuitry 403a, and the arrow from permutation circuitry 403a to physical address bits PA[l :0].

[0042] Figure 4B illustrates a generalized mapping of a Q-bit external row address that ranges over an address space corresponding 2P-2Qcontiguous rows to a P-bit physical row address space that ranges over an address space corresponding to 2Prows and may be configured to avoid a single bad row in physical address groups of 2(P'Q)rows, where P and Q are positive integers. For example, if P=16 and Q=13, the logical address space will be 56k rows, the physical address space will be 64k rows, and the address groups will each have eight (8) addresses. In Figure 4B, external row address EA 407 is illustrated having a first field composed of the Q number of least significant bits (EA[Q-1 :0]) and a second field composed of the P-Q number of most significant bits (EA[P-1 :Q]). External row address 407 is processed to form an intermediate address 408 by shifting the first field of EA 407 to the Q number of most significant bits of intermediate address 408. These Q number of most significant bits of intermediate address 408 are to be used as a group address that point to (or correspond to) each of 2Qnumber of address groups that each have 2(P'Q)rows. This is illustrated in Figure 4B by the arrow running from EA[Q-1 :0] field to group address the GA[Q-1 :0] field of intermediate address 408. External row address 407 is also processed to form intermediate address 408 by shifting the second field of EA 407 to the P-Q least significant bits of intermediate address 408. This is illustrated in Figure 4B by the arrow running from EA[P-1 :Q] field to the index bits ID[P-Q-1 :0] field of intermediate address 408.

[0043] The group address GA[Q-l :0] field of intermediate address 408 is used as the most significant Q number of bits of physical row address 4095 PA[P-1 :P-Q]. This is illustrated in Figure 4B by the arrow running from the GA[Q-1 :0] field to the Q number MSBs PA[P-1 :P-Q] of physical row address 409. The group address GA[Q-l :0] field is also used as an index into table function 404b. This is illustrated in Figure 4B by the arrow running from the GA[Q-1 :0] field to table function 404b. Based on the value of the group address GA[Q-1 :0] field, table function provides (outputs) an indicator of a permutation to be applied to the value of the index bits ID[P-Q-1 :0] field to implement a configured permutation associated with the value of the group address GA[Q-1 :0] field. Based on theindicator of a permutation from table function 404b, permutation circuitry 403b modifies the value(s) of the index bits ID[P-Q-1 :0] field to produce the indicated permutation.

[0044] After the intermediate address index bits ID[P-Q-1 :0] field have been modified to implement an intra-group permutation of external row addresses to physical row addresses, the modified value of the ID[P-Q-1 :0] field bits are used as the least significant P-Q bits of physical row address 409. This is illustrated in Figure 4B by the arrow from ID[P-Q-1 :0] field of intermediate address 408 running to permutation circuitry 403b, the arrow from table function 404b to permutation circuitry 403b, and the arrow from permutation circuitry 403b to physical address bits PA[P-Q-l :0].

[0045] In Figures 4A-4B, table functions 404a-404b function to relate group addresses GA[] to permutation indicators to be applied to index bits ID[], It should be understood that table functions 404a-404b may be or comprise one or more of a conventional one-to-one style lookup table (e.g., memory, CAM, etc.) and / or linear algebra based approaches such as a linear filter (or multiple linear filters). Also in Figures 4A-4B, the modified ID[1 :0] bits are used as the least significant 2 -bits of physical row address 405. However, this is merely one example. The modified ID bits can be placed in other locations (i.e., bit position range, noncontiguous bit positions, etc.) of the final physical row address 405. Placing the modified ID bits in more significant bit position(s), non-contiguous bit position(s), and / or varying / configurable bit position(s) of the final physical row address 405 may, for example, allow for more robust repair technique(s) in cases where failed rows happen to cluster around contiguous physical address ranges. In an embodiment, the placement of the modified ID bits in the final physical row address 405 may be based on, for example, configuration information 114.

[0046] Figure 5 is a block diagram illustrating an example system to map row addresses. Figure 5 illustrates a mapping system whereby a 48k external address space (i.e., 2p-2Q=48k) is mapped to 64k physical address space (i.e., 2p=64k) and there are Ik of repair rows (e.g., 2R=lk). However, it should be understood that this is merely one example. As discussed herein with respect to Figure 4B, other selections of values for P, Q, and R are contemplated.

[0047] In Figure 5, mapping system 500 comprises lookup table function 514, repair circuitry 515, nonvolatile memory 541, bitwise XOR 542, shift and combine circuitry 543, gating circuitry 545a, gating circuitry 545b, main array 530, and repair rows 535. Repair circuitry 515 includes content addressable memory (CAM) circuitry 515a. Nonvolatile memory 541 and repair circuitry 515 (and CAM circuitry 515a, in particular), may be configured with information about bad rows in main array 530 and repair rows 535 during amanufacturing and / or test process. In particular, nonvolatile memory 541 may be configured with lookup table information that relates respective groups of four external addresses to permutation indicators. These permutation indicators may be selected to avoid accessing one or more bad rows in main array 530. CAM circuitry 515a may be configured with information about bad rows in main array that the permutation indicators from nonvolatile memory 541 were not able to avoid.

[0048] An external address EA[15:0] with a 48k address range is received by system 500 and operatively coupled to repair circuitry 515. The least significant fourteen bits (EA[13:0]) of the external address are operatively coupled as an input to lookup table function 514 and shift and combine circuitry 543. The most significant two bits (EA[15: 14]) of the external address are operatively coupled as an input to bitwise XOR 542.

[0049] Nonvolatile memory 541 is operatively coupled to lookup table function 514. Nonvolatile memory 541 is operatively coupled to lookup table function 514 to configure lookup table function 514 with 2 -bit permutation indicators. Once configured and based on the least significant fourteen bits (EA[13:0]) of the external address, lookup table function 514 outputs, two bit permutation indicators (TW[1 :0]) that are provided to bitwise XOR 542. The two bit permutation indicators (TW[1 :0]) are bitwise XOR’d with the most significant two bits (EA[15: 14]) of the external address by bitwise XOR 542. The two bit result of XOR’ing TW[1 :0] and EA[15: 14] is provided to shift and combine circuitry 543. Shift and combine circuitry 543 places the two bit result of XOR’ing TW[l :0] and EA[15: 14] as the two least significant bits of the physical address (PA[1 :0]). The least significant fourteen bits (EA[13:0]) of the external address are used by shift and combine circuitry 543 as the fourteen most significant bits of the physical address. In an embodiment, lookup table function 514 relates the least significant fourteen bits (EA[13:0]) of the external address to respective permutation indicators (TW[l :0]) using circuitry and or functionality that includes at least one linear filter.

[0050] Based on information stored in CAM circuitry 515a and based on the external address EA[15:0], repair circuitry 515 outputs a “repair hit” (RPRH) indicator when the row addressed by EA[15:0] in main array 530 should not be accessed and a row in repair rows 535 should be accessed instead. If the RPRH indicator indicates that main array 530 should be accessed, gating circuitry 545a allows the physical address PA[15:0] to be used to access the addressed row in main array 530. If the RPRH indicator indicates that main array 530 should not be accessed, gating circuitry 545b allows a repair address RA[9:0] to be used to access the addressed row in repair rows 535.

[0051] Figure 6 is a diagram illustrating a first example external to physical row address mapping. The mapping illustrated by Figure 6 may be, for example, implemented by row address mapping 113. In Figure 6, a range of external row addresses (EA[]) are illustrated on the left, a larger range of physical addresses are illustrated on the right (PA[]) with arrows between respective external addresses and corresponding physical addresses to illustrate an example mapping. In Figure 6, good rows are mapped directly from the external row address to the physical row address that is the same address. This is illustrated in Figure 6 by all of the rows (e.g., EA[0]) that do not have an “X” on their physical address having a mapping where the external row address and the physical address are the same (e.g., PA[0]). Bad rows (e.g., EA[X], EA[Y]) are mapped to the same least significant bits of address in the unused range of physical addresses. In other words, an external address EA[X] that would otherwise be mapped to bad physical row PA[X] is mapped to PA[M+XLSB] instead, where M is the reduced external row address range (e.g., 32k, 48k, 56k, etc.). This is illustrated in Figure 6 by the arrow from EA[X] to PA[M+XLSB], and the arrow from EA[Y] to PA[M+YLSB], where the “X”’s on PA[X] and PA[Y] indicate those are bad rows. In an embodiment, row address mapping 113 may use linear filter cascades to store the mappings from external row addresses to physical row addresses as illustrated in Figure 6. In a filter cascade, information is gathered from multiple filters such as linear filters, Bloom filters, etc. In some cases, the filters may indicate separate but related information, such as one filter indicating whether a row is bad, and the second indicating, for bad rows only, where the row should be remapped. In other cases, the cascaded filters may both indicate the same information, but they may be separate for efficiency reasons: for example, where a first table indicates some information with errors such as false positives, and a second (or further) table corrects those errors. See for example CRLite: A Scalable System for Pushing All TLS Revocations to All Browsers (Larisch et al, IEEE Symposium on Security and Privacy 2017, https: / / ieeexplore.ieee.org / document / 7958597) and Improved CRL Compression with Structured Linear Functions (Hamburg, Real World Crypto 2022, https: / / iacr.org / submit / files / slides / 2022 / rwc / rwc2022 / 34 / slides.pptx). Although the information in the filter tables contains logical dependencies, these may not be reflected as physical dependencies. For example, an implementation might check multiple filters in parallel to reduce latency, even though the result of one table may render the other irrelevant. Likewise the stages of the cascade may be physically combined into one larger table even though they are logically separate. In an embodiment, the implementation might perform alookup into a larger filter table, and then process the result using a decoder circuit to determine the output of the cascade.

[0052] Figures 7A-7B are diagrams illustrating a second example external row address to physical row address mapping. The mapping illustrated by Figures 7A-7 may be, for example, implemented by row address mapping 113. In Figures 7A-7B, a range of external row addresses (EA[]) are illustrated on the left, a larger range of physical addresses are illustrated on the right (PA[]) with arrows between respective external addresses and corresponding physical addresses to illustrate an example mapping. In Figures 7A-7B, good rows are mapped directly from the external row address to the physical row address that is the same address. This is illustrated in Figures 7A-7B by all of the rows (e.g., EA[0]) that do not have an “X” on their physical address having a mapping where the external row address and the physical address are the same (e.g., PA[0]). Bad rows (e.g., EA[X]) are mapped to one of a number of choices. These choices may be based on the external row address EA[X], These choices may be algorithmically and / or arithmetically selected based on the external row address EA[X] (e.g., PA[M+XLSB+1], PA[M+XLSB], PA[M+XLSB-1], or PA[M+XLSB-2]). In an example, an external address EA[X] that would otherwise be mapped to bad physical row PA[X] is mapped to a selected one of PA[M+XLSB+1], PA[M+XLSB], PA[M+XLSB-1], or PA[M+XLSB-2], where M is the reduced external row address range (e.g., 32k, 48k, 56k, etc.). This is illustrated in Figure 7A by the arrows leading to PA[M+XLSB+1], PA[M+XLSB], PA[M+XLSB-1], or PA[M+XLSB-2] each having question marks (?). In another example, an external row address EA[X] that would otherwise be mapped to bad physical row PA[X] is mapped to a selected one of PA[M+XLSB-2], PA[M+XLSB], PA[M+YLSB-1], or PA[M+YLSB-1], This is illustrated in Figure 7A by the arrow from EA[X] splitting to lead to PA[M+XLSB-2], PA[M+XLSB], PA[M+YLSB-1], and PA[M+YLSB-1],

[0053] The selection of which of the choices is selected may be based on whether a choice is already mapped with another external row address. This is illustrated in Figure 7B by PA[M+XLSB] having a prohibition symbol on it and the arrow leading to PA[M+XLSB] having an “X” instead of a question mark (?). The selection of which of the choices is selected may be based on whether a choice is also a bad row. This is illustrated in Figure 7B by PA[M+YLSB+1] having an “X” on it, and the arrow leading to PA[M+YLSB+1] having an “X” instead of a question mark (?).

[0054] In the example illustrated in Figure 7A-7B, two bits per bad row (i.e., four choices) are needed by row mapping to store the information about which rows are bad, and which row of the four choices in the unused physical address range was selected to replacethe bad row. In an embodiment, a linear filter may be used by row address mapping 113 to store the mappings from external row addresses to physical row addresses as illustrated in Figures 7A-7B.

[0055] Figure 8 is a diagram illustrating a third example external row address to physical row address mapping. The mapping illustrated by Figure 8 may be, for example, implemented by row address mapping 113. In Figure 8, a range of external row addresses (EA[]) are illustrated on the left, a larger range of physical addresses and a block of repair rows are illustrated on the right (PA[]) with arrows between respective external addresses and corresponding physical addresses to illustrate an example mapping.

[0056] Figure 8 illustrates an example mapping that uses what may be called a “tiered” or “weighted” approach. The first choice for a mapping for a given reduced range external row address is for good rows. Good rows are mapped directly from the external row address to the physical row address that is the same address. This is illustrated in Figure 8 by all of the rows (e.g., EA[0]) that do not have an “X” on their physical address having a mapping where the external row address and the physical address are the same (e.g., PA[0]) and by the row EA[X] with an arrow showing a choice indicator “?1”.

[0057] The second choice for a mapping involves rows that are bad. The second choice of mapping is for bad rows (e.g., EA[X]) are mapped to the same least significant bits of address in the unused range of physical addresses. In other words, an external address EA[X] that would otherwise be mapped to bad physical row PA[X] is mapped to PA[M+XLSB], if available and good, instead, where M is the reduced external row address range (e.g., 32k, 48k, 56k, etc.). This is illustrated in Figure 8 by an arrow from EA[X] to PA[M+XLSB] showing a choice indicator “?2”.

[0058] A third choice for mapping involves rows that were not able to be mapped to the same least significant bits of address in the unused range of physical addresses (i.e., the rows in the unused range of physical were unavailable and / or bad). The third choice for an external address EA[X] that would otherwise be mapped to bad physical row PA[X], and also cannot be mapped to PA[M+XLSB], is mapped to two to four other locations in the unused range of physical addresses. For example, when EA[X] cannot be mapped to PA[X] or PA[M+XLSB], EA[X] may be mapped to a selected one of PA[M+YLSB+1], PA[M+YLSB-1], PA[M+XLSB-2], or PA[M+1], This is illustrated in Figure 8 by the arrows showing choice indicators “?3a”, “?3b”, “?3c”, and “?3d”.

[0059] Finally, if the preceding mappings are unavailable (i.e., all bad rows or already used rows in the unused physical address range), rows from repair rows 135 may be used.This is illustrated in Figure 8 by the arrow EA[X] to the area of repair rows showing a choice indicator “?4”.

[0060] In an embodiment, row address mapping 113 may use a priority encoding to indicate the choices for each external row address EA[], This encoding may be stored in a linear filter. For example, a 6-bit value (a.k.a., “locator”) may be output by a linear filter in row address mapping 113 that indicates to row address mapping 113 which of the four choices for a mapping described herein is to be used.

[0061] Figure 9 is a diagram illustrating an example full external row address range to physical plus repair row address mapping. The mapping illustrated by Figure 9 may be, for example, implemented by row address mapping 113 and thereby allow the elimination of repair CAM 115. In Figure 9, a full range of external row addresses (EA[] from 0 to N-l) are illustrated on the left, a larger range of physical addresses that includes a block of repair rows (PA[] from 0 to N+Z-l) are illustrated on the right (PA[]) with arrows between respective external addresses and corresponding physical addresses to illustrate an example mapping, where Z equals the number of repair rows (e.g., Z=2R=lk).

[0062] Figure 9 illustrates an example mapping that also uses what may be called a “tiered” or “weighted” approach. The first choice for a mapping for a given full range external row address is for good rows. Good rows are mapped directly from the external row address to the physical row address that is the same address. This is illustrated in Figure 9 by all of the rows (e.g., EA[0]) that do not have an “X” on their physical address having a mapping where the external row address and the physical address are the same (e.g., PA[0]) and by the row EA[X] with an arrow showing a choice indicator “?1”.

[0063] The second choice for a mapping involves rows that are bad. The second choice of mapping is for bad rows (e.g., EA[X]) are mapped to the same least significant bits of address in the repair range of physical addresses. In other words, an external address EA[X] that would otherwise be mapped to bad physical row PA[X] is mapped to PA[N+XLSB], if available and good, instead, where N is the full external row address range (e.g., 64k, etc.). This is illustrated in Figure 9 by an arrow from EA[X] to PA[N+XLSB] showing a choice indicator “?2”.

[0064] A third choice for mapping involves rows that were not able to be mapped to the same least significant bits of address in the repair range of physical addresses (i.e., the rows in the repair range of physical were unavailable and / or bad). The third choice for an external address EA[X] that would otherwise be mapped to bad physical row PA[X], and also cannot be mapped to PA[M+XLSB], is mapped to two to four other locations in the repair range ofphysical addresses. For example, when EA[X] cannot be mapped to PA[X] or PA[N+XLSB], EA[X] may be mapped to a selected one of: PA[N+YLSB+1], PA[N+YLSB-1], PA[N+XLSB-2], or PA[N+1], This is illustrated in Figure 9 by the arrows showing choice indicators “?3a”, “?3b”, “?3c”, and “?3d”

[0065] In an embodiment, row address mapping 113 may use a priority encoding to indicate the choices for each external row address EA[], This encoding may be stored in a linear filter. For example, a 6-bit value (a.k.a., “locator”) may be output by a linear filter in row address mapping 113 that indicates to row address mapping 113 which of the four choices for a mapping described herein is to be used.

[0066] Figure 10 is a block diagram illustrating a weighted matching system to map row addresses. Figure 10 illustrates a mapping system whereby a 48k external address space (i.e., 2p-2Q=48k) is mapped to 64k physical address space (i.e., 2p=64k) and there are repair rows (e.g., 2R=lk). However, it should be understood that this is merely one example. As discussed herein with respect to Figure 4B and Figure 5, other selections of values for P, Q, and R are contemplated.

[0067] In Figure 10, mapping system 1000 comprises linear filter 1014, nonvolatile memory 1041, decoder circuitry 1045, 5 by 16-bit inputs to one 16-bit output multiplexor (MUX) 1046, and alternate address generator 1047. Nonvolatile memory 1041 is used to configure linear filter 1014. Nonvolatile memory 1041 may be configured with “locator” information about good rows and bad rows in, for example, primary array 130 and repair rows 135 during a manufacturing and / or test process. In particular, nonvolatile memory 1041 may be configured with locator information that relates each used external row address to a physical address according to a weighted or tiered approach (e.g., as described with respect to Figure 8).

[0068] An external row address EA[15:0] with a 48k address range is received by system 1000 and operatively coupled to linear filter 1014, MUX 1046, and alternate address generator 1047. Based on the external row address EA[15:0], linear filter 1014 provides a 6- bit locator value LC[5:0] to decoder circuitry 1045. Based on the external row address EA[15:0], alternate address generator 1047 provides 16-bit candidate physical addresses CPA1[], CPA2[], etc. to MUX 1046. In an embodiment,

[0069] Based on the locater value, decoder circuitry 1045 controls MUX 1046 to select and output a one of the external row address provided (i.e., physical row is good), the corresponding row in the unused physical address range, or a one of four candidate physicaladdresses CPA1[], CPA2[], etc. as the physical address PA[15:0] used to address, for example, primary array 130.

[0070] In an embodiment, the 6-bit locator value LC[5:0] may be encoded, for example, as follows (where lower case ‘x’ means a bit is not used / don’t care). If the corresponding physical row is good, the 6-bit locator LC[5:0] output by linear filter 1014 is one of Ixxxxxb, Olxxxxb, or OOlxxxb. In these cases, decoder circuitry 1045 would control MUX 1046 to output the received external row address EA[15:0], If the corresponding physical row is bad, and the corresponding row in the unused physical address space is good and available, the 6- bit locator LC[5:0] output by linear filter 1014 is OOOOlxxb. In this case, decoder circuitry 1045 controls MUX 1046 to output a physical address the same least significant bits of address in the unused range of physical addresses (e.g., EA[13:0]+3*214). If the corresponding physical row is bad, and the corresponding row in the unused physical address space not good or not available, the 6-bit locator LC[5:0] output by linear filter 1014 is 0000 lyzb, where “yz” is a 2 -bit value that indicates which of the candidate physical addresses (e.g., CPAl[15:0], CPA2[15:0], etc.) should be selected by decoder circuitry 1045. In these cases, decoder circuitry 1045 controls MUX 1046 to output the selected (i.e., by the value of the 2-bits “yz”) candidate physical address CPAl[15:0], CPA2[15:0], etc. as the physical address PA[15:0] to be used.

[0071] Figure 11 is a flowchart illustrating a method of operating a memory device. One or more steps illustrated in Figure 11 may be performed by, for example, memory system 100, mapping system 500, mapping system 1000, and / or their components. At a command / address (CA) interface, a first plurality of external row addresses from a contiguous external row address range is received (1102). For example, memory device 110 may receive, from controller 120 and via CA interface 121 and CA interface 111, a first set of three external row addresses that have been confined to a reduced contiguous address range row addresses (e.g., addresses are limited to between 0 and 48k rows per bank vs. a full capacity 0 to 64k rows per bank) and all have the same 14 least significant bits.

[0072] Each of the first plurality of external row addresses are translated to a first group address that addresses a first group of contiguous physical addresses used to access a first group of rows of a memory array (1104). For example, row address mapping 113 may translate each of the first set of three row addresses to the same group address by selecting the 14 least significant bits of each of the first set of three row addresses (which are all the same value) and using those 14 least significant bits as a 14 bit group address corresponding the 14 most significant bits of the physical addresses of a contiguous set of physicaladdresses. Based on the first group address of the first group of contiguous physical addresses, a first permutation indicator is received (1106). For example, based on the group address, row address mapping 113 use the 14 least significant bits of the external row address as a group address that is used to index into a lookup table function (e.g., lookup table function 514, table function 404a, table function 404b) that provides an indicator of a permutation to be applied to the addresses associated with the group address of the first set of three row addresses.

[0073] Based on the first permutation indicator and the first plurality of external row addresses, a first plurality of physical addresses each corresponding to a one of the first plurality of external row addresses that access a first proper subset of rows in the first group of rows of the memory array is generated (1108). For example, every time a respective one of the first set of three row address with the same group addresses is received, the permutation indicated by the indicator is applied to the respective external row address to, in combination with the group address, form physical addresses that only access a proper subset of the contiguous set of physical addresses associated with that set of three external row addresses. The permutation indicated may, for example, have been selected during manufacturing and programmed into a nonvolatile memory of the memory device to avoid bad rows in a memory array (a.k.a., bank).

[0074] Figure 12 is a flowchart illustrating a method of mapping external row addresses to avoid bad rows. One or more steps illustrated in Figure 12 may be performed by, for example, memory system 100, mapping system 500, mapping system 1000, and / or their components. An external row address is received (1202). For example, memory device 110 may receive, from controller 120 and via CA interface 121 and CA interface 111, a P-bit external row address (e.g., P=16) from a reduced contiguous address range of external row addresses (e.g., a range of 0 to (2p-2Q)=48k, where Q=14 and P=16).

[0075] A first plurality of bits of the external row address are selected to associate the external row address with a group address associated with a group of physical addresses (1204). For example, row address mapping 113 may translate the first external row address to a group address by selecting the Q least significant bits of the first external row address to be a Q-bit group address corresponding the Q most significant bits of a first group of contiguous physical addresses in a P-bit physical address range. Based on the group address, a permutation indicator is determined (1206). For example, based on the group address derived from the Q least significant bits of the first external row address, row address mapping 113 may use the group address to index into a lookup table function (e.g., lookuptable function 514, table function 404a, table function 404b) that provides an indicator of a permutation to be applied to the addresses associated with the group address.

[0076] Based on the permutation indicator, a second plurality of bits are permuted to generate an intra-group address that is not associated with a bad row withing the group of physical addresses, the second plurality of bits composed of the external row address bits that are not members of the first plurality of bits (1208). For example, the P-Q most significant bits of the first external row address, may be permuted according to the permutation indicator for the lookup table function in order to form a P-Q intra-group address. The group address and the intra-group address are combined to generate a physical address that is not associated with a bad row (1210). For example, the group address may be used as the most significant bits and the intra-group address used as the least significant bits to form a physical address that, because of the selected permutation indicated by the permutation indicator, does not correspond to a bad row.

[0077] Figure 13 is a flowchart illustrating a method of selecting external row address mappings. One or more steps illustrated in Figure 13 may be performed by, for example, memory system 100, mapping system 500, mapping system 1000, and / or their components. An external row address that is in a first row address range is received (1302). For example, memory device 110 may receive, from controller 120 and via CA interface 121 and CA interface 111, a P-bit external row address (e.g., P=16) from a reduced contiguous address range of external row addresses (e.g., a range of 0 to M=(2p-2Q)=48k, where Q=14 and P=16).

[0078] The external row address is determined to be associated with a bad row (1304). For example, row mapping 213 using a linear filter 1014 may, when queried using the external row address and / or a value derived from the external row address (e.g., hash of external row address), provide a locator value that indicates the row associated with the external row address is bad. Based on the external row address, a plurality of candidate physical row addresses in a physical address range that is not part of the first row address range are generated (1206). For example, alternate row mapping 213 using address generator 1047 may, based on the external row address, generate multiple (e.g., 2, 4, etc.) candidate physical addresses (e.g., EA[Q-1 :0]+2Q, CPA1[], CPA2[], etc.).

[0079] A linear filter is queried for a candidate physical row address indicator (1308). For example, row mapping 213, as part of the query of linear filter 1014 to determine whether the external row address was associated with a bad row, linear filter 1014 may provide an additional indicator of which candidate physical address should be output for use during thecurrent access. In another example, row mapping 213 may query linear filter 1014 for an additional indicator of which candidate physical address should be output for use during the current access. Based on the candidate physical row address indicator, a one of the plurality of candidate physical row addresses is selected to be accessed based on the external row address (1310). For example, row mapping 213 may, based on the additional indicator of which candidate physical address should be output for use during the current access, use decoder circuitry 1045 to control MUX 1046 to output the indicated candidate physical address for use in place of the received external address.

[0080] Figure 14 is a flowchart illustrating a method of using a linear filter for external row address to physical address row mapping. One or more steps illustrated in Figure 14 may be performed by, for example, memory system 100, mapping system 500, mapping system 1000, and / or their components. A first external row address that is in a first row address range is received (1402). For example, memory device 110 may receive, from controller 120 and via CA interface 121 and CA interface 111, a first external row address having P number of bits (e.g., P=16) from a reduced contiguous address range of external row addresses (e.g., a range of 0 to M=(2p-2Q)=48k, where Q=14 and P=16).

[0081] A linear filter is queried based on the first external row address to determine a memory array row corresponding to the first external row address is not bad (1404). For example, row mapping 213 using a linear filter 1014 may, when queried using the first external row address and / or a value derived from the first external row address (e.g., hash of the first external row address), provide a locator value that indicates the row associated with the first external row address is not bad. The memory array is accessed based on the first external row address (1406). For example, row mapping 213 may, based on the indication that the row corresponding to the first external row address is not bad, access the row addressed by the first external row address.

[0082] A second external row address that is in the first row address range is received (1408). For example, memory device 110 may receive, from controller 120 and via CA interface 121 and CA interface 111, a second external row address from the reduced contiguous address range of external row addresses. The linear filter is queried based on the second external row address to determine the memory array row corresponding to the second external row address is not bad and that a first candidate physical row address, derived from the second external row address that is in the physical address range that is not part of the first row address range is associated with the second external row address (1410). For example, row mapping 213 using linear filter 1014 may, when queried using the secondexternal row address and / or a value derived from the second external row address (e.g., hash of second external row address), provide a locator value that indicates the row associated with the second external row address is bad and that the corresponding row to the second external row address in the unused physical address range should be used in place of the second external row address. The memory array is accessed based on the first candidate physical row address (1412). For example, row mapping 213 may, based on the indication that the first candidate physical row address should be used in place of the second external row address, access the row addressed by the first candidate physical row address.

[0083] A third external row address that is in the first row address range is received (1414). For example, memory device 110 may receive, from controller 120 and via CA interface 121 and CA interface 111, a third external row address from the reduced contiguous address range of external row addresses. The linear filter is queried based on the third external row address to determine the memory array row corresponding to the third external row address is not associated with the third external row address, and that a third candidate physical row address in the physical address range that is not part of the first row address range is associated with the third external row address (1416). For example, row mapping 213 using linear filter 1014 may, when queried using the third external row address and / or a value derived from the third external row address (e.g., hash of third external row address), provide a locator value that indicates the row associated with the third external row address is bad, that the corresponding row to the third external row address in the unused physical address range should not be used in place of the third external row address, and that a third candidate physical row address should be used in place of the third external row address to access the row addressed by the third candidate physical row address. The memory array is accessed based on the third candidate physical row address (1418). For example, row mapping 213 may, based on the indication that the third candidate physical row address should be used in place of the third external row address, access the row addressed by the third candidate physical row address.

[0084] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system 100, mapping system 500, mapping system 1000, and their components. These software descriptions maybe: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0085] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0086] Figure 15 is a block diagram illustrating one embodiment of a processing system 1500 for including, processing, or generating, a representation of a circuit component 1520. Processing system 1500 includes one or more processors 1502, a memory 1504, and one or more communications devices 1506. Processors 1502, memory 1504, and communications devices 1506 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1508.

[0087] Processors 1502 execute instructions of one or more processes 1512 stored in a memory 1504 to process and / or generate circuit component 1520 responsive to user inputs 1514 and parameters 1516. Processes 1512 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1520 includes data that describes all or portions of memory system 100, mapping system 500, mapping system 1000, and their components, as shown in the Figures.

[0088] Representation 1520 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1520 may be stored on storage media or communicated by carrier waves.

[0089] Data formats in which representation 1520 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0090] User inputs 1514 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1516 may include specifications and / or characteristics that are input to help define representation 1520. For example, parameters 1516 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0091] Memory 1504 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1512, user inputs 1514, parameters 1516, and circuit component 1520.

[0092] Communications devices 1506 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1500 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1506 may transmit circuit component 1520 to another system. Communications devices 1506 may receive processes 1512, user inputs 1514, parameters 1516, and / or circuit component 1520 and cause processes 1512, user inputs 1514, parameters 1516, and / or circuit component 1520 to be stored in memory 1504.

[0093] Implementations discussed herein include, but are not limited to, the following examples:

[0094] Example 1. A memory device, comprising: a memory array having a first number of rows accessed according to a corresponding first physical row address range; a command / address interface to, in a first mode, receive a plurality of external row addresses comprising a first row address range that is contiguous; and externally configurable row address mapping circuitry to, in the first mode, to provide translations of the plurality of external row addresses from the first row address range to the first physical row address range, the translations to comprise permuting addresses within groups of row addresses in first physical row address range to avoid bad rows within respective groups of row addresses in the first physical row address range.

[0095] Example 2: The memory device of example 1, wherein the externally configurable row address mapping circuitry comprises: lookup table circuitry to provide respective mapping indicators that determine respective permutations of addresses within respective groups of row addresses in the first physical row address range.

[0096] Example 3: The memory device of example 2, wherein information based on the mapping indicators is stored in a compressed form.

[0097] Example 4: The memory device of example 3, wherein the lookup table circuitry comprises linear filter circuitry.

[0098] Example 5: The memory device of claim 3, wherein the plurality of external row addresses consists of the first row address range that is contiguous.

[0099] Example 6: The memory device of example 1, wherein the memory array further comprises redundant rows accessed by a second physical row address range and the externally configurable row address mapping circuitry provide translations of the plurality of external row addresses from the first row address range to the second physical row address range.

[0100] Example 7: The memory device of example 1, wherein the first row address range is configurable to be less than the first physical row address range.

[0101] Example 8: A memory device, comprising: a memory array; a command / address interface to receive a first contiguous range of external row addresses to access the memory array; and row address mapping circuitry configured to translate a plurality of sets of received addresses in the first contiguous range of external addresses to a respective plurality of sets of physical addresses that access rows of the memory array, where each of the plurality of sets of received addresses in the first contiguous range of external addresses has a first number of addresses, and each of the plurality of sets of physical addresses has a second number of addresses, the second number being greater than the first number, the translations of the plurality of sets of received addresses to the respective plurality of sets of physical addresses to include permuting addresses within the plurality of sets of received addresses to avoid accessing bad rows within corresponding ones of the plurality of sets of physical addresses.

[0102] Example 9: The memory device of example 8, wherein the row address mapping circuitry comprises: lookup table circuitry to relate addresses in the plurality of sets of received addresses to respective ones of a plurality of permutation indicators.

[0103] Example 10: The memory device of example 9, wherein the row address mapping circuitry comprises: circuitry to, based on the respective ones of the plurality of permutation indicators, translate respective addresses of respective members of respective ones of the plurality of sets of received addresses to addresses of respective members of respective ones of the plurality of sets of physical addresses.

[0104] Example 11 : The memory device of example 8, wherein the row address mapping circuitry is configured to translate the plurality of sets of received addresses in the firstcontiguous range of external addresses to the respective plurality of sets of physical addresses using linear filter circuitry.

[0105] Example 12: The memory device of example 8, wherein the row address mapping circuitry is configured to translate the plurality of sets of received addresses in the first contiguous range of external addresses to the respective plurality of sets of physical addresses using linear filter circuitry and weighted matching.

[0106] Example 13: The memory device of example 8, wherein the memory array further comprises redundant rows and the row address mapping circuitry is configured to translate a first external row addresses to access a first row of the redundant rows.

[0107] Example 14: The memory device of example 8, wherein the memory array has a first number of physically addressable rows and there are a second number of addresses in the first contiguous range of external addresses and the first number of physically addressable rows is greater than the second number of addresses in the first contiguous range of external addresses.

[0108] Example 15: A method of operating a memory device, comprising: receiving, at a command / address (CA) interface, a first plurality of external row addresses from a contiguous external row address range; translating each of the first plurality of external row addresses to a first group address that addresses a first group of contiguous physical addresses used to access a first group of rows of a memory array; based on the first group address of the first group of contiguous physical addresses, receiving a first permutation indicator; and based on the first permutation indicator and the first plurality of external row addresses, generating a first plurality of physical addresses each corresponding to a one of the first plurality of external row addresses that access a first proper subset of rows in the first group of rows of the memory array.

[0109] Example 16: The method of example 15, wherein the first permutation indicator is received from lookup table circuitry that relates group addresses used to access groups of rows of the memory array to respective permutation indicators.

[0110] Example 17: The method of example 16, further comprising: receiving, at the command / address (CA) interface, a second plurality of external row addresses from the contiguous external row address range; translating each of the second plurality of external row addresses to a second group address, not equal to the first group address, that addresses a second group of contiguous physical addresses used to access a second group of rows of the memory array; based on the first group address of the second group of contiguous physical addresses, receiving a second permutation indicator; and based on the second permutationindicator and the second plurality of external row addresses, generating a second plurality of physical addresses each corresponding to a one of the second plurality of external row addresses that access a second proper subset of rows in the second group of rows of the memory array.

[0111] Example 18: The method of example 17, wherein the lookup table circuitry includes linear filter circuitry.

[0112] Example 19: The method of example 17, wherein the lookup table circuitry includes linear filter circuitry and weighted matching.

[0113] Example 20: The method of example 17, wherein the memory array includes redundant rows that include the second group of rows of the memory array.

[0114] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. A memory device, comprising: a memory array having a first number of rows accessed according to a corresponding first physical row address range; a command / address interface to, in a first mode, receive a plurality of external row addresses comprising a first row address range that is contiguous; and externally configurable row address mapping circuitry to, in the first mode, to provide translations of the plurality of external row addresses from the first row address range to the first physical row address range, the translations to comprise permuting addresses within groups of row addresses in first physical row address range to avoid bad rows within respective groups of row addresses in the first physical row address range.

2. The memory device of claim 1, wherein the externally configurable row address mapping circuitry comprises: lookup table circuitry to provide respective mapping indicators that determine respective permutations of addresses within respective groups of row addresses in the first physical row address range.

3. The memory device of claim 2, wherein information based on the mapping indicators is stored in a compressed form.

4. The memory device of claim 3, wherein the lookup table circuitry comprises linear filter circuitry.

5. The memory device of claim 3, wherein the plurality of external row addresses consists of the first row address range that is contiguous.

6. The memory device of claim 1, wherein the memory array further comprises redundant rows accessed by a second physical row address range and the externally configurable row address mapping circuitry provide translations of the plurality of external row addresses from the first row address range to the second physical row address range.

7. The memory device of claim 1, wherein the first row address range is configurable to be less than the first physical row address range.

8. A memory device, comprising: a memory array; a command / address interface to receive a first contiguous range of external row addresses to access the memory array; and row address mapping circuitry configured to translate a plurality of sets of received addresses in the first contiguous range of external addresses to a respective plurality of sets of physical addresses that access rows of the memory array, where each of the plurality of sets of received addresses in the first contiguous range of external addresses has a first number of addresses, and each of the plurality of sets of physical addresses has a second number of addresses, the second number being greater than the first number, the translations of the plurality of sets of received addresses to the respective plurality of sets of physical addresses to include permuting addresses within the plurality of sets of received addresses to avoid accessing bad rows within corresponding ones of the plurality of sets of physical addresses.

9. The memory device of claim 8, wherein the row address mapping circuitry comprises: lookup table circuitry to relate addresses in the plurality of sets of received addresses to respective ones of a plurality of permutation indicators.

10. The memory device of claim 9, wherein the row address mapping circuitry comprises: circuitry to, based on the respective ones of the plurality of permutation indicators, translate respective addresses of respective members of respective ones of the plurality of sets of received addresses to addresses of respective members of respective ones of the plurality of sets of physical addresses.

11. The memory device of claim 8, wherein the row address mapping circuitry is configured to translate the plurality of sets of received addresses in the first contiguous range of external addresses to the respective plurality of sets of physical addresses using linear filter circuitry.

12. The memory device of claim 8, wherein the row address mapping circuitry is configured to translate the plurality of sets of received addresses in the first contiguous range of external addresses to the respective plurality of sets of physical addresses using linear filter circuitry and weighted matching.

13. The memory device of claim 8, wherein the memory array further comprises redundant rows and the row address mapping circuitry is configured to translate a first external row addresses to access a first row of the redundant rows.

14. The memory device of claim 8, wherein the memory array has a first number of physically addressable rows and there are a second number of addresses in the first contiguous range of external addresses and the first number of physically addressable rows is greater than the second number of addresses in the first contiguous range of external addresses.

15. A method of operating a memory device, comprising: receiving, at a command / address (CA) interface, a first plurality of external row addresses from a contiguous external row address range; translating each of the first plurality of external row addresses to a first group address that addresses a first group of contiguous physical addresses used to access a first group of rows of a memory array; based on the first group address of the first group of contiguous physical addresses, receiving a first permutation indicator; and based on the first permutation indicator and the first plurality of external row addresses, generating a first plurality of physical addresses each corresponding to a one of the first plurality of external row addresses that access a first proper subset of rows in the first group of rows of the memory array.

16. The method of claim 15, wherein the first permutation indicator is received from lookup table circuitry that relates group addresses used to access groups of rows of the memory array to respective permutation indicators.

17. The method of claim 16, further comprising:receiving, at the command / address (CA) interface, a second plurality of external row addresses from the contiguous external row address range; translating each of the second plurality of external row addresses to a second group address, not equal to the first group address, that addresses a second group of contiguous physical addresses used to access a second group of rows of the memory array; based on the first group address of the second group of contiguous physical addresses, receiving a second permutation indicator; and based on the second permutation indicator and the second plurality of external row addresses, generating a second plurality of physical addresses each corresponding to a one of the second plurality of external row addresses that access a second proper subset of rows in the second group of rows of the memory array.

18. The method of claim 17, wherein the lookup table circuitry includes linear filter circuitry.

19. The method of claim 17, wherein the lookup table circuitry includes linear filter circuitry and weighted matching.

20. The method of claim 17, wherein the memory array includes redundant rows that include the second group of rows of the memory array.

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