Devices and methods with buried bonded waveguides (BBW)

Abstract

A buried bonded waveguide (BBW) structure includes a lower cladding layer (LCL), waveguide core (WG Core), and thin partial upper cladding layer (PUCL) realized using III-Nitride alloys (e.g., InAlGaN). The PUCL layer includes layers or layer stacks. The first is the spacer layer, which offsets the BBW lateral confining layers (LaCLs) from the WG core. The second is the BBW patterned cladding layer (PCL), wherein the BBW LaCL is formed. Wafer bonding techniques enable the burying LaCLs in the upper confining layer (UCL). These LaCLs can serve to confine the light laterally and can optionally be of a limited vertical extent provided they are in sufficient proximity to the waveguide core.

Description

Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 DEVICES AND METHODS WITH BURIED BONDED WAVEGUIDES (BBW)   CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. provisional patent application No. 63 / 649,786, filed on May 20, 2024, and titled “DEVICES AND METHODS WITH BURIED BONDED WAVEGUIDES (BBW),” the disclosure of which is expressly incorporated herein by reference in its entirety.   BACKGROUND

[0002] High-performance optoelectronic and photonic devices in the visible and ultraviolet (VU) spectrum have critical emerging applications for sensing (environmental, health / medical, imaging, etc.), atomic / quantum devices and circuits (atomic clocks, magnetometers, gyroscopes, etc.), and communications (underwater and very lower power inter-chip and intra- chip). High-performance VU spectrum sources, which can be integrated into a full-function photonic IC (PIC) platform, are enabling components for the realization of transformative impacts in these fields. Specifically, narrow-linewidth / low-phase noise, high-power, tunable laser sources that can be integrated with high-Quality factor (high-Q) tunable resonators, filters, amplifiers, detectors, and modulators that operate across the VU spectrum are needed.

[0003] While tremendous advances have been made in the development and realization of light-emitting diodes and laser diodes in the VU spectrum through the development if III- Nitride alloys, several inherent challenges have limited the development of PICs in this spectral regime, including: the ability to realize very low-loss waveguides, the low-loss / low back reflection integration of passive waveguides with active devices, high-performance single lateral and longitudinal mode sources, the integration of multiple active regions on to a photonic IC, and the integration of high-Q (and tunable) resonators with engineered reflection spectra. These limitations arise from a number of inherent challenges in the III-Nitride materials, including: the reduced index contrast between the different constituent InGaN and AlGaN alloys, the limited ability to integrate the full range of alloys of AlGaN and InGaN into a single device structure due to high lattice and thermal expansion mismatch, the lack of selective area growth and butt-joint regrowth techniques to integrate multiple III-Nitride alloys on a chip, and the inability to realize buried devices structures by regrowth (e.g., for buried heterostructure and buried ridge waveguides and active devices). Furthermore, shortcomings on III-Nitride fabrication techniques to produce ultra-smooth etched waveguide sidewalls are 1  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 increasingly an issue for high-performance devices as scattering losses substantially increase with reduced wavelength. In fact, scattering loss is proportional to the inverse 2ndto 4thpower of the wavelength (Lacey and Payne 1990) (Deri and Kapon 1991) (Zheltikov 2006). In addition, the challenges of realizing crack-free integration of low-index dielectrics and integrated (buried) low-order grating structures further limit the realization of VU spectrum high-performance sources and PICs.

[0004] There is a need for improved optoelectronic and photonic devices. SUMMARY

[0005] Exemplary systems and methods are disclosed that employ high-performance III-N optoelectronic devices on PIC platforms that are capable of yielding high-performance sources and PICs. The platform is capable of integrating low-loss waveguides (<4dB / cm, preferably <2dB / cm, most preferably <1dB / cm) with high-performance single-mode III-Nitride active devices with 100% coupling efficiency, low insertion loss (<1dB, preferably <0.5dB, most preferably <0.1dB) and <-30dB, and preferably <-50dB back reflection. This architecture will enable the realization of low-noise, high-power spectroscopic grade VU spectrum tunable lasers as well as the integration of a full suite of active and passive devices in the VU spectrum.

[0006] In some aspects, implementations of the present disclosure include an apparatus, including: a substrate; a first region (e.g., first LCL region) provided on the substrate, the first region being a lower cladding region including a first Group-III-nitride semiconductor; a second region (e.g., second UCL region) provided on the first region, the second region being an upper cladding region including a second Group-III-nitride semiconductor; a third region (e.g., third core or active region) provided between the first and second regions, the third region including a third Group-III-nitride semiconductor; a wafer bonded interface provided above the substrate; a fourth region (e.g., fourth one of the BBWG regions) provided above the substrate; and a fifth region (e.g., fifth a second one of the BBWG regions) region provided above the substrate, the fourth region being spaced from the fifth region, such that an optical mode is confined to a confinement region defined by the upper and lower cladding regions in a first direction and the fourth and fifth regions in a second direction.

[0007] In some aspects, implementations of the present disclosure include an apparatus, wherein the first direction that the optical mode is confined is a lateral direction.

[0008] In some aspects, implementations of the present disclosure include an apparatus, wherein a refractive index of confinement region is different than a refractive index of at least the fourth region (e.g., one of the BBWG regions). 2  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0009] In some aspects, implementations of the present disclosure include an apparatus, wherein the third region includes an active layer.

[0010] In some aspects, implementations of the present disclosure include an apparatus, wherein the third regions includes a plurality of layers, one of which being an active layer.

[0011] In some aspects, implementations of the present disclosure include an apparatus, further including a buffer layer provided between the lower cladding layer and the substrate.

[0012] In some aspects, implementations of the present disclosure include an apparatus, further including a plurality of buffer layers provided between the substrate and the lower cladding layer.

[0013] In some aspects, implementations of the present disclosure include an apparatus, wherein the upper cladding region includes a plurality of layers.

[0014] In some aspects, implementations of the present disclosure include an apparatus, wherein the lower cladding region includes a plurality of layers.

[0015] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth and fifth regions include a highly resistive material.

[0016] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of the lower cladding region or the upper cladding region, such that a current is confined to a portion of the apparatus between the fourth and fifth regions.

[0017] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth region includes a first cavity and the fifth region includes a second cavity.

[0018] In some aspects, implementations of the present disclosure include an apparatus, wherein an inert gas is included in the first and second cavities.

[0019] In some aspects, implementations of the present disclosure include an apparatus, wherein the inert gas is selected from a group consisting of N2, He, Ar, Xe, and Kr.

[0020] In some aspects, implementations of the present disclosure include an apparatus, wherein at least one of a gas selected from the group consisting of H2, O2, and N2 is included in the first and second cavities.

[0021] In some aspects, implementations of the present disclosure include an apparatus, wherein the highly resistive material includes a dielectric.

[0022] In some aspects, implementations of the present disclosure include an apparatus, wherein the dielectric includes one or more of an oxide of InAlN, InAlGaN, AlGaN, AlN, SiN, Si, or Al. 3  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0023] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth and fifth regions includes material having a bandgap that is greater than a bandgap of the lower cladding region and a bandgap of the upper cladding region.

[0024] In some aspects, implementations of the present disclosure include an apparatus, wherein the material included in the fourth and fifth regions has a resistivity that is greater than a resistivity of the upper and lower cladding regions.

[0025] In some aspects, implementations of the present disclosure include an apparatus, wherein the first and second regions have first and second refractive indices, respective, the fourth and fifth regions have a refractive index that is less than the first and second refractive indices.

[0026] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of upper and lower cladding regions.

[0027] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth and fifth regions have a refractive index that is less than the first and second refractive indices, wherein the lower cladding layer, and the fourth and fifth regions constitute at least part of a waveguide.

[0028] In some aspects, implementations of the present disclosure include an apparatus, further including a buffer layer provided between the lower cladding layer and the substrate.

[0029] In some aspects, implementations of the present disclosure include an apparatus, further including a plurality of buffer layers provided between the substrate and the lower cladding layer.

[0030] In some aspects, implementations of the present disclosure include an apparatus, wherein the upper cladding region includes a plurality of layers.

[0031] In some aspects, implementations of the present disclosure include an apparatus, wherein the lower cladding region includes a plurality of layers.

[0032] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of the lower cladding region and the upper cladding region, such that a current is confined to a portion of the apparatus between the fourth and fifth regions.

[0033] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth region includes a first cavity and the fifth region includes a second cavity. 4  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0034] In some aspects, implementations of the present disclosure include an apparatus, wherein an inert gas is included in the first and second cavities.

[0035] In some aspects, implementations of the present disclosure include an apparatus, wherein the inert gas is selected from a group consisting of He, Ar, and Xe and Kr.

[0036] In some aspects, implementations of the present disclosure include an apparatus, wherein at least one of a gas selected from the group consisting of H2, O2, and N2 is included in the first and second cavities.

[0037] In some aspects, implementations of the present disclosure include an apparatus, wherein the highly resistive material includes a dielectric.

[0038] In some aspects, implementations of the present disclosure include an apparatus, wherein the dielectric includes one or more of an oxide of InAlN, InAlGaN, AlGaN, AlN, SiN, Si, or Al

[0039] In some aspects, implementations of the present disclosure include an apparatus, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of the third region, such that a current is confined to a portion of the apparatus between the fourth and fifth regions.

[0040] In some aspects, implementations of the present disclosure include an apparatus, wherein an interface between the fourth region and the third region constitutes a first heterobarrier and an interface between the fifth region and the third region constitutes a second heterobarrier, such that a current is confined to a portion of the apparatus between the fourth and fifth regions

[0041] In some aspects, implementations of the present disclosure include an apparatus, wherein the apparatus includes a laser.

[0042] In some aspects, implementations of the present disclosure include an apparatus, wherein the apparatus includes a light emitting diode.

[0043] In some aspects, implementations of the present disclosure include an apparatus, wherein the apparatus includes waveguide.

[0044] In some aspects, implementations of the present disclosure include an apparatus, wherein the wafer bonded interface is provided in the first region, the fourth and fifth regions being provided in the first region.

[0045] In some aspects, implementations of the present disclosure include an apparatus, wherein the wafer bonded interface is provided in the second region, wherein the fourth and fifth regions are provided in the second region. 5  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0046] In some aspects, implementations of the present disclosure include an apparatus, wherein the wafer bonded interface is in the third region, wherein the fourth and fifth regions are provided in the third region.

[0047] In some aspects, implementations of the present disclosure include an apparatus, wherein the wafer bonded interface is an interface between the third region and the first region,wherein fourth region extends into the first region and the third region, and the fifth [BBWOG] region extends into the first region and the third region.

[0048] In some aspects, implementations of the present disclosure include an apparatus, wherein the wafer bonded interface is an interface between the third region and the second region, wherein fourth region extends into the second region and the third region, and the fifth region extends into the second region and the third region.

[0049] In some aspects, implementations of the present disclosure include an apparatus, wherein the first, second, and third regions constitute a plurality of layers provided on the substrate, the wafer bonded interface being an interface between first and second ones of the plurality of layers, such that the fourth region and fifth region extend into the first one of the plurality of layers.

[0050] In some aspects, implementations of the present disclosure include an apparatus, including: a substrate; a lower cladding layer of group III-N semiconductors provided on the substrate, the lower cladding layer having a first refractive index; an upper cladding layer provided on the lower cladding layer, the upper cladding layer having a second refractive index and including a plurality of group III-N semiconductor layers, a wafer bonded interface being provided between first and second ones of the plurality of semiconductor layers, the plurality of semiconductor layers including: a first p-type semiconductor layer having a first concentration (p); a second p-type semiconductor layer having a second concentration (p+) greater than the first concentration, the second p-type layer being provided on the first p-type layer; a first n-type semiconductor layer having a first concentration (n+) provided on the second p-type semiconductor layer (p+); and a second n-type layer semiconductor layer having a second concentration (n) less than the first concentration (n+) of first n-type layer, such that the first concentration of the first n-type semiconductor layer (n+) and the second concentration of the second p-type layer (p+) is sufficient to enable tunneling of electrons from the first n- type semiconductor layer (n+) to the second p-type semiconductor layer (p+) when a reverse bias is applied across the first n-type semiconductor layer (n+) and the second p-type semiconductor layer (p+). 6  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0051] In some aspects, implementations of the present disclosure include an apparatus, wherein the first one of the plurality of layers is the second p-type (p+) semiconductor layer and the second one of the plurality of semiconductor layers is the first n-type (n+) semiconductor layer.

[0052] In some aspects, implementations of the present disclosure include an apparatus, wherein the first one of the plurality of layers is the first n-type (n+) semiconductor layer and the second one of the plurality of semiconductor layers is the second n-type (n) semiconductor layer.

[0053] In some aspects, implementations of the present disclosure include an apparatus, wherein the first one of the plurality of layers is the first p-type (p) semiconductor layer and the second one of the plurality of semiconductor layers is the second p-type (p+) semiconductor layer.

[0054] In some aspects, implementations of the present disclosure include an apparatus, further including: a first region adjacent the wafer bonded interface; and a second region provided adjacent the wafer bonded interface, the first region being spaced from the second region, and the first and second regions having a refractive index that is less than the first and second refractive indices , wherein the upper cladding layer, the lower cladding layer, and the first and second regions constitute at least part of a waveguide, such that the first upper and lower cladding regions are operable to confine an optical mode in a first direction and the first and second regions confine the optical mode in a second direction.

[0055] In some aspects, implementations of the present disclosure include an apparatus, wherein the first and second regions extend into the first one of the plurality of semiconductor layers.

[0056] In some aspects, implementations of the present disclosure include an apparatus, wherein the first one of the plurality of semiconductor layers is provided between the second one of the plurality of semiconductor layers and the substrate.

[0057] In some aspects, implementations of the present disclosure include an apparatus, wherein the second one of the plurality of semiconductor layers is provided between the first one of the plurality of semiconductor layers and the substrate.

[0058] In some aspects, implementations of the present disclosure include an apparatus, wherein the first and second regions include a highly resistive material.

[0059] In some aspects, implementations of the present disclosure include an apparatus, wherein the first and second regions have a resistivity that is greater than a resistivity of the 7  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 lower cladding region and the upper cladding region, such that a current is confined to a portion of the apparatus between the first and second regions.

[0060] In some aspects, implementations of the present disclosure include an apparatus, wherein the first region includes a first cavity and the second region includes a second cavity.

[0061] In some aspects, implementations of the present disclosure include an apparatus, wherein an inert gas is included in the first and second cavities.

[0062] In some aspects, implementations of the present disclosure include an apparatus, wherein the inert gas is selected from a group consisting of N2, He, Ar, Xe, and Kr.

[0063] In some aspects, implementations of the present disclosure include an apparatus, wherein at least one of a gas selected from the group consisting of H2, O2, and N2 is included in the first and second cavities.

[0064] In some aspects, implementations of the present disclosure include an apparatus, wherein the highly resistive material includes a dielectric.

[0065] In some aspects, implementations of the present disclosure include an apparatus, wherein the dielectric includes one or more of an oxide of InAln, InAlGaN, AlGaN, AlN, SiN, SiO, SiON, or AlO, or AlON.

[0066] In some aspects, implementations of the present disclosure include an apparatus (e.g., tunnel junction layers include InGaN or InAlGaN), wherein at least one of the first n-type semiconductor layer and the second p-type semiconductor layer includes InGaN or InAlGaN.

[0067] In some aspects, implementations of the present disclosure include an apparatus (e.g., narrow bandgap material at the junction), wherein a bandgap 46, wherein at least one 46, wherein at least one of the first (n+) n-type semiconductor layer and the second (n) n-type semiconductor layer includes a subgroup of layers.

[0068] Other systems, methods, features, and / or advantages will be or may become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and / or advantages be included within this description and be protected by the accompanying claims. BRIEF DESCRIPTION OF DRAWINGS

[0069] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.

[0070] FIG.1 illustrates shallow-etched ridge-waveguides, according to embodiments of the present disclosure. 8  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0071] FIG.2 illustrates an example low-loss waveguide structure, referred to herein as a Buried Bonded Waveguide (BBW), according to embodiments of the present disclosure.

[0072] FIG.3 illustrates an example method for fabricating a BBW waveguide, according to embodiments of the present disclosure.

[0073] FIG.4 illustrates an example fabrication method to fabricate the BBW structure of FIG.2, according to embodiments of the present disclosure.

[0074] FIG.5 illustrates a device fabricated by the method of FIG.4, according to embodiments of the present disclosure.

[0075] FIG.6 illustrates an alternative structure for a BBW waveguide, according to embodiments of the present disclosure.

[0076] FIG.7 illustrates a comparison of an example BBW waveguide according to embodiments of the present disclosure to a shallow-etched ridge-waveguide.

[0077] FIG.8 illustrates a deep-etched surface waveguide, according to embodiments of the present disclosure.

[0078] FIG.9 illustrates a BBW waveguide structure etched into or through a core, according to embodiments of the present disclosure.

[0079] FIG.10 illustrates a comparison of an example BBW waveguide according to embodiments of the present disclosure to a deep-etched ridge-waveguide..

[0080] FIG.11 illustrates a scanning electron microcope (SEM) cross-section of a patterned wafer-bonded free-standing GaN substrate to a free-standing GaN substrate, according to an example embodiment of the present disclosure.

[0081] FIG.12 illustrates an example substrate where airgaps are patterned so that they can be used to form a waveguide patterned across a chip, according to embodiments of the present disclosure.

[0082] FIG.13 illustrates an example method of forming an LCL, waveguide core, InAlN layer, and GaN cap layer on a GaN substrate, according to embodiments of the present disclosure.

[0083] FIG.14 illustrates a composite BBW lateral confining layer including InAlO and an airgap, according to embodiments of the present disclosure.

[0084] FIG.15 illustrates a lower cladding layer, multi-layer waveguide core, and a partial upper cladding layer are grown upon a substrate (with optional buffer layers), according to embodiments of the present disclosure. 9  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0085] FIG.16 illustrates a III-Nitride added upper cladding layer is grown epitaxially or wafer-bonded on top of the partial upper confining layer, according to embodiments of the present disclosure.

[0086] FIG.17 illustrates, an index-guided laser diode, according to embodiments of the present disclosure.

[0087] FIG.18 illustrates an example impurity induced layer disordering (IILD) method, according to embodiments of the present disclosure.

[0088] FIG.19 illustrates an example BBW waveguide structure used in an active device, according to embodiments of the present disclosure.

[0089] FIG.20A illustrates an example current-voltage characteristic for a Ga-face of a GaN wafer that is wafer-bonded to a N-face of a GaN wafer, according to a study of an example embodiment of the present disclosure.

[0090] FIG.20B illustrates an example current-voltage characteristic for a Ga-face of a GaN wafer that is wafer-bonded to a N-face of a GaN wafer, according to a study of an example embodiment of the present disclosure.

[0091] FIG.21 illustrates an example of a BBW active device structure incorporating a tunnel junction, according to embodiments of the present disclosure.

[0092] FIG.22A illustrates an example micro-LED structure, according to embodiments of the present disclosure.

[0093] FIG.22B illustrates an example III-Nitride LED structure, according to embodiments of the present disclosure.

[0094] FIG.23 illustrates an example of a III-N laser transition to a BBW passive waveguide, according to embodiments of the present disclosure.

[0095] FIG.24A illustrates an example cross section of a III-N laser to BBW waveguide structure for an active-passive transition, according to embodiments of the present disclosure.

[0096] FIG.24B illustrates an example cross-section of a III-N laser to BBW waveguide taper for active-passive transition of FIG.24A.

[0097] FIG.25 illustrates coupling efficiency compared to transition length for the ridge laser to BBW transition, according to a study of an example embodiment of the present disclosure.

[0098] FIG.26 illustrates reflection loss at various taper tip widths, according to the example embodiments of the present disclosure. 10  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0099] FIG.27 illustrates measurements of refractive index and absorption coefficient, according to a study of an example embodiment of the present disclosure.

[0100] FIG.28 illustrates a planar view of an active-passive transition for a BBW active laser to a SiN-based waveguide, according to embodiments of the present disclosure.

[0101] FIG.29A illustrates a cross-section of a BBW laser with shallow etched buried ridge, according to embodiments of the present disclosure.

[0102] FIG.29B illustrates a cross section of an example design for a BBW laser, according to embodiments of the present disclosure.

[0103] FIG.30A illustrates a cross section of a structure along length of the transition for a III-N shallow-ridge active to passive waveguide transition, according to embodiments of the present disclosure.

[0104] FIG.30B illustrates an example of a cross section of a structure along length of the transition for a III-N shallow-ridge active to passive waveguide transition, according to embodiments of the present disclosure.

[0105] FIG.31A illustrates an example cross section of a structure along length of the transition for a III-N shallow-ridge active to passive waveguide transition after the mode transfer process is completed, according to embodiments of the present disclosure.

[0106] FIG.31B illustrates an example cross section of a structure along length of the transition for a III-N shallow-ridge active to passive waveguide transition at a region when mode transfer is completed, according to embodiments of the present disclosure.

[0107] FIG.32 illustrates coupling efficiency vs. transition length for the BBW laser to passive waveguide transition example, according to embodiments of the present disclosure.

[0108] FIG.33 illustrates reflection loss at different taper tip widths for the example of Fig.32, according to embodiments of the present disclosure.

[0109] FIG.34 illustrates a view of an active-passive transition, according to embodiments of the present disclosure.

[0110] FIG.35 illustrates a corresponding cross-section for shallow ridge laser structure with disordered regions.

[0111] FIG.36 illustrates a cross section for an IID waveguide, according to embodiments of the present disclosure.

[0112] FIG.37 illustrates insertion loss with various tip taper widths for the structures illustrated in FIGS.34-36, according to a study of an example embodiment of the present disclosure. 11  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0113] FIG.38 illustrates back reflection loss for different tip widths, according to a study of an example embodiment of the present disclosure.

[0114] FIG.39A illustrates a comparison of extinction coefficients for different types of SiN films, according to embodiments of the present disclosure.

[0115] FIG.39B illustrates a SEM cross-section of a deuterated SiN-SiO waveguide according to embodiments of the present disclosure.

[0116] FIG.40 illustrates waveguides of variable lengths configured on a single die with different wavelengths of excitation, according to embodiments of the present disclosure.

[0117] FIG.41 illustrates transmission loss as a function of waveguide length, according to a study of an example embodiment of the present disclosure.

[0118] FIG.42A illustrates an example of a cross-section of an of a deuterated SiN- SiO waveguide, according to a study of an example embodiment of the present disclosure.

[0119] FIG.42B illustrates an example simulated mode-field for a deuterated SiN- SiO waveguide, according to embodiments of the present disclosure.

[0120] FIG.42C illustrates an example plot of insertion loss vs. wavelength, according to embodiments of the present disclosure.

[0121] FIG.43 illustrates a comparison of low-temperature deposited SiNx:D waveguides with state-of-the-art results of high-temperature (HT) deposited SiNx waveguides, according to a study of an example embodiment of the present disclosure.       DETAILED DESCRIPTION

[0122] It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate aspects, can also be provided in combination with a single aspect. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single aspect, can also be provided separately or in any suitable subcombination. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure.

[0123] For all of the figures shown herein, it should be understood that any or all layers may actually represent a series of layers that make up one of the layers, as shown in the figure 12  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 in this writeup. That is, a layer in the figures herein is meant to show a single function or average alloy composition. In practice, several layers may make up these layers to realize this same functionality. For example, a bulk layer shown herein may be replaced with a strained layer superlattice or a singular layer III-N may be replaced by a series of III-N layers. The figures are also meant to be a schematic representation of the general geometry of the device. However, fabrication realities will result in real-world variations, including rounded corners, variations in thicknesses, etc. None of the figures are to scale unless specifically noted (this includes areas that schematically indicate areas of roughness, etc.). When multi-quantum well (MQW) structures are referred to herein, they also cover the variant where the MQW structure only includes one quantum well.

[0124] Scattering loss from the sidewalls of waveguides is a limitation to achieving low loss, especially at shorter wavelengths. The shallow-etched ridge-waveguides shown in Fig.1 can be fabricated with dry-etching. This wafer fabrication process typically results in significant surface roughness (e.g., ~15nm, (Sekiya, Sasaki et al.2015)) on the sidewalls of the waveguide (see Fig. 1). While there is roughness in the field from the etch, the side walls generally are significantly rougher than the field region parallel to the layers (Shah, Azizur Rahman, et al. 2020). In the short wavelength regime (e.g., 200-600nm), this scattering loss can be significant and limits low-loss waveguide performance. As a result, it is desirable to limit the volumetric extent of the sidewall roughness to improve the performance of these short- wavelength devices. In order to achieve such reduction, implementations of the present disclosure include a device structure and fabrication techniques with significantly reduced volumetric roughness along the sidewall of waveguides and waveguide-based devices, and hence, reduced scattering and reduced waveguide loss.

[0125] Example Devices

[0126] Fig. 2 shows an example low-loss waveguide structure also referred to a Buried Bonded Waveguide (BBW) 200. Alternative structures for the BBW waveguide are shown in Figs.5 and 6. The example Buried Bonded Waveguide (BBW) 200 can be formed on a layer of substrate and / or buffers 218.

[0127] Example Device #1. In the example shown in Fig.2, a waveguide structure includes a lower cladding layer (LCL) 208, waveguide core (WG Core) 216, and thin partial upper cladding layer (PUCL) 204 realized using III-Nitride alloys (e.g., InAlGaN). The PUCL layer 204 includes layers or layer stacks. The first is the spacer layer 205, which offsets the BBW lateral confining layers (LaCLs) 210 from the WG core 216. The second is the BBW patterned 13  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 cladding layer (PCL) 212, where the BBW LaCL 210 is formed. Wafer bonding techniques enable the burying LaCLs 210 in the upper confining layer (UCL) 206. These LaCLs 210 serve to confine the light laterally and may be of a limited vertical extent provided they are in sufficient proximity to the waveguide core. In general, this means they can be offset by a spacer layer 205, as shown in Fig.2, but also penetrate partially or fully through the WG Core 216 (as to be described herein). This offset or penetration is such that the lateral effective index step is > 1x 10-3and < 5 x 10-1and, in some cases, is preferably step is > 1x 10-2and < 1 x 10-1. Higher effective index steps (from the LaCL region to the center BBW WG) result in increased confinement but also increased optical scattering the optical mode overlap with etch surface roughness from the fabrication is higher.

[0128] Buried in the upper cladding layer (UCL) 206 is the BBW lateral confining layer (LaCL) 210 that is formed by wafer bonding a bonded upper cladding layer (BUCL) 202. Each of the vertical layers can include multiple III-N layers for a given targeted waveguide or device structure. For waveguide passive devices, the BUCL 202 can be a III-N or other wide bandgap or insulating or dielectric layer, provided it is of sufficiently low index and low optical loss to guide the mode with low-loss. The preferred index may depend on the other layer in the structure but must be less than that of the thickness weighted average of the core waveguide and preferably <2.25, or more and most preferably <2.1, <1.7 and <1.5.

[0129] Materials that can optionally be used for this layer are III-N alloys, including AlGaN and InAlN, but also include porous III-Nitrides of GaN (Huang, Zhang et al. 2013, Zhang, Park et al. 2015), AlGaN (Wang, Hong et al. 2017) and other III-N alloys, and dielectrics such as SiN, SiON, SiO2, AlO, AlON, AlGaON, and InAlGaON as well as ZnO, MgO, ZrO, or GaO. The material may be crystalline, polycrystalline, or amorphous and may be stochiometric or non-stochiometric. The preferred optical loss of the layers is <10-4and more and<10-2or <10-1per cm. The BBW LaCL 210 can be anything that creates a lower refractive index than PUCL and is sufficient for creating the aforementioned lateral index step. This includes air, He, N2, H2, Kr, Ar, Xe, O2, a dielectric or oxide layer including porous III- Nitrides of GaN, AlGaN and other III-N alloys, dielectrics or oxides such as SiN, SiON, SiO2, AlO, AlON, AlGaON, and InAlGaON, as well as ZnO, MgO, ZrO, or GaO, or III-N layers that are crystalline, polycrystalline, or any combination thereof.

[0130] The LaCLs 210 of the BBW waveguide shown in Fig.2 are of finite lateral extent as they may be comprised of air gaps (or gaps filled with other gases). As a result, it is desirable to have the width of these gaps be such that there is no lateral mode leakage, but small enough 14  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 to provide sufficient mechanical integrity and size to be free of adjacent device structures. Thus, the the LaCLs 210 should be greater than >3x and preferably >5x, and most preferably >10x the size of the wavelength of light that the BBW waveguide is guiding. From a mechanical integrity perspective, if the BBW LaCL 210 material contains a gap, it is desirable to be <20^m, and preferably <10^m, and most preferably <5^m. In some implementations, the BBW LaCL may be formed from solid material, hence removing the constraint based on mechanical stability.

[0131] Example Method of Fabrication

[0132] Fig.3 shows an example method for fabricating the BBW waveguide 200. On top of substrate and buffer layers 302 (which can include other device layers) is grown a III-Nitride lower-cladding layer (LCL) 208, and a III-N waveguide core (WG Core) 216, as well as III-N partial upper cladding layer (PUCL) 207 is masked and subsequently patterned to form the BBW lateral confining layers (LaCL)210 in the patterned cladding layers (PCL) 212. One example way of forming the LaCl 210 is by masking the center strip with a dielectric or photoresist and etching (e.g., inductively coupled plasma etching using Cl2 or BCl3). A shallow ridge of limited extent is created in the partial upper cladding layer (PUCL) 207 of the waveguide structure. The limited extent can ensure there is sufficient mechanical strength to support the bonded upper cladding layer 202. Any masking layers for the formation of this area are then removed and subsequently, a bonded upper confining layer 202 on a sacrificial substrate (with optional buffer layers) 302 is wafer-bonded to the partial upper cladding layer (PUCL) 207 to form the resultant BBW lateral confining layers (LaCLs) 210 shown in Fig.2. Subsequently, the sacrificial substrate and any buffer layers 302 (optional) from the top wafer- bonded substrate are removed to realize the structure shown in Fig 2. The substrate to be removed preferably can include Si, SiC, GaN, AlN and / or Al2O3 if III-N crystalline alloys are utilized for the bonded upper cladding layer. However, if any substrate is utilized, alternative layers, as described earlier, can be utilized. In order to facilitate the wafer bonding, it the coefficient of thermal expansion (CTE) of the bottom substrate and sacrificial top substrate can be relatively well-matched (e.g., within 30% of each other).

[0133] The wafer-bonding can be performed by various techniques. For the wafer-bonding of III-N to III-N layers, techniques such as those applied to realize high-performance wafer- bonded AlGaInP LEDs may be preferred (Kish, Steranka et al. 1994) (Kish 1994). Alternatively, and preferably, new techniques that build upon these methods may be utilized, including the newly invented technique of crystal heterogeneous integration (CHI). 15  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 Accordingly, additional ambient gases provide a column V overpressure during the bonding processes. This ambient serves the purpose of preserving the crystalline surface (enabling higher bonding temperatures and lower defect interfaces) and promoting mass-transport and solid-state regrowth during the formation of the wafer-bonded interface. A wide variety of other processes can be utilized for wafer bonding, especially if a III-N alloy is not employed as the bonded upper cladding layer. Some alternate wafer bonding techniques are described in (Kish and Fletcher 1997).

[0134] The sacrificial substrate 302 can optionally be removed for subsequent device processing. A variety of techniques may be used for this, including griding, lapping, polishing, chemical etching, electrochemical etching, photoelectrochemical etching, laser lift-off, implanting plus fracturing, spalling (Bedell, Lauro et al. 2017), and mechanical release using porous III-N layers or any combination thereof. If III-N alloy layers are utilized, it may be preferable to utilize an N+ GaN substrate (e.g., N+ > 1x1019cm-3) that can be electrochemically removed if III-N crystalline epitaxial layers are used for the bonded upper cladding layer. Alternatively, an N+ thin layer (e.g., N+ > 1x1019cm-3, preferably N+ > 5x1019cm-3or most preferably N+ > 1x1020cm-3) or an InGaN layer may enable lateral electrochemical or photoelectrochemical etching for substrate reuse. III-N layers grown epitaxially on Si or sapphire substrates are also preferable as the substrates are low-cost and may be removed by chemical etching (Si and associated III-N buffer layers) or laser-liftoff.

[0135] A feature of the BBW waveguide formation, in some embodiments, is that it enables the formation of structures deep into the device structure (near or through the waveguide core) without having to process through the entire depth of the surface from the finished device structure. This enables the formation of regions with a significantly reduced amount of damage from an etch or oxidation, or in other cases, enables processing at shallow depths (later buried by wafer-bonding or regrowth) that would not be possible if undertaken from the surface (e.g., diffusion or oxidation). In addition, the BBW waveguide structures and processes are performed by shallow planar processing (over thickness of <200nm, and preferably <100nm, and most preferably <50nm), which can enable very precise definition of structures (e.g., 200nm, 100nm or even 50nm) versus thick-film (>0.5^m) processes which make this level of pattern definition extremely challenging. While lateral etching or oxidation has been proposed to achieve these structures, the lateral waveguide width is not very controllable (especially for complex device geometries and waveguide shapes, including curves and partial curves). Also, 16  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 the additional defects that are formed from the etch or oxidation may be significant, such as to substantially limiting the performance of the device. (Megalini, Shenoy et al.2016)

[0136] Example Device #2. An alternative fabrication method to realize the structures shown and described with reference to Fig. 2 is shown in Fig. 4. In this case, the patterned BBW LaCL 210 are formed in the sacrificial substrate 302 side (opposite side of the wafer bond from Fig. 3) by placing the BBW patterned cladding layer (PLC) 212 on the sacrificial substrate 302 side of the wafer-bond. The resultant device structure is shown in Fig. 5, which can be identical to that of Fig. 2, except the wafer-bond is formed on the opposite side of the BBW lateral confining layers 210. It may be advantageous to do this for a number of reasons depending on the BBW waveguide structure, including: the ability to realize improved quality for the PCL, improved flatness of the layers on the sacrificial substrate (for more accurate patterning), and reduction of stress at the wafer-bonded interface.

[0137] Example Device #3. An alternative structure for the BBW waveguide is shown in Fig. 6. In this case, the BBW patterned layers are placed below the substrate in the lower cladding layer 208. The upper cladding layers 206, waveguide core 216, and spacer layers 205 are provided on the sacrificial substrate (and optional buffer layers), which are subsequently removed. The wafer-bond can be placed on either side of the BBW LaCL by analogous techniques to that described in Fig. 3 or Fig. 4. Placing the patterned BBW LaCL below the WG core 216 can be advantageous to facilitate the optical mode transition to device structures that are above the BBW waveguide (to be discussed later herein).

[0138] Experimental Results and Additional Examples

[0139] The advantages of the BBW waveguide (Figs. 2, 5, 6), compared to a shallow- etched surface ridge waveguide (Fig. 1) are shown in Fig. 7, which plots waveguide loss (dB / cm) from scattering versus bend radius for the III-N waveguide structure described below. The loss shows factors in both scattering and radiation (bend) loss. Not included in this analysis is absorption loss for various layers in the heterostructure. No scattering is assumed at the wafer-bonded interface (only at the sidewalls as indicated in Figs.1, 2, 5, and 6). Also shown is the scattering loss for a straight waveguide (indicated on the far-right y-axis). Accordingly, the minimum bend radius at a fixed loss is substantially reduced for the BBW waveguide. For example, for 1 dB of loss, the bend radius of the shallow-etched surface ridge waveguide is 630 ^m compared to 310 ^m for the BBW waveguide. Furthermore, for straight waveguides, the loss is roughly an order of magnitude less for the BBW waveguide. In this example, the device structure includes a waveguide core and cladding layers grown on GaN, using an etched 17  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 ridge to define the lateral index contrast. In this example, the lower cladding layer includes 500 nm of x = 0.1 AlxGa1-xN. The waveguide core includes three quantum wells 3 nm thick each of x=0.1 InxGa 1-xN alternating with two 8 nm barriers of x = 0.08 InxGa1-xN; this construction is sandwiched between two layers of 60 nm thick of x=0.08 InxGa1-xN to complete the waveguide core for this example. The upper cladding layer includes a 30nm layer of GaN spacer followed by a 500 nm x = 0.1 AlxGa1-xN upper cladding layer. The shallow-etched waveguide is etched through the entire 500 nm x=0.1 AlxGa 1-xN upper cladding layer, with the etch stopping above the 30 nm GaN layer. The BBW waveguide is configured such that the wafer-bond is at the GaN spacer and 500nm x=0.1 AlxGa 1-xN upper cladding layer interface. The BBW lateral confining layers are etched 50 nm into the x = 0.1 AlxGa1-xN bonded upper cladding layer. For the simulations, the waveguide width is 3 ^m, and the propagation wavelength is 450 nm.

[0140] Mode simulations were carried out using Synopsys FEMSim. The same grid size was used for all structures, while the domain bounds were altered to ensure the complete field was encompassed for each structure individually. Only the fundamental mode was considered, and only real indices were used to directly compare the structures on bend and sidewall roughness losses. After solving the fundamental mode for a straight segment, a series of bends with radii of curvature from 1500 ^m to 100 ^m were induced using the conformal index method. This transforms the index profile of the grid to emulate a bend. The modal index and extinction coefficient from the straight segment was used as a seed to solve the 1500^m bend; the resulting modal index and extinction coefficient were used to solve the next smaller radius of curvature, and so on, until the sweep was complete. The step size for the radius of curvature was optimized for each structure based on the rate of change of the modal index through the sweep to maintain stable and physical mode solutions. The bend loss for each radius of curvature was calculated using the extinction coefficient for the mode according to Equation 1, as any leakage of the mode was due to the bend. 4^^^^ ൌ [1]

[0141] The sidewall roughnessis the total mode power, Es is the power of the integrated lateral electric field amplitude along a vertical slice through the sidewall region of the structure, ^^ is the root mean square sidewall roughness and nmode, nguide and nclad are the modal index and the vertical average index through 18  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 the waveguide region and the etched region, respectively. This approach is detailed in Deri and Kapon (Deri and Kapon 1991), building on the work of Tien (Tien 1971). A sidewall root mean squared roughness of 15nm was used for all four structures, a representative figure for an ICP etched GaN sidewall (Sekiya, Sasaki et al.2015). The losses at the right and left sidewalls were calculated individually, then added together for the total sidewall loss. 4^^ଶ^^ଶ൫n^௨^ௗ^ െ n ൯nE ^^௪^^^ൌ^^^ௗ ^௨^ௗ^ ^^^ௗ^  ^^ଶE்[2]

[0142] Finally, the the structure, less any

[0143] Deep-etched surface waveguides, as shown in Fig.8, are utilized to obtain a sharper bend radius with lower loss. Accordingly, these deep-etched surface waveguides are etched into and typically through the waveguide core and into the cladding. This results in improved bend loss performance at the tradeoff of increased scattering loss (as the roughened waveguide sidewall has not more overlap with the high-intensity portions of the optical mode). Similarly, the BBW waveguide structure can also be etched into or through the core, as shown in Fig. 9. In Fig. 9, a BBW waveguide structure is shown wherein the BBW lateral confining layers (LaCLs) includes etching through the complete core adjacent to the BBW waveguide. Other variations are also possible wherein the LaCLs are etched partially though the core (not shown). In this case, the wafer-bond may be on either side of the core layer (option 1 or option 2, as shown in Fig. 9) depending on which substrate it is preferential to grow the waveguide core (the remaining or sacrificial substrate) as well as other considerations for integrating additional devices. In the structures shown in Figs. 2, 5, and 6, the BBW lateral confining layers can extend partly into the upper or lower cladding layers, depending on the location of the wafer bond. In this situation, the patterning can penetrate all or part of the core layer.

[0144] Performance. An example of the performance advantages of the BBW waveguide compared to a deep-etched surface ridge waveguide is shown in Fig.10, which plots waveguide loss from scattering and radiation versus waveguide bend radius. In this case the BBW waveguide is partially etched into the core and the upper cladding layer (to be described subsequently). The BBW waveguide shows significantly superior loss over the entire range of bend radii as well as for the straight waveguides by ~10x. In this example, the vertical layer structures for both waveguides are the same as described previously in Fig. 7. The difference is that the deep-etched surface waveguide is etched through the core and into the GaN substrate. 19  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 The BBW waveguide is etched through 30nm of the GaN spacer layer and 45nm of the core. All other parameters are the same as described for Fig.7.

[0145] Prototypes. An exampleintegration of BBW LaCLs is shown in Fig. 11 and 12. Fig. 11 shows a scanning electron microscope (SEM) cross-section of a patterned wafer- bonded free-standing GaN substrate to a free-standing GaN substrate. The patterning is performed by masking the wafer with a patterned SiN layer formed via plasma-enhanced chemical vapor deposition (PECVD) and reactive ion etching (RIE). The wafer is subsequently etched in an inductively coupled plasma (ICP) etcher using Cl2 and BCl3 as the etchant gases. After etching, the SiN is removed by RIE etching, and the patterned wafer is bonded to a GaN substrate by crystal heterogeneous integration (CHI) at 850°C for 0.5h using source gases to generate a column V overpressure in the wafer bonding chamber to preserve the bonding surface. The CHI process, a next-generation form of wafer bonding, enables enhanced bond strength and reduced defects at the bonded interface. The cross-section shown in Fig.11 shows air-gaps that can function as lateral confining layers (LaCLs) in a BBW waveguide structure. This data shows bonding of GaN to GaN, which has no coefficient of thermal expansion (CTE) mismatch. Optionally, bonding to free-standing GaN wafers to GaN on sapphire, and GaN on silicon as well (data not shown) can be performed, demonstrating the CHI process can accommodate significant CTE mismatch in the bonding substates (which may dominate the stress in the wafer-bonded stack).

[0146] Fig.12 shows an additional example of a plan view substrate (~1cm x 1cm) where air-gaps were patterned such that they could be utilized to form a waveguide pattern across a chip. To exemplify this, Fig.12 shows airgaps etched with the cross-section of Fig.11 with a variety of bends with a radius of curvatures varying form 50 ^m to 400 ^m.

[0147] The BBW waveguide lateral confining layers can optionally include an airgap. They also may be filled with other gases including He, N2, H2, Kr, Ar, Xe, O2 or combinations thereof. Alternatively, other materials of lower index than the layer in which they are patterned by may be employed. One way to achieve this is by oxidation of Al-bearing III-N layers (Peart, Wei et al. 2019). One instantiation of this method is shown in Fig. 13 wherein an LCL , waveguide core, InAlN layer, and GaN cap layer are formed on a GaN substrate. The BBW waveguide region is masked with SiN, patterned to expose the InAlN layer, and then subjected to a wet (Peart, Wei et al. 2019) or dry oxidation (Palmese, Xue, et al. 2023). The patterning mask may be left intact during the oxidation if it is sufficiently robust (e.g., SiN instead of photoresist). If the masking material is not robust, then the patterning material must be 20  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 sufficiently robust to not be damaged by the oxidation (or be capable of removing the damage prior to wafer bonding).

[0148] The resultant oxidation transforms the InAlN into a stable, lower index (n~1.5-1.9), electrically insulating InAlO layer with the index depending on the oxidation conditions (Palmese, Xue et al. 2023). InxAl1-xN is an especially interesting alloy for the III-Nitrides as for x~0.17 it is lattice-matched to GaN and provides increased bandgap and lower index than mismatched AlGaN layers can be grown with high quality on GaN substrates. For BBW waveguide structures the InAlN can be grown lattice-matched or lattice mismatched to the underlying III-N layers and subsequently oxidized.

[0149] In addition to the InAlN, InAlGaN may also be employed, provided there is sufficient aluminum. Sufficient Al content is wherein the molar ratio of the Al to the total column III molecules (Al+Ga+In) is > 50%. In this case, the oxidized film can include InAlGaO.

[0150] The oxidation process causes an expansion of the oxidized film (by ~1.25x to ~2.1x) (Palmese, Xue, et al. 2023). As a result, it is necessary to utilize a capping layer so that after the oxidation, the resultant oxide is not thicker than the total height of the BBW waveguide (after removal of the patterning mask layer and any partial removal of the cap layer as well). In the example in Fig.13, GaN is used as the capping layer, albeit other layers can be utilized. For BBW layers that will form part of an active device (to be discussed later), the capping layer should formed of a III-N alloy. Otherwise, the capping layer may be a dielectric or insulator.

[0151] The masking layer used in the example in Fig.13 is SiN, albeit other films can be used to mask the etching process (e.g., SiO2, SiON, etc.). After oxidation, if still in place, the patterning mask layer is removed, and the top of the PUCL is wafer-bonded to Bonded UCL, which is provided on a sacrificial substrate as shown in Fig.14. The substrate and buffer layers are removed (as discussed previously) subsequently to yield the final BBW waveguide structure (not shown).

[0152] The structure shown in Fig. 14 has a composite BBW lateral confining layer including InAlO and an airgap (above it). The use of InAlO in this case can be advantageous because the refractive index step between the BBW waveguide and the lateral confining layers is reduced than that when the LaCL includes 100% of an airgap (or one filled with an aforementioned gas). This lower refractive index difference reduces the scattering loss at the patterned edges of the BBW waveguide. The use of InAlO may also be preferred as it provides an insulating layer above the WG core. This is advantageous if the BBW waveguide is to be 21  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 part of an active device (e.g., laser diode, semiconductor optical amplifier, modulator, photodetector, light-emitting diode).

[0153] As described for the air-gap devices in Figs. 2, 5, and 6, other variants may be employed to realize a BBW with an InAlO or InAlGaO LaCL. Specifically, these variants can include adding a spacer layer between the InAlN and the waveguide core. This spacer layer may not be oxidized and serves to offset the InAlN and InAlO layer from the WG core. Also, InAlN or InAlGaN layers may be deployed on either the original substrate or sacrificial substrate side of the device (by similarly moving the location of the wafer bond). Furthermore, the InAlN layer can be located above or below the waveguide core. It is further noted that in devices where the BBW waveguide is part of an active device, it may be desirable to locate this layer on the n-side of the p-n junction as InAlN and InAlGaN are easier to dope n-type than p-type. An exception to this is for active devices wherein a tunnel-junction is employed in the device (to be discussed later).

[0154] Impurity induced layer disordering (IILD) of the BBW regions. An alternate method to realize the BBW lateral confining layer is by impurity induced layer disordering (IILD) of the BBW regions outside of the center BBW stripe (Guido, Hsieh et al.1987, Guido, Plano et al. 1987, Deppe, Plano et al. 1988, Deppe and Holonyak Jr 1988, Guido and Holonyak 1989, Guido, Major Jr et al.1989, Wu, Hsieh et al.1991, Holonyak 1998). For purposes herein, IILD and IID (impurity induced disordering) are used interchangeably.

[0155] Accordingly, a layer stack of III-V layers may be locally intermixed by diffusion of impurities (n-type or p-type) or defects, as discussed in the aforementioned references. This can be achieved by diffusion from a source at the surface of the layers (solid source or vapor) source, dopants or defects that are grown into the crystalline layers and subsequently diffused, or defects or dopants that are implanted into the layers and subsequently diffused. As a result, a wider bandgap (lower refractive index) region results which can be utilized to confine light as well as carriers for the realization of waveguides (Julien, Swanson et al. 1987) and index- guided laser diodes (Deppe and Holonyak Jr 1988, Major, Guido et al. 1990). Unfortunately, the diffusion of impurities in the III-N requires high temperatures with relatively low diffusion rates making it difficult to either diffuse impurities or defects from the surface or to diffuse defects to enable the diffusion and intermixing of in-grown impurities or defects. For example, even at temperatures of 1100°C for 2h, Si has only been shown to diffuse <0.1^m in p-GaN (Pan, Chi et al. 2004). Similarly, Mg has only been shown to diffuse <0.2^m into GaN at 1100°C (for 5 min)(Itoh, Lu et al.2022). Thus, despite reports of IILD in III-Nitrides (Wierer, 22  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 Allerman, et al. 2010, Allerman, Wierer et al. 2012), the low diffusion rates and high- temperatures required for diffusion in the III-N alloys have made it prohibitive to utilize IILD to realize high-performance index-guided passive waveguides and active laser diodes like have been realized in the III-AsP compounds. Furthermore, the extreme conditions (high temperatures) required for these diffusions risk degrading the crystal quality in the mask regions that would form the waveguide or laser diode stripe.

[0156] For these structures, the waveguide core is buried approximately >0.5^m from the surface of the device, making the diffusion of impurities or defects from the surface impractical in III-Nitrides. The issues can be circumvented by employing a BBW waveguide structure and fabrication method, as shown in Figs.15 and 16. Accordingly, as shown in Fig.15, III-N layers including. The partial upper cladding layer should be <0.2^m thick, preferably <0.1 ^m thick, and most preferably <0.05 ^m thick such that impurities and / or defects can be driven into the WG core from the surface under conditions that do not adversely impact the material under masking region (e.g., <1200 °C, preferably, <1100 °C, and most preferably < 1000°C for times < 24 h, preferably <3 h, and most preferably <1 h). The multi-layer WG core can include of one or more quantum wells, quantum barriers, and additional layers including lighting guiding layers and carrier confining layers (including separate confinement heterostructure layers and carrier blocking layers). The latter can include one or more layers. In an alternate embodiment, the WG core can include a single or small number of bulk-layers. In either case, the bandgap of one or more layers of this waveguide core will be shifted to larger bandgap (lower refractive index) by the IILD process. This is achieved by masking a center BBW waveguide region and then subjecting the crystal to the IILD process. The IILD may be initiated from the surface, from a solid-source (e.g, Si, Ge, Mg, Zn or other p-type or n-type source of impurities) or vapor source (e.g., SiH4, GeH4, Cp2Mg, DEZn, DMZn, or some other gaseous source of impurities). Alternatively, n-type, p-type, or neutral impurities can be implanted into the film (e.g., Si, Ge, S, Se, Mg, Zn, B, Be, C, Ga, N, Al, Ar, Kr, F) to act as a source of impurities or defects.

[0157] Alternatively, in-grown impurities or defects in one or more layers of the WG core or adjacent PUCL or LCL may serve as a source for IILD. The patterned masking can include SiN, SiON, SiO, AlO, AlON or other materials such that it prevents the diffusion of impurities and / or defects under the BBW width. The patterned structure is subsequently subjected to elevated temperatures in an environment including N2and possibly NH3to help maintain a column V overpressure to preserve the exposed crystal regions. In some implementation, an SiO, SiO2, and / or SiON layer can be used outside of the BBW width to promote Ga out- 23  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 diffusion into this layer (and improve the diffusion of impurities or defects into the crystal). After annealing, some or all of the layers outside the BBW width are intermixed, increasing their bandgap and decreasing the refractive index. After completion of this step, the masking layer and any other layers (e.g., SiO2for Ga out-diffusion) are removed, and a III-Nitride added upper cladding layer is grown epitaxially or wafer-bonded on top of the partial upper confining layer as shown in Fig. 16. If epitaxial growth is utilized, the growth may be performed by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or other similar techniques. If wafer-bonding is utilized, any of the aforementioned wafer-bonding techniques may be utilized, albeit CHI is preferred using a column V source. If wafer bonding is utilized, the sacrificial substrate and any optional buffer layers are removed to result in the structure as shown in Fig.16.

[0158] Like the other layers, the added upper confining layer can include one or more III- N layers. This added confining layer, in combination with the partial upper confining layer, provides sufficient thickness in the vertical direction to confine the mode vertically (> 0.4 ^m, preferably > 0.5 ^m, most preferably > 0.6 ^m). While the structure of Fig.16 is for a passive waveguide, an index-guided laser diode may also be realized using this structure as shown in Fig.17. In this case, the partial upper confining layer and the added upper confining layer are doped p-type, and the lower confining layer is doped n-type. The p-n junction is formed within the multi-layer core which adds a separate confinement and / or waveguide region that sandwiches on each side one or more quantum wells and quantum barriers. In addition, an electron-blocking layer is placed on the p-side of the quantum wells. In addition, a contact layer is placed on top of the added confining layer and is doped p+ to facilitate making electrical contacts to the device. In order to confine the current to the center stripe of the device, it may be necessary to form an isolation layer in the device. This can be done with an implant and optional annealing. The implant should extend past the contact and into the added confining layer. It may extend partially through this layer or fully through it. It may also extend into the partial upper cladding layer but should stop short of the WG core. The implant can include atoms to help create insulating regions (e.g., He or N) or other atoms for forming a blocking p- N junction (e.g., n-type implant in the p-type confining layers such as Si, Ge, S, or Se). In a different embodiment as an alternative to the structure shown in Fig. 17, the polarity of the doping can also be reversed for all of the layers wherein each of the p-layers above is swapped with an n-layer and each of the n-layers is swapped with a p-layer (not shown). In this case, for blocking junctions, a p-type implant is preferred such as Zn, Mg, or C. In addition to enabling 24  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 passive BBW waveguides and index-guided lasers, such techniques can be utilized to form a wider-bandgap region at the facet of a laser diode to improve the catastrophic damage limit and device reliability. (Thornton, Burnham, et al. 1987). Accordingly, the same techniques shown in Figs.15-17 can be employed to realize a wider bandgap region at the facet of the laser diode.

[0159] An example IILD technique is shown in Fig. 18, which shows the photoluminescence (PL) spectra of a mutli-quantum well sample before (as-grown) and after IILD (diffused). In this case, the multiple quantum well (MQW) sample was grown using the metalorganic chemical vapor deposition (MOCVD). The epitaxial layers were grown on a 50mm diameter GaN on a sapphire template (~4.5mm-thick GaN template). The growth stack can include 0.5mm of un-intentionally doped (UID) GaN layer, a 20 period of UID 2nm GaN / 2nm InxGa1-xN (x=0.052) strain relief superlattice, a 5-period MQW structure including 14nm GaN quantum barriers and 2.5nm InxGa1-xN (x = 0.17) quantum wells, and a 14nm GaN capping layer. The quantum barriers and the capping layer were doped with Si ~ 1 x 1019cm-3to serve as a dopant source for the IILD. The samples were masked with ~100nm SiN layers deposited by high-temperature (~720°C) low-pressure chemical vapor deposition (LPCVD) that were subsequently patterned by dry-etching. The samples were subsequently annealed for 18 h at a temperature of 975°C in an atmosphere of N2 and NH3. The SiN mask prevents or substantially retards the IILD process, enabling the formation of BBW lateral confining layers with an increased bandgap (shorter wavelength PL) in the unmasked regions compared to the masked regions (which have a PL spectra similar to the as-grown curve of Fig. 18, data not shown). In this example, the IILD impurity (Si) was doped and formed from a grown-in source in the barriers and capping layers. Alternatively, other n-type sources (e.g., Ge, S, Se) can be utilized, as well as p-type sources (e.g., Mg, Zn) or impurities, including C or O. Also, the dopants may be placed in the wells in addition or as an alternative to the barriers, or alternatively, only in capping layers, or alternatively only in layer(s) below the MQW structure. The doping level of the impurity is important as samples with doping of 5 x 1018cm-3 did not exhibit IILD under similar annealing conditions. However, lower doping levels such as these may be more viable at more extreme annealing conditions (time and / or temperature) or when other impurities are employed.

[0160] BBW waveguide active device with a p-n junction. The BBW waveguide structure can also be employed in an active device such as in Fig.19, which shows an exemplary cross- section wherein the BBW waveguide is employed in an active device with a p-n junction. Such a device could be operated as a laser diode, semiconductor optical amplifier, modulator, or 25  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 photodetector. The structure includes an n-type lower cladding layer (LCL), an n-type lower waveguide (WG), an active layer (AL), a p-type upper waveguide (WG) layer, a p-type upper cladding layer (UCL), and a p+ contact layer. The active layer can include single or multiple quantum wells. The upper waveguide layer may be completely p-doped, partially p-doped, or unintentionally doped. An optional electron blocking layer (not shown) may be placed in the active layer after the last barrier or alternatively somewhere between the last quantum well and the p-type upper cladding layer. The BBW waveguide structure is formed in at least one of the lower cladding layers (as shown in Fig.19), lower waveguide (not shown), or active layer (not shown) via the integration of BBW lateral confining layers (BBW LaCLs). The wafer-bond for the BBW may be at the top of or the bottom of the BBW region as described previously and as shown as either Option 1 or Option 2 in Fig.19. This structure is advantageous in that it enables low-scattering loss from the lateral waveguide. Also, for active devices, the BBW lateral confining layers can serve to confine the carriers (in this case, n-type electrons) to the width of the active stripe. Alternative embodiments are also contemplated, where the same structure is utilized with the exception of placing the BBW LaCLs and the wafer-bond in at least one of the p-type upper cladding layer (UCL), upper waveguide (WG), or active layer (AL). These devices can be fabricated as described previously, including using the methods as described in Figs.3, 4, 13, 14, 16.

[0161] As the BBW LaCLs of Fig. 19 are in close vertical proximity to the active layer (<0.25mm, preferably <0.2mm, most preferably <0.1mm), the wafer-bonded interface should be designed and fabricated for not only low optical loss and high mechanical strength but also low resistance electrical conduction. Accordingly, the resistivity of the bonded interface should be < 1x10-3Ω•cm2, and preferably < 1 x 10-4Ω•cm2and most preferably <1 x 10-5Ω•cm2. Low electrical resistance conduction across wafer-bonded interfaces has been previously demonstrated in the III-V alloys containing As and P [see for example, (Kish, Steranka, et al. 1994, Kish, Vanderwater, et al.1995, Kish and Fletcher 1997, Kish Jr.1997)].

[0162] Figs. 20A and 20B each show an example of the low-resistance electrical conduction. These plots show the current-voltage characteristics for wafer-bonded GaN-GaN junctions, with Fig.20a showing the results of a Ga-face of a GaN wafer that is wafer-bonded to a N-face of a GaN wafer, and Fig. 20b showing the results Ga-face of a GaN wafer that is wafer-bonded to a N-face of a GaN wafer. The wafer-bonding technique utilized to form these GaN homojunctions is a Crystal Heterogeneous Integration (CHI), a next-generation form of wafer-bonding wherein the wafers are kept separate to elevated temperatures and column V 26  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 gases are utilized for the benefit of surface preservation and preparation as well as enhancing the solid-state regrowth at the bonded interface. CHI samples for this study were prepared using free-standing n-type GaN substrates with an electron concentration of ~2 x 1018cm-3. Prior to CHI, the substrates were positioned in two orientations: Ga-polar to Ga-polar (Ga-Ga) and Ga- polar to N-polar (Ga-N). In both cases, the substrates were processed in an ambient atmosphere of N2and NH3at a peak wafer-bonding temperature of 800°C for 90min with an applied force of >2MPa. The CHI samples were then lapped and polished using diamond films. A planar Ti / Al contact was deposited on the backside of the samples using electron-beam evaporation. Then, a patterned Ti / Al contact was deposited on the topside of the samples as well. Circles of varying radii were patterned using standard photolithography lift-off techniques. Current- voltage characteristics of the processed CHI samples were measured using a Keithley 2400 Source Measurement Unit. Several circles of varying radii were measured with a vertical current conduction path through the device. Typical current-voltage characteristics of the Ga- Ga (Fig.20a) and Ga-N (Fig. 20b) CHI samples are shown for varying radii dots. Resistance values were calculated by linear regression of the current-voltage data of Fig. 20 with coefficient of determination (R2) >0.99. Resistivity values were extracted from these resistance values using a modified methodology from the Cox-Strack method wherein a term for the wafer-bonded interface was added as shown in Equation [3], which describes the total vertical resistance measured as the series sum of several components (where ^^்is the total resistance, ^^^is the semiconductor spreading resistance, ^^^is the contact resistance, ^^^is the interfacial wafer-bonded resistance, and R0is a geometry-independent series resistance). These components are further decomposed in Eqs.4-6, where ^^ is the radius of the top contact, ^^^is the thickness of the entire sample, ^^^is depth of the wafer-bonded interface from the topcontact, and ^^^ , ^^^ , ^^^ are the semiconductor, contact, and interfacial wafer-bondedresistivities, respectively. Eq. 4 assumes that the current spreads conically at an angle of 45 degrees underneath the top contact (Baliga 2010).  ^^^^ ൌ ^^^^ ^ ^^^^ ^ ^^^^ ^ ^^0[3] ^^ ^^ 4 4 4^ െ1 ^^^ ^^^^^ ^^^^^^^^^^^^^^^^ ^^ [4] [5]  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 ^^ ^^ ൌ^^^^ ^^^^^ ^ ^^^^^2[6]

[0163] The contact and the above method to a bulk (non-wafer-the above method along with the data in Fig.20a and Fig.20b to determine, with a coefficient of determination (R2) >0.99, the interfacial wafer-bonded resistivities (Ri): 9.8 x 10- 5 Ω•cm2for the Ga-Ga wafer-bonded interface (Fig. 20a) and 3.8 x 10-5Ω•cm2for the Ga-N wafer-bonded interface (Fig.20b). Thus, these data indicate that such a low-resistance wafer- bond as prescribed for the inventions herein has been reduced to practice. These results for GaN to GaN wafer-bonded interfaces; however, it should be understood that the wafer-bonded interfaces can utilize other III-N materials for purposes of device design (as described in the designs previously described herein) or to aid in the wafer-bonded process. For wafer-bonding purposes, it can be advantageous to have the III-Nitride wafer-bonded including In-bearing alloys (such as InGaN, InAlN, InAlGaN) on one or both sides of the interface. In the event of wafer-bonding of p-type interfaces (p-type to p-type or p-type to n-type), it may be further desirable to etch lateral trenches outside the lateral extent of the device structures (beyond the extent of the BBW LaCLs) down at least to a depth of the p-type layers after the wafer-bonding (and preferably after subsequent removal of a sacrificial substrate) and then perform high- temperature (> 650 °C, preferably > 700 °C) annealing in an H-free ambient to remove any H incorporated in the films (before or during the wafer bonding process) in order to eliminate or reduce the compensation of p-type carriers by H in the films.

[0164] A benefit of the wafer bonding process is the ability to integrate two different epi- layer stacks that may be difficult to grow in one stack (for reasons of stress, defects, growth conditions or methods, etc.). One such layer stack that can be beneficially integrated using wafer bonding is a tunnel-junction. Reverse-biased tunnel junctions are advantageous in optoelectronic devices for their promise to be able to replace considerable thicknesses of p- type layers in devices, with advantages that can include reduced resistance, improved current spreading, and reduced optical loss (Sugg, Chen et al.1993, Wierer, Evans et al.1997, Wierer, Evans et al.1998, Takeuchi, Kamiyama, et al.2021).

[0165] Fig. 21 shows an embodiment of a BBW active device structure that integrates tunnel junction (TJ) with the BBW structure. The structure includes a substrate (e.g., GaN) plus additional optional buffer layers. Thereon, an n-type lower cladding layer (LCL) is grown, followed by an n-type lower waveguide (WG), an active layer (AL), a p-type upper waveguide 28  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 (WG), and a p-type partial upper cladding layer (UCL). The active layer can include single or multiple quantum wells. The upper waveguide layer can be completely p-doped, partially p- doped or unintentionally doped. An optional electron blocking layer (not shown) may be placed in the active layer after the last barrier or alternatively somewhere between the last quantum well and the p-type partial upper cladding layer. On top of the partial p-type upper cladding layer is grown a tunnel junction including a p+ layer and then a n+ layer. The p+ and n+ layers may be by GaN or other III-N alloys with the doping levels as described in the art (Takeuchi, Kamiyama, et al. 2021). The p+ and n+ layers may be of the same alloy composition or different. The BBW lateral confining layers (BBW LaCLs) may then be formed in this layer stack. Subsequently, an n-type bonded upper cladding layer and n+ contact layer grown on a sacrificial substrate with optional additional layers (not shown in Fig.21) are wafer-bonded to the layer stack at the wafer-bond location shown in Fig. 21. The sacrificial substrate and additional optional layers are subsequently selectively removed as discussed previously in this application. The BBW lateral waveguide structure extends through at least one of the partial upper cladding layer in depth but may also be extended into the upper waveguide (not shown), active layer (not shown), or deeper. The wafer-bond for the BBW may be at the top of or the bottom of the BBW region as described previously (shown at the top in Fig.21). These devices can be fabricated as described previously, including using the methods as described in Figs.3, 4, 13, 14, 16.

[0166] The tunnel junction layers can be located at differing positions relative to the wafer bond depending on the optimal device structure and means of forming the tunnel junction. Specifically, the tunnel junction includes an n-layer, followed by a n+ layer, followed by a p+ layer, followed by a p-layer (referenced from the top of the device of Fig.21). The wafer bond may be located within any of these layers or at the interface between any of these layers. Accordingly, the appropriate layers for the tunnel junction would be grown on top of the partial upper cladding layer or upon the bonded upper cladding layer (on the sacrificial substrate, not shown). For example, as low-resistance conduction has been demonstrated across n-n isotype junction, it may be advantageous to place the wafer bond in the n-layer, in the n+ layers, or at the n / n+ interface. Alternatively, it may be advantageous to form the tunnel junction at the wafer-bonded interface. In this case, the wafer bond would be placed at the n+ / p+ interface. It may also be advantageous to form the tunnel junction in p-type layers, in this case, the wafer bond may be placed in the p+ or p layers or at the p+ / p interface. In any of these cases, it may be desirable to utilize crystal heterogenous integration (CHI) for the wafer-bonding. As the p- 29  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 type materials are located near the wafer-bonded interface, it may be further desirable to etch lateral trenches outside the lateral extent of the device structures (beyond the extent of the BBW LaCLs) down at least to a depth of the p-type layers after the wafer-bonding (and preferably after subsequent removal of a sacrificial substrate) and subsequently perform high-temperature (>650°C, preferably >700°C) annealing in a H-free ambient to remove any H incorporated in the films (before or during the wafer bonding process) in order to eliminate or reduce the compensation of p-type carriers by H in the films.

[0167] The BBW LaCLs and the tunnel-junction can be formed beneath the active layer (in the lower cladding layer) as described previously herein. In this case, the n+ contact layer, upper cladding layer, upper waveguide, active layer, and lower waveguide, and a partial lower waveguide layer would be grown on a sacrificial substrate (e.g., GaN). The bonded lower cladding layer would be grown on the bottom substrate. The tunnel junction could be placed on either of the layers stacks depending on the desirable position of the wafer bond with respect to the tunnel junction layers.

[0168] The structure described in Fig. 21 can be especially advantageous in eliminating significant thickness of p-type cladding layers that have significant optical absorption, thus improving the overall performance (efficiency) of III-N active devices.

[0169] The BBW lateral confining layers disclosed herein have been shown to be ones that enable a change of effective refractive index between the lateral confining region and the adjoining BBW waveguide region. As discussed herein, they may also enable reduced current conduction in this region, enabling current confinement in the BBW waveguide region. Such benefits (higher index of refraction and, or, current confinement) can benefit other devices (e.g., light-emitting diodes (LEDs) or vertical cavity surface-emitting layers). Thus, the techniques and device structures taught herein can also be used beneficially in these devices. In the case of light-emitting diodes, the BBW lateral confining layers can be beneficial in isolating carriers from the edge of an etched mesa defining a micro-LED wherein in the etched mesa that defines the micro-LED is < 30 ^m in diameter. This can be even more important for devices with diameters <10^m, and most important for devices < 4 ^m in diameter. By confining carriers away from the edge of the mesa, such device structures reduce and potentially eliminate the effects of defects and non-radiative recombination at the edge of devices that substantially reduce the device efficiency and reliability. Furthermore, the BBW lateral confining may be fabricated such that the bandgap of the active region in the BBW lateral confining layers is increased. This increase in bandgap can aid in light-extraction of 30  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 these devices. Finally, arrays of these devices (e.g., for displays or high-speed communications) can be more readily fabricated as the aperture that defines the emitting area of the micro-LED can be patterned close to the active region with high precision enabling close patterning from emitter to emitter (e.g., <1^m or even as small as < 0.5 ^m). This is most useful for small aperture devices (e.g., apertures <4^m, even more useful for < 2mm and most useful for <1mm devices). The maximum packing density can be realized when bottom contact is realized by a common ground plane achieved by a widely spaced contact and thick n-type current spreading layers or a conductive bottom substrate.

[0170] The embedded patterning enables a planar or near-planar top surface (e.g., < 0.1 ^m in flatness variation, preferably < 0.05^m, and most preferably < 0.01 ^m) when the devices are fabricating on a conductive substrate. This is advantageous for integration with other elements in the displays (e.g., upstream optics or electronic device drivers wherein the light is output through the bottom of a transparent substrate). Thus, these techniques make possible very small micro-LED arrays of devices with higher density and / or higher fabrication yields.

[0171] MicroLED. Fig. 22a shows an example of a micro-LED structure using the aforementioned device structures and techniques. The device includes a substrate with optional buffer layers. An optional bottom reflector layer, an n-type lower cladding layer, an active layer, a p-type partial upper confining layer, an optional p+ / n+ tunnel junction with an optional n-type partial cladding layer, a wafer-bonded interface, an added upper cladding layer, an optional contact layer, and an optional upper reflector layer. If the optional tunnel junction is included, the upper cladding layer and optional upper contact layer are doped n-type. If the optional tunnel junction is not included, the partial upper cladding layer and the optional upper contact layer are doped n-type. Contacts are made to the upper cladding regions on the top of the device and to the lower cladding layer through an etched trench on the side of the device. To facilitate the contact, therein may be added an optional heavily doped layer (doping concentration >1x1018cm-3, preferably >5 x 1018cm-3, most preferably >1 x 1019cm-3) with a bandgap such that it is transparent to the LED layers. Layers disposed above the wafer-bonded interface are realized on a sacrificial substrate with optional buffer layers (not shown) that is subsequently removed as described previously. The contacts are then added after this substrate removal. The optional upper reflector may be part of the integral device layers (including a III- N alloy) or can be added after the substrate removal and include a transparent dielectric or semiconductor layer stack. The upper reflector layer may be designed around different design principles: (i) where it is reflective and the rest of the design of the LED layers thickness use 31  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 the design principles for resonant cavity LEDs to enhance at least one of: light-output (increased), light-output radiation pattern (narrowed), LED speed (increased), and LED spectrum (narrowed), as discussed in (Ünlü and Strite 1995), (ii) wherein it is reflective and used in conjunction with a bottom light emitting LED, or wherein (iii) wherein this layer is anti-reflective to reduce the reflection at the LED to environment interface. In addition, to confine the current to the central emitting aperture, BBW lateral confining layers are disposed at the edges of the device. These BBW lateral confining layers can include etched cavities and / or oxidized Al-bearing III-N materials using the structures and methods described herein as it is most important to confine the current in these structures, alternate and additional techniques to form the BBW lateral confining layers may be utilized, including the formation of a p-n junction (via diffusion or implantation plus optional diffusion). Furthermore, impurity- induced layer disordering may also be utilized, as described previously. Also, as described previously, the wafer-bonded interface may be located either on the top or bottom of the BBW lateral confining layers. In the case where it is above the BBW lateral confining layers (not shown), the BBW processing (etching, oxidation, diffusion, implantation, IILD, etc.) is performed on the substrate side of the device prior to wafer bonding. In embodiments where the BBW lateral confining layers are formed for current confinement, an IILD region need not penetrate into the active region. Rather it can intermix regions adjacent to the active layer (forming a higher bandgap and / or current-blocking heterojunction or homojunction). Other variations of this device structure are also contemplated. One variant includes removing the tunnel junction (and optional n-type partial upper cladding layer). Another variant utilizes a conductive substrate (and optional conductive buffer layers). In this case the lower-cladding layer contact may be positioned below the substrate. This configuration enables the densest micro-LED display pixels. Another option is to attach the top of the device to a submount or driver (not shown) and have the light exit though the substrate and optional buffer layers, provided they are transparent. Alternatively, the substrate and optional buffer layers may be removed (after affixing the LED or LED array) to a submount or driver by the substrate removal techniques discussed herein.

[0172] In the case wherein the BBW lateral confining layer is achieved by an etched void, it may be desirable that the void does not extend all of the way to the edge of the device to improve the structural integrity of the device. In this case, the outer lateral edge of the BBW lateral confining layer may be inset from the edge of the device along all or only part of the defined mesa. In these cases, it may be desirable to add a current blocking region between the 32  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 mesa and the lateral confining layer (e.g., via an implant prior to wafer bonding). This current blocking region should extend to the edge of the mesa but should be recessed from the inner lateral extent of the BBW lateral confining layer (that defines the LED aperture) by at least 50% of the lateral extent of the BBW lateral confining layer. In some embodiments, the apertures defined by these techniques can be of any shape, including but not limited to circles, ellipses, squares, triangles, and hexagons). When an LED aperture is specified herein, it refers to the smallest cross-sectional length of the device. We note that while we describe herein structures for a micro-LED, they may also be used for LEDs of any dimension.

[0173] It may be desirable to use IILD to define the structure. In that case, Fig.22b shows an alternative III-Nitride LED structure using the designs and method described herein. Accordingly, an optional III-N bottom reflector layer is grown upon a substrate with optional III-N buffer layers. Upon the bottom reflector layer is an n-type III-N lower cladding layer followed by a III-N active region quantum well active region. The active region can include one or more III-N quantum wells. If there are multiple quantum wells, they are separated by III-N quantum barriers. An optional wider bandgap electron blocking layer (EBL) is included in the active region above the light-emitting layers.

[0174] The III-N EBL can include AlGaN or InAlGaN. After the active layer, a partial p- type III-N upper cladding layer is grown. This layer is preferably 10nm-200nm in thickness, most preferably < 100nm in thickness. The growth is terminated at this point, and devices are selectively masked over the active region to preserve the layer structure. The samples are then subjected to conditions to perform IILD in the active region outside of the masked region. This can be accomplished by techniques described previously, including utilizing a SiN masking region and then having impurities diffuse into or within the active region. Those impurities can be n-type, p-type, or isotype. These impurities can be grown into one or more layers in the structure, diffused from the surface (with either a gaseous or solid source), or implanted and then diffused. If the impurities are grown into the LED structure, they are desirable to be grown in the active region (in one or more layers of the active region) or in close proximity (<100nm, preferably <50nm, most preferably < 25nm) into the active region. Preferred placement of these impurities includes in the quantum barriers of the active region, or beneath the active region, using a n-type dopant (e.g., Si or Ge). These source dopant layers are preferably doped > 5 x 1018cm-3, more preferably > 8 x 1018cm-3, and most preferably > 1x1019cm-3. Source dopant layers can optionally be a fraction of an individual layer (e.g., only part of the multi-quantum barrier maybe be doped for IILD). After the IILD process is completed by annealing at 33  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 temperature, the SiN or other mask is stripped, and a p-cladding layer is grown on top of the p-type partial upper cladding layer. This is followed by optional upper contact layers or upper reflector layers as described in the description of Fig. 22(a). The IILD of the active layer is desirable in that it creates a wider bandgap heterobarrier (a heterojunction) laterally to the central LED active layer. This heterobarrier (heterojunction) prevents diffusion of carriers to the edge of the devices where they can combine non-radiatively. Furthermore, the lateral carrier confinement isolates carriers from the edge of the device where process-induced defects can occur in defining the mesa shown in Fig. 22b). Current flow and current injection across defected device perimeters can result in reduced performance (light output) or reliability issues (change in light-output over time). The creation of the lateral confinement by IILD can eliminate or significantly reduce these effects. In addition to creating lateral confinement in and in immediate proximity to the active layer by IILD, it may be desirable to also confine the carriers to the center of the device in one or both of the p-type cladding layer and p-type partial upper cladding layer. In this embodiment, an implant including of N, He, and / or other species can confine currents from the perimeter of the device. The implant can optionally extend to the periphery as shown in Fig.22(b) or can be recessed partially from the edge perimeter (like the BBW LaCLs as shown in Fig. 22(a)). In Fig. 22(a) and Fig. 22(b), new device structures for LEDs are disclosed. However, such structure may also be employed in vertical cavity surface emitting lasers (VCSELs) wherein the IILD or BBW LaCLs serve to provide one or both of index confinement and carrier confinement for the central emission area of the VCSELs.

[0175] The techniques described herein can be utilized to realize a high-performance active passive transition for single lateral mode devices with low insertion loss and low back- reflection from the transition back into the active device. One such transition from a shallow- ridge laser diode (or other active device) to a BBW passive waveguide is shown in Fig. 23. Therein, w^is the laser ridge width, and wଶis the width of the BBW passive waveguide. The solid curve shows the taper structure that is tapering w^down to w^ି^୧୮, while wଶ(dot-curve) is fixed in the whole transition region. The shallow ridge laser structure is employed wherein the ridge in the active region (outside the taper) is etched above the active region (Redaelli, Martens, et al. , Ryu, Ha et al. 2006, Lee, Son, et al. 2008, Castiglia, Malinverni, et al.2021). Thus, the laser or active device's shallow ridge width (w^) should be in the range of 1-2.5^m, preferably 1.25-2^m, a width to enable single-mode operation of the active device (which for laser diodes is greater than the maximum single-mode waveguide width as the overlap with the gain in the stripe selectively prefers the lowest order waveguide mode). The taper is divided 34  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 into two sections by using different ridge etch depths. A shallow ridge is preserved in the beginning of the taper, while a deep ridge is adopted when approaching the end of the taper. Fig. 24(a) shows the corresponding cross-section. In this design, an active structure is wafer- bonded to the top of a BBW at one of two wafer bond interfaces as indicated in the figure. The laser upper confining layer (laser UCL) and laser lower confining layer (laser LCL) provide vertical mode confinement to the laser structure. The multi-quantum well (MQW) layer serves as the active layer of the laser structure. The separate upper and lower confinement heterostructures (SCHs) combined with the MQW serve as the waveguide core of the laser structure. The contact layers facilitate low-resistance contact to contact metals (metallization layers). Two different ridge depths are shown in Fig. 24(a) to illustrate the variation of the cross-section in different sections of the taper structure (see arrows on the left-hand side of the figure). As mentioned in Fig.23, the shallow ridge depth is adopted in the laser structure and the majority of the taper structure, while the deep ridge depth is implemented near the tip of the taper. The shallow etch ridge should terminate above the active region and preferably above the upper laser SCH region. The deep ridge should extend through the active region, and preferably into or completely through the lower laser SCH. In another embodiment, the deep ridge extends into or completely through the laser LCL. At the bottom-half in Fig. 24(a), the cross-section of the BBW is shown. The WG upper confining layer (WG UCL) and WG lower confining layer (WG LCL) provide the vertical confinement of the BBW waveguide. The passive waveguide is formed WG BBW layer and is laterally confined by the buried air gaps. As discussed previously for passive waveguides, the airgaps forming the lateral confinement for the BWW WG may include additional materials (gaseous species and / or lower refractive index thin films). Airgaps with thickness t are introduced at the sides of the BBW to provide lateral confinement. The thickness of the airgap can extend partially or fully through the thickness of the WG BBW layer. It can also extend either into the substrate cladding layer (if wafer bond option 1 is utilized) or into the WG LCL layer (if wafer bond option 2 is utilized). The thickness of the airgap can range from 10-400nm. The widths w^and wଶare defined. A spacer layer (LD to WG Spacer) is inserted to adjust thebetween the laser SCH and the WG layer in order to modify the coupling strength between two structures. The WG substrate cladding serves to prevent launching of substrate mode during the transition process and ensuring efficient mode coupling.

[0176] To achieve the maximum mode transition efficiency, several critical design variables are identified: deep ridge depth, BBW modal index, LD to WG spacer thickness, and 35  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 taper shape. The deep ridge structure ensures efficient tapering of the modal index of the laser mode during the transition process. Specifically, the etch depth needs to reach through the active layer and preferably to are below the lower Laser SCH to ensure sufficient coupling between the laser mode and BBW mode. The BBW modal index is controlled by adjusting the thickness and material composition of the WG UCL / LCL and WG layer. This adjustment ensures that the BBW passive waveguide modal index falls within a specific range, allowing for phase-matching between the laser active device modal index and BBW passive waveguide modal index to be achieved with an acceptable w1െtip. The width of the tip should typically be in the range of 50 – 500 nm, wherein smaller tips provide improved performance with more fabrication challenges, and wider tips have lower performance and eased fabrication tolerances. Generally, dimensions in the 100 - 300 nm provide a reasonable tradeoff between performance and fabrication challenges. The thickness of the LD to WG spacer directly influences the mode overlap between the laser mode and BBW mode, and consequently, the coupling coefficient. Since a larger coupling coefficient requires a smaller w1െtip, the LD to WG spacer must fall within a reasonable range to ensure optimal of transition length and couplingefficiency (0.1 to 0.5um). The taper shape can be any as long as the adiabatic criteria are met through the transition process to ensure maximum transition. The arctan taper shape is preferred as it offers the shortest possibly total transition length with maximum coupling efficiency. The width of the passive waveguide should be that which supports a single-mode. Depending on the design of the BBW waveguide structure and layers, the waveguide width w2 is preferably 1-2^m.

[0177] After configuring all the critical design variables, the mode transition can be achieved as described below. The laser mode is initially launched in the shallow ridge structure through carrier injection and optical recombination in the active device area. As it enters the initial segment of the taper structure, w1begins to taper down, resulting in a reduction of the laser modal index accordingly. When the laser modal index approaches the BBW modal index, mode coupling begins. The system then switches to the deep ridge structure as it approaches the phase-matching point, where maximum mode coupling occurs. After passing the phase- matching point, w1continues to taper down until all the power is completely transferred into the BBW.

[0178] Fig. 24(b) shows an example cross-section of the design for active-passive transition between a ridge laser and BBW of Fig.24(a). This is one design solution using III- N layers. Other designs that meet the aforementioned criteria are also contemplated. For the 36  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 ridge laser structure, an example embodiment uses 2.5 nm x = 0.17 InxGa1-xN and 7 nm GaN to form MQW as the active region, sandwiched by 0.143 um x = 0.076 InxGa1-xN upper and lower laser SCH as WG core layer, 0.505 um x = 0.066 AlxGa1-xN as Laser UCL, and x = 0.066 AlxGa1-xN 0.805 um as Laser LCL. For the BBW waveguide structure, a 0.143 um x = 0.076 InxGa1-xN layer may be used sandwiched by GaN layers to form a symmetric WG structure. The air-gap layer is 0.05 um GaN, and a 1 um x = 0.10 AlxGa1-xN is on the bottom as a WG substrate cladding layer. The width of semiconductor in the air-gap layer is fixed at 2 um. As for the taper structure, the method can include etching down to the lower SCH layer to form a deep ridge structure. The phase-matching condition happens when the ridge is tapered down to 0.35um. The original x=0.066 AlxGa1-xN Laser LCL then serve as the LD to WG spacer, which varies from 0.2um to 0.5um in the analysis.

[0179] The modeling method provided here is based on the coupled mode theory (CMT) for the analysis of super-mode evolution in a given coupled WG system. The shortest adiabatic route is applied by adopting the arctan taper profile that obeys the adiabatic criterion. The 2D mode profiles and the corresponding modal indices are calculated by the finite-element method (FEM), and serve as inputs for the mode coupling matrix to generate the output amplitudes at certain transfer lengths. The allowed range of propagation constant mismatch is determined by the modal indices at the phase-matching point and the case of 0.1 um tip width. The reflection loss is calculated by the residual power in the unwanted WG multiplied by the reflection coefficient at the tip interface.

[0180] Fig.25 shows the coupling efficiency versus transition length for the ridge laser to BBW transition with various thicknesses of LD to WG spacer. The complete mode transfer varies from 29 um to 319 um. The variation is dominantly caused by the strength of the coupling coefficient, which varies with the overlap between the vertical coupled active and passive WGs. Fig. 26 shows the reflection loss at various taper tip widths (w1െtip). In this calculation, the reflection loss is defined at the interface between III-N active and passive WG. In the small tip width region (w1െtip< 0.2 um), the reflection loss is dominantly determined by the residual power in the unwanted mode. For the case with LD to WG spacer = 0.3 um, the stronger coupling results in a more complete transition. In the wide tip width region (w1െtip> 0.35 um), the structure with LD to WG spacer =0.3um requires a larger propagation constant mismatch to achieve maximum transition, which results in a larger reflection loss at the same tip width compared to the case with LD to WG spacer = 0.4um. 37  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0181] An alternative material used for fabricating low-loss waveguides is SiN with SiO2 cladding (or alternatively, SiON can be used for the core and cladding provided the refractive index for these materials is such the ncore> ncladding.While low-pressure chemical vapor deposited (LPCVD) SiN has been demonstrated to yield low-loss waveguides (<1dB / cm) in the violet-blue spectral regime (403-453nm) (Morin, Chang et al. 2021), it requires high- temperature deposition temperature and annealing (typically >750-900°C) which makes its integration prohibitive (e.g. integrating these low loss SiN films with more mature InP-based materials for infrared PICs requires multiple wafer bonding steps (Xiang, Jin et al. 2020)). In contrast, unannealed SiN PECVD films have a high loss due to the presence of the H in the film, which results in significant absorption. In the infrared, SiN-SiON materials under the trademark Hydex using deuterated sources have been shown to enable low-loss waveguides in the infra-red spectrum (<0.1 dB / cm) while being compatible with low-temperature PECVD deposition [(Shih, Yeh et al. 2001, Little 2003, Little, Chu et al. 2008)]. Hydex refers to deuterated films of SiN, SiON, and SiO and it should be understood that embodiments of the present disclosure can be implemented using non-deuterated films of the fabrication process permits (meaning the III-N structures are not degraded to be not useful as a result of the fabrication process). Hydex is an example embodiment as the low-deposition temperature for low optical loss films makes the integration of Hydex films with a wide range of III-N materials possible without degrading the III-N films. Embodiments of the present disclosure include the development of Hydex SiN-SiON capability with low-loss in the visible and ultraviolet spectrum deposited at low temperatures (<400°C). This is advantageous in that these films provide low optical loss in the near ultraviolet and visible spectrum even though they are deposited at lower temperatures with a low thermal budget (<400°C maximum temperature). As a result, these films can be utilized in more sophisticated integration schemes without the added complexity or limitations of high temperature deposited and annealed SiN films.

[0182] Fig. 27 shows measurements of refractive index (n) (Fig. 27 top) and extinction coefficient (k) measured by a spectroscopic ellipsometer with a mean-squared error (MSE) <10% for a variety of different SiN films. The extinction coefficient is converted to the absorption coefficient (^^) (Fig.27 bottom). Shown in Fig.27 is the date for: (i) conventional Silicon Nitride deposited on a Si-wafer with a silane (SiH4) and ammonia (NH3) precursors by LPCVD at 750C (LPCVD-SiN); (ii) a silicon-rich SiN film was deposited using the PECVD tool with the same precursors at 200 °C on a Si substrate (non-deuterated SiN), and (iii) SiN films deposited by PECVD at 200 °C using deuterated sources for Si and N (SiD4 and ND3). 38  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 As seen in Fig. 27, the low-temperature deposited deuterated films have substantially lower loss in the near UV and visible spectrum than conventional non-deuterated films. The deuterated films (also referred to as Hydex films) approach the loss of that of the high- temperature LPCVD films (Fig.27 bottom).

[0183] The low-loss VU spectrum Hydex films used for passive waveguides in combination with a BBW laser structure (e.g., similar to that shown in Figs.19 or 21) enable a low-loss active device to passive waveguide transition.

[0184] Fig.28 illustrates the planar view of the active-passive transition for a BBW active laser to a low-loss Hydex dielectric waveguide. Here, w1represents the width of the BBW laser, and w2is the width of the dielectric waveguide. The taper structure on the left tapers w1down to w1െtipfor mode transfer, while the taper structure on the right tapers w2down to w2െtipto convert a multi-mode waveguide into a single-mode waveguide. This transition utilizes a BBW laser structure. The taper for mode transfer can include two sections with different etch depths (or air-gap thickness), creating a shallow etched buried BBW ridge at the beginning and a deep etched buried BBW ridge towards the end.

[0185] Fig. 29(a) depicts the corresponding cross-section of the BBW laser with the shallow etched buried ridge. The waveguide and active layer are enclosed between the upper confining layer (UCL) and lower confining layer (LCL). Airgaps are introduced into a portion of the LCL layer to offer lateral confinement for the laser mode. As discussed previously for passive waveguides, the airgaps forming the lateral confinement for the BWW WG may include additional materials (gaseous species and / or lower refractive index thin films). A thin highly-doped semiconductor layer (labeled as Bottom LCL) is retained right below the air-gap layer to sustain current injection (n > 5 x 1017cm-3, preferably n > 1 x 1018cm-3, and most preferably n > 5 x 1018cm-3. A substrate cladding layer is implemented to prevent the launching of substrate modes.

[0186] Fig. 30(a) shows the cross-section of the taper structure. In this configuration, the airgap layer extends into the waveguide through deep etching, penetrating further into a portion of the UCL. This extension facilitates efficient mode coupling during mode transfer. Additionally, a Hydex-based SiON dielectric waveguide is deposited on the top of the BBW laser, serving as the target for the mode transfer process. This Hydex SiON waveguide can have a core including SiN, or SiON and a cladding including SiON or SiO2 (provided the index of the core is greater than that of the cladding to result in confinement of the mode and sufficient matching of the waveguide modal index and phase matching of the waveguides as described 39  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 below. The Hydex waveguides are formed at lower temperatures (< 400 °C) from deuterated sources by PECVD or other similar deposition techniques including Plasma Activated Chemical Vapor Deposition (PA CVD) or High-Density (HD) PECVD. The dielectric WG LCL functions as the adjustment layer, enabling the modulation of the coupling strength between the BBW laser and the dielectric waveguide.

[0187] Fig. 31(a) depicts the cross-section of the configuration after the mode transfer process is completed, in which the deep-etching taper structure utilized during the mode transfer has been replaced with the extended LCL of the dielectric waveguide.

[0188] In this configuration, deep ridge depth, dielectric waveguide modal index, thickness of dielectric WG LCL, and taper shape are defined as critical design variables. The deep ridge structure plays a crucial role in ensuring efficient tapering of the modal index of the BBW laser mode during the transition process. Moreover, it helps prevent the creation of parasitic waveguides that could occur at the partial UCL of the BBW laser. Given the substantial variation in modal index during the transfer process (from the III-N laser / active waveguide to the dielectric waveguide), efforts are made to maintain a large modal index in the dielectric waveguide to achieve the phase-matching condition. This is typically achieved by utilizing a large w2, wherein w2is preferably 1.5 – 4 ^m, and preferably 3 – 4 ^m. However, employing a thicker dielectric waveguide can also increase the modal index, albeit at the expense of reduced mode coupling efficiency. The thickness of the core of the dielectric (e.g., SiN) waveguide is preferably 0.1 - 0.5 ^m. The thickness of the dielectric waveguide LCL can be adjusted to fine-tune the coupling strength between the BBW laser mode and the dielectric waveguide mode. It is essential to ensure that the dielectric WG LCL thickness falls within a reasonable range to optimize the transition length and coupling efficiency (for example, up to 0.5 ^m). Since a larger coupling coefficient requires a smaller w1െtip, careful consideration is required in selecting the dielectric WG LCL thickness. The tip width is preferably < 0.3 ^m and most preferably < 0.15 ^m. The taper shape can take on any form as long as it meets the adiabatic criteria throughout the transition process to ensure maximum efficiency. However, the arctan taper shape is preferred due to its ability to provide the shortest possible total transition length while maximizing coupling efficiency.

[0189] The laser mode is initially launched in the BBW laser structure (Fig. 29(a)) from carrier injection in the laser diode / active structure. Upon entering the initial segment of the taper structure, w1gradually tapers down, resulting in a corresponding reduction of the BBW laser modal index. As the BBW laser modal index approaches that of the dielectric waveguide, 40  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 mode coupling initiates. Subsequently, the system transitions to the deep ridge structure (Fig. 30(a)), characterized by a thicker air-gap layer, as it approaches the phase-matching point, where maximum mode coupling occurs. Upon surpassing the phase-matching point, w1continues to taper down until all power is completely transferred into the dielectric waveguide (Fig.31(a)).

[0190] Fig. 29(b) shows an example cross section of the design for a BBW laser to dielectric waveguide transition. For the BBW laser structure, an example embodiment uses three 2.5 nm x = 0.17 InxGa1-xN quantum wells (QWs), each surrounded by 7nm GaN quantum barriers (QBs) to comprise the MQW active region. The MQW active layer is sandwiched by 0.065 um x = 0.076 InxGa1-xN SCH as the waveguide core layer. The UCL can include two layers: a 0.3um GaN on the top of 0.2 um x = 0.066 AlxGa1-xN. The LCL is divided into three layers: a 0.1 um GaN followed by 0.2 um x = 0.066 AlxGa1-xN and 0.1um GaN. The 0.2um x = 0.066 AlxGa1-xN layer also serves as the layer to pattern the air gaps. A porous GaN substrate cladding layer or SiO2layer is placed on the bottom to prevent the mode leakage. The semiconductor aperture at the air-gap layer is fixed at 2um. Fig.30(b) shows an example cross section at the transition region, in which the air gap is extended by etching through all the way to the x=0.066 AlxGa1-xN UCL and etch down to 0.1 um into the x=0.066 AlxGa1-xN UCL layer to form a deep ridge structure. On the top of the active structure, the example embodiment includes a deposit of a 0.2 um ~ 0.5 um Hydex SiON layer, a 3 um x 0.32 um Hydex SiN WG, and covered by 1um Hydex SiON. The deep-ridge structure can be tapered down, and the phase-matching condition happens when the ridge is tapered down to 0.12um. Fig.31(b) shows an example cross section at the region when mode transfer is completed, in which the deep ridge taper structure is replaced by a 0.566 um Hydex SiON.

[0191] An analysis of transition performance based on the aforementioned CMT coupled with 2D FEM simulation was conducted. Fig. 32 presents the coupling efficiency versus transition length for the BBW laser structure to Hydex SiN passive transition with various dielectric waveguide LCL thicknesses. The maximum mode transfer length ranges from 29 μm to 251 μm. Unlike the previous design shown in Figs 23-26, this variation is primarily attributed to the range of allowed propagation constant mismatch, constrained by the modal index and minimum tip width that can be fabricated. Smaller dielectric waveguide LCL thicknesses result in stronger coupling coefficients and necessitate wider propagation constant mismatches to achieve complete transition. Fig. 33 illustrates the reflection loss at different taper tip widths with dielectric waveguide LCL thicknesses of 0.3 μm and 0.4 μm. Once again, 41  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 the reflection loss is primarily influenced by the permitted propagation constant mismatch. With smaller dielectric waveguide LCL thicknesses, the coupling coefficient is stronger, requiring larger propagation constant mismatches to achieve equivalent transition efficiency, subsequently resulting in larger reflection losses.

[0192] The general design principle of coupled mode transition encompasses threeessential points. Firstly, it's crucial to minimize the difference in modal indices (Δn ൌ n୧୬୧^୧ୟ୪ െn^ୟ୰^^^, assume ninitial ^ ntarget) between the two coupled waveguides in the transition structureto within 0.0001%, preferably achieving exact matching. For some examples, initial = the active device and target = the passive waveguide. This condition, known as the phase-matching condition, should ideally be met at a specific point in the taper structure. Moreover, the taperstructure should further decrease Δn and transition to negative values (ninitial ^ ntarget). Thisensures effective decoupling of the modes at the end of the taper, enabling the mode to propagate into the target waveguide. Secondly, it's important that the propagation constants between the two coupled waveguides are closely matched to maximize coupling efficiency. Any disparity in propagation constants introduces limitations, necessitating minimizing the difference between the two coupled waveguides. Thirdly, ensuring smooth mode evolution prevents reflection or dissipation of residual power during the transition, a condition known as the adiabatic criteria. Achieving this requires the geometric variation of the taper structure to be gradual.

[0193] Applying these principles to the ridge laser to BBW transition structure involves several key steps. Initially, in Fig.24(a), the SCH plus MQW active layer is identified as one of the coupled waveguides, while the WG layer in the BBW serves as the target waveguide of the coupled waveguide system. As the shallow ridge tapers down, the laser modal index decreases, ideally matching the BBW modal index at a specific point in the taper, fulfilling the phase-matching condition. Subsequently, further tapering reduces the modal index, ensuring decoupling of the modes, with the mode remaining in the BBW.

[0194] Similarly, the same design principle is applied to the transition structure for a BBW laser to dielectric waveguide. Initially, in Fig. 29(a), the mode is launched at the BBW waveguide + active layer. In Fig.30(a), the dielectric WG core layer is identified as the target waveguide of the coupled waveguide system, and the laser modal index decreases with the reduction of the taper width. Ideally, phase-matching occurs at a specific taper point, followedby further taper width to achieve negative Δn and decouple the waveguides. Despite theintrinsic propagation constant difference in the two waveguides due to the large index 42  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 difference in their core materials, careful taper structure design maximizes transition efficiency within a short transfer length.

[0195] A further alternative active-passive transition can be realized using IILD using the techniques and structures described previously herein (Figs. 15-17 and associated descriptions). Accordingly, IILD is used to shift the bandgap edge of a MQW active region such that it is transparent to the laser wavelength generated and propagated through the active device section. A shallow ridge is used throughout for lateral waveguiding of both the active device (MQW intact) and passive device (MQW disordered). Fig.34 shows the planar view of the active-passive transition using such an IILD scheme. Here, w1represents the IILD aperture, and w2is the width of the shallow laser ridge which is patterned inside the IILD aperture. The dotted curve represents the taper structure, tapering the IILD region w1down to w1െtip, while w2represents the width of the shallow ridge which remains fixed across the entire transition region. The area surrounded by dash lines presents the metal contact area which is deposited cross the transition region to maintain carrier injection into the areas of the active device that have not been disordered, ensuring that the transition structure remains under electrical injection and is non-absorbing. Fig.35 shows the corresponding cross-section for shallow ridge laser structure. In this design, a standard shallow ridge laser structure is employed. The upper confinement layer (UCL) and lower confinement layer (LCL) provide the vertical condiment for the laser mode. The multi-quantum well (MQW) layer serves as the active layer of the laser structure. The separate confinement heterostructure (SCH) serves as the waveguide core of the laser structure. In the region before entering the taper structure, lateral confinement is solely provided from the shallow ridge. This is due to the fact that w1is larger than w2in the laser structure, and the laser mode remains unaffected by the

[0196] Fig.36 shows the corresponding cross-section for the IID waveguide, wherein the disordering region extends throughout the entire active layer, and the IID aperture is closed(w1 ൌ 0). Such IID layer now functions as the core of the waveguide structure. This examplearchitecture can be relatively simple to fabricate (one single shallow ridge used for both active and passive waveguides). Furthermore, the IILD process is a diffusion process, and hence the change in refractive index produced by the disordering process is gradual and not abrupt. As a result, the IILD – non-IILD interfaces should be subject to significantly less scattering than that from an etched ridge.

[0197] The critical design variables in the active-passive transition for the IILD structure are identified as the IILD intermixing completeness (which manifests itself as bandgap shift or 43  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 refractive index change) and the taper length of the transition. The refractive index of the IILD layer is lower than that of the non-IILD layer, resulting in an IILD waveguide mode with less confinement. Furthermore, the index contrast (Δn) induced by the disordering is directly proportional to the reflective loss in the taper. Conversely, since the core region is identical between the IILD laser structure and IILD waveguide structure, the degree of IILD must be sufficiently large to increase the effective bandgap in the MQW and thus avoid band-edge absorption in the IID waveguide. Therefore, the balance of these two design variables is critical to ensure optimal performance. For IILD of an III-N MQW active layer, a wavelength shift of ~5-25nm can result in a refractive index change of ~0.3-1.8 %. For example, the IILD shift in Fig.18 corresponds to a ~1.4% shift refractive index. In order to ensure that the passive region is shifted sufficiently from the band edge IILD active region, it is desirable to have the shift >10nm and most desirable >20nm. This must be balanced with the reflection from the active passive transition which increases with an increasing shift amount of bandgap shift. On the other hand, the predominant loss in the IILD taper structure is the reflection loss, which arises from mode reflection along the taper and at the tip interface. As a result, the taper length is critical to ensure a smooth transition and, consequently, to minimize reflection loss in the taper structure.

[0198] For the IILD active-passive transition architecture, the laser mode is launched within the shallow ridge laser structure (Fig. 35). As it progresses into the initial segment of the taper structure, w1gradually diminishes, leading to a corresponding decrease in the IILD laser modal index.taper extends to the tip (w1െtip), where the IILD laser mode gradually transforms into the IILD waveguide mode with a slightly reduced modal index. Subsequently, the mode propagates within the IID waveguide, as depicted in Fig.36. In this example design, there is no mode coupling process as the waveguide's core remains unchanged throughout the transition. Consequently, mode coupling loss is absent, with reflection loss emerging as the primary loss mechanism. An identical shallow ridge laser structure, as used in the design for active-passive transition between a ridge laser and BBW, is adopted to create the cross-section for the transition structure utilizing IID. The only difference is the introduction of the IILD aperture which is generated by implementing IID to the MQW layer.

[0199] A numerical analysis to evaluate the transition performance employing a combination of beam propagation method (BPM) coupled with 2D FEM simulation for the launching mode profile was conducted. Fig.37 shows the insertion loss with various taper tip widths for the architecture of Figs.34 - 36 for a laser III-N InGaN MQW active region. In this 44  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 example design it is assumed the IILD shift is sufficient so that no band edge absorption occurs. In this case, the insertion loss is primarily dominated by the reflection loss since the IILD waveguide and the laser waveguide share the same waveguide core layer, with one being disordered and the other not. Additionally, since the whole transition tapered structure is under carrier injection by virtue of the larger area planar metal contact overlaying the taper, the absorption loss is negligible. Fig.38 shows the back reflection loss versus different tip widths. The simulation shows the reflection loss remains below 30dB in the region where w1െtip< 0.2um. All the simulations for Figs.37 and 38 assume a refractive index of 1.0% after implementing IILD and a 250 um linear taper.

[0200] Example:

[0201] An example implementation of the present disclosure was designed and tested in astudy. Deuterated silicon nitride (SiN^: D)-silicon oxide (SiO^: D) waveguides grown by low-temperature ( 300∘C ) plasma-enhanced chemical vapor deposition (PECVD) operating in the violet ( 405 nm ) to cyan ( 505 nm ) visible spectrum are demonstrated. The waveguides exhibit low insertion losses ranging from ଷ.ଶ ^^ ^^.଼ ^^ୡ୫ 405 nm^ to ୡ୫ ^505 nm^. The performance of these waveguides is competitive to conventional SiN^waveguides that require significantlyhigher processing temperatures (^ 800∘C). The low-temperature deposition and low loss ofthese waveguides enable advanced heterogeneous integration schemes for visible-spectrum photonic integrated circuits.

[0202] Photonic integrated circuits (PICs) have enabled the exponential scaling of the optical communications network since the introduction of the first electro-absorption modulated laser (EML). [1] Continued innovation in PIC technologies has enabled full optical system-on-chip (SOC) solutions integrating hundreds of functions on a single chip, [2] and1.6 Tb / s transceiver PICs operating at 100Gbaud. ^3^ To date, PICbased opticalcommunications solutions have been primarily developed using InP-based [2] and Si- photonics-based [4,5] technologies for operation in the 1.5 and 1.3^^ m low-loss regimes of optical fibers.

[0203] The development of PIC technology in the visible spectrum offers the potential for significant impacts in quantum information applications, [6] high-performance sensing, [7, 8] and short-distance communications. [9, 10] In particular, many of these applications requirethe utilization of wavelengths in the near ultraviolet (UV)-green spectral regime (365 െ535 nm ). PIC solutions using these wavelengths require the realization of low-losswaveguides for use in functions including routing, splitting / coupling, 45  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 multiplexing / demultiplexing, and highquality factor resonators. Thus far, SiN^-based waveguides have exhibited the highest performance (lowest loss) in the near UV-green spectralregime.

[0011] However, high-temperature processing ( ^ 800∘C deposition and or annealing) isrequired to realize this performance by minimizing the contribution of H -based absorption inthe films (via N െ H and Si െ H stretching vibrations). [12-14] As a result, such SiN^-basedwaveguides are not compatible with the low temperatures required in back-end of line (BEOL) processing of compound semiconductors for the realization of PICs with integrated active and passive devices. These solutions typicallyrequire temperatures ^ 400∘C for compatibility with the host of processes required forfabricating the full suite of active photonic building blocks in an application-relevant solution. Consequently, high-temperature SiN^-based waveguides have been limited to solutions using discrete or hybrid integrated SiN^-based passive PICs

[0015] or in solutions that use complex front-end of line FEOL solutions (e.g., using two wafer-bonding steps).

[0016]

[0204] An alternative to the high-temperature deposited SiN^ష-based waveguides is to useSiN^ (and SiO^ ) deposited from deuterated sources.

[0017] These deuterated films ( SiN^: D andSiO^: D ) can be deposited at low temperatures (^ 300∘C ) and similarly minimize thecontributions of H-complex absorption in the films. [17, 18] Waveguides using thesedeuterated films have been realized in the infrared regime (1550 nm) with losses ^ 0.1 dB / m.

[0019] Furthermore, this platform has realized highperformance ring resonators ^Q ^ 10଼^

[0020] and passive PICs for applications including add / drop multiplexing solutions.ଶ^To date, the deuterated SiN^waveguide and PICs have been focused on infrared wavelengths for optical communication applications. This example includes a demonstration of visible-spectrum violet (405 nm) - cyan (505 nm) waveguides using low-temperature ( 300∘C ) PECVD deuteratedsilicon nitride (SiN^: D ) and deuterated silicon oxide ( SiO^: D ). The resultant highly confinedwaveguides exhibit loss as low as 0.8 dB / cm and are comparable in performance to the best hightemperature SiN^waveguides with similar optical confinement. In addition, the study shows the performance of these waveguides is limited by both scattering and absorption loss and use the resulting model to highlight paths for further improvement.

[0205] SiN^:D films deposited on (100) Si substrates were developed using a PlasmaTherm SLR 720 parallel plate PECVD system. Source gases are 2%SiDସin He and NDଷ, with Nଶgas added to control the plasma and film properties. Gas flows ranged from 900to 950sccmSiD4: He, 5 to 90 sccmNDNଷ, and 200 to 600sccmNNଶ. Chamber pressure wasvaried from 700 to 1200 mTorr. Temperatures from 200 to 340∘C were explored, and plasma 46  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 power was varied from 25 to 125 W. Process conditions were adjusted to co-optimize low optical loss and film stress. The extinction coefficient ( ^^ ) was measured by spectroscopic ellipsometry (J. A. Woollam) and the film stress was measured using scanning-laser bowmeasurements (Frontier Semiconductor FSM 128NT). Film stress was targeted to be 0 െ100MPa compressive. Optimized SiN : D films were grow ∘^ n to a thickness of 103 nm at 300 Cwith an NDଷ: SiDସ flow ratio of 2.78, resulting in a film compressive stress of 66 MPa. Forcomparison, similar parameter variations were used to optimize a nondeuterated SiN^filmusing SiHସ: He and NHଷ, yielding a 102 nm thick film grown at 300∘C with an NHଷ: SiHସ flowratio of 1.22, resulting in a compressive stress of 25 MPa. Finally, for additional comparison, LPCVD SiN^was deposited at 725∘C using an open tube furnace at 32 lm Torr with SiHଶClଶand NHଷ gas flows of 40 and 120 sccm, respectively. Using this NHଷ: SiHଶClଶ ratio of 3, theresultant film was 99.8 nm thick with a tensile stress of 1.2 GPa.

[0206] A comparison of the extinction coefficient ( ^^ ) for each of these SiN^ filmsmeasured using spectroscopic ellipsometry is shown in FIG. 39A. The sensitivity of thespectroscopic ellipsometer used in this work is limited to measurements of ^^ ≳ 1 ൈ 10ି^, andoverestimation of k due to an asymptote as measurements approach the sensitivity limit is a known limitation of ellipsometry for low-k transparent thin films. [22, 23] Nonetheless, theellipsometry data do demonstrate that the absorption of the deuterated SiN^: D film (depositedat 300∘C ) is substantially less than that of the standard PECVD H-based source film (also deposited at 300∘C) as well as the LPCVD SiN^film (deposited at 725∘C ). These advantages are shown by both the metrics of the threshold wavelength where the first non-zero extinction coefficient is measured (referred to herein as onset wavelength) and the magnitude of the extinction coefficient at a given wavelength. This threshold is larger than the measurement capability due to digital accuracy of the monochromator in the ellipsometer. The onset wavelengths for each film are 245 nm for the SiN^: D film, 286 nm for the 725∘C LPCVDfilm, and 428 nm for the SiN^: H PECVD film. The extinction for each film at the onsetwavelength of the SiNx:D at 245 nm is 9.8 ൈ 10ିହ for the SiN : D fi ିଶ^ lm, 2.7 ൈ 10 for theLPCVD film, and 1.98 ൈ 10ି^ for the SiN^: H PECVD film. Thus, the deuterated film has anextinction coefficient two and a half orders of magnitude lower than the LPCVD film and four orders of magnitude compared to the standard PECVD film. The LPCVD and PECVD film performance may be improved through higher-temperature deposition and / or annealing steps;while achieving low-loss, these occur at temperatures ^ 800C and are prohibitive for BEOLprocessing. [14, 24] Furthermore, the deuterated film may be improved through additional 47  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 process optimization. Clearly, deuterated films provide a low-temperature processing option for visible-spectrum waveguides that is useful for active-passive photonic integration applications with similar performance compared to conventional high-temperature LPCVD.

[0207] Waveguides designed for operation in the violet-to-cyan spectral regime (405 െ505 nm ) were fabricated using the deuterated film technology. A scanning electronmicroscope (SEM) cross section of a finished waveguide device is shown in FIG. 39B. The waveguides are fabricated on a (100) Si substrate by first depositing a 2.25^^ m thick lowercladding layer (LCL) including a deuterated film of silicon oxide (SiO ∘^: D) deposited at 300 C.The SiO^: D films were developed using the same range of chamber pressures and powers andresulting films were grown with a 22.1 NଶO: SiDସ ratio resulting in a compressive film stressof 76 MPa. The film exhibited an extinction coefficient of 0 above the lower wavelength measurement limit of the ellipsometer of 192 nm. The real refractive index ranged from1.495 ^405 nm^ to 1.486(505 nm). Chemical-mechanical polishing (CMP) was then performed using 0.02^^ m colloidalsilica, leaving a thickness of 2.1^^ m of SiO^: D remaining. A 103 nm thick SiN^ :D waveguidecore was deposited next after thorough cleaning of polishing contamination. The root meansquare (RMS) roughness of the bottom of the core post-CMP (and pre-deposition of the SiN^: D) was measured to be 0.13 nm using a Digital Instruments atomic force microscope (AFM). As-grown RMS roughness of the SiN^:D core grown on the polished SiO^:D LCL layer was0.20 nm. The real refractive index for the core ranged from 1.864 ^405 nm^ to1.837^505 nm^. Photolithographic patterning using an i-line stepper was used to define the waveguide ridges. Fluorine-based reactive ion etching (RIE) was then used to transfer the pattern into the waveguide core layer with a sidewall angle of 92∘measured by SEM. Thewaveguide core width is 1.5^^ m. The 2.25^^ m thick SiO^: D upper cladding layer (UCL) wasdeposited using the same process conditions as the LCL after organic residue cleaning. SEM inspection showed no evidence of voiding or seams at or around the core-cladding interface and the sidewalls were featureless at SEM magnifications over 100 k. The waveguides are designed to be of various lengths across the chip with a single 90∘bend around the die diagonal to enable variable length measurements on a single die size as shown in FIG. 40. Dies were singulated by sawing. Facets were prepared by edge polishing. Optical microscope inspectionat 500 ൈ showed uniform facet quality across measured waveguides.

[0208] Optical loss measurements were performed using lensed single mode fiber with2^^ m spot size (Coherent S405-XP, Oz Optics) at the input and a horizontally oriented48  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 polarizer in front of a free-space detector (Thorlabs S130VC) at the output, both mounted on motorized positioners with stepper and piezo-actuators arranged at 90∘to each other with an automated alignment algorithm for consistency and repeatability. Single-mode, fiber-coupled, 14-pin butterfly packaged GaN-based lasers with wavelengths of 402,453,492, and 505 nm were used. Input polarization was controlled so that the horizontal to vertical polarized power ratio was 50:1 or greater for each wavelength. Output polarization ratio was approximated by measuring with and without the polarizer at the same coupling position. Each waveguide in the design was tested by maximizing the power passed through the waveguide. FIG.40 shows top- view images of the die and waveguide devices under test at each wavelength tested with fiber- coupled inputs and outputs. A variety of waveguide lengths are fabricated across the chip with right angle turns of radius of curvatures (ROCs) varying from 1 to 4 mm. Turning loss withthis range of ROCs was insignificant across the 402 െ 505 nm wavelength range; the devicesshown in FIG.40 and data selected for FIG.41 are for a 90∘ROC of 1.5 mm.

[0209] Insertion loss (IL) is extracted from the curves of FIG. 41 wherein the slope is IL and the intercept represents the total constant excess loss across waveguides, including facet coupling efficiency and additional insertion loss from the right turn bend (which was negligible). Accordingly, the loss ranges from െ3.2 dB / cm at 402 nm to െ0.8 dB / cm at 505 nm. Per-facet coupling loss (assuming negligible curve loss) ranges from -5.4 dB / facet at 402 nm to -4.5 dB / facet at 505 nm. These coupling losses are expected given the differences in mode-field diameter of the fiber and SiN^waveguides.

[0210] To understand the mechanisms of loss in the SiN^:D-based waveguides, the IL data vs wavelength was fit to a model for interface scattering-induced loss and absorption, ^^^^ ൌ ^^^^ఙ ^ ^^^^ୟ^^ ^1^

[0211] where ^^^^ఙis the loss due to surface roughness, and ^^^^^^^is that due to absorption. The loss induced by surface roughness, ^^^^ఙ, is described by the Payne and Laceyଶହ,ଶ^model per surface as follows: 2Δଶఙ,^ ∗ 0.5 ∗ ^^^ଶ^^ ^^^^ ൌ 4.343^^ଷ^^^^ ^2^core

[0212] where n isof the core, Δn is the modal index contrast withcladding (each squared), and ^^^is the normalized electric field intensity at that interface. The factor of 0.5 adjusts the model to consider only one surface. The expression for ^^ incorporates the exponential autocorrelation function as follows: 49  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 ^ ^^4^^ଶ^^ଶ^ ^ ^^ଶ^ ^ ଶ ଶ^ ^^൨^^ ൌ √2^^^^ଶ^ ^^^^^3^

[0213] of a given core cladding the propagation constants of thesum of the scattering loss at the four corecladding interfaces,

[0214] ^^^^ఙ ൌ ^^^^ఙ^ ^ ^^^^ఙ^ ^ ^^^^ఙ^ ^ ^^^^ఙ್^4^

[0215] where ^^^,^^^,^^௧, and ^^^are the RMS roughness values ^^^^ for each surface of the waveguide core [left (l), right (r)), top (t), and bottom (b)] and ^^^^ఙis evaluated at the respective normalized electric field intensities at each surface ^^^,^^^,^^௧, and ^^^. The values for ^^ and ^^^measured by AFM were used for top and bottom surfaces. The definition of terms for the roughness of each core-cladding interface is illustrated in FIG.42A.

[0216] A finite-element method (FEM) field solver was used to calculate the two- dimensional transverse electric field profile of the fundamental mode and extract the field intensities for each surface separately. The simulated mode-field is illustrated in FIG.42B with an overlay of the core location (black rectangular outline). While the roughness of the top andbottom is low (^^௧ ൌ 0.2 and ^^^ ൌ 0.13 nm), the field strength is much higher there due to thevertically compressed mode, so the model includes contributions from roughness at these interfaces. Only the fundamental transverse mode is considered. This is consistent with simulations that show that the fundamental TE mode ^^^^^^^ is excited by two orders of magnitude more than TM or higher- order TE modes, and there is no coupling between TE^and TM and other higher-order TE modes even in bending segments. The fundamental TM modal index is 3.6% lower than that of the fundamental TE mode, which is too significant to meet the phase matching condition, making coupling between these modes prohibitive. This is further confirmed by experimental data that show the fundamental TE mode dominates the transmitted power (50:1). Further, TM and higher-order TE mode contributions, while expected to be small due to higher loss from larger sidewall overlap, are incorporated into the measurements as an overestimate of the insertion loss for the fundamental mode.

[0217] Absorption loss ^^^^^^^was determined by fitting a band fluctuations model

[0027] to the ellipsometry measurement, 50  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 ^^ ^^^^^^^ ൌ 4.343 ^ℏ^^^^ଶℐୡ^ ^^^൫ℏ^^ െ ^^^൯^ ^5^

[0218] where ^^^is a constant, ^^ dimensionless joint densityof states ℐ ^^^^ ൌ െగLi ^െ^^௭^, ℏ^^௩ସଶ ^ and ^^^ is the bandgapenergy. This model is valid through both the high absorption regime as well as the sub-gap Urbach regime.ଶଷ,ଶ^Absorption due to the cladding is neglected based on ellipsometry results and the larger bandgap of SiOଶ. Absorption by the Si substrate is not considered as the simulated magnitude of the field in the substrate is negligible due to the high-confinement waveguide design.

[0219] Non-linear least squares fitting was used to fit Eq. (5) to find an Urbach slope ^^^^ of 8.8 eV and bandgap ൫E^൯ of 5.2 eV , which were then used to fit the sidewall roughness ( ^^side) of 11.5 nm and autocorrelation length ^^^^^ of 82 nm using Eq. (1). While the fitted E^is high compared to reported PECVD SiN^: H bandgaps with similar ammonia flows(waveguide core ND3 / (ND3+SiD4) flow of 73.5%), the low index of the resulting film is consistent with this value. [28-30] FIG.42C shows a fit to the measured IL data as well as the components of absorption and scattering loss. In the short wavelength regime (200-245 nm), IL experimental data (red dotted line) are derived from the ellipsometry data of FIG. 39A. Mean absolute error for the fit for the waveguide IL data is 0.35 dB / cm. These data show scattering loss as the dominant loss mechanism throughout the tested wavelength range and suggest these SiNx:D waveguides may remain scattering dominated as far into the UV as 300 nm.

[0220] The loss of SiN^-based waveguides is highly dependent on the modal confinement of the waveguide structure. While these results do not represent the absolute lowest loss reported for a SiN^-based waveguide, they are competitive with high-temperature (HT) deposited waveguides by LPCVD of similar modal confinement.

[0023] FIG. 43 shows datacomparing the low-temperature (LT) deposited SiN^: D waveguides with state-of-the-artresults of high-temperature (HT) deposited SiN^waveguides for both low-confinement (2Dconfinement factor Γ ൌ 0.065^^^ and high-confinement ( 2 D confinement factor Γ ൌ 0.92^

[0023] designs. As shown in FIG. 5, the data for the LT deposited deuterated waveguides (2Dconfinement factor Γ ൌ 0.47 ) show a similar loss to the high-confinement LPCVDwaveguides in the 450 െ 505 nm regime. The deuterated waveguides have a similar trendwith wavelength as the low-confinement LPCVD waveguides (indicating they are both largely limited by scattering). 51  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01

[0221] Using the loss model to draw useful guidance for pursuing sub1 dB / cm losses at 405 nm, the example herein first looks to the dominant source of scattering loss. Top andbottom roughness accounts for 27% of the scattering loss for the SiN^: D waveguidesmeasured at 405 nm, suggesting that improvements to sidewall pattern definition processes (lithography and etching) will be most impactful. At 405 nm, the model predicts sub- 1 dB / cmlosses for sidewall roughness less than 4.9 nm with the same top and bottom roughness ( Γ ൌ0.47 ), a reasonable goal relative to other reports. [11, 23] Absorption loss is1.3 ൈ 10ିସ dB / cm at 405 nm. Thus, we believe sub- 1 dB / cm losses down to 405 nm arepossible in high confinement ^Γ ^ 0.95^SiN^: D waveguides with fabrication processimprovements in roughness. Low stress films make the technique scalable to multiple vertically coupled waveguide layers integrated with compound semiconductor actives (e.g., using III-N alloys). SiN^:D is therefore a low-loss, BEOL-compatible waveguide platform.

[0222] Discussion

[0223] Conventional SiN waveguide platforms have been limited to discrete platforms, hybrid integration, or very complex integration schemes due to the high-temperature process requirements to realize low-loss waveguides. The study shows a demonstration of deuteratedSiN^ െ SiO^ waveguides in the visible spectrum (405 െ 505 nm) deposited by PECVD at aBEOL-compatible temperature of 300∘C. Scattering loss-dominated waveguide devices are achieved that are comparable to the state-of-the-art high-temperature-deposited LPCVD waveguides with similar modal confinement. The deuterated SiN^waveguide platform offers the capability to realize PICs in the violet to cyan spectrum with heterogeneously integrated III-N actives and SiN^:D passive waveguides.

[0224] While the methods and systems have been described in connection with certain embodiments and specific examples, it is not intended that the scope be limited to the particular embodiments set forth, as the embodiments herein are intended in all respects to be illustrative rather than restrictive.

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Claims

Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 What is claimed is:

1. An apparatus, including: a substrate; a first region provided on the substrate, the first region being a lower cladding region including a first Group-III-nitride semiconductor; a second region provided on the first region, the second region being an upper cladding region including a second Group-III-nitride semiconductor; a third region provided between the first and second regions, the third region including a third Group-III-nitride semiconductor; a wafer bonded interface provided above the substrate; a fourth region provided above the substrate; and a fifth region provided above the substrate, the fourth region being spaced from the fifth region, such that an optical mode is confined to a confinement region defined by the upper and lower cladding regions in a first direction and the fourth and fifth regions in a second direction.

2. The apparatus of claim 1, wherein the first direction that the optical mode is confined is a lateral direction.

3. The apparatus of claim 1, wherein a refractive index of confinement region is different than a refractive index of at least the fourth region.

4. The apparatus of claim 1, wherein the third region includes an active layer.

5. The apparatus of claim 1, wherein the third regions includes a plurality of layers, one of which being an active layer.

6. The apparatus of claim 4, further including a buffer layer provided between the lower cladding layer and the substrate.

7. The apparatus of claim 4, further including a plurality of buffer layers provided between the substrate and the lower cladding layer. 60  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 8. The apparatus of claim 4, wherein the upper cladding region includes a plurality of layers.

9. The apparatus of claim 4, wherein the lower cladding region includes a plurality of layers.

10. The apparatus of claim 4, wherein the fourth and fifth regions include a highly resistive material.

11. The apparatus of claim 4, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of the lower cladding region or the upper cladding region, such that a current is confined to a portion of the apparatus between the fourth and fifth regions.

12. The apparatus of claim 4, wherein the fourth region includes a first cavity and the fifth region includes a second cavity.

13. The apparatus of claim 4, wherein an inert gas is included in the first and second cavities.

14. The apparatus of claim 13, wherein the inert gas is selected from a group consisting of N2 , He, Ar, Xe, and Kr.

15. The apparatus of claim 12, wherein at least one of a gas selected from the group consisting of H2, O2, and N2 is included in the first and second cavities.

16. The apparatus of claim 10, wherein the highly resistive material includes a dielectric.

17. The apparatus of claim 16, wherein the dielectric includes one or more of an oxide of InAlN, InAlGaN, AlGaN, AlN, SiN, Si, , or Al.

18. The apparatus of claim 4, wherein the the fourth and fifth regions includes material having a bandgap that is greater than a bandgap of the lower cladding region and a bandgap of the upper cladding region. 61  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 19. The apparatus of claim 18, wherein the material included in the fourth and fifth regions has a resistivity that is greater than a resistivity of the upper and lower cladding regions.

20. The apparatus of claim 1, wherein the first and second regions have first and second refractive indices, respective, the fourth and fifth regions have a refractive index that is less than the first and second refractive indices.

21. The apparatus of claim 20, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of upper and lower cladding regions.

22. The apparatus of claim 1, wherein the fourth and fifth regions have a refractive index that is less than the first and second refractive indices, wherein the lower cladding layer, and the fourth and fifth regions constitute at least part of a waveguide.

23. The apparatus of claim 1, further comprising a buffer layer provided between the lower cladding layer and the substrate.

24. The apparatus of claim 1, further including a plurality of buffer layers provided between the substrate and the lower cladding layer.

25. The apparatus of claim 1, wherein the upper cladding region includes a plurality of layers.

26. The apparatus of claim 1, wherein the lower cladding region includes a plurality of layers.

27. The apparatus of claim 22, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of the lower cladding region and the upper cladding region, such that a current is confined to a portion of the apparatus between the fourth and fifth regions. 62  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 28. The apparatus of claim 22, wherein the fourth region includes a first cavity and the fifth region includes a second cavity.

29. The apparatus of claim 22, wherein an inert gas is included in the first and second cavities.

30. The apparatus of claim 29, wherein the inert gas is selected from a group consisting of He, Ar, and Xe and Kr.

31. The apparatus of claim 28, wherein at least one of a gas selected from the group consisting of H2, O2, and N2 is included in the first and second cavities.

32. The apparatus of claim 10, wherein the highly resistive material includes a dielectric.

33. The apparatus of claim 32, wherein the dielectric includes one or more of an oxide of InAlN, InAlGaN, AlGaN, AlN, SiN, Si, or Al 34. The apparatus of claim 1, wherein the fourth and fifth regions have a resistivity that is greater than a resistivity of the third region, such that a current is confined to a portion of the apparatus between the fourth and fifth regions.

35. The apparatus of claim 1, wherein an interface between the fourth region and the third region constitutes a first heterobarrier and an interface between the fifth region and the third region constitutes a second heterobarrier, such that a current is confined to a portion of the apparatus between the fourth and fifth regions 36. The apparatus of claim 21, wherein the apparatus includes a laser.

37. The apparatus of claim 4, wherein the apparatus includes a light emitting diode.

38. The apparatus of claim 21, wherein the apparatus includes waveguide. 63  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 39. The apparatus of claim 1, wherein the wafer bonded interface is provided in the first region, the fourth and fifth regions being provided in the first region.

40. The apparatus of claim 1, wherein the wafer bonded interface is provided in the second region, wherein the fourth and fifth regions are provided in the second region.

41. The apparatus of claim 4, wherein the wafer bonded interface is in the third region, wherein the fourth and fifth regions are provided in the third region.

42. The apparatus of claim 4, wherein the wafer bonded interface is an interface between the third region and the first region, wherein fourth region extends into the first region and the third region, and the fifth BBWOG region extends into the first region and the third region.

43. The apparatus of claim 4, wherein the wafer bonded interface is an interface between the third region and the second region, wherein fourth region extends into the second region and the third region, and the fifth region extends into the second region and the third region.

44. The apparatus of claim 1, wherein the first, second, and third regions constitute a plurality of layers provided on the substrate, the wafer bonded interface being an interface between first and second ones of the plurality of layers, such that the fourth region and fifth region extend into the first one of the plurality of layers.

45. An apparatus, including: a substrate; a lower cladding layer of group III-N semiconductors provided on the substrate, the lower cladding layer having a first refractive index; an upper cladding layer provided on the lower cladding layer, the upper cladding layer having a second refractive index and including a plurality of group III-N semiconductor layers, a wafer bonded interface being provided between first and second ones of the plurality of semiconductor layers, the plurality of semiconductor layers including: a first p-type semiconductor layer having a first concentration (p); 64  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 a second p-type semiconductor layer having a second concentration (p+) greater than the first concentration, the second p-type layer being provided on the first p-type layer; a first n-type semiconductor layer having a first concentration (n+) provided on the second p-type semiconductor layer (p+); and a second n-type layer semiconductor layer having a second concentration (n) less than the first concentration (n+) of first n-type layer, such that the first concentration of the first n- type semiconductor layer (n+) and the second concentration of the second p-type layer (p+) is sufficient to enable tunneling of electrons from the first n-type semiconductor layer (n+) to the second p-type semiconductor layer (p+) when a reverse bias is applied across the first n- type semiconductor layer (n+) and the second p-type semiconductor layer (p+).

46. The apparatus of claim 45, wherein the first one of the plurality of layers is the second p-type (p+) semiconductor layer and the second one of the plurality of semiconductor layers is the first n-type (n+) semiconductor layer.

47. The apparatus of claim 45, wherein the first one of the plurality of layers is the first n- type (n+) semiconductor layer and the second one of the plurality of semiconductor layers is the second n-type (n) semiconductor layer.

48. The apparatus of claim 45, wherein the first one of the plurality of layers is the first p- type (p) semiconductor layer and the second one of the plurality of semiconductor layers is the second p-type (p+) semiconductor layer.

49. An apparatus in accordance with claim 45, further including: a first region adjacent the wafer bonded interface; and a second region provided adjacent the wafer bonded interface, the first region being spaced from the second region, and the first and second regions having a refractive index that is less than the first and second refractive indices , wherein the upper cladding layer, the lower cladding layer, and the first and second regions constitute at least part of a waveguide, such that the first upper and lower cladding regions are operable to confine an optical mode in a first direction and the first and second regions confine the optical mode in a second direction. 65  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 50. The apparatus of claim 49, wherein the first and second regions extend into the first one of the plurality of semiconductor layers.

51. The apparatus of claim 50, wherein the first one of the plurality of semiconductor layers is provided between the second one of the plurality of semiconductor layers and the substrate.

52. The apparatus of claim 50, wherein the second one of the plurality of semiconductor layers is provided between the first one of the plurality of semiconductor layers and the substrate.

53. The apparatus of claim 49, wherein the first and second regions include a highly resistive material.

54. The apparatus of claim 49, wherein the first and second regions have a resistivity that is greater than a resistivity of the lower cladding region and the upper cladding region, such that a current is confined to a portion of the apparatus between the first and second regions.

55. The apparatus of claim 49, wherein the first region includes a first cavity and the second region includes a second cavity.

56. The apparatus of claim 55, wherein an inert gas is included in the first and second cavities.

57. The apparatus of claim 56, wherein the inert gas is selected from a group consisting of N2, He, Ar, Xe, and Kr.

58. The apparatus of claim 55, wherein at least one of a gas selected from the group consisting of H2, O2, and N2 is included in the first and second cavities.

59. The apparatus of claim 53, wherein the highly resistive material includes a dielectric. 66  Attorney Docket No.10620-151WO1 NCSU No.2024-186-01 60. The apparatus of claim 59, wherein the dielectric includes one or more of an oxide of InAln, InAlGaN, AlGaN, AlN, SiN, SiO, SiON, or AlO, or AlON.

61. The apparatus of claim 45, wherein at least one of the first n-type semiconductor layer and the second p-type semiconductor layer includes InGaN or InAlGaN.

62. The apparatus of claim 45, wherein a bandgap of the first (n+) n-type semiconductor layer and a bandgap of the second (p+) p-type semiconductor layer are less than a bandgap of the second (n) n-type semiconductor layer and a bandgap of the first (p) p-type semiconductor layer.

63. The apparatus of claim 46, wherein at least one of the first (p) p-type semiconductor layer and the second (p+) p-type semiconductor layer includes a subgroup of layers.

64. The apparatus of claim 46, wherein at least one of the first (n+) n-type semiconductor layer and the second (n) n-type semiconductor layer includes a subgroup of layers. 67

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