Pixel circuit and driving method therefor, and display panel

Abstract

A pixel circuit (10) and a driving method therefor, and a display panel (1000). In the pixel circuit (10), a second electrode of a first light-emitting element (D1) is electrically connected to a first electrode of a second light-emitting element (D2), a first electrode of the first light-emitting element (D1) receives a first power supply voltage (VDD), and a second electrode of the second light-emitting element (D2) receives a second power supply voltage (VSS); the first light-emitting element (D1) and the second light-emitting element (D2) emit light of different colors; a first gating sub-circuit (201) is connected to the first light-emitting element (D1) in parallel, and determines, in response to a first gating signal (DA) applied to a driving end of the first gating sub-circuit (201), whether a first end and a second end of the first gating sub-circuit (201) are connected by means of the first gating sub-circuit (201) and whether a driving current flows through the first light-emitting element (D1); and a second gating sub-circuit (202) is connected to the second light-emitting element (D2) in parallel, and determines, in response to a second gating signal (DB) applied to a driving end of the second gating sub-circuit (202), whether a first end and a second end of the second gating sub-circuit (202) are connected by means of the second gating sub-circuit (202) and whether the driving current flows through the second light-emitting element (D2).

Description

Pixel circuit, driving method thereof and display panel TECHNICAL FIELD

[0001] The present disclosure relates to a pixel circuit, a driving method thereof and a display panel. BACKGROUND

[0002] An organic light emitting diode (OLED) display device has gradually attracted widespread attention due to its wide viewing angle, high contrast, fast response speed, and higher luminous brightness and lower driving voltage than inorganic light emitting display devices. Due to the above characteristics, the organic light emitting diode (OLED) can be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, and instruments.

[0003] The pixel circuit in the OLED display device generally adopts a matrix driving mode, and is divided into active matrix (AM) driving and passive matrix (PM) driving according to whether a switching component is introduced in each pixel unit. Although PMOLED has a simple process and low cost, it cannot meet the needs of high-resolution large-size display due to cross crosstalk, high power consumption, low life, and other shortcomings. In contrast, AMOLED integrates a group of thin film transistors and storage capacitors in the pixel circuit of each pixel, and controls the current flowing through the OLED by driving and controlling the thin film transistors and storage capacitors, so that the OLED emits light as needed. Compared with PMOLED, AMOLED requires less driving current, has low power consumption, and has a longer life, and can meet the needs of high-resolution multi-gray large-size display. At the same time, AMOLED has obvious advantages in viewing angle, color restoration, power consumption, and response time, and is suitable for high-information-content, high-resolution display devices.

[0004] With the progress of display technology, improving the resolution and aperture ratio of the OLED display device is of great significance to improve the display quality and greatly improve the user's experience.

[0005] SUMMARY

[0006] In at least one embodiment of the present disclosure, a pixel circuit is provided. The pixel circuit includes a first sub-pixel circuit, a first gating sub-circuit and a second gating sub-circuit. The first sub-pixel circuit includes a first driving sub-circuit, a first light emitting element and a second light emitting element. The first driving sub-circuit is configured to control a size of a driving current flowing through the first light emitting element or a size of a driving current flowing through the second light emitting element. A second electrode of the first light emitting element and a first electrode of the second light emitting element are electrically connected. The first electrode of the first light emitting element is configured to receive a first power voltage. A second electrode of the second light emitting element is configured to receive a second power voltage. The first light emitting element and the second light emitting element have different light emitting colors. The first gating sub-circuit is connected in parallel with the first light emitting element. The first gating sub-circuit is configured to determine whether a first end and a second end of the first gating sub-circuit are conducted through the first gating sub-circuit and whether the driving current flows through the first light emitting element in response to a first gate signal applied to a driving end of the first gating sub-circuit. The second gating sub-circuit is connected in parallel with the second light emitting element. The second gating sub-circuit is configured to determine whether a first end and a second end of the second gating sub-circuit are conducted through the second gating sub-circuit and whether the driving current flows through the second light emitting element in response to a second gate signal applied to a driving end of the second gating sub-circuit.

[0007] For example, in the pixel circuit provided by an embodiment of the present disclosure, the first end of the first gating sub-circuit is electrically connected with the first electrode of the first light emitting element. The second end of the first gating sub-circuit, the second electrode of the first light emitting element, the first electrode of the second light emitting element and the first end of the second gating sub-circuit are electrically connected to a first node. The second end of the second gating sub-circuit is electrically connected with the second electrode of the second light emitting element.

[0008] For example, the pixel circuit provided by an embodiment of the present disclosure further includes: a first gate control sub-circuit and a second gate control sub-circuit. The first gate control sub-circuit is configured to apply the first gate signal to the driving end of the first gate sub-circuit in response to a first gate control signal applied to the control end of the first gate control sub-circuit, the driving end of the first gate control sub-circuit being electrically connected to the first gate control end to receive the first gate control signal, the first end of the first gate control sub-circuit being connected to the first gate signal end to receive the first gate signal, and the second end of the first gate control sub-circuit being electrically connected to the driving end of the first gate sub-circuit. The second gate control sub-circuit is configured to apply the second gate signal to the driving end of the second gate sub-circuit in response to a second gate control signal applied to the control end of the second gate control sub-circuit, the driving end of the second gate control sub-circuit being electrically connected to the second gate control end to receive the second gate control signal, the first end of the second gate control sub-circuit being connected to the second gate signal end to receive the second gate signal, and the second end of the second gate control sub-circuit being electrically connected to the driving end of the second gate sub-circuit.

[0009] For example, the pixel circuit provided by an embodiment of the present disclosure further includes: a first gate control sub-circuit and a second gate control sub-circuit. The first gate control sub-circuit is configured to apply the first gate signal to the driving end of the first gate sub-circuit in response to a first gate control signal applied to the control end of the first gate control sub-circuit, the driving end of the first gate control sub-circuit being electrically connected to the first gate control end to receive the first gate control signal, the first end of the first gate control sub-circuit being connected to the first gate signal end to receive the first gate signal, and the second end of the first gate control sub-circuit being electrically connected to the driving end of the first gate sub-circuit. The second gate control sub-circuit is configured to apply the second gate signal to the driving end of the second gate sub-circuit in response to a second gate control signal applied to the control end of the second gate control sub-circuit, the driving end of the second gate control sub-circuit being electrically connected to the second gate control end to receive the second gate control signal, the first end of the second gate control sub-circuit being connected to the second gate signal end to receive the second gate signal, and the second end of the second gate control sub-circuit being electrically connected to the driving end of the second gate sub-circuit.

[0010] For example, the pixel circuit provided by an embodiment of the present disclosure includes a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit includes a first light-emitting element and a first sub-gate sub-circuit. The first sub-gate sub-circuit is configured to control a size of a driving current flowing through the first light-emitting element. The second sub-pixel circuit includes a second light-emitting element and a second sub-gate sub-circuit. The second sub-gate sub-circuit is configured to control a size of a driving current flowing through the second light-emitting element. The first light-emitting element and the second light-emitting element have different light-emitting colors.

[0011] For example, the pixel circuit provided by an embodiment of the present disclosure includes a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit includes a first light-emitting element and a first sub-gate sub-circuit. The first sub-gate sub-circuit is configured to control a size of a driving current flowing through the first light-emitting element. The second sub-pixel circuit includes a second light-emitting element and a second sub-gate sub-circuit. The second sub-gate sub-circuit is configured to control a size of a driving current flowing through the second light-emitting element. The first light-emitting element and the second light-emitting element have different light-emitting colors.

[0012] For example, the pixel circuit provided by an embodiment of the present disclosure includes a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit includes a first light-emitting element and a first sub-gate sub-circuit. The first sub-gate sub-circuit is configured to control a size of a driving current flowing through the first light-emitting element. The second sub-pixel circuit includes a second light-emitting element and a second sub-gate sub-circuit. The second sub-gate sub-circuit is configured to control a size of a driving current flowing through the second light-emitting element. The first light-emitting element and the second light-emitting element have different light-emitting colors.

[0013] For example, the pixel circuit provided by an embodiment of the present disclosure includes a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit includes a first light-emitting element and a first sub-gate sub-circuit. The first sub-gate sub-circuit is configured to control a size of a driving current flowing through the first light-emitting element. The second sub-pixel circuit includes a second light-emitting element and a second sub-gate sub-circuit. The second sub-gate sub-circuit is configured to control a size of a driving current flowing through the second light-emitting element. The first light-emitting element and the second light-emitting element have different light-emitting colors.

[0014] For example, the pixel circuit provided by an embodiment of the present disclosure further includes a first data write sub-circuit and a second data write sub-circuit. The first data write sub-circuit is configured to write a first data signal to a control end of the first drive sub-circuit in response to a first data scan signal, and the first drive sub-circuit is configured to control the size of the drive current flowing through the first light emitting element or the second light emitting element according to the first data signal. The second data write sub-circuit is configured to write a second data signal to a control end of the second drive sub-circuit in response to a second data scan signal, and the second drive sub-circuit is configured to control the size of the drive current flowing through the third light emitting element according to the second data signal.

[0015] For example, in the pixel circuit provided by an embodiment of the present disclosure, the pixel circuit further includes a first data storage sub-circuit and a second data storage sub-circuit. The first data write sub-circuit is electrically connected to a first end of the first data storage sub-circuit, and the first data storage sub-circuit is configured to transmit the first data signal to the first end of the first data storage sub-circuit in response to the first data scan signal. The first drive sub-circuit includes a control end, a first end and a second end, the control end of the first drive sub-circuit is electrically connected to the first end of the first data storage sub-circuit, the first end of the first drive sub-circuit is configured to receive the first power voltage, and the second end of the first drive sub-circuit, the second end of the first data storage sub-circuit, the first electrode of the first light emitting element and the first end of the first gate sub-circuit are electrically connected to a second node. The second data write sub-circuit is electrically connected to a first end of the second data storage sub-circuit and is configured to transmit the second data signal to the first end of the second data storage sub-circuit in response to the second data scan signal. The second drive sub-circuit includes a control end, a first end and a second end, the control end of the second drive sub-circuit is electrically connected to the first end of the second data storage sub-circuit, the first end of the second drive sub-circuit is configured to receive the first power voltage, and the second end of the second drive sub-circuit, the second end of the second data storage sub-circuit and the first electrode of the third light emitting element are electrically connected to a third node.

[0016] For example, in the pixel circuit provided by an embodiment of the present disclosure, the first driving sub-circuit comprises a first driving transistor configured to control a current for driving the first light emitting element to emit light under the control of a voltage at a gate of the first driving transistor, a first electrode of the first driving transistor is configured to receive the first power supply voltage, and a second electrode of the first driving transistor is electrically connected with a first electrode of the first light emitting element, and a second electrode of the second light emitting element is configured to receive the second power supply voltage; the second driving sub-circuit comprises a second driving transistor configured to control a current for driving the third light emitting element to emit light under the control of a voltage at a gate of the second driving transistor, a first electrode of the second driving transistor is configured to receive the first power supply voltage, and a second electrode of the second driving transistor is electrically connected with a first electrode of the third light emitting element, and a second electrode of the third light emitting element is configured to receive the second power supply voltage; the first data storage sub-circuit comprises a first data storage capacitor, a first electrode of the first data storage capacitor is electrically connected with the gate of the first driving transistor, and a second electrode of the first data storage capacitor is electrically connected with the second electrode of the first driving transistor, the first electrode of the first light emitting element, and the first electrode of the first selection transistor, and the second node; and the second data storage sub-circuit comprises a second data storage capacitor, a first electrode of the second data storage capacitor is electrically connected with the gate of the second driving transistor, and a second electrode of the second data storage capacitor, the second electrode of the first driving transistor, and the first electrode of the first light emitting element are electrically connected with the third node.

[0017] For example, in the pixel circuit provided by an embodiment of the present disclosure, the first data write sub-circuit comprises a first data transistor, a first electrode of the first data transistor is electrically connected with the first electrode of the first data storage capacitor and the gate of the first driving transistor, a second electrode of the first data transistor is configured to receive a first data signal, and the first data transistor is configured to write the first data signal to the gate of the first driving transistor and the first data storage capacitor in response to a first data scan signal; and the second data write sub-circuit comprises a second data transistor, a first electrode of the second data transistor is electrically connected with the first electrode of the second data storage capacitor and the gate of the second driving transistor, a second electrode of the second data transistor is configured to receive a second data signal, and the second data transistor is configured to write the second data signal to the gate of the second driving transistor and the second data storage capacitor in response to a second data scan signal.

[0018] For example, in the pixel circuit provided by an embodiment of the present disclosure, the first sub-pixel circuit further comprises a first sensing sub-circuit. A first end of the first sensing sub-circuit is electrically connected to the first electrode of the first light-emitting element, a control end of the first sensing sub-circuit is configured to receive a first sensing scan signal, and a second end of the first sensing sub-circuit is electrically connected to a first sensing signal line, which is electrically connected to a first external detection circuit. The first sensing sub-circuit is configured to detect the electrical characteristics of the sub-pixel to which the first sensing sub-circuit belongs through the first external detection circuit in response to the first sensing scan signal to achieve compensation. The second sub-pixel circuit further comprises a second sensing sub-circuit. A first end of the second sensing sub-circuit is electrically connected to the first electrode of the third light-emitting element, a control end of the second sensing sub-circuit is configured to receive a second sensing scan signal, and a second end of the second sensing sub-circuit is electrically connected to a second sensing signal line, which is electrically connected to a second external detection circuit. The second sensing sub-circuit is configured to detect the electrical characteristics of the sub-pixel to which the second sensing sub-circuit belongs through the second external detection circuit in response to the second sensing scan signal to achieve compensation.

[0019] For example, in the pixel circuit provided by an embodiment of the present disclosure, the first sensing sub-circuit comprises a first sensing transistor. A first electrode of the first sensing transistor is electrically connected to the first electrode of the first light-emitting element, a second electrode of the first sensing transistor is electrically connected to the first sensing signal line to be connected to the first external detection circuit, and a gate of the first sensing transistor is configured to receive the first sensing scan signal. The first sensing transistor is configured to detect the electrical characteristics of the sub-pixel to which the first sensing transistor belongs through the first external detection circuit in response to the first sensing scan signal to achieve external compensation. The second sensing sub-circuit comprises a second sensing transistor. A first electrode of the second sensing transistor is electrically connected to the first electrode of the third light-emitting element, a second electrode of the second sensing transistor is electrically connected to the second sensing signal line to be connected to the second external detection circuit, and a gate of the second sensing transistor is configured to receive the second sensing scan signal. The second sensing transistor is configured to detect the electrical characteristics of the sub-pixel to which the second sensing transistor belongs through the second external detection circuit in response to the second sensing scan signal to achieve external compensation.

[0020] For example, in the pixel circuit provided by an embodiment of the present disclosure, the pixel circuit further comprises a second sub-pixel circuit, a third gating sub-circuit and a fourth gating sub-circuit. The second sub-pixel circuit further comprises a second driving sub-circuit, a third light emitting element and a fourth light emitting element, the second driving sub-circuit is configured to control the size of the driving current flowing through the third light emitting element or the size of the driving current flowing through the fourth light emitting element; the second electrode of the third light emitting element and the first electrode of the fourth light emitting element are electrically connected, the first electrode of the third light emitting element is configured to receive the first power voltage, and the second electrode of the fourth light emitting element is configured to receive the second power voltage; the light emitting colors of the first light emitting element, the second light emitting element, the third light emitting element and the fourth light emitting element are different from each other; the third gating sub-circuit is connected in parallel with the third light emitting element, and is configured to determine whether the driving current flows through the third light emitting element in response to a third gate signal applied to the driving end of the third gating sub-circuit; the fourth gating sub-circuit is connected in parallel with the fourth light emitting element, and is configured to determine whether the driving current flows through the fourth light emitting element in response to a fourth gate signal applied to the driving end of the fourth gating sub-circuit.

[0021] For example, in the pixel circuit provided by an embodiment of the present disclosure, the first end of the third gating sub-circuit is electrically connected with the first electrode of the third light emitting element, the second end of the third gating sub-circuit, the second electrode of the third light emitting element, the first electrode of the fourth light emitting element and the first end of the fourth gating sub-circuit are electrically connected to a fourth node; and the second end of the fourth gating sub-circuit is electrically connected with the second electrode of the fourth light emitting element.

[0022] For example, the pixel circuit provided by an embodiment of the present disclosure further includes: a third gate control sub-circuit and a fourth gate control sub-circuit. The third gate control sub-circuit is configured to apply the third gate signal to the driving end of the third gate sub-circuit in response to the third gate control signal applied to the control end of the third gate control sub-circuit, the driving end of the third gate control sub-circuit is electrically connected to the third gate control end to receive the third gate control signal, the first end of the third gate control sub-circuit is connected to the third gate signal end to receive the third gate signal, and the second end of the third gate control sub-circuit is electrically connected to the driving end of the third gate sub-circuit; the fourth gate control sub-circuit is configured to apply the fourth gate signal to the driving end of the fourth gate sub-circuit in response to the fourth gate control signal applied to the control end of the fourth gate control sub-circuit, the driving end of the fourth gate control sub-circuit is electrically connected to the fourth gate control end to receive the fourth gate control signal, the first end of the fourth gate control sub-circuit is connected to the fourth gate signal end to receive the fourth gate signal, and the second end of the fourth gate control sub-circuit is electrically connected to the driving end of the fourth gate sub-circuit.

[0023] For example, the pixel circuit provided by an embodiment of the present disclosure further includes: a third gate control sub-circuit and a fourth gate control sub-circuit. The third gate control sub-circuit is configured to apply the third gate signal to the driving end of the third gate sub-circuit in response to the third gate control signal applied to the control end of the third gate control sub-circuit, the driving end of the third gate control sub-circuit is electrically connected to the third gate control end to receive the third gate control signal, the first end of the third gate control sub-circuit is connected to the third gate signal end to receive the third gate signal, and the second end of the third gate control sub-circuit is electrically connected to the driving end of the third gate sub-circuit; the fourth gate control sub-circuit is configured to apply the fourth gate signal to the driving end of the fourth gate sub-circuit in response to the fourth gate control signal applied to the control end of the fourth gate control sub-circuit, the driving end of the fourth gate control sub-circuit is electrically connected to the fourth gate control end to receive the fourth gate control signal, the first end of the fourth gate control sub-circuit is connected to the fourth gate signal end to receive the fourth gate signal, and the second end of the fourth gate control sub-circuit is electrically connected to the driving end of the fourth gate sub-circuit.

[0024] For example, in the pixel circuit provided by an embodiment of the present disclosure, the third sub-gating circuit comprises a third gating transistor, a gate of the third gating transistor serving as a driving end of the third sub-gating circuit, a first pole of the third gating transistor being electrically connected with a third electrode of the third light-emitting element, and a second pole of the third gating transistor being electrically connected with a fourth electrode of the third light-emitting element; and the fourth sub-gating circuit comprises a fourth gating transistor, a gate of the fourth gating transistor serving as a driving end of the fourth sub-gating circuit, a first pole of the fourth gating transistor being electrically connected with a third electrode of the fourth light-emitting element, and a second pole of the fourth gating transistor being electrically connected with a second electrode of the fourth light-emitting element.

[0025] For example, in the pixel circuit provided by an embodiment of the present disclosure, the third sub-gating control circuit comprises a third gating control transistor, a gate of the third gating control transistor being electrically connected with the third gating control end to receive the third gating control signal, a first pole of the third gating control transistor being connected with the third gating signal end to receive the first gating signal, and a second pole of the third gating control transistor being electrically connected with a gate of the third gating transistor; and the fourth sub-gating control circuit comprises a fourth gating control transistor, a gate of the fourth gating control transistor being electrically connected with the fourth gating control end to receive the fourth gating control signal, a first pole of the fourth gating control transistor being connected with the fourth gating signal end to receive the fourth gating signal, and a second pole of the fourth gating control transistor being electrically connected with a gate of the fourth gating transistor.

[0026] For example, in the pixel circuit provided by an embodiment of the present disclosure, the first data scanning signal is applied to a control end of the first data writing sub-circuit, and the second data scanning signal is applied to a control end of the second data writing sub-circuit; the control end of the first data writing sub-circuit, the control end of the second data writing sub-circuit, the control end of the first sensing sub-circuit, and the control end of the second sensing sub-circuit are electrically connected with a same sensing scanning line, and the first data scanning signal, the second data scanning signal, the first sensing scanning signal, and the second sensing scanning signal are the same scanning signal.

[0027] For example, in the pixel circuit provided by an embodiment of the present disclosure, one of the first end of the first gate control sub-circuit and the first end of the second gate control sub-circuit is electrically connected to one of the first end of the third gate control sub-circuit and the first end of the fourth gate control sub-circuit through the same first gate signal line and the same first gate signal end, and the other of the first end of the first gate control sub-circuit and the first end of the second gate control sub-circuit is electrically connected to the other of the first end of the third gate control sub-circuit and the first end of the fourth gate control sub-circuit through the same second gate signal line and the same second gate signal end, and the gate control signals from the first gate signal end and the second gate signal end are different.

[0028] For example, in the pixel circuit provided by an embodiment of the present disclosure, in adjacent pixel columns, the same gate signal line is used to transmit the same gate signal, and the same gate signal is at least one of the first gate signal, the second gate signal, the third gate signal and the fourth gate signal.

[0029] At least one embodiment of the present disclosure also provides a driving method of any one of the pixel circuits provided by the embodiments of the present disclosure. A display period of a frame of image includes at least two time periods, and the driving method of the pixel circuit includes: controlling the first light emitting element and the second light emitting element to emit light in different time periods by controlling the first gate signal applied to the driving end of the first gate sub-circuit and the second gate signal applied to the driving end of the second gate sub-circuit.

[0030] For example, in the driving method of the pixel circuit provided by an embodiment of the present disclosure, the at least two time periods include a first time period and a second time period, in the first time period, one of the first light emitting element and the second light emitting element emits light of a first color, in the second time period, the other of the first light emitting element and the second light emitting element emits light of a second color; the first time period includes a first gate-on and data writing stage and a first light emitting stage after the first gate-on and data writing stage; the second time period includes a second gate-on and data writing stage and a second light emitting stage after the second gate-on and data writing stage; in the first gate-on and data writing stage and the second gate-on and data writing stage, the first gate-on control signal and the second gate-on control signal are both open signals, the first gate-on signal is written to the control end of the first gate-on subcircuit through the first gate-on control subcircuit, and the second gate-on signal is written to the control end of the second gate-on subcircuit through the second gate-on control subcircuit; in the first gate-on and data writing stage and the second gate-on and data writing stage, the first gate-on signal and the second gate-on signal are signals opposite to each other, so that one of the first gate-on subcircuit and the second gate-on subcircuit is turned on, and the other of the first gate-on subcircuit and the second gate-on subcircuit is turned off, so that in the first light emitting stage and the second light emitting stage, the light emitting element connected in parallel with the turned-on one does not emit light and the light emitting element connected in parallel with the turned-off other does not emit light.

[0031] For example, in the driving method of the pixel circuit provided by an embodiment of the present disclosure, in the pixel circuit including a first data writing subcircuit configured to write a first data signal to the control end of the first driving subcircuit in response to a first data scanning signal, and the first driving subcircuit configured to control the size of the driving current flowing through the first light emitting element or the second light emitting element according to the first data signal, the driving method of the pixel circuit includes: in the first gate-on and data writing stage, writing the first data signal for controlling the gray scale of the first color; and in the second gate-on and data writing stage, writing the second data signal for controlling the gray scale of the second color.

[0032] For example, in the driving method of the pixel circuit provided by an embodiment of the present disclosure, the first period further includes a first reset stage before the first gate-on and data writing stage; in the first reset stage, the first gate-on control signal is an open signal to make the first end and the second end of the first gate-on control sub-circuit conductive, the first gate-on signal written to the control end of the first gate-on sub-circuit through the first gate-on control sub-circuit is an open signal to make the first end and the second end of the first gate-on sub-circuit conductive via the first gate-on sub-circuit, the second gate-on control signal is an open signal to make the first end and the second end of the second gate-on control sub-circuit conductive, the second gate-on signal written to the control end of the second gate-on sub-circuit through the second gate-on control sub-circuit is a closed signal to make the first end and the second end of the second gate-on sub-circuit not conductive, and the first reset signal is applied to the second electrode of the first light emitting element via the first electrode of the first light emitting element, the first end and the second end of the first gate-on sub-circuit, to reset the electrical signal of the second electrode of the first light emitting element.

[0033] For example, in the driving method of the pixel circuit provided by an embodiment of the present disclosure, the pixel circuit includes a second sub-pixel circuit, the second sub-pixel circuit includes a second driving sub-circuit and a third light emitting element, the second driving sub-circuit is configured to control the size of the driving current flowing through the third light emitting element, and the light emitting colors of the first light emitting element, the second light emitting element and the third light emitting element are different from each other; the at least two periods include a first period and a second period, the first period includes a first light emitting stage, and the second period includes a second light emitting stage; in the first light emitting stage, the third light emitting element emits light with one of the first light emitting element and the second light emitting element; in the second light emitting stage, the third light emitting element emits light with the other of the first light emitting element and the second light emitting element.

[0034] For example, in the driving method of the pixel circuit provided by an embodiment of the present disclosure, the second sub-pixel circuit further comprises a second driving sub-circuit, a third light-emitting element and a fourth light-emitting element, a third gating sub-circuit and a fourth gating sub-circuit, the second driving sub-circuit is configured to control the size of the driving current flowing through the third light-emitting element or the size of the driving current flowing through the fourth light-emitting element; the second electrode of the third light-emitting element and the first electrode of the fourth light-emitting element are electrically connected, the first electrode of the third light-emitting element is configured to receive the first power supply voltage, and the second electrode of the fourth light-emitting element is configured to receive the second power supply voltage; the light-emitting colors of the first light-emitting element, the second light-emitting element, the third light-emitting element and the fourth light-emitting element are different from each other; the third gating sub-circuit is connected in parallel with the third light-emitting element, and is configured to determine whether the driving current flows through the third light-emitting element in response to a third gating signal applied to the driving end of the third gating sub-circuit; the fourth gating sub-circuit is connected in parallel with the fourth light-emitting element, and is configured to determine whether the driving current flows through the fourth light-emitting element in response to a second gating signal applied to the driving end of the fourth gating sub-circuit; the at least two time periods comprise a first time period and a second time period, and the driving method comprises: by controlling the first gating signal applied to the driving end of the first gating sub-circuit, the second gating signal applied to the driving end of the second gating sub-circuit, the third gating signal applied to the driving end of the third gating sub-circuit and the fourth gating signal applied to the driving end of the fourth gating sub-circuit, so that: in the first time period, one of the first light-emitting element and the second light-emitting element and one of the third light-emitting element and the fourth light-emitting element emit light; and in the second time period, the other of the first light-emitting element and the second light-emitting element and the other of the third light-emitting element and the fourth light-emitting element emit light.

[0035] For example, in the driving method of the pixel circuit provided by an embodiment of the present disclosure, the first time period further includes a first reset stage located before the first gate-on and data writing stage; in the first reset stage, the first gate-on control signal is an open signal to make the first end and the second end of the first gate-on control sub-circuit conductive, the first gate-on signal written to the control end of the first gate-on sub-circuit through the first gate-on control sub-circuit is a closed signal to make the first end and the second end of the first gate-on sub-circuit not conductive, the second gate-on control signal is an open signal to make the first end and the second end of the second gate-on control sub-circuit conductive, the second gate-on signal written to the control end of the second gate-on sub-circuit through the second gate-on control sub-circuit is an open signal to make the first end and the second end of the second gate-on sub-circuit conductive via the second gate-on sub-circuit, and the second power supply voltage is applied to the second electrode of the first light-emitting element via the second gate-on sub-circuit to reset the electrical signal of the second electrode of the first light-emitting element.

[0036] At least one embodiment of the present disclosure further provides a display panel, which comprises any one of the pixel circuits provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, but not limit the present disclosure.

[0038] FIG. 1 is a schematic diagram of the overall plane of a display substrate;

[0039] FIG. 2 is a schematic diagram of the overall plane of a display substrate provided by an embodiment of the present disclosure;

[0040] FIG. 3 is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0041] FIG. 4 is a timing diagram of a driving method of the pixel circuit shown in FIG. 3;

[0042] FIG. 5A is a schematic diagram of the circuit conduction state of the first reset stage of the first time period shown in FIG. 4;

[0043] FIG. 5B is a schematic diagram of the circuit conduction state of the first gate-on and data writing stage of the first time period shown in FIG. 4;

[0044] FIG. 5C is a schematic diagram of the circuit conduction state of the first light-emitting stage of the first time period shown in FIG. 4;

[0045] FIG. 5D is a schematic diagram of the circuit conduction state of the second reset stage of the second time period shown in FIG. 4;

[0046] Figure 5E is a schematic diagram of the circuit conduction state during the second gating and data writing stage of the second time period shown in Figure 4;

[0047] Figure 5F is a schematic diagram of the circuit conduction state in the second light-emitting stage of the second time period shown in Figure 4;

[0048] Figure 6 is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0049] Figure 7 is a timing diagram of one driving method for the pixel circuit shown in Figure 6;

[0050] Figure 8A is a schematic diagram of the circuit conduction state in the first reset stage of the first time period shown in Figure 6;

[0051] Figure 8B is a schematic diagram of the circuit conduction state during the first gating and data writing stage of the first time period shown in Figure 6.

[0052] Figure 8C is a schematic diagram of the circuit conduction state in the first light-emitting stage of the first time period shown in Figure 6;

[0053] Figure 8D is a schematic diagram of the circuit conduction state in the second reset stage of the second time period shown in Figure 6;

[0054] Figure 8E is a schematic diagram of the circuit conduction state during the second gating and data writing stage of the second time period shown in Figure 6;

[0055] Figure 8F is a schematic diagram of the circuit conduction state in the second light-emitting stage of the second time period shown in Figure 6;

[0056] Figure 9 is a timing diagram of another driving method for the pixel circuit shown in Figure 6 provided in an embodiment of this disclosure;

[0057] Figure 10A is a timing diagram of another driving method for the pixel circuit shown in Figure 6 provided in an embodiment of this disclosure;

[0058] Figure 10B is a schematic diagram of the circuit conduction state during the first reset stage of the pixel circuit shown in Figure 10A.

[0059] Figure 11 is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0060] Figure 12 is a timing diagram of a driving method for the pixel circuit shown in Figure 11 provided in an embodiment of this disclosure;

[0061] Figure 13 is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0062] Figure 14 is a timing diagram of a driving method for the pixel circuit shown in Figure 13 provided in an embodiment of the present disclosure;

[0063] FIG. 15A is a schematic diagram of circuit conduction states of a first reset stage of a first time period shown in FIG. 14;

[0064] FIG. 15B is a schematic diagram of circuit conduction states of a first gate and data write stage of the first time period shown in FIG. 14;

[0065] FIG. 15C is a schematic diagram of circuit conduction states of a first light emission stage of the first time period shown in FIG. 14;

[0066] FIG. 15D is a schematic diagram of circuit conduction states of a second reset stage of a second time period shown in FIG. 14;

[0067] FIG. 15E is a schematic diagram of circuit conduction states of a second gate and data write stage of the second time period shown in FIG. 14;

[0068] FIG. 15F is a schematic diagram of circuit conduction states of a second light emission stage of the second time period shown in FIG. 14;

[0069] FIG. 16 is a schematic block diagram of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. The embodiments described below are part of, rather than all of, the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art without any creative effort based on the described embodiments of the present disclosure shall fall within the scope of protection of the present disclosure.

[0071] Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meanings as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0072] It should be noted that in the embodiments of the present disclosure, each signal line and element in the equivalent circuit diagram, such as a scan signal line, a data line, a power signal line, a sensing signal line, each transistor, and a capacitor, etc., is only to show the electrical connection relationship, and the specific position and structural relationship, arrangement position thereof in the display substrate can be designed as needed. Therefore, in the embodiments of the present disclosure, the schematic positions of each signal line and element in the equivalent circuit diagram do not constitute a limitation on the structural arrangement and positional relationship thereof in the actual display substrate.

[0073] FIG. 1 is a schematic overall plan view of a display substrate. Referring to FIG. 1, a general display substrate 101 includes a display region DR and a non-display region NR at least partially surrounding the display region DR. The display substrate 101 includes a plurality of display units PU located in the display region DR and arranged in an array, and the display units PU perform a display function. Each display unit PU includes a plurality of sub-pixels R / G / B, for example, in FIG. 1, one display unit PU includes three sub-pixels, which are a first sub-pixel R emitting red light, a second sub-pixel G emitting green light, and a second sub-pixel B emitting blue light, of course, the number of sub-pixels included in one display unit PU can be less than three or more than three, and each sub-pixel 100 includes a light emitting element and a pixel circuit driving the light emitting element. The display substrate 101 further includes a plurality of scan lines GL and a plurality of data lines DL. The plurality of scan lines GL and the plurality of data lines DL cross each other in the display region DR to define a plurality of pixel regions arranged in an array, and one pixel circuit of a sub-pixel is arranged in each pixel region.

[0074] It can be seen that in such a display substrate 101, on the one hand, a plurality of sub-pixels R / G / B of one display unit PU respectively occupy a certain area, thus limiting the improvement of the resolution (PPI) of the display substrate 101, and being not conducive to achieving a breakthrough in the PPI; on the other hand, for each sub-pixel R / G / B, an independently driven circuit needs to be arranged, and a corresponding signal line needs to be arranged, for example, at least an independent data line DL and a power line need to be arranged for each sub-pixel R / G / B, so that the number of signal lines is relatively large, which limits the improvement of the aperture ratio of the display substrate 101; and there is a leakage current problem between the openings of the plurality of sub-pixels, which will adversely affect the performance of the device, however, improving the resolution and aperture ratio of the OLED display panel or display device is of great significance to improve the display quality, greatly improving the user experience.

[0075] The pixel circuit includes a first sub-pixel circuit, a first gating sub-circuit and a second gating sub-circuit. The first sub-pixel circuit includes a first driving sub-circuit, a first light emitting element and a second light emitting element. The first driving sub-circuit is configured to control the size of a driving current flowing through the first light emitting element or the size of a driving current flowing through the second light emitting element. A second electrode of the first light emitting element and a first electrode of the second light emitting element are electrically connected. The first electrode of the first light emitting element is configured to receive a first power voltage. A second electrode of the second light emitting element is configured to receive a second power voltage. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. The first gating sub-circuit is connected in parallel with the first light emitting element and is configured to determine, in response to a first gate signal applied to a driving end of the first gating sub-circuit, whether a first end and a second end of the first gating sub-circuit are conducted through the first gating sub-circuit and whether the driving current flows through the first light emitting element. The second gating sub-circuit is connected in parallel with the second light emitting element and is configured to determine, in response to a second gate signal applied to a driving end of the second gating sub-circuit, whether a first end and a second end of the second gating sub-circuit are conducted through the second gating sub-circuit and whether the driving current flows through the second light emitting element.

[0076] The display period of a frame of image includes at least two time periods. The driving method of the pixel circuit includes: controlling the first gate signal applied to the driving end of the first gating sub-circuit and the second gate signal applied to the driving end of the second gating sub-circuit to control the first light emitting element and the second light emitting element to emit light in different time periods, respectively.

[0077] The display panel includes any one of the pixel circuits provided in the embodiments of the present disclosure.

[0078] The pixel circuit provided by the embodiments of the present disclosure can be applied to a display device such as a display substrate or a display panel, at least two sub-pixel circuits, for example, a first sub-pixel circuit and a second sub-pixel circuit, are arranged in one pixel circuit. In the first sub-pixel circuit, the second electrode of the first light emitting element and the first electrode of the second light emitting element are electrically connected, and the first driving sub-circuit can not only control the size of the driving current flowing through the first light emitting element, but also control the size of the driving current flowing through the second light emitting element. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. In addition, the first selection sub-circuit is connected in parallel with the first light emitting element, and the second selection sub-circuit is connected in parallel with the second light emitting element. Therefore, the light emitting elements that are turned on are controlled by the first selection sub-circuit and the second selection sub-circuit. Thus, by using the time-sharing control method, the color display can be realized by controlling the first light emitting element and the second light emitting element to emit light of different colors at different time periods in one sub-pixel. The combination of multiple sub-pixels with different light emitting colors is realized. In addition, in the pixel circuit, the driving sub-circuit for controlling the driving current flowing through the first light emitting element and the second light emitting element is the same driving sub-circuit, which simplifies the circuit structure, reduces the space occupied by multiple sub-pixels with different light emitting colors, and is beneficial to significantly improve the PPI. In addition, the driving method of the pixel circuit is simple and reliable.

[0079] For example, FIG. 2 is a schematic diagram of the overall plane of a display substrate provided by an embodiment of the present disclosure, and FIG. 3 is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure. Referring to FIG. 2, for example, the display substrate 10 provided by at least one embodiment of the present disclosure includes a display region DR and a non-display region NR surrounding at least part of the display region DR. The display substrate 10 includes a plurality of display units PU arranged in an array in the display region DR, and the display units PU perform a display function. Each display unit PU includes one sub-pixel RGB. For example, the display substrate 10 includes a substrate 1, the substrate 1 includes a main surface, and a pixel array including a plurality of display units PU is arranged on the main surface of the substrate 1. In combination with FIG. 2 and FIG. 3, each sub-pixel RGB includes a first light emitting element D1, a second light emitting element D2, and a pixel circuit for driving the first light emitting element D1 and the second light emitting element D2. The first light emitting element D1 and the second light emitting element D2 respectively emit light of different colors. Thus, one sub-pixel can emit light of multiple colors. For example, in FIG. 2, one display unit PU emits light of three different colors, for example, one sub-pixel RGB can emit red (R) light, green (B) light, and blue (G) light. Of course, the types of light that can be emitted by one display unit PU are not limited to three, and can be less than three or more than three. The light emitting colors of one display unit PU are not limited to red, green, and blue. The number of light emitting elements and the specific light emitting colors of each sub-pixel are not limited in the embodiments of the present disclosure.

[0080] For example, as shown in FIG. 2, the display substrate 10 further includes a plurality of scan lines GL and a plurality of data lines DL. The plurality of scan lines GL and the plurality of data lines DL cross each other to define a plurality of pixel regions arranged in an array in the display region DR, and each of the pixel regions is provided with a pixel circuit of a sub-pixel RGB.

[0081] For example, as shown in FIG. 2, the display substrate 10 can further include a scan driving circuit SC and a data driving circuit DC in the non-display region NR. The scan driving circuit SC is, for example, a gate driving circuit (e.g., a GOA driving circuit). The scan driving circuit SC is connected to the pixel circuit through the scan line GL to provide various scan signals, and the data driving circuit DC is connected to the pixel circuit through the data line DL to provide a data signal. The positions of the scan driving circuit SC and the data driving circuit DC, the scan line GL and the data line DL in the display substrate shown in FIG. 1 are only examples, and the actual arrangement positions can be designed as needed.

[0082] For example, the display substrate 10 can further include a control circuit (not shown). For example, the control circuit is configured to control the data driving circuit DC to apply the data signal, and control the gate driving sub-circuit to apply the scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit can be various forms, for example, including a processor and a memory, the memory including executable code, and the processor executing the executable code to perform the above-described detection method.

[0083] For example, the processor can be a central processing unit (CPU) or other forms of processing apparatus having data processing capability and / or instruction execution capability, for example, can include a microprocessor, a programmable logic controller (PLC), etc.

[0084] For example, the storage apparatus can include one or more computer program products, which can include various forms of computer readable storage media, for example, volatile memory and / or non-volatile memory. The volatile memory can include, for example, a random access memory (RAM) and / or a cache, etc. The non-volatile memory can include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions can be stored on the computer readable storage medium, and the processor can execute the program instructions to perform the desired functions. Various application programs and various data can also be stored in the computer readable storage medium.

[0085] It should be noted that in the pixel circuit provided by the embodiments of the present application, for the sub-pixel circuit for driving the first light emitting element and the second light emitting element to emit light, for example, the first sub-pixel circuit and the second sub-pixel circuit, it is not limited to the 3T1C (i.e., 3 transistors and 1 capacitor, for example, the first sub-pixel circuit includes the first drive transistor T2, the first data writing transistor T1 and the first sensing transistor T3 and the first storage capacitor CstA) pixel circuit shown in FIG. 3, and can be designed as needed, can be an nTmC (n, m are positive integers) pixel circuit, and in different embodiments, the pixel circuit can further include a compensation sub-circuit, which includes an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit can include transistors, capacitors, etc. For example, the pixel circuit can further include a reset circuit, a light emitting control sub-circuit, a detection circuit, etc. as needed.

[0086] In the following, the structure and driving method of the pixel circuit for realizing color display provided by the embodiments of the present application are introduced in combination with specific equivalent circuit diagrams.

[0087] FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. Referring to FIG. 3, the pixel circuit 10 according to at least one embodiment of the present disclosure includes a first sub-pixel circuit including a first driving sub-circuit 101, a first light emitting element D1, a second light emitting element D2, a first gating sub-circuit 201, and a second gating sub-circuit 202. The first driving sub-circuit 101 is configured to control a size of a driving current flowing through the first light emitting element D1 or a size of a driving current flowing through the second light emitting element D2; a second electrode of the first light emitting element D1 and a first electrode of the second light emitting element D2 are electrically connected, the first electrode of the first light emitting element D1 is configured to receive a first power voltage VDD, and the second electrode of the second light emitting element D2 is configured to receive a second power voltage; the first light emitting element D1 and the second light emitting element D2 have different light emitting colors from each other; the first gating sub-circuit 201 is connected in parallel with the first light emitting element D1 and is configured to determine whether a first end and a second end of the first gating sub-circuit 201 are turned on via the first gating sub-circuit 201 and whether the driving current flows through the first light emitting element D1 in response to a first gate signal DA applied to a driving end of the first gating sub-circuit 201; and the second gating sub-circuit 202 is connected in parallel with the second light emitting element D2 and is configured to determine whether a first end and a second end of the second gating sub-circuit 202 are turned on via the second gating sub-circuit 202 and whether the driving current flows through the second light emitting element D2 in response to a second gate signal DB applied to a driving end of the second gating sub-circuit 202. That is, since the first gating sub-circuit 201 is connected in parallel with the first light emitting element D1 and the second gating sub-circuit 202 is connected in parallel with the second light emitting element D2, in one light emitting stage, one of the first gating sub-circuit 201 and the second gating sub-circuit 202 is turned on and the other is turned off, so that the turned-on one can be equivalent to a wire, the light emitting element connected in parallel with the turned-on one does not emit light, and the light emitting element connected in parallel with the turned-off one emits light.

[0088] Thus, in the pixel circuit 10 provided in the embodiments of the present disclosure, by cooperation of at least two selection sub-circuits and one driving sub-circuit, at least two light emitting elements are driven to emit light at different time periods, for example, to emit light of different colors at different time periods, so as to realize color display, and the structure of the pixel circuit and the driving method can be simplified. In the pixel circuit 10 provided in the embodiments of the present disclosure, pixel merging is realized. On the one hand, since the pixel circuit for driving multiple light emitting elements to emit light is set as a repeating unit in the conventional pixel circuit shown in FIG. 1, the area occupied by one pixel for realizing multiple color light emission can be reduced. On the other hand, in the structural design of the pixel circuit, for example, the light emitting elements driven by the same driving sub-circuit to emit light can be stacked in one pixel, so as to further reduce the total area occupied by the multiple light emitting elements for emitting light of different colors in one pixel. Therefore, the pixel circuit provided in the embodiments of the present disclosure can realize higher PPI, and the simplified circuit structure is also beneficial to increase the aperture ratio of the pixel, improve the product life, increase the yield and refresh rate of the product, and reduce the hardware cost of the product, thereby providing a wider design space for the layout optimization of the signal lines of the pixel circuit.

[0089] For example, in the first sub-pixel circuit, at least two light emitting elements, for example, a first light emitting element D1 and a second light emitting element D2, are provided, the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 are electrically connected, the size of the driving current flowing through the first light emitting element D1 and the size of the driving current flowing through the second light emitting element D2 can be controlled by the first driving sub-circuit 101, the light emitting colors of the first light emitting element D1 and the second light emitting element D2 are different from each other, the first selection sub-circuit 201 is connected in parallel with the first light emitting element D1, and the second selection sub-circuit 202 is connected in parallel with the second light emitting element D2, so as to control and select the light emitting element to be turned on by the first selection sub-circuit 201 and the second selection sub-circuit 202. Thus, by using the time-sharing control method, color display can be realized by controlling the first light emitting element D1 and the second light emitting element D2 to emit light of different colors at different time periods in one sub-pixel, and the merging of multiple sub-pixels with different light emitting colors is realized. In the pixel circuit, the driving sub-circuit for controlling the driving current flowing through the first light emitting element D1 and the second light emitting element D2 is the same first driving sub-circuit 101, the circuit structure is simplified, the space occupied by the multiple sub-pixels with different light emitting colors is reduced, which is beneficial to significantly improve the PPI, and the driving method of the pixel circuit 10 is simple and reliable.

[0090] In a traditional pixel circuit, one sub-pixel only includes a light emitting element emitting light of one color, the pixel circuit using the one sub-pixel drives the light emitting element to emit light of one color only, and different colors of light are emitted by multiple sub-pixels to realize color display. Compared with the traditional pixel circuit, on the one hand, the pixel circuit provided in the embodiments of the present disclosure realizes the combination of multiple sub-pixels emitting multiple colors of light respectively in the traditional pixel circuit, for example, the pixel circuit provided in the embodiments of the present disclosure converts the first sub-pixel R, the second sub-pixel G emitting green light and the second sub-pixel B emitting blue light in FIG. 1 into one sub-pixel RGB; on the other hand, due to the realization of pixel combination, the space occupied by the structure of the added gating circuit is much smaller than the complexity and space occupied by the structure of multiple sub-pixel circuits respectively controlling different light emitting colors, greatly reducing the number of transistors such as thin film transistors (TFT) of the entire display panel using the pixel circuit, and there is no need to provide a data line and a power voltage line for each of the first sub-pixel R, the second sub-pixel G emitting green light and the second sub-pixel B emitting blue light in FIG. 1 respectively, greatly reducing the number of signal lines of the entire display panel using the pixel circuit. Therefore, in the display substrate using the pixel circuit provided in the embodiments of the present disclosure, the area occupied by the pixels with multiple light emitting colors and the signal lines for providing corresponding signals to each sub-pixel, such as gate lines providing scan signals, data lines providing data signals, power lines providing power signals, and the like, is reduced, thereby being able to significantly improve the aperture ratio and resolution (PPI) of the display substrate, being able to realize higher resolution (PPI), and being applicable to realize a display panel with ultra-high PPI.

[0091] For example, referring to FIG. 3, the first end of the first gating sub-circuit 201 is electrically connected with the first electrode of the first light emitting element D1, the second end of the first gating sub-circuit 201, the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 and the first end of the second gating sub-circuit 202 are electrically connected to the first node N1; the second end of the second gating sub-circuit 202 is electrically connected with the second electrode of the second light emitting element D2. In this way, the first gating sub-circuit 201 is connected in parallel with the first light emitting element D1, and the second gating sub-circuit 202 is connected in parallel with the second light emitting element D2.

[0092] With reference to FIG. 3, for example, the first light emitting element D1 and the second light emitting element D2 can each be an electroluminescent element, such as an organic light emitting diode (OLED) element, or an inorganic light emitting diode element, etc. For example, the first electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 are each an anode, and the second electrode of the first light emitting element D1 and the second electrode of the second light emitting element D2 are each a cathode; or, in some embodiments, the first electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 are each a cathode, and the second electrode of the first light emitting element D1 and the second electrode of the second light emitting element D2 are each an anode. The same is true, for example, for the third light emitting element D2 and the fourth light emitting element D4 described below.

[0093] For example, the first sub-pixel circuit further comprises a first gate control sub-circuit 301 and a second gate control sub-circuit 302. The first gate control sub-circuit 301 is configured to apply the first gate signal DA to the driving end of the first gate sub-circuit 201 in response to the first gate control signal G3 applied to the control end of the first gate control sub-circuit 301, the driving end of the first gate control sub-circuit 301 being electrically connected to the first gate control end to receive the first gate control signal G3, the first end of the first gate control sub-circuit 301 being connected to the first gate signal end to receive the first gate signal DA, and the second end of the first gate control sub-circuit 301 being electrically connected to the driving end of the first gate sub-circuit 201; the second gate control sub-circuit 302 is configured to apply the second gate signal DB to the driving end of the second gate sub-circuit 202 in response to the second gate control signal G4 applied to the control end of the second gate control sub-circuit 302, the driving end of the second gate control sub-circuit 302 being electrically connected to the second gate control end to receive the second gate control signal G4, the first end of the second gate control sub-circuit 302 being connected to the second gate signal end to receive the second gate signal DB, and the second end of the second gate control sub-circuit 302 being electrically connected to the driving end of the second gate sub-circuit 202. In this way, the first gate control sub-circuit 301 and the second gate control sub-circuit 302 can be controlled to be turned on and turned off by the first gate control signal G3 and the second gate control signal G4. When both are turned on, the first gate signal DA and the second gate signal DB are written to the driving end of the first gate sub-circuit 201 and the driving end of the second gate sub-circuit 202, respectively, to control the first gate sub-circuit 201 and the second gate sub-circuit 202 to be turned on and turned off by the first gate signal DA and the second gate signal DB. In the light-emitting stage, one of the first gate sub-circuit 201 and the second gate sub-circuit 202 can be turned on and the other can be turned off. The one that is turned on can be equivalent to a wire, so that the driving current flows through the one that is turned on and does not flow through the light-emitting element connected in parallel with the one that is turned on, so that the light-emitting element connected in parallel with the one that is turned on does not emit light, while the driving current flows through the light-emitting element connected in parallel with the other that is turned off, so that the light-emitting element connected in parallel with the other that is turned off emits light.

[0094] For example, the first gate signal end and the second gate signal end can be the same signal end, and the first gate control signal G3 and the second gate control signal G4 can be the same signal. Of course, in other embodiments, the first gate control signal G3 and the second gate control signal G4 can also be independent signals controlled by their respective control ends without affecting each other.

[0095] For example, referring to FIG. 3, the pixel circuit 10 provided by at least one embodiment of the present disclosure further includes a first gate storage sub-circuit 401 and a second gate storage sub-circuit 402. The first gate control sub-circuit 301 is configured to transmit a first gate signal DA to a first end of the first gate storage sub-circuit 401 in response to a first gate control signal G3, the first gate storage sub-circuit 401 is configured to store the first gate signal DA, the first end of the first gate control sub-circuit 301 is electrically connected to the driving end of the first gate sub-circuit 201 and the second end of the first gate control sub-circuit 301 at the first gate node M1, and the second end of the first gate storage sub-circuit 401 is connected to the first power supply end to receive the first power supply voltage VDD. The second gate control sub-circuit 302 is configured to transmit a second gate signal DB to a first end of the second gate storage sub-circuit 402 in response to a second gate control signal G4, the second gate storage sub-circuit 402 is configured to store the second gate signal DB, the first end of the second gate storage sub-circuit 402 is electrically connected to the driving end of the second gate sub-circuit 202 and the second end of the second gate control sub-circuit 302 at the second gate node M2, and the second end of the second gate storage sub-circuit 402 is connected to the first power supply end to receive the first power supply voltage VDD. In this way, the first gate signal DA can be stored in the first gate storage sub-circuit 401, and the second gate signal DB can be stored in the second gate storage sub-circuit 402, so that in a certain stage, for example, in the light emitting stage, the stored first gate signal DA and the second gate signal DB are used to keep the first gate sub-circuit 201 and the second gate sub-circuit 202 in the open state or the closed state, respectively, to selectively control different light emitting elements (the first light emitting element D1 or the second light emitting element D2) to emit light.

[0096] Specifically, referring to FIG. 3, for example, the first gate sub-circuit 201 includes a first gate transistor T5, the gate of the first gate transistor T5 serving as the driving end of the first gate sub-circuit 201, the first electrode of the first gate transistor T5 being electrically connected to the first electrode of the first light emitting element D1, and the second electrode of the first gate transistor T5 being electrically connected to the second electrode of the first light emitting element D1; the second gate sub-circuit 202 includes a second gate transistor T7, the gate of the second gate transistor T7 serving as the driving end of the second gate sub-circuit 202, the first electrode of the second gate transistor T7 being electrically connected to the first electrode of the second light emitting element D2, and the second electrode of the second gate transistor T7 being electrically connected to the second electrode of the second light emitting element D2.

[0097] Referring to FIG. 3, for example, the first gate control sub-circuit 301 includes a first gate control transistor T4, a gate of the first gate control transistor T4 is electrically connected to the first gate control terminal to receive the first gate control signal G3, a first electrode of the first gate control transistor T4 is connected to the first gate signal terminal to receive the first gate signal DA, and a second electrode of the first gate control transistor T4 is electrically connected to a gate of the first gate transistor T5; the second gate control sub-circuit 302 includes a second gate control transistor T6, a gate of the second gate control transistor T6 is electrically connected to the second gate control terminal to receive the second gate control signal G4, a first electrode of the second gate control transistor T6 is connected to the second gate signal terminal to receive the second gate signal DB, and a second electrode of the second gate control transistor T6 is electrically connected to a gate of the second gate transistor T7.

[0098] Referring to FIG. 3, for example, the first gate control sub-circuit 301 includes a first gate control transistor T4, a gate of the first gate control transistor T4 is electrically connected to the first gate control terminal to receive the first gate control signal G3, a first electrode of the first gate control transistor T4 is connected to the first gate signal terminal to receive the first gate signal DA, and a second electrode of the first gate control transistor T4 is electrically connected to a gate of the first gate transistor T5; the second gate control sub-circuit 302 includes a second gate control transistor T6, a gate of the second gate control transistor T6 is electrically connected to the second gate control terminal to receive the second gate control signal G4, a first electrode of the second gate control transistor T6 is connected to the second gate signal terminal to receive the second gate signal DB, and a second electrode of the second gate control transistor T6 is electrically connected to a gate of the second gate transistor T7.

[0099] For example, referring to FIG. 3, the pixel circuit 10 further includes a second sub-pixel circuit. The second sub-pixel circuit includes a second driving sub-circuit 102 and a third light emitting element D3, the second driving sub-circuit 102 is configured to control the size of the driving current flowing through the third light emitting element D3; the light emitting colors of the first light emitting element D1, the second light emitting element D2 and the third light emitting element D3 are different from each other. In this way, by adopting the time-sharing driving method, the first light emitting element D1 and the second light emitting element D2 can be driven to emit light of the first color and the second color respectively in different light emitting stages by cooperation of the first sub-pixel circuit, the first gate sub-circuit and the second gate sub-circuit, and on this basis, the second sub-pixel circuit is additionally provided to drive the third light emitting element D3 to emit light of the third color, so that rich color display can be realized. For example, the third light emitting element D3 can be caused to emit light simultaneously with at least one of the first light emitting element D1 and the second light emitting element D2, so that the three colors of light can be emitted by one pixel in the display period of one frame of image.

[0100] For example, the first color of light emitted by the first light emitting element D1 is red light, the second color of light emitted by the second light emitting element D2 is blue light, and the third color of light emitted by the third light emitting element D3 is green light. Of course, in other embodiments, the colors of the first color of light, the second color of light, and the third color of light are not limited to the above cases. For example, in other embodiments, the colors of the light emitted by the plurality of light emitting elements in the pixel circuit provided by the embodiments of the present disclosure can include other colors in addition to red, green, and blue light. Under the design principle of the embodiments of the present disclosure, the types of light emitting elements can be adjusted as needed to adjust the colors of the light emitted by the light emitting elements.

[0101] For example, referring to FIG. 3, the pixel circuit 10 further includes a first data writing sub-circuit 501 and a second data writing sub-circuit 502. That is, the first sub-pixel circuit includes the first data writing sub-circuit 501, and the second sub-pixel circuit includes the second data writing sub-circuit 502. The first data writing sub-circuit 501 is configured to write the first data signal Data_A (or the third data signal Data_C) to the control end of the first driving sub-circuit 101 in response to the first data scanning signal G1, and the first driving sub-circuit 101 is configured to control the size of the driving current flowing through the first light emitting element D1 or the second light emitting element D2 according to the first data signal Data_A (or the third data signal Data_C); the second data writing sub-circuit 502 is configured to write the second data signal Data_B to the control end of the second driving sub-circuit 102 in response to the second data scanning signal G5, and the second driving sub-circuit 102 is configured to control the size of the driving current flowing through the third light emitting element D3 according to the second data signal Data_B. The first data signal Data_A, the third data signal Data_C, and the second data signal Data_B can be used to control the light emitting brightness of the corresponding light emitting element by controlling the size of the driving current, thereby controlling the display gray scale of the display panel using the pixel circuit.

[0102] For example, the second data scanning signal G5 and the first data scanning signal G1 can be the same signal. Of course, in other embodiments, the second data scanning signal G5 and the first data scanning signal G1 can also be signals that are controlled by separate control ends and do not affect each other.

[0103] For example, with reference to FIG. 3, the pixel circuit 10 further includes a first data storage sub-circuit 601 and a second data storage sub-circuit 602. That is, the first sub-pixel circuit includes the first data storage sub-circuit 601, and the second sub-pixel circuit includes the second data storage sub-circuit 602. The first data write-in sub-circuit 501 is electrically connected to a first terminal of the first data storage sub-circuit 601, and the first data storage sub-circuit 601 is configured to transmit a first data signal Data_A to the first terminal of the first data storage sub-circuit 601 in response to a first data scan signal G1; the first drive sub-circuit 101 includes a control terminal, a first terminal and a second terminal, the control terminal of the first drive sub-circuit 101 is electrically connected to the first terminal of the first data storage sub-circuit 601, the first terminal of the first drive sub-circuit 101 is configured to receive a first power voltage VDD, and the second terminal of the first drive sub-circuit 101, the second terminal of the first data storage sub-circuit 601, a first electrode of the first light emitting element D1 and a first terminal of the first gate sub-circuit 201 are electrically connected to a second node N2; the second data write-in sub-circuit 502 is electrically connected to a first terminal of the second data storage sub-circuit 602, and is configured to transmit a second data signal Data_B to the first terminal of the second data storage sub-circuit 602 in response to a second data scan signal G5; the second drive sub-circuit 102 includes a control terminal, a first terminal and a second terminal, the control terminal of the second drive sub-circuit 102 is electrically connected to the first terminal of the second data storage sub-circuit 602, the first terminal of the second drive sub-circuit 102 is configured to receive the first power voltage VDD, and the second terminal of the second drive sub-circuit 102, the second terminal of the second data storage sub-circuit 602 and a first electrode of the third light emitting element D3 are electrically connected to a third node N3. A second electrode of the second light emitting element D2 and a second electrode of the third light emitting element D3 are configured to receive a second power voltage VSS.

[0104] Thus, the first data written into the first data writing sub-circuit 501 can be stored in the first data storage sub-circuit 601 as the first data signal Data_A written into the control terminal of the first driving sub-circuit 101, so that, for example, in the first light emitting stage, the first driving current driving the first light emitting element D1 to emit light can be generated according to the first data signal Data_A to drive the first light emitting element D1 to emit light of the first color; in the second light emitting stage, the second driving current driving the second light emitting element D2 to emit light can be generated according to the third data signal Data_C to drive the second light emitting element D2 to emit light of the second color, and the first light emitting element D1 or the second light emitting element D2 can be optionally made to emit light as described above. Also, the second data signal Data_B written into the control terminal of the second driving sub-circuit 102 via the second data writing sub-circuit 502 can be stored in the second data storage sub-circuit 602, so that in the first light emitting stage or the second light emitting stage, the third driving current driving the third light emitting element D3 to emit light can be generated according to the second data signal Data_B to drive the third light emitting element D3 to emit light as well, for example, the third light emitting element D3 to emit light of the third color. The first color, the second color and the third color are different from each other, and the first light emitting stage and the second light emitting stage are two different light emitting stages in the display period of the same frame image, so that time-division driving is realized, and the three light emitting elements of the pixel circuit emit light of different colors in two different light emitting stages in the display period of the same frame image, realizing color display.

[0105] For example, the first power supply voltage is, for example, a high power supply voltage VDD, and the second power supply voltage is, for example, a low power supply voltage VSS. For example, the second power supply voltage terminal is a ground terminal.

[0106] Specifically, for example, with reference to FIG. 3, the first driving sub-circuit 101 includes a first driving transistor T2 configured to control a current for driving the first light emitting element D1 to emit light under control of a voltage at a gate of the first driving transistor T2, a first electrode of the first driving transistor T2 configured to receive a first power supply voltage VDD, a second electrode of the first driving transistor T2 electrically connected with a first electrode of the first light emitting element D1, a second electrode of the second light emitting element D2 configured to receive a second power supply voltage; the second driving sub-circuit 102 includes a second driving transistor T9 configured to control a current for driving the third light emitting element D3 to emit light under control of a voltage at a gate of the second driving transistor T9, a first electrode of the second driving transistor T9 configured to receive the first power supply voltage VDD, a second electrode of the second driving transistor T9 electrically connected with a first electrode of the third light emitting element D3, a second electrode of the third light emitting element D3 configured to receive the second power supply voltage; the first data storage sub-circuit 601 includes a first data storage capacitor CstA, a first electrode of the first data storage capacitor CstA electrically connected with the gate of the first driving transistor T2, a second electrode of the first data storage capacitor CstA electrically connected with the second electrode of the first driving transistor T2, the first electrode of the first light emitting element D1, and the first electrode of the first selection transistor T5, all of which are electrically connected with a second node N2; the second data storage sub-circuit 602 includes a second data storage capacitor CstB, a first electrode of the second data storage capacitor CstB electrically connected with the gate of the second driving transistor T9, a second electrode of the second data storage capacitor CstB, the second electrode of the first driving transistor T2, and the first electrode of the first light emitting element D1, all of which are electrically connected with a third node N3.

[0107] For example, with reference to FIG. 3, the first data writing sub-circuit 501 includes a first data transistor T1, a first electrode of the first data transistor T1 electrically connected with the first electrode of the first data storage capacitor CstA and the gate of the first driving transistor T2, a second electrode of the first data transistor T1 configured to receive a first data signal Data_A or a third data signal Data_C, the first data transistor T1 configured to write the first data signal Data_A or the third data signal Data_C to the gate of the first driving transistor T2 and the first data storage capacitor CstA in response to a first data scan signal G1; the second data writing sub-circuit 502 includes a second data transistor T8, a first electrode of the second data transistor T8 electrically connected with the first electrode of the second data storage capacitor CstB and the gate of the second driving transistor T9, a second electrode of the second data transistor T8 configured to receive a second data signal Data_B, the second data transistor T8 configured to write the second data signal Data_B to the gate of the second driving transistor T9 and the second data storage capacitor CstB in response to a second data scan signal G5.

[0108] For example, referring to FIG. 3, the first sub-pixel circuit further comprises a first sensing sub-circuit 701. The first end of the first sensing sub-circuit 701 is electrically connected to the first electrode of the first light emitting element D1, the control end of the first sensing sub-circuit 701 is configured to receive a first sensing scan signal G2, and the second end of the first sensing sub-circuit 701 is electrically connected to a first sensing signal line to receive a first sensing signal Sense1. The first sensing signal Sense1 can come from a first external detection circuit, for example, the first sensing signal line is electrically connected to the first external detection circuit, and the first sensing sub-circuit 701 is configured to detect the electrical characteristics of the sub-pixel to which it belongs through the first external detection circuit in response to the first sensing scan signal G2 to achieve compensation. The second sub-pixel circuit further comprises a second sensing sub-circuit 702, the first end of the second sensing sub-circuit 702 is electrically connected to the first electrode of the third light emitting element D3, the control end of the second sensing sub-circuit 702 is configured to receive a second sensing scan signal G6, and the second end of the second sensing sub-circuit 702 is electrically connected to a second sensing signal line to receive a second sensing signal Sense2. The second sensing signal Sense2 can come from a second external detection circuit, for example, the second sensing signal line is electrically connected to the second external detection circuit, and the second sensing sub-circuit 702 is configured to detect the electrical characteristics of the sub-pixel to which it belongs through the second external detection circuit in response to the second sensing scan signal G6 to achieve compensation. For example, the first external detection circuit and the second external detection circuit can be the same circuit, or different circuits that work independently.

[0109] For example, the "electrical characteristics of the sub-pixel" here include at least one of the threshold voltage and / or the carrier mobility of the first driving transistor T2 and / or the second driving transistor T9, and / or the driving current of the first light emitting element D1 and / or the second light emitting element D2 and / or the third light emitting element D3. The first external detection circuit is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), and the method of detection and compensation will be introduced later.

[0110] For example, the second sensing scan signal G6 and the first sensing scan signal G2 can be the same signal. Of course, in other embodiments, the second sensing scan signal G6 and the first sensing scan signal G2 can also be signals that are controlled by their own control ends and do not affect each other.

[0111] For example, referring to FIG. 3, the first sensing sub-circuit 701 includes a first sensing transistor T3, a first electrode of the first sensing transistor T3 is electrically connected with a first electrode of the first light emitting element D1, a second electrode of the first sensing transistor T3 is electrically connected with a first sensing signal line to be connected to a first external detection circuit, a gate electrode of the first sensing transistor T3 is configured to receive a first sensing scan signal G2, and the first sensing transistor T3 is configured to detect an electrical characteristic of a sub-pixel belonging to the first sensing transistor T3 through the first external detection circuit in response to the first sensing scan signal G2 to achieve external compensation; the second sensing sub-circuit 702 includes a second sensing transistor T10, a first electrode of the second sensing transistor T10 is electrically connected with a first electrode of the third light emitting element D3, a second electrode of the second sensing transistor T10 is electrically connected with a second sensing signal line to be connected to a second external detection circuit, a gate electrode of the second sensing transistor T10 is configured to receive a second sensing scan signal G6, and the second sensing transistor T10 is configured to detect an electrical characteristic of a sub-pixel belonging to the second sensing transistor T10 through the second external detection circuit in response to the second sensing scan signal G6 to achieve external compensation.

[0112] The driving method of the pixel circuit provided in at least one embodiment of the present disclosure is also provided. In the driving method of the pixel circuit provided in at least one embodiment of the present disclosure, a display period of one frame includes at least two time periods, and the driving method includes: controlling the first light emitting element D1 and the second light emitting element D2 to emit light in different time periods by controlling a first gate signal DA applied to a driving end of the first gating sub-circuit 201 and a second gate signal DB applied to a driving end of the second gating sub-circuit 202. In this way, the driving method can drive at least two light emitting elements to emit light in different time periods, for example, to emit light of different colors in different time periods, so as to realize color display, and the structure of the pixel circuit and the driving method can be simplified. On this basis, the third light emitting element D3 can also be controlled to emit light at the same time as at least one of the first light emitting element D1 and the second light emitting element D2, so as to realize that one pixel emits light of three colors in the display period of one frame, and realize color display.

[0113] FIG. 4 is a timing diagram of a control method of the pixel circuit shown in FIG. 3. The driving method of the pixel circuit shown in FIG. 3 will be described below in combination with FIG. 3 and FIG. 4.

[0114] Referring to FIG. 3 and FIG. 4, for example, the at least two time periods included in the display period of one frame include a first time period 1 and a second time period 2, in the first time period 1, one of the first light emitting element D1 and the second light emitting element D2 emits light of a first color, and in the second time period 2, the other of the first light emitting element D1 and the second light emitting element D2 emits light of a second color.

[0115] For example, for the pixel circuit shown in FIG. 3, the light emitting colors of the first light emitting element D1, the second light emitting element D2 and the third light emitting element D3 are different from each other; referring to FIG. 3 and FIG. 4, the first time period 1 includes a first light emitting stage t3, and the second time period 2 includes a second light emitting stage t6; in the first light emitting stage t3, the third light emitting element D3 emits light with one of the first light emitting element D1 and the second light emitting element D2; in the second light emitting stage t6, the third light emitting element D3 emits light with the other of the first light emitting element D1 and the second light emitting element D2.

[0116] For example, here, the first time period 1 is the first 1 / 2 frame (1 / 2 Frame), and the second time period 2 is the second 1 / 2 frame (1 / 2 Frame), which is advantageous for obtaining better color display effect and reducing the difficulty of control. Of course, it is not limited to this case, the time lengths of the first time period 1 and the second time period 2 can also be unequal, and the time lengths of each light emitting stage can be equal or unequal, for example, the light emitting time lengths of the light emitting elements emitting light of different colors can be adjusted according to the differences between the characteristics of the light emitting elements of different colors, so as to perform color balance, and the specific light emitting time length of each light emitting element can be designed as needed, and the embodiments of the present disclosure are not limited thereto.

[0117] FIG. 5A is a schematic diagram of the circuit conduction state of the first reset stage of the first time period shown in FIG. 4. Here, the transistors of the pixel circuit in FIG. 3 are all N-type transistors, which are turned on in response to a high potential and turned off in response to a low potential.

[0118] In combination with FIGS. 3-4 and FIG. 5A, the first period 1 includes a first reset stage t1. In the first reset stage t1, the second gate control signal G4 is an on signal to make the first end and the second end of the second gate control sub-circuit 302 conductive, the second gate signal DB written to the control end of the second gate sub-circuit 202 through the second gate control sub-circuit 302 is an off signal to make the first end and the second end of the second gate sub-circuit 202 not conductive, the first gate control signal G3 is an on signal to make the first end and the second end of the first gate control sub-circuit 301 conductive, the first gate signal DA written to the control end of the first gate sub-circuit 201 through the first gate control sub-circuit 301 is an on signal to make the first end and the second end of the first gate sub-circuit 201 conductive via the first gate sub-circuit 201; and at this time, the first sensing scan signal G2 is an on signal to make the first end and the second end of the first sensing sub-circuit 701 conductive, the first reset signal Vinit1 is input to the second end of the first sensing sub-circuit 701 (it can be understood that the first sensing signal Sense1 at this moment is the first reset signal Vinit1), and the first reset signal Vinit1 is applied to the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 via the first sensing sub-circuit 701, the first electrode of the first light emitting element D1, the first end and the second end of the first gate sub-circuit 201, to reset the electrical signal of the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2, i.e., to reset the second node N2 and the first node N1. In the first reset stage t1, the first end and the second end of the second gate sub-circuit 202 are not conductive, the second gate transistor T7 is turned off, and simultaneous resetting of N1 by the second power supply voltage Vss and the first reset signal Vinit1 can be prevented.

[0119] Specifically, for the pixel circuit shown in FIG. 3, in the first reset stage t1, the first gate control signal G3 and the second gate control signal G4 are both on signals, so that the first gate control transistor T4 and the second gate control transistor T6 are both turned on, the first gate signal DA is written to the gate of the first gate transistor T5 via the first gate control transistor T4, the first gate signal DA is an on signal to turn on the first gate transistor T5, and the second gate signal DB is written to the gate of the second gate transistor T7 via the second gate control transistor T6, the second gate signal DB is an off signal to turn off the second gate transistor T7. The first sensing scan signal G2 written to the gate of the first sensing transistor T3 is an on signal to turn on the first sensing transistor T3, so that the first reset signal Vinit1 is applied to the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 via the first sensing transistor T3 and the first gate transistor T5, to reset the electrical signal of the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2, i.e., to reset the second node N2 and the first node N1.

[0120] And in the first reset stage t1, the second sensing scan signal G6 is an on signal to turn on the first end and the second end of the second sensing sub-circuit 702, the second reset signal Vinit2 is applied to the first electrode of the third light emitting element D3 via the second end of the second sensing sub-circuit 702 (it can be understood that the second sensing signal Sense2 at this time is the second reset signal Vinit2), to reset the electrical signal of the first electrode of the third light emitting element D3, i.e., to reset the third node N3. Specifically, the second sensing scan signal G6 written to the gate of the second sensing transistor T10 is an on signal to turn on the second sensing transistor T10, so that the second reset signal Vinit2 is applied to the first electrode of the third light emitting element D3 via the second sensing transistor T10, to reset the electrical signal of the first electrode of the third light emitting element D3, i.e., to reset the third node N3.

[0121] For example, in the first reset stage t1, the first data scan signal G1 is an on signal, so that the first data write sub-circuit 501 is turned on, and the first data signal Data_A is written to the control terminal of the first drive sub-circuit 101 via the first data write sub-circuit 501. For example, the first data scan signal G1 written to the gate of the first data transistor T1 is an on signal, so that the first data transistor T1 is turned on, and the first data signal Data_A is written to the gate of the first drive transistor T2 via the first data transistor T1. If T1 is turned on after the reset is completed, the data writing will be coupled, which will affect the display gray scale. Therefore, the data signal, for example, the first data signal Data_A, used to control the display gray scale of the pixel is written in the first reset stage t1, which can prevent the display gray scale from being affected. The same is true in the subsequent second reset stage t2.

[0122] Of course, in the first reset stage t1, the first data scan signal G1 can also be an off signal, that is, the first data transistor T1 is kept off in the first reset stage t1, and the first data signal is not written.

[0123] Similarly, in the first reset stage t1, the second data scan signal G5 can be an on signal or an off signal, and the second data transistor T8 is kept off in the first reset stage t1, and the second data signal is not written.

[0124] FIG. 5B is a schematic diagram of the circuit conduction state of the first gating and data writing stage t2 of the first period shown in FIG. 4. For example, with reference to FIG. 4 and FIG. 5B, the first period 1 further includes the first gating and data writing stage t2 after the first reset stage t1, and the first light-emitting stage t3 after the first gating and data writing stage t2, that is, the first reset stage t1 is before the first gating and data writing stage t2; the second period 2 further includes the second gating and data writing stage t5 after the second reset stage t4, and the second light-emitting stage t6 after the second gating and data writing stage t5, that is, the second reset stage t2 is before the second gating and data writing stage t5.

[0125] For example, referring to FIG. 4, in the first gate and data writing stage t2 and the second gate and data writing stage t5, the first gate control signal G3 and the second gate control signal G4 are both on signals, so that the first gate signal DA is written to the control terminal of the first gate sub-circuit 201 through the first gate control sub-circuit 301, and the second gate signal DB is written to the control terminal of the second gate sub-circuit 202 through the second gate control sub-circuit 302. And, in the first gate and data writing stage t2 and the second gate and data writing stage t5, the first gate signal DA and the second gate signal DB are both signals opposite to each other, so that one of the first gate sub-circuit 201 and the second gate sub-circuit 202 is turned on, and the other one of the first gate sub-circuit 201 and the second gate sub-circuit 202 is turned off, so that in the first light emitting stage t3 and the second light emitting stage t6, the light emitting element in parallel with the turned-on one does not emit light and the light emitting element in parallel with the turned-off one does not emit light, so that the first light emitting element and the second light emitting element can emit light in time division, so that pixel merging and color display can be realized.

[0126] In the present disclosure, the "opposite signals" refer to one of which is an on signal for turning on the driving transistor, and the other is an off signal for turning off the driving transistor. For example, for an N-type transistor, the on signal is a high-level signal, and the off signal is a low-level signal; for a P-type transistor, the on signal is a low-level signal, and the off signal is a high-level signal.

[0127] For example, referring to FIG. 4 and FIG. 5B, in the first gate and data writing stage t2, the first gate control signal G3 and the second gate control signal G4 are both on signals, so that the first gate control transistor T4 and the second gate control transistor T6 are both turned on, the first gate signal DA is written to the gate of the first gate transistor T5 through the first gate control transistor T4, and the second gate signal DB is written to the gate of the second gate transistor T7 through the second gate control transistor T6; the first gate signal DA is an off signal, for example, a low-level signal, and the second gate signal DB is an on signal, for example, a high-level signal, so that the first gate sub-circuit 201 is turned off, that is, the first gate transistor T5 is turned off, and the second gate sub-circuit 202 is turned on, that is, the second gate transistor T7 is turned on. And, in the first gate and data writing stage t2, the first gate signal DA is written to the first gate storage capacitor Cst1 through the first gate control transistor T4 and stored in the first gate storage capacitor Cst1, and the second gate signal DB is written to the second gate storage capacitor Cst2 through the second gate control transistor T6 and stored in the second gate storage capacitor Cst2.

[0128] For example, in the first gate-on and data write stage t2, the first data signal Data_A is written for controlling the gray scale of the first color. In the first gate-on and data write stage t2, the first data scan signal G1 is an on signal, so that the first data write sub-circuit 501 is turned on, for example, the first data transistor T1 is turned on, the first data signal Data_A is written to the control terminal of the first drive sub-circuit 101 via the first data write sub-circuit 501 (for example, via the first data transistor T1), for example, to the gate of the first drive transistor T2, that is, the first data signal Data_A is transmitted to the gate of the first drive transistor T2 via the first data transistor T1; for example, the first reset signal Vinit1 is written to the second node N2 via the first sensing signal line and the first sensing transistor T3 by an analog-to-digital converter, for example, the first reset signal Vinit1 is a constant voltage, the first drive transistor T2 is turned on and generates a first drive current to charge the second node N2 to the working voltage of the first light emitting element D1; and the first data signal Data_A is stored into the first data storage sub-circuit 601 via the first data transistor T1, for example, in the first data storage capacitor CstA.

[0129] And, referring to FIGS. 3-4 and 5B, in the driving method of the pixel circuit 10, in the first gate-on and data write stage t2, the second data scan signal G5 is an on signal, so that the second data write sub-circuit 502 is turned on, that is, the second data transistor T8 is turned on, thereby writing the second data signal Data_B to the control terminal of the second drive sub-circuit 102 via the second data write sub-circuit 502, for example, the second data signal Data_B is transmitted to the gate of the second drive transistor T9 via the second data transistor T8; for example, the second reset signal Vinit2 is written to the third node N3 via the second sensing signal line and the second sensing transistor T10 by an analog-to-digital converter, for example, the second reset signal Vinit2 is a constant voltage, the second drive transistor T9 is turned on and generates a third drive current to charge the third node N3 to the working voltage of the third light emitting element D3; and the second data signal Data_B is stored into the second data storage sub-circuit 602 via the second data transistor T8, that is, the second data signal Data_B is stored into the second data storage capacitor CstB.

[0130] Referring to FIG. 4, the first time period 1 further includes a first light emitting stage t3, which is after the first gate and data writing stage t2. FIG. 5C is a circuit conduction state diagram of the first light emitting stage t3 of the first time period shown in FIG. 4. Referring to FIGS. 3-4 and 5C, in the driving method of the pixel circuit 10, in the first light emitting stage t3, the first data scanning signal G1, the first sensing scanning signal G2, the first gate control signal G3, and the second gate control signal G4 are all set as a turn-off signal, for example, all set as a low level, and the potential of the first gate node M1 is maintained by the first gate storage capacitor Cst1 as a low level; and the second data scanning signal G5 and the second sensing scanning signal G6 are set as a turn-off signal, for example, as a low level, and the potential of the second gate node M2 is maintained by the second gate storage capacitor Cst2 as a high level. Thus, as shown in FIG. 5C, the first gate transistor T5 is turned off, the second gate transistor T7 is turned on, and due to the bootstrap effect of the first data storage capacitor CstA, the potential of the gate of the first drive transistor T2 is maintained by the first data storage capacitor CstA, and the first drive transistor T2 is kept turned on. For example, the first drive transistor T2 works in a saturation state and the current is constant, and the second gate transistor T7 works in a linear region. Thus, the first light emitting path shown by the dashed arrow on the left side in FIG. 5C is formed. Therefore, in the first light emitting stage t3, the driving current will flow through the first light emitting element D1 without flowing through the second light emitting element D2 in parallel with the second gate sub-circuit 202, the first light emitting element D1 emits light, and the second light emitting element D2 does not emit light. Moreover, the first driving current for driving the first light emitting element D1 to emit light can be generated according to the first data signal Data_A to drive the first light emitting element D1 to emit light, for example, the first light emitting element D1 emits light of a first color, and different display gray scales are realized.

[0131] For example, in the first light emitting stage t3, the second data scanning signal G5 and the second sensing scanning signal G6 are both set as a turn-off signal, for example, both set as a low level. Due to the bootstrap effect of the second data storage capacitor CstB, the potential of the gate of the second drive transistor T9 is maintained by the second data storage capacitor CstB, and the second drive transistor T9 is kept turned on. For example, the second drive transistor T9 works in a saturation state and the current is constant. Thus, the second light emitting path shown by the dashed arrow on the right side in FIG. 5C is formed. Therefore, in the first light emitting stage t3, the third driving current for driving the third light emitting element D3 to emit light can be generated according to the second data signal Data_B to drive the third light emitting element D3 to also emit light, for example, the third light emitting element D3 emits light of a third color, and different display gray scales are realized.

[0132] For example, referring to FIG. 4, the second period 2 includes a second reset phase t4, a second gate and data write phase t5 after the second reset phase t4, and a second light emitting phase t6 after the second gate and data write phase t5.

[0133] FIG. 5D is a schematic diagram of the circuit conduction state of the second reset phase of the second period shown in FIG. 4. Referring to FIG. 4 and FIG. 5D, the second period 2 includes the second reset phase t4, and the timing and working process of the pixel circuit 10 in the second reset phase t4 is the same as that in the first reset phase t1, i.e., the second node N2 and the first node N1 are reset again.

[0134] FIG. 5E is a schematic diagram of the circuit conduction state of the second gate and data write phase t5 of the second period 2 shown in FIG. 4. Referring to FIG. 4 and FIG. 5E, in the second gate and data write phase t5, the first gate control signal G3 and the second gate control signal G4 are both on signals, so that the first gate control transistor T4 and the second gate control transistor T6 are both turned on, the first gate signal DA is written to the gate of the first gate transistor T5 via the first gate control transistor T4, and the second gate signal DB is written to the gate of the second gate transistor T7 via the second gate control transistor T6; the first gate signal DA is an on signal, e.g., a high-level signal, and the second gate signal DB is an off signal, e.g., a low-level signal, so that the first gate sub-circuit 201 is turned on, i.e., the first gate transistor T5 is turned on, and the second gate sub-circuit 202 is turned off, i.e., the second gate transistor T7 is turned off. Moreover, in the second gate and data write phase t5, the first gate signal DA is written to the first gate storage capacitor Cst1 via the first gate control transistor T4 and is stored in the first gate storage capacitor Cst1, and the second gate signal DB is written to the second gate storage capacitor Cst2 via the second gate control transistor T6 and is stored in the second gate storage capacitor Cst2.

[0135] For example, in the second gate-on and data write stage t5, the third data signal Data_C for controlling the gray scale of the second color is written, where the third data signal Data_C is a different data signal from the first data signal Data_A written in the first gate-on and data write stage t2, both of which can be written through the same data signal terminal and the same data signal line. In the second gate-on and data write stage t5, the first data scan signal G1 is an on signal, so that the first data write sub-circuit 501 is turned on, for example, the first data transistor T1 is turned on, the third data signal Data_C is written to the control terminal of the first drive sub-circuit 101 via the first data write sub-circuit 501 (for example, via the first data transistor T1), for example, to the gate of the first drive transistor T2, that is, the third data signal Data_C is transmitted to the gate of the first drive transistor T2 via the first data transistor T1; for example, the first reset signal Vinit1 is written to the second node N2 via the first sensing signal line and the first sensing transistor T3 by an analog-to-digital converter, for example, the first reset signal Vinit1 is a constant voltage, the first drive transistor T2 is turned on and generates a first drive current to charge the second node N2 to the operating voltage of the second light emitting element D2; and the third data signal Data_C is stored into the first data storage sub-circuit 601 via the first data transistor T1, for example, in the first data storage capacitor CstA.

[0136] In addition, with reference to FIGS. 3-4 and 5E, in the driving method of the pixel circuit 10, in the second gate-on and data write stage t5, the second data scan signal G5 is an on signal, so that the second data write sub-circuit 502 is turned on, that is, the second data transistor T8 is turned on, thereby writing the second data signal Data_B to the control terminal of the second drive sub-circuit 102 via the second data write sub-circuit 502, for example, the second data signal Data_B is transmitted to the gate of the second drive transistor T9 via the second data transistor T8; for example, the second reset signal Vinit2 is written to the third node N3 via the second sensing signal line and the second sensing transistor T10 by an analog-to-digital converter, for example, the second reset signal Vinit2 is a constant voltage, the second drive transistor T9 is turned on and generates a third drive current to charge the third node N3 to the operating voltage of the third light emitting element D3; and the second data signal Data_B is stored into the second data storage sub-circuit 602 via the second data transistor T8, that is, the second data signal Data_B is stored into the second data storage capacitor CstB.

[0137] Fig. 5F is a schematic diagram of the circuit conduction state of the second light emitting stage t6 of the second time period shown in Fig. 4. Referring to Figs. 3-4 and 5C, in the driving method of the pixel circuit 10, in the second light emitting stage t6, the first data scan signal G1, the first sensing scan signal G2, the first gate control signal G3, and the second gate control signal G4 are all off signals, for example, all are low level, the potential of the first gate node M1 is maintained by the first gate storage capacitor Cst1, for example, is high level, and the potential of the second gate node M2 is maintained by the second gate storage capacitor Cst2, for example, is low level. Thus, as shown in Fig. 5F, the first gate transistor T5 is turned on, the second gate transistor T7 is turned off, and due to the bootstrap effect of the first data storage capacitor CstA, the potential of the gate of the first drive transistor T2 is maintained by the first data storage capacitor CstA, and the first drive transistor T2 is kept on. For example, the first drive transistor T2 works in the saturation state and the current is constant, and the first gate transistor T5 works in the linear region. Thus, the third light emitting path shown by the left side of the dashed line with arrow in Fig. 5F is formed. Therefore, in the second light emitting stage t6, the driving current will flow through the second light emitting element D2 without flowing through the first light emitting element D1 in parallel with the second gate sub-circuit 202, the second light emitting element D2 emits light, and the first light emitting element D1 does not emit light. And the second driving current driving the second light emitting element D2 to emit light can be generated according to the first data signal Data_A written in the second data writing and compensation stage t5 to drive the second light emitting element D2 to emit light, for example, the second light emitting element D2 emits light of the second color, and different display gray scales are realized.

[0138] For example, in the second light emitting stage t6, the second data scan signal G5 and the second sensing scan signal G6 are both off signals, for example, both are low level. Due to the bootstrap effect of the second data storage capacitor CstB, the potential of the gate of the second drive transistor T9 is maintained by the second data storage capacitor CstB, and the second drive transistor T9 is kept on. For example, the second drive transistor T9 works in the saturation state and the current is constant. Thus, the second light emitting path shown by the right side of the dashed line with arrow in Fig. 5F is formed. Therefore, in the second light emitting stage t6, the third driving current driving the third light emitting element D3 to emit light can be generated according to the second data signal Data_B to drive the third light emitting element D3 to also emit light, for example, the third light emitting element D3 emits light of the third color, and different display gray scales are realized.

[0139] In the above embodiment, of course, the third light emitting element D3 emits light in both the first light emitting stage t3 and the second light emitting stage t6, in other embodiments, the third light emitting element D3 can also be caused to emit light only in the first light emitting stage t3 or only in the second light emitting stage t6. For example, the second data signal Data_B written to the gate of the second drive transistor T9 can be controlled to be an off signal to control the second drive transistor T9 to be off in the first light emitting stage t3 or the second light emitting stage t6, so that the third drive current flowing through the third light emitting element D3 is not generated, and the third light emitting element D3 does not emit light.

[0140] In the embodiments of the present disclosure, the first light emitting element D1 and the second light emitting element D2 can be selectively controlled to emit light in different light emitting stages by the above method, and the period of time when the third light emitting element D3 emits light is selectively controlled.

[0141] For example, in the embodiments shown in FIGS. 4 and 5A-5F, in the first period 1, the first light emitting element D1 and the third light emitting element D3 both emit light, emitting light of the first color and the third color respectively, and in the second period 2, the second light emitting element D2 and the third light emitting element D3 both emit light, emitting light of the second color and the third color respectively, so that color display is realized by time-division light emission.

[0142] Alternatively, in other embodiments, in the first period 1, the second light emitting element D2 and the third light emitting element D3 both emit light, emitting light of the second color and the third color respectively, and in the second period 2, the first light emitting element D1 and the third light emitting element D3 both emit light, emitting light of the first color and the third color respectively, so that color display is realized by time-division light emission.

[0143] Alternatively, in other embodiments, one of the first light emitting element D1 and the second light emitting element D2 emits light in one of the first period 1 and the second period 2, and the other of the first light emitting element D1 and the second light emitting element D2 emits light in the other of the first period 1 and the second period 2, on the basis of which the third light emitting element D3 emits light only in the first light emitting stage t3 or only in the second light emitting stage t6.

[0144] By controlling whether the first selection signal DA and the second selection signal DB are off signals or on signals in the first selection and data writing stage t2 and the second selection and data writing stage t5, the light emitting order of the first light emitting element and the second light emitting element can be exchanged by similar principles as the above driving method, and the present disclosure does not limit the order of the first light emitting element and the second light emitting element.

[0145] For example, in other embodiments, in the first reset stage t1, the first data signal Data_A for controlling the gray scale of the first color can also be written. Similarly, in the second reset stage t4, the second data signal Data_B for controlling the gray scale of the second color can also be written.

[0146] FIG. 6 is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure. The pixel circuit shown in FIG. 6 is different from the pixel circuit shown in FIG. 3 in that the second sub-pixel circuit of the pixel circuit 10 shown in FIG. 6 has a similar structure as the first sub-pixel circuit, and the first sub-pixel circuit and the second sub-pixel circuit each include two light emitting elements, and the two light emitting elements are controlled to emit light in time division, so that more light emitting elements are controlled to emit light in time division on the basis of realizing color display, pixel merging is realized, and the structure of the pixel capable of emitting multiple color light is simplified.

[0147] Referring to FIG. 6, the second sub-pixel circuit of the pixel circuit 10 includes a second driving sub-circuit 102, a third light emitting element D3, and a fourth light emitting element D4, the second driving sub-circuit 102 is configured to control the size of the driving current flowing through the third light emitting element D3 or the size of the driving current flowing through the fourth light emitting element D4; the second electrode of the third light emitting element D3 and the first electrode of the fourth light emitting element D4 are electrically connected, the first electrode of the third light emitting element D3 is configured to receive a first power voltage VDD, and the second electrode of the fourth light emitting element D4 is configured to receive a second power voltage VSS; the light emitting colors of the first light emitting element D1, the second light emitting element D2, the third light emitting element D3, and the fourth light emitting element D4 are different from each other; the third gating sub-circuit 203 is connected in parallel with the third light emitting element D3, and is configured to determine whether the driving current flows through the third light emitting element D3 in response to a third gate signal DC applied to the driving end of the third gating sub-circuit 203; the fourth gating sub-circuit 204 is connected in parallel with the fourth light emitting element D4, and is configured to determine whether the driving current flows through the fourth light emitting element D4 in response to a fourth gate signal DD applied to the driving end of the fourth gating sub-circuit 204. That is, since the third gating sub-circuit 203 is connected in parallel with the third light emitting element D3, and the fourth gating sub-circuit 204 is connected in parallel with the fourth light emitting element D4, in one light emitting stage, one of the third gating sub-circuit 203 and the fourth gating sub-circuit 204 is turned on, and the other is turned off, so that the one turned on can be equivalent to a wire, the light emitting element connected in parallel with the one turned on does not emit light, and the light emitting element connected in parallel with the one turned off emits light.

[0148] Thus, in the first sub-pixel circuit and the second sub-pixel circuit, at least two light emitting elements are driven to emit light at different time periods, for example, to emit light of different colors at different time periods, to realize color display, and the structure of the pixel circuit and the driving method can be simplified, and pixel merging is further realized. In the pixel circuit 10 shown in FIG. 6, the first light emitting element D1 and the second light emitting element D2 of the first sub-pixel circuit emit light at different time periods, the third light emitting element D3 and the fourth light emitting element D4 of the second sub-pixel circuit emit light at different time periods, and the first sub-pixel circuit and the second sub-pixel circuit are independently controlled, so that any one of the first light emitting element D1 and the second light emitting element D2 and any one of the third light emitting element D3 and the fourth light emitting element D4 can emit light at the same time, so that the combination of light of four different colors can be realized by causing the four light emitting elements D1-D4 to emit light of four different colors, which not only realizes color display, but also meets more requirements for display color.

[0149] Thus, in the first sub-pixel circuit and the second sub-pixel circuit, pixel merging is realized, the structure of the traditional pixel circuit realizing two-color light emitting elements is simplified, and the area occupied by one pixel realizing multi-color light emitting can be reduced. Therefore, the pixel circuit provided by the embodiments of the present disclosure can realize higher PPI, and simplifying the circuit structure is also beneficial to increasing the aperture ratio of the pixel, improving the product life, increasing the yield and refresh rate of the product, and reducing the hardware cost of the product, thereby providing a wider design space for the layout optimization of the signal lines of the pixel circuit.

[0150] For example, the first color of light emitted by the first light emitting element D1 is red light, the second color of light emitted by the second light emitting element D2 is blue light, the third color of light emitted by the third light emitting element D3 is white light, and the fourth color of light emitted by the fourth light emitting element D4 is green light. Of course, in other embodiments, the colors of the first color of light, the second color of light, the third color of light, and the fourth color of light can be arbitrarily interchanged, or are not limited to the above four colors. According to the design principle of the embodiments of the present disclosure, the colors of light emitted by the light emitting elements can be adjusted as needed.

[0151] For example, referring to FIG. 6, the first end of the third gating sub-circuit 203 is electrically connected to the first electrode of the third light emitting element D3, the second end of the third gating sub-circuit 203, the second electrode of the third light emitting element D3, the first electrode of the fourth light emitting element D4, and the first end of the fourth gating sub-circuit 204 are electrically connected to the fourth node N4; and the second end of the fourth gating sub-circuit 204 is electrically connected to the second electrode of the fourth light emitting element D4. Thus, the third gating sub-circuit 203 is connected in parallel with the third light emitting element D3, and the fourth gating sub-circuit 204 is connected in parallel with the fourth light emitting element D4.

[0152] For example, referring to FIG. 6, the third light emitting element D3 and the fourth light emitting element D4 can each also be an OLED element. For example, the first electrode of the third light emitting element D3 and the first electrode of the fourth light emitting element D4 are each an anode, and the second electrode of the third light emitting element D3 and the second electrode of the fourth light emitting element D4 are each a cathode; or, in some embodiments, the first electrode of the third light emitting element D3 and the first electrode of the fourth light emitting element D4 are each a cathode, and the second electrode of the third light emitting element D3 and the second electrode of the fourth light emitting element D4 are each an anode. The same is true, for example, for the third light emitting element D2 and the fourth light emitting element D4 described below.

[0153] For example, referring to FIG. 6, the first sub-pixel circuit further comprises a third gate control sub-circuit 303 and a fourth gate control sub-circuit 304. The third gate control sub-circuit 303 is configured to apply a third gate signal DC to the driving end of the third gate sub-circuit 203 in response to a third gate control signal G7 applied to the control end of the third gate control sub-circuit 303; the driving end of the third gate control sub-circuit 303 is electrically connected to the third gate control end to receive the third gate control signal G7, the first end of the third gate control sub-circuit 303 is connected to the third gate signal DC end to receive the third gate signal DC, and the second end of the third gate control sub-circuit 303 is electrically connected to the driving end of the third gate sub-circuit 203; the fourth gate control sub-circuit 304 is configured to apply a fourth gate signal DD to the driving end of the fourth gate sub-circuit 204 in response to a fourth gate control signal G8 applied to the control end of the fourth gate control sub-circuit 304; the driving end of the fourth gate control sub-circuit 304 is electrically connected to the fourth gate control end to receive the fourth gate control signal G8, the first end of the fourth gate control sub-circuit 304 is connected to the fourth gate signal DD end to receive the fourth gate signal DD, and the second end of the fourth gate control sub-circuit 304 is electrically connected to the driving end of the fourth gate sub-circuit 204. In this way, the third gate control sub-circuit 303 and the fourth gate control sub-circuit 304 can be controlled to turn on and off by the third gate control signal G7 and the fourth gate control signal G8. When both are turned on, the third gate signal DC and the fourth gate signal DD are written to the driving end of the third gate sub-circuit 203 and the driving end of the fourth gate sub-circuit 204, respectively, to control the turning on and off of the third gate sub-circuit 203 and the fourth gate sub-circuit 204 by the third gate signal DC and the fourth gate signal DD. In the light-emitting stage, one of the third gate sub-circuit 203 and the fourth gate sub-circuit 204 can be turned on, and the other can be turned off. The one that is turned on can be equivalent to a wire, so that the driving current flows through the one that is turned on and does not flow through the light-emitting element connected in parallel with the one that is turned on, so that the light-emitting element connected in parallel with the one that is turned on does not emit light, while the driving current flows through the light-emitting element connected in parallel with the other that is turned off, so that the light-emitting element connected in parallel with the other that is turned off emits light.

[0154] For example, the third gate signal end and the fourth gate signal end can be the same signal end, and the third gate control signal G7 and the fourth gate control signal G8 can be the same signal.

[0155] For example, the first gate signal end, the second gate signal end, the third gate signal end, and the fourth gate signal end can all be the same signal end, and the first gate control signal G3 and the second gate control signal G4, the third gate control signal G7 and the fourth gate control signal G8 can be the same signal.

[0156] Of course, in other embodiments, the first gate control signal G3, the second gate control signal G4, the third gate control signal G7 and the fourth gate control signal G8 can also be mutually independent signals controlled by control terminals independent of each other.

[0157] For example, referring to FIG. 6, the pixel circuit 10 further includes a third gate storage sub-circuit 403 and a fourth gate storage sub-circuit 404. The third gate storage sub-circuit 403 is configured to transmit a third gate signal DC to a first end of the third gate storage sub-circuit 403 in response to a third gate control signal G7, wherein the first end of the third gate storage sub-circuit 403 is electrically connected to the third gate node M3 with the driving end of the third gate sub-circuit 203 and the second end of the third gate control sub-circuit 303, and the second end of the third gate storage sub-circuit 403 is connected to the first power supply end to receive the first power supply voltage VDD; the fourth gate storage sub-circuit 404 is configured to transmit a fourth gate signal DD to a first end of the fourth gate storage sub-circuit 404 in response to a fourth gate control signal G8; the first end of the fourth gate storage sub-circuit 404 is electrically connected to the fourth gate node M4 with the driving end of the fourth gate sub-circuit 204 and the second end of the fourth gate control sub-circuit 304, and the second end of the fourth gate storage sub-circuit 404 is connected to the first power supply end to receive the first power supply voltage VDD. In this way, the third gate signal DC can be stored in the third gate storage sub-circuit 403, and the fourth gate signal DD can be stored in the fourth gate storage sub-circuit 404, so that in a certain stage, for example, in the light emitting stage, the stored third gate signal DC and the fourth gate signal DD are used to keep the third gate sub-circuit 203 and the fourth gate sub-circuit 204 in the open state or the closed state, respectively, to achieve the above-mentioned selective control of different light emitting elements (the third light emitting element D3 or the fourth light emitting element D4) to emit light.

[0158] Specifically, referring to FIG. 6, for example, the third gate sub-circuit 203 includes a third gate transistor T12, the gate of the third gate transistor T12 serving as the driving end of the third gate sub-circuit 203, the first pole of the third gate transistor T12 being electrically connected with the first electrode of the third light emitting element D3, and the second pole of the third gate transistor T12 being electrically connected with the second electrode of the third light emitting element D3; the fourth gate sub-circuit 204 includes a fourth gate transistor T14, the gate of the fourth gate transistor T14 serving as the driving end of the fourth gate sub-circuit 204, the first pole of the fourth gate transistor T14 being electrically connected with the first electrode of the fourth light emitting element D4, and the second pole of the fourth gate transistor T14 being electrically connected with the second electrode of the fourth light emitting element D4.

[0159] Referring to FIG. 6, for example, the third gating control sub-circuit 303 includes a third gating control transistor T11, a gate of the third gating control transistor T11 is electrically connected to the third gating control terminal to receive the third gating control signal G7, a first pole of the third gating control transistor T11 is connected to the third gating signal DC terminal to receive the first gating signal DA, and a second pole of the third gating control transistor T11 is electrically connected to a gate of a third gating transistor T12; the fourth gating control sub-circuit 304 includes a fourth gating control transistor T13, a gate of the fourth gating control transistor T13 is electrically connected to the fourth gating control terminal to receive the fourth gating control signal G8, a first pole of the fourth gating control transistor T13 is connected to the fourth gating signal DD terminal to receive the fourth gating signal DD, and a second pole of the fourth gating control transistor T13 is electrically connected to a gate of a fourth gating transistor T14.

[0160] Referring to FIG. 6, for example, the third gating control sub-circuit 303 includes a third gating control transistor T11, a gate of the third gating control transistor T11 is electrically connected to the third gating control terminal to receive the third gating control signal G7, a first pole of the third gating control transistor T11 is connected to the third gating signal DC terminal to receive the first gating signal DA, and a second pole of the third gating control transistor T11 is electrically connected to a gate of a third gating transistor T12; the fourth gating control sub-circuit 304 includes a fourth gating control transistor T13, a gate of the fourth gating control transistor T13 is electrically connected to the fourth gating control terminal to receive the fourth gating control signal G8, a first pole of the fourth gating control transistor T13 is connected to the fourth gating signal DD terminal to receive the fourth gating signal DD, and a second pole of the fourth gating control transistor T13 is electrically connected to a gate of a fourth gating transistor T14.

[0161] For example, referring to FIG. 6, the second sub-pixel circuit of the pixel circuit 10 further includes a second data writing sub-circuit 502. The second data writing sub-circuit 502 is configured to write a second data signal Data_B (or a fourth data signal Data_D) to a control terminal of the second driving sub-circuit 102 in response to a second data scanning signal G5, and the second driving sub-circuit 102 is configured to control the size of the driving current flowing through the third light emitting element D3 or the fourth light emitting element D4 according to the second data signal Data_B (or the fourth data signal Data_D). The second data signal Data_B and the fourth data signal Data_D can be used to control the luminance of the corresponding light emitting element by controlling the size of the driving current, thereby controlling the display gray scale of the display panel using the pixel circuit.

[0162] For example, referring to FIG. 6, the second sub-pixel circuit of the pixel circuit 10 further includes a second data storage sub-circuit 602. The second data write-in sub-circuit 502 is electrically connected to a first end of the second data storage sub-circuit 602, and is configured to transmit a second data signal Data_B to the first end of the second data storage sub-circuit 602 in response to a second data scan signal G5; the second drive sub-circuit 102 includes a control end, a first end and a second end, the control end of the second drive sub-circuit 102 is electrically connected to the first end of the second data storage sub-circuit 602, the first end of the second drive sub-circuit 102 is configured to receive a first power voltage VDD, the second end of the second drive sub-circuit 102, the second end of the second data storage sub-circuit 602, the first electrode of the third light emitting element D3 and the first end of the third gate sub-circuit 203 are electrically connected to a third node N3. The second electrode of the fourth light emitting element D4 is configured to receive a second power voltage VSS.

[0163] In this way, the first data signal Data_A or the third data signal Data_C written into the control end of the first drive sub-circuit 101 via the first data write-in sub-circuit 501 can be stored in the first data storage sub-circuit 601, and the second data signal Data_B or the fourth data signal Data_D written into the control end of the second drive sub-circuit 102 via the second data write-in sub-circuit 502 can be stored in the second data storage sub-circuit 602, so as to be used for controlling the corresponding light emitting element to emit light in the corresponding light emitting phase.

[0164] For example, in the first light emitting stage, a first drive current driving the first light emitting element D1 to emit light is generated according to the first data signal Data_A, so as to drive the first light emitting element D1 to emit light of a first color, and a third drive current driving the third light emitting element D3 to emit light is generated according to the second data signal Data_B, so as to drive the third light emitting element D3 to emit light of a third color; in the second light emitting stage, a second drive current driving the second light emitting element D2 to emit light is generated according to the third data signal Data_C, so as to drive the second light emitting element D2 to emit light of a second color, and a fourth drive current driving the fourth light emitting element D4 to emit light is generated according to the fourth data signal Data_D, so as to drive the fourth light emitting element D4 to emit light of a fourth color. That is, in the first light emitting stage during the display of one frame of image, one of the first light emitting element D1 and the second light emitting element D2 is caused to emit light simultaneously with one of the third light emitting element D3 and the fourth light emitting element D4, and in the second light emitting stage during the display of the one frame of image, the other of the first light emitting element D1 and the second light emitting element D2 is caused to emit light simultaneously with the other of the third light emitting element D3 and the fourth light emitting element D4. For example, the first color, the second color, the third color and the fourth color are different from each other, and the first light emitting stage and the second light emitting stage are three different light emitting stages in the display period of the same frame of image, respectively, so as to realize time-division driving, and cause the four light emitting elements of the pixel circuit to emit light of different colors in two different light emitting stages in the display period of the same frame of image, respectively, so as to realize color display.

[0165] Of course, it is not limited to two light emitting stages, according to the design principle of the pixel circuit for time-division display provided in the present application, the display period of the same frame of image can also include more than two light emitting stages, and the plurality of light emitting elements are caused to emit light in more than two light emitting stages, respectively, by the above-mentioned control method of time-division light emission, so as to also realize color display. In comparison, the case that the display period of the same frame of image has two light emitting stages is advantageous to simplify the driving method of the pixel circuit.

[0166] Specifically, for example, referring to FIG. 6, the second driving sub-circuit 102 includes a second driving transistor T9 configured to control a current for driving the third light emitting element D3 or the fourth light emitting element D4 to emit light under control of a voltage at a gate of the second driving transistor T9, a first pole of the second driving transistor T9 configured to receive the first power supply voltage VDD, a second pole of the second driving transistor T9 electrically connected with a first electrode of the third light emitting element D3, a second electrode of the fourth light emitting element D4 configured to receive the second power supply voltage; the second data storage sub-circuit 602 includes a second data storage capacitor CstB, a first pole of the second data storage capacitor CstB electrically connected with the gate of the second driving transistor T9, a second pole of the second data storage capacitor CstB electrically connected with the second pole of the second driving transistor T9, the first electrode of the third light emitting element D3 and the first pole of the third selection transistor T12.

[0167] For example, referring to FIG. 6, the second data writing sub-circuit 502 includes a second data transistor T8, a first pole of the second data transistor T8 electrically connected with the first pole of the second data storage capacitor CstB and the gate of the second driving transistor T9, a second pole of the second data transistor T8 configured to receive the second data signal Data_B or the fourth data signal Data_D, the second data transistor T8 configured to write the second data signal Data_B or the fourth data signal Data_D to the gate of the second driving transistor T9 and the second data storage capacitor CstB in response to the second data scanning signal G5.

[0168] For example, referring to FIG. 6, the second sub-pixel circuit further includes a second sensing sub-circuit 702, a first end of the second sensing sub-circuit 702 electrically connected with the first electrode of the third light emitting element D3, i.e. electrically connected with the third node N3, a control end of the second sensing sub-circuit 702 configured to receive a second sensing scanning signal G6, a second end of the second sensing sub-circuit 702 electrically connected with a second sensing signal line to receive a second sensing signal Sense2. The second sensing signal Sense2 can come from a second external detection circuit, for example, the second sensing signal line is electrically connected with the second external detection circuit, the second sensing sub-circuit 702 configured to detect an electrical characteristic of the sub-pixel to which the second sensing sub-circuit 702 belongs through the second external detection circuit in response to the second sensing scanning signal G6 to achieve compensation. For example, the first external detection circuit and the second external detection circuit can be the same circuit, or different circuits that work independently.

[0169] For example, referring to FIG. 6, the second sensing sub-circuit 702 includes a second sensing transistor T10, a first electrode of the second sensing transistor T10 is electrically connected with the first electrode of the third light emitting element D3, a second electrode of the second sensing transistor T10 is electrically connected with the second sensing signal line to be connected to the second external detection circuit, a gate of the second sensing transistor T10 is configured to receive a second sensing scan signal G6, and the second sensing transistor T10 is configured to detect the electrical characteristics of the sub-pixel to which the second sensing transistor T10 belongs through the second external detection circuit in response to the second sensing scan signal G6 to realize external compensation.

[0170] FIG. 7 is a timing diagram of a control method of the pixel circuit shown in FIG. 6. The driving method of the pixel circuit shown in FIG. 6 will be described below in combination with FIG. 6 and FIG. 7, and the driving method of the pixel circuit shown in FIG. 6 is different from the above-described driving method of the pixel circuit shown in FIG. 3 in the following aspects.

[0171] The at least two time periods included in the display period of one frame of image include a first time period 1 and a second time period 2, and the driving method of the pixel circuit includes: by controlling the first gate signal DA applied to the driving end of the first gating sub-circuit 201, the second gate signal DB applied to the driving end of the second gating sub-circuit 202, the third gate signal DC applied to the driving end of the third gating sub-circuit 203, and the fourth gate signal DD applied to the driving end of the fourth gating sub-circuit 204, so that: in the first time period 1, one of the first light emitting element D1 and the second light emitting element D2 and one of the third light emitting element D3 and the fourth light emitting element D4 emit light; in the second time period 2, the other of the first light emitting element D1 and the second light emitting element D2 and the other of the third light emitting element D3 and the fourth light emitting element D4 emit light.

[0172] Referring to FIG. 6 and FIG. 7, the working process of the first sub-pixel circuit in which the first light emitting element D1 and the second light emitting element D2 are located is the same as that shown in FIG. 3-4. The working process of the second sub-pixel circuit in which the third light emitting element D3 and the fourth light emitting element D4 are located is similar to that of the first sub-pixel circuit.

[0173] Specifically, referring to FIG. 6 and FIG. 7, the first time period 1 includes a first light emitting stage t3, and the second time period 2 includes a second light emitting stage t6. For the pixel circuit shown in FIG. 3, here, the case where the first light emitting element D1 and the third light emitting element D3 both emit light in the first light emitting stage t3, and the second light emitting element D2 and the fourth light emitting element D4 both emit light in the second light emitting stage t6 is taken as an example.

[0174] FIG. 8A is a circuit conduction state diagram of the first reset stage of the first time period shown in FIG. 7. Here, the transistors of the pixel circuit in FIG. 6 are all taken as N-type transistors, which are turned on in response to a high potential and turned off in response to a low potential.

[0175] In combination with FIGS. 6-7 and FIG. 8A, the first time period 1 includes a first reset stage t1. In the first reset stage t1, the first gate control signal G3, the second gate control signal G4, the third gate control signal G7, and the fourth gate control signal G8 are all on signals, so that the first end and the second end of the first gate control sub-circuit 301 are turned on, the first end and the second end of the second gate control sub-circuit 302 are turned on, the first end and the second end of the third gate control sub-circuit 303 are turned on, and the first end and the second end of the fourth gate control sub-circuit 304 are turned on, for example, the first gate control transistor T4, the second gate control transistor T6, the third gate control transistor T11, and the fourth gate control transistor T13 are all turned on.

[0176] Also, in the first reset stage t1, for the first sub-pixel circuit, the first gate signal DA written to the control end of the first gate sub-circuit 201 by the first gate control sub-circuit 301 is an on signal to make the first end and the second end of the first gate sub-circuit 201 turned on via the first gate sub-circuit 201, for example, the first gate transistor T5 is turned on, and the second gate signal DB written to the control end of the second gate sub-circuit 202 by the second gate control sub-circuit 302 is an off signal to make the first end and the second end of the second gate sub-circuit 202 not turned on via the second gate sub-circuit 202, for example, the second gate transistor T7 is turned off; similarly, for the second sub-pixel circuit, the third gate signal DC written to the control end of the third gate sub-circuit 203 by the third gate control sub-circuit 301 is an on signal to make the first end and the second end of the third gate sub-circuit 203 turned on via the third gate sub-circuit 203, for example, the third gate transistor T12 is turned on, and the fourth gate signal DD written to the control end of the fourth gate sub-circuit 204 by the fourth gate control sub-circuit 304 is an off signal to make the first end and the second end of the fourth gate sub-circuit 204 not turned on, for example, the fourth gate transistor T14 is turned off.

[0177] And, in the first reset stage t1, the first sensing scan signal G2 and the second sensing scan signal G6 are both on signals, so that the first end and the second end of the first sensing sub-circuit 701 are turned on, the first end and the second end of the second sensing sub-circuit 702 are turned on, for example, the first sensing transistor T3 and the second sensing transistor T10 are both turned on. Thus, for the first sub-pixel circuit, the first reset signal Vinit1 is input via the second end of the first sensing sub-circuit 701 (it can be understood that the second sensing signal Sense2 is the second reset signal Vinit2 at this time), and the first reset signal Vinit1 is applied to the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 via the first sensing sub-circuit 701, the first electrode of the first light emitting element D1, the first end and the second end of the first gating sub-circuit 201, so as to reset the electrical signal of the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2, that is, to reset the second node N2 and the first node N1; similarly, for the second sub-pixel circuit, the second reset signal Vinit2 is input via the second end of the second sensing sub-circuit 702 (it can be understood that the second sensing signal Sense2 is the second reset signal Vinit2 at this time), and the second reset signal Vinit2 is applied to the second electrode of the third light emitting element D3 and the first electrode of the fourth light emitting element D4 via the second sensing sub-circuit 702, the first electrode of the third light emitting element D3, the first end and the second end of the third gating sub-circuit 203, so as to reset the electrical signal of the second electrode of the third light emitting element D3 and the first electrode of the fourth light emitting element D4, that is, to reset the third node N3 and the fourth node N4. In the first reset stage t1, the first end and the second end of the second gating sub-circuit 202 are not turned on, for example, the second gating transistor T7 is turned off, which can prevent the first node N1 from being reset by the second power supply voltage Vss and the first reset signal Vinit1 at the same time, so as to prevent the signal of the first node N1 from being unstable; similarly, the first end and the second end of the fourth gating sub-circuit 204 are not turned on, for example, the fourth gating transistor T14 is turned off, which can prevent the fourth node N4 from being reset by the second power supply voltage Vss and the second reset signal Vinit2 at the same time, so as to prevent the signal of the fourth node N4 from being unstable.

[0178] Specifically, for the pixel circuit shown in FIG. 6, in the first reset stage t1, for the first sub-pixel circuit, the first gate control signal G3 and the second gate control signal G4 are both open signals, so that the first gate control transistor T4 and the second gate control transistor T6 are both turned on, so that the first gate signal DA is written to the gate of the first gate transistor T5 via the first gate control transistor T4, the first gate signal DA is an open signal to turn on the first gate transistor T5, and the second gate signal DB is written to the gate of the second gate transistor T7 via the second gate control transistor T6, the second gate signal DB is a closed signal to turn off the second gate transistor T7. The first sensing scan signal G2 written to the gate of the first sensing transistor T3 is an open signal to turn on the first sensing transistor T3, so that the first reset signal Vinit1 is applied to the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2 via the first sensing transistor T3 and the first gate transistor T5, to reset the electrical signals of the second electrode of the first light emitting element D1 and the first electrode of the second light emitting element D2, i.e., to reset the second node N2 and the first node N1. In the first reset stage t1, for the second sub-pixel circuit, the third gate control signal G7 and the fourth gate control signal G8 are both open signals, so that the third gate control transistor T11 and the fourth gate control transistor T13 are both turned on, so that the third gate signal DC is written to the gate of the third gate transistor T12 via the third gate control transistor T11, the third gate signal DC is an open signal to turn on the third gate transistor T12, and the fourth gate signal DD is written to the gate of the fourth gate transistor T14 via the fourth gate control transistor T13, the fourth gate signal DD is a closed signal to turn off the fourth gate transistor T14. The second sensing scan signal G6 written to the gate of the second sensing transistor T10 is an open signal to turn on the second sensing transistor T10, so that the first reset signal Vinit1 is applied to the second electrode of the third light emitting element D3 and the first electrode of the fourth light emitting element D4 via the second sensing transistor T10 and the third gate transistor T12, to reset the electrical signals of the second electrode of the third light emitting element D3 and the first electrode of the fourth light emitting element D4, i.e., to reset the third node N3 and the fourth node N4.

[0179] For example, in the first reset stage t1, the first data scan signal G1 and the second data scan signal G5 are both on signals, so that the first data write sub-circuit 501 and the second data write sub-circuit 502 are both turned on, the first data signal Data_A is written to the control terminal of the first drive sub-circuit 101 via the first data write sub-circuit 501, and the second data signal Data_B is written to the control terminal of the second drive sub-circuit 102 via the second data write sub-circuit 502. For example, the first data scan signal G1 written to the gate of the first data transistor T1 is an on signal, so that the first data transistor T1 is turned on, and the first data signal Data_A is written to the gate of the first drive transistor T2 via the first data transistor T1; the second data scan signal G5 written to the gate of the second data transistor T8 is an on signal, so that the second data transistor T8 is turned on, and the second data signal Data_B is written to the gate of the second drive transistor T9 via the first data transistor T8. Of course, the first data scan signal G1 and / or the second data scan signal G5 can also be off signals in the first reset stage t1, that is, the first data transistor T1 and / or the second data transistor T8 are kept off in the first reset stage t1, and the first data signal and / or the second data signal are not written.

[0180] FIG. 8B is a circuit conduction state diagram of the first gating and data writing stage t2 of the first time period shown in FIG. 7. For example, referring to FIG. 7 and FIG. 8B, the first time period 1 further includes the first gating and data writing stage t2 after the first reset stage t1, in the first gating and data writing stage t2, the first gating control signal G3 and the second gating control signal G4 are both on signals, so that the first gating signal DA is written to the control terminal of the first gating sub-circuit 201 via the first gating control sub-circuit 301, and the second gating signal DB is written to the control terminal of the second gating sub-circuit 202 via the second gating control sub-circuit 302. And, in the first gating and data writing stage t2 and the second gating and data writing stage t5, the first gating signal DA and the second gating signal DB are both signals opposite to each other, so that one of the first gating sub-circuit 201 and the second gating sub-circuit 202 is turned on, and the other of the first gating sub-circuit 201 and the second gating sub-circuit 202 is turned off, so that in the first light emitting stage t3 and the second light emitting stage t6, the light emitting element in parallel with the turned-on one does not emit light and the light emitting element in parallel with the turned-off one does not emit light.

[0181] Exemplarily, referring to FIG. 7 and FIG. 8B, in the first gate and data writing stage t2, the first gate control signal G3, the second gate control signal G4, the third gate control signal G7 and the fourth gate control signal G8 are all on signals, so that the first gate control transistor T4, the second gate control transistor T6, the third gate control transistor T11 and the fourth gate control transistor T13 are all turned on, the first gate signal DA is written to the gate of the first gate transistor T5 via the first gate control transistor T4, the second gate signal DB is written to the gate of the second gate transistor T7 via the second gate control transistor T6, the third gate signal DC is written to the gate of the third gate transistor T12 via the third gate control transistor T11, and the fourth gate signal DD is written to the gate of the fourth gate transistor T14 via the fourth gate control transistor T13; the first gate signal DA and the third gate signal DC are both off signals, for example, low level signals, and the second gate signal DB and the fourth gate signal DD are both on signals, for example, high level signals, so that the first gate sub-circuit 201 and the third gate sub-circuit 203 are both turned off, for example, the first gate transistor T5 and the third gate transistor T12 are both turned off, and the second gate sub-circuit 202 and the fourth gate sub-circuit 204 are both turned on, for example, the second gate transistor T7 and the fourth gate transistor T14 are both turned on. And, in the first gate and data writing stage t2, the first gate signal DA is written to the first gate storage capacitor Cst1 via the first gate control transistor T4 and stored in the first gate storage capacitor Cst1, the second gate signal DB is written to the second gate storage capacitor Cst2 via the second gate control transistor T6 and stored in the second gate storage capacitor Cst2, the third gate signal DC is written to the third gate storage capacitor Cst3 via the third gate control transistor T11 and stored in the third gate storage capacitor Cst3, and the fourth gate signal DD is written to the fourth gate storage capacitor Cst4 via the fourth gate control transistor T13 and stored in the fourth gate storage capacitor Cst4.

[0182] For example, in the first gate and data writing stage t2, the first data signal Data_A for controlling the gray scale of the first color and the second data signal Data_B for controlling the gray scale of the second color are written.

[0183] Referring to FIGS. 7 and 8B, in the first gate and data writing stage t2, the first data scanning signal G1 and the second data scanning signal G5 are both on signals, so that the first data writing sub-circuit 501 and the second data writing sub-circuit 502 are both turned on, for example, the first data transistor T1 and the second data transistor T8 are both turned on, the first data signal Data_A is written to the control terminal of the first driving sub-circuit 101 via the first data writing sub-circuit 501, for example, to the gate of the first driving transistor T2 via the first data transistor T1, and the second data signal Data_B is written to the control terminal of the second driving sub-circuit 102 via the second data writing sub-circuit 502, for example, to the gate of the second driving transistor T9 via the second data transistor T8.

[0184] In the first gate and data writing stage t2, for example, the first reset signal Vinit1 is written to the second node N2 via the first sensing signal line and the first sensing transistor T3 by an analog-to-digital converter, for example, the first reset signal Vinit1 is a constant voltage, the first driving transistor T2 is turned on and generates a first driving current to charge the second node N2 to the operating voltage of the first light emitting element D1; and the first data signal Data_A is stored into the first data storage sub-circuit 601 via the first data transistor T1, for example, in the first data storage capacitor CstA. Similarly, in the first gate and data writing stage t2, for example, the second reset signal Vinit2 is written to the third node N3 via the second sensing signal line and the second sensing transistor T10 by an analog-to-digital converter, for example, the second reset signal Vinit2 is a constant voltage, the second driving transistor T9 is turned on and generates a second driving current to charge the third node N3 to the operating voltage of the third light emitting element D3; and the second data signal Data_B is stored into the second data storage sub-circuit 602 via the second data transistor T9, for example, in the second data storage capacitor CstB.

[0185] Referring to FIG. 7, the first period 1 further comprises a first light emitting phase t3 after the first gate and data writing phase t2. FIG. 8C is a circuit conduction state diagram of the first light emitting phase t3 of the first period shown in FIG. 7. Referring to FIG. 7 and FIG. 8C, in the driving method of the pixel circuit 10, in the first light emitting phase t3, the first data scanning signal G1 and the second data scanning signal G5, the first sensing scanning signal G2 and the second sensing scanning signal G6, the first gate control signal G3, the second gate control signal G4, the third gate control signal G7 and the fourth gate control signal G8 are all off signals, for example, all are low level, the potential of the first gate node M1 and the potential of the third gate node M3 are maintained by the first gate storage capacitor Cst1 and the third gate storage capacitor Cst3 respectively, both are low level, and the potential of the second gate node M2 and the potential of the fourth gate node M4 are maintained by the second gate storage capacitor Cst2 and the fourth gate storage capacitor Cst4 respectively, both are high level. Thus, as shown in FIG. 8C, the first gate transistor T5 and the third gate transistor T12 are both off, the second gate transistor T7 and the fourth gate transistor T14 are both on, and due to the bootstrap effect of the first data storage capacitor CstA and the second data storage capacitor CstB, the potential of the gate of the first drive transistor T2 is maintained by the first data storage capacitor CstA, the potential of the gate of the second drive transistor T9 is maintained by the second data storage capacitor CstB, so that the first drive transistor T2 and the second drive transistor T9 are both maintained on. For example, the first drive transistor T2 and the second drive transistor T9 are both working in the saturation state and the current is constant, and the second gate transistor T7 and the fourth gate transistor T14 are both working in the linear region. Thus, the first light emitting path shown by the left arrowed dashed line and the second light emitting path shown by the right arrowed dashed line in FIG. 8C are formed. Therefore, in the first light emitting phase t3, the first drive current flows through the first light emitting element D1 without flowing through the second light emitting element D2 in parallel with the second gate sub-circuit 202, and the second drive current flows through the third light emitting element D3 without flowing through the fourth light emitting element D4 in parallel with the fourth gate sub-circuit 204, and the first light emitting element D1 and the third light emitting element D3 both emit light, and the second light emitting element D2 and the fourth light emitting element D4 do not emit light. And the first drive current driving the first light emitting element D1 to emit light can be generated according to the first data signal Data_A, and the second drive current driving the third light emitting element D3 to emit light can be generated according to the second data signal Data_B, so as to drive the first light emitting element D1 and the third light emitting element D3 to emit light respectively, for example, the first light emitting element D1 emits light of the first color, and the third light emitting element D3 emits light of the third color, and different display gray scales are realized.

[0186] For example, referring to FIG. 7, the second period 2 includes a second reset phase t4, a second gate and data writing phase t5 after the second reset phase t4, and a second light emitting phase t6 after the second gate and data writing phase t5.

[0187] FIG. 8D is a schematic diagram of the circuit conduction state of the second reset phase of the second period shown in FIG. 7. Referring to FIG. 7 and FIG. 8D, the second period 2 includes a second reset phase t4, and the timing and working process of the pixel circuit 10 in the second reset phase t4 are the same as those of the first reset phase t1, i.e., the second node N2 and the first node N1, the third node N3 and the fourth node N4 are reset again.

[0188] FIG. 8E is a schematic diagram of the circuit conduction state of the second gate and data writing phase t5 of the second period 2 shown in FIG. 7. Referring to FIG. 7 and FIG. 8E, in the second gate and data writing phase t5, the first gate control signal G3, the second gate control signal G4, the third gate control signal G7, and the fourth gate control signal G8 are all open signals, so that the first gate control transistor T4, the second gate control transistor T6, the third gate control transistor T11, and the fourth gate control transistor T13 are all turned on, the first gate signal DA is written to the gate of the first gate transistor T5 via the first gate control transistor T4, the second gate signal DB is written to the gate of the second gate transistor T7 via the second gate control transistor T6, the third gate signal DC is written to the gate of the third gate transistor T12 via the third gate control transistor T11, and the fourth gate signal DD is written to the gate of the fourth gate transistor T14 via the fourth gate control transistor T13; the first gate signal DA and the third gate signal DC are both open signals, e.g., high-level signals, and the second gate signal DB and the fourth gate signal DD are both closed signals, e.g., low-level signals, so that the first gate sub-circuit 201 and the third gate sub-circuit 203 are both turned on, e.g., the first gate transistor T5 and the third gate transistor T12 are both turned on, and the second gate sub-circuit 202 and the fourth gate sub-circuit 204 are both turned off, e.g., the second gate transistor T7 and the fourth gate transistor T14 are both turned off. Moreover, in the second gate and data writing phase t5, the first gate signal DA is stored in the first gate storage capacitor Cst1 by being written to the first gate storage capacitor Cst1 via the first gate control transistor T4, the second gate signal DB is stored in the second gate storage capacitor Cst2 by being written to the second gate storage capacitor Cst2 via the second gate control transistor T6, the third gate signal DC is stored in the third gate storage capacitor Cst3 by being written to the third gate storage capacitor Cst3 via the third gate control transistor T11, and the fourth gate signal DD is stored in the fourth gate storage capacitor Cst4 by being written to the fourth gate storage capacitor Cst4 via the fourth gate control transistor T13.

[0189] For example, in the second gate-on and data write stage t5, the third data signal Data_C for controlling the gray scale of the third color and the fourth data signal Data_D for controlling the gray scale of the fourth color are written.

[0190] Referring to FIGS. 7 and 8E, in the second gate-on and data write stage t5, the first data scan signal G1 and the second data scan signal G5 are both on signals, so that the first data write sub-circuit 501 and the second data write sub-circuit 502 are both turned on, for example, the first data transistor T1 and the second data transistor T8 are both turned on, the third data signal Data_C is written to the control terminal of the first drive sub-circuit 101 via the first data write sub-circuit 501, for example, to the gate of the first drive transistor T2 via the first data transistor T1, and the fourth data signal Data_D is written to the control terminal of the second drive sub-circuit 102 via the second data write sub-circuit 502, for example, to the gate of the second drive transistor T9 via the second data transistor T8.

[0191] In the first gate-on and data write stage t2, for example, the first reset signal Vinit1 is written to the second node N2 via the first sense signal line and the first sense transistor T3 by an analog-to-digital converter, for example, the first reset signal Vinit1 is a constant voltage, the first drive transistor T2 is turned on and generates a third drive current to charge the second node N2 to the operating voltage of the second light emitting element D2; and the third data signal Data_C is stored into the first data storage sub-circuit 601 via the first data transistor T1, for example, in the first data storage capacitor CstA. Similarly, in the first gate-on and data write stage t2, for example, the second reset signal Vinit2 is written to the third node N3 via the second sense signal line and the second sense transistor T10 by an analog-to-digital converter, for example, the second reset signal Vinit2 is a constant voltage, the second drive transistor T9 is turned on and generates a fourth drive current to charge the third node N3 to the operating voltage of the fourth light emitting element D4; and the fourth data signal Data_D is stored into the second data storage sub-circuit 602 via the second data transistor T9, for example, in the second data storage capacitor CstB.

[0192] Fig. 8F is a schematic diagram of the circuit conduction state of the second light emitting stage t6 of the second time period shown in Fig. 7. Referring to Figs. 7 and 8F, in the driving method of the pixel circuit 10, in the second light emitting stage t6, the first data scan signal G1 and the second data scan signal G5, the first sensing scan signal G2 and the second sensing scan signal G6, the first gate control signal G3, the second gate control signal G4, the third gate control signal G7 and the fourth gate control signal G8 are all off signals, for example, are all low, the potential of the first gate node M1 and the potential of the third gate node M3 are maintained by the first gate storage capacitor Cst1 and the third gate storage capacitor Cst3 respectively, are both high, and the potential of the second gate node M2 and the potential of the fourth gate node M4 are maintained by the second gate storage capacitor Cst2 and the fourth gate storage capacitor Cst4 respectively, are both low. Thus, as shown in Fig. 8F, the first gate transistor T5 and the third gate transistor T12 are both turned on, the second gate transistor T7 and the fourth gate transistor T14 are both turned off, and due to the bootstrap effect of the first data storage capacitor CstA and the second data storage capacitor CstB, the potential of the gate of the first drive transistor T2 is maintained by the first data storage capacitor CstA, the potential of the gate of the second drive transistor T9 is maintained by the second data storage capacitor CstB, so that the first drive transistor T2 and the second drive transistor T9 are both maintained to be turned on. For example, the first drive transistor T2 and the second drive transistor T9 are both working in the saturation state and the current is unchanged, and the first gate transistor T5 and the third gate transistor T12 are both working in the linear region. Thus, the third light emitting path shown by the left arrowed dashed line and the fourth light emitting path shown by the right arrowed dashed line in Fig. 8F are formed. Therefore, in the second light emitting stage t6, the third drive current flows through the second light emitting element D2 without flowing through the first light emitting element D1 in parallel with the first gate sub-circuit 201, the fourth drive current flows through the fourth light emitting element D4 without flowing through the third light emitting element D3 in parallel with the third gate sub-circuit 203, and the second light emitting element D2 and the fourth light emitting element D4 both emit light, and the first light emitting element D1 and the third light emitting element D3 do not emit light. Moreover, the third drive current driving the second light emitting element D2 to emit light can be generated according to the third data signal Data_C, and the fourth drive current driving the fourth light emitting element D4 to emit light can be generated according to the fourth data signal Data_D, so as to drive the second light emitting element D2 and the fourth light emitting element D4 to emit light respectively, for example, the second light emitting element D2 emits light of the second color, and the fourth light emitting element D4 emits light of the fourth color, and different display gray scales are realized.

[0193] Thus, the pixel circuit 10 shown in FIG. 6 can further realize more light-emitting elements emitting light in time division, realize pixel merging, simplify the structure of the pixel capable of emitting multiple color lights, and simplify the structure of the pixel circuit, which is not only conducive to reducing the space occupied by each pixel circuit, but also conducive to simplifying the manufacturing process and reducing the manufacturing difficulty of the display panel including the pixel circuit, thereby improving the yield of the display panel. Moreover, the driving method of the pixel circuit 10 is simple and easy to implement.

[0194] Other features of the pixel circuit shown in FIG. 6 not mentioned herein are the same as those in the embodiment shown in FIG. 3. Please refer to the previous description, which will not be repeated here.

[0195] In other embodiments, the arrangement combination of the light-emitting sequence of the four light-emitting elements can be realized by using a driving method similar to the present embodiment, as long as the following conditions are met: in the first time period 1, one of the first light-emitting element D1 and the second light-emitting element D2 emits light with one of the third light-emitting element D3 and the fourth light-emitting element D4; in the second time period 2, the other one of the first light-emitting element D1 and the second light-emitting element D2 emits light with the other one of the third light-emitting element D3 and the fourth light-emitting element D4. According to the above principle, by controlling the first to fourth selection signals DA-DD to be an on signal or an off signal, so that the first selection signal DA and the second selection signal DB are mutually opposite signals, and the first selection signal DA and the second selection signal DB are mutually opposite signals, so that in the first selection and data writing stage t2 and the second selection and data writing stage t5, the first selection signal DA and the second selection signal DB are mutually opposite signals, and the third selection signal DC and the fourth selection signal DD are mutually opposite signals, so that one of the first selection sub-circuit 201 and the second selection sub-circuit 202 is turned on, the other one of the first selection sub-circuit 201 and the second selection sub-circuit 202 is turned off, and one of the third selection sub-circuit 203 and the fourth selection sub-circuit 204 is turned on, the other one of the third selection sub-circuit 203 and the fourth selection sub-circuit 204 is turned off, so that in the first light-emitting stage t3 and the second light-emitting stage t6, the light-emitting element in parallel with the one turned on does not emit light and the light-emitting element in parallel with the other turned off does not emit light, thus, the first light-emitting element and the second light-emitting element emit light in time division, and the third light-emitting element and the fourth light-emitting element emit light in time division, so as to realize pixel merging and color display.

[0196] Exemplarily, FIG. 9 is a timing diagram of another driving method of the pixel circuit shown in FIG. 6 according to an embodiment of the present disclosure. In the driving method of the pixel circuit shown in FIG. 9, the light-emitting sequence of the first to fourth light-emitting elements D1-D4 is different from that of the driving method shown in FIG. 7.

[0197] Referring to FIG. 9, in the first gate and data write stage t2, the first gate signal DA and the fourth gate signal DD are both on signals, for example, both high level signals, and the second gate signal DB and the third gate signal DC are both off signals, for example, both low level signals, so that the first gate sub-circuit 201 and the fourth gate sub-circuit 204 are both turned on, for example, the first gate transistor T5 and the fourth gate transistor T14 are both turned on, and the second gate sub-circuit 202 and the third gate sub-circuit 203 are both turned off, for example, the second gate transistor T7 and the third gate transistor T12 are both turned off. Also, in the first gate and data write stage t2, the first gate signal DA is stored in the first gate storage capacitor Cst1, the second gate signal DB is stored in the second gate storage capacitor Cst2, the third gate signal DC is stored in the third gate storage capacitor Cst3, and the fourth gate signal DD is stored in the fourth gate storage capacitor Cst4.

[0198] In the first light emitting stage t3, the potentials of the first gate node M1 and the fourth gate node M4 are both maintained by the first gate storage capacitor Cst1 and the fourth gate storage capacitor Cst4 respectively, both at high level, and the potentials of the second gate node M2 and the third gate node M3 are both maintained by the second gate storage capacitor Cst2 and the third gate storage capacitor Cst3 respectively, both at low level. Thus, the first gate transistor T5 and the fourth gate transistor T14 are both turned on, the second gate transistor T7 and the third gate transistor T12 are both turned off, and due to the bootstrap effect of the first data storage capacitor CstA and the second data storage capacitor CstB, the potential of the gate of the first drive transistor T2 is maintained by the first data storage capacitor CstA and the potential of the gate of the second drive transistor T9 is maintained by the second data storage capacitor CstB, so that the first drive transistor T2 and the second drive transistor T9 are both maintained turned on. For example, the first drive transistor T2 and the second drive transistor T9 are both working in saturation state with constant current, and the first gate transistor T5 and the fourth gate transistor T14 are both working in linear region. Thus, the second drive current and the third drive current are formed according to the corresponding data signals, the second drive current flows through the second light emitting element D2 without flowing through the first light emitting element D1 in parallel with the first gate sub-circuit 201, and the third drive current flows through the third light emitting element D3 without flowing through the fourth light emitting element D4 in parallel with the fourth gate sub-circuit 204, and the second light emitting element D2 and the third light emitting element D3 both emit light, and the first light emitting element D1 and the fourth light emitting element D4 do not emit light.

[0199] In the second gate-on and data write stage t5, the first gate signal DA and the fourth gate signal DD are both off signals, for example, both low level signals, and the second gate signal DB and the third gate signal DC are both on signals, for example, both high level signals, so that the first gate sub-circuit 201 and the fourth gate sub-circuit 204 are both turned off, for example, the first gate transistor T5 and the fourth gate transistor T14 are both turned off, and the second gate sub-circuit 202 and the third gate sub-circuit 203 are both turned on, for example, the second gate transistor T7 and the third gate transistor T12 are both turned on. In addition, in the second gate-on and data write stage t5, the first gate signal DA is stored in the first gate storage capacitor Cst1, the second gate signal DB is stored in the second gate storage capacitor Cst2, the third gate signal DC is stored in the third gate storage capacitor Cst3, and the fourth gate signal DD is stored in the fourth gate storage capacitor Cst4.

[0200] In the second light emitting stage t6, the potentials of the first gate node M1 and the fourth gate node M4 are both maintained by the first gate storage capacitor Cst1 and the fourth gate storage capacitor Cst4 respectively, both at low levels, and the potentials of the second gate node M2 and the third gate node M3 are both maintained by the second gate storage capacitor Cst2 and the third gate storage capacitor Cst3 respectively, both at high levels. Thus, the first gate transistor T5 and the fourth gate transistor T14 are both turned off, the second gate transistor T7 and the third gate transistor T12 are both turned on, and due to the bootstrap effect of the first data storage capacitor CstA and the second data storage capacitor CstB, the potential of the gate of the first drive transistor T2 is maintained by the first data storage capacitor CstA, and the potential of the gate of the second drive transistor T9 is maintained by the second data storage capacitor CstB, so that the first drive transistor T2 and the second drive transistor T9 are both maintained in the on state. For example, the first drive transistor T2 and the second drive transistor T9 are both in the saturation state and the current is constant, and the first gate transistor T5 and the fourth gate transistor T14 are both in the linear region. Thus, the first drive current and the fourth drive current are formed according to the corresponding data signals, the first drive current flows through the first light emitting element D1 without flowing through the second light emitting element D2 in parallel with the second gate sub-circuit 202, and the fourth drive current flows through the fourth light emitting element D4 without flowing through the third light emitting element D3 in parallel with the third gate sub-circuit 203, and the first light emitting element D1 and the fourth light emitting element D4 both emit light, and the second light emitting element D2 and the third light emitting element D3 do not emit light.

[0201] According to the above principle of exchanging the light emitting sequence of each light emitting element, various arrangement combinations of the light emitting sequence can be realized, and these arrangement combinations are all covered in the working process of the pixel circuit provided in the embodiments of the present disclosure.

[0202] The timing of other stages not mentioned in the driving method shown in FIG. 9 is the same as that of the embodiment shown in FIG. 7. Refer to the previous description.

[0203] FIG. 10A is a timing diagram of another driving method of the pixel circuit shown in FIG. 6 according to an embodiment of the present disclosure; and FIG. 10B is a circuit conduction state diagram of a first reset stage of the working process of the pixel circuit shown in FIG. 10A. The working process of the pixel circuit shown in FIG. 10A and FIG. 10B is different from the embodiment shown in FIG. 9 in the following aspects.

[0204] Referring to FIG. 10A and FIG. 10B, in the first reset stage t1, the first gate control signal G3 and the second gate control signal G4 are both on signals to make the first end and the second end of the first gate control sub-circuit 301 conductive, the first end and the second end of the second gate control sub-circuit 302 conductive, the first gate signal DA written to the control end of the first gate sub-circuit 201 through the first gate control sub-circuit 301 is an off signal to make the first end and the second end of the first gate sub-circuit 201 open, the second gate signal DB written to the control end of the second gate sub-circuit 202 through the second gate control sub-circuit 302 is an on signal to make the first end and the second end of the second gate sub-circuit 202 conductive via the second gate sub-circuit 202, and the second power supply voltage VSS is applied to the second electrode of the first light emitting element D1 via the second gate sub-circuit 202, so that the electrical signal of the second electrode of the first light emitting element D1 can be reset by the second power supply voltage VSS.

[0205] For example, referring to FIG. 10A and FIG. 10B, the timing and working process of the second reset stage t2 are the same as those of the first reset stage t1.

[0206] The working process of the pixel circuit shown in FIG. 10A and FIG. 10B is the same as that of the embodiment shown in FIG. 9 in other stages not mentioned.

[0207] FIG. 11 is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure; and FIG. 12 is a timing diagram of a driving method of the pixel circuit shown in FIG. 11 according to an embodiment of the present disclosure. The pixel circuit shown in FIG. 11 is different from the pixel circuit shown in FIG. 6 in the following aspects.

[0208] Referring to FIG. 11, the control terminal of the first data write sub-circuit 501, the control terminal of the second data write sub-circuit 502, the control terminal of the first sensing sub-circuit 701, and the control terminal of the second sensing sub-circuit 702 are electrically connected to the same sensing scan line, and the first data scan signal G1, the second data scan signal G5, the first sensing scan signal G2, and the second sensing scan signal G6 are the same scan signal. Referring to FIGS. 11-12, the difference between the timing of the pixel circuit 10 shown in FIG. 12 and the timing shown in FIG. 7 is that the first data scan signal G1, the second data scan signal G5, the first sensing scan signal G2, and the second sensing scan signal G6 are all the same scan signal. The working process of the pixel circuit 10 can be the same as that in the above-mentioned embodiments. Please refer to the previous description.

[0209] For example, in some embodiments, one of the first end of the first gating control sub-circuit 301 and the first end of the second gating control sub-circuit 302 is electrically connected to one of the first end of the third gating control sub-circuit 303 and the first end of the fourth gating control sub-circuit 304 through the same first gate signal line and the same first gate signal terminal, the other of the first end of the first gating control sub-circuit 301 and the first end of the second gating control sub-circuit 302 is electrically connected to the other of the first end of the third gating control sub-circuit 303 and the first end of the fourth gating control sub-circuit 304 through the same second gate signal line and the same second gate signal terminal, and the gating control signals from the first gate signal terminal and the second gate signal terminal are different. That is, one of the first gate signal DA and the second gate signal DB and one of the third gate signal DC and the fourth gate signal DD are the same signal from the same first gate signal terminal, and the other of the first gate signal DA and the second gate signal DB and the other of the third gate signal DC and the fourth gate signal DD are the same signal from the same second gate signal terminal. Therefore, according to the principle of controlling the light-emitting sequence of the plurality of light-emitting elements in the above-mentioned embodiments, it can be known that in this case, the light-emitting sequence of the plurality of light-emitting elements is bound. That is, one of the first light-emitting element D1 and the second light-emitting element D2 and one of the third light-emitting element D3 and the fourth light-emitting element D4 emit light at the same time or do not emit light at the same time, and the other of the first light-emitting element D1 and the second light-emitting element D2 and the other of the third light-emitting element D3 and the fourth light-emitting element D4 emit light at the same time or do not emit light at the same time.

[0210] For example, FIG. 13 is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure. The pixel circuit shown in FIG. 13 is different from the pixel circuit shown in FIG. 6 in the following aspects.

[0211] Referring to FIG. 13, for example, the first end of the first gate control sub-circuit 301 and the first end of the third gate control sub-circuit 303 are electrically connected to the same first gate signal end through the same first gate signal line, and the first end of the second gate control sub-circuit 302 and the first end of the fourth gate control sub-circuit 304 are electrically connected to the same second gate signal end through the same second gate signal line. The gate control signals from the first gate signal end and the second gate signal end are different. In this way, the first gate signal DA and the third gate signal DC are the same signal from the same first gate signal end, and the second gate signal DB and the fourth gate signal DD are the same signal from the same second gate signal end. Therefore, according to the principle of controlling the light-emitting sequence of multiple light-emitting elements in the above-mentioned embodiment, the first light-emitting element D1 and the third light-emitting element D3 emit light at the same time or do not emit light at the same time, and the second light-emitting element D2 and the fourth light-emitting element D4 emit light at the same time or do not emit light at the same time.

[0212] Of course, in other embodiments, there can be different arrangements and combinations. For example, the first gate signal DA and the fourth gate signal DD are the same signal from the same first gate signal end, the first gate signal DA and the fourth gate signal DD are the same signal from the same first gate signal end, and the second gate signal DB and the third gate signal DC are the same signal from the same first gate signal end.

[0213] In the pixel circuit 10 shown in FIG. 6, one pixel includes 14 transistors, 6 storage capacitors, 2 data signal lines respectively providing first to fourth data signals, 4 gate signal lines respectively providing first to fourth gate signals, 2 gate lines providing driving scan signals (G1-G8), 1 sense line (Sense1 and Sense2 can be combined into the same signal and provided through the same sense signal line), 1 first power voltage signal VDD, 1 second power voltage signal VSS, and for example, a stacked light-emitting device with two layers stacked on each other.

[0214] In the pixel circuit 10 shown in FIG. 13, after simplification, one pixel includes 14 transistors, 6 storage capacitors, 2 data signal lines respectively providing first to fourth data signals, 2 gate signal lines respectively providing first to fourth gate signals, 2 gate lines providing driving scan signals (G1-G8), 1 sense line (Sense1 and Sense2 can be combined into the same signal and provided through the same sense signal line), 1 first power voltage signal VDD, 1 second power voltage signal VSS, and for example, a stacked light-emitting device with two layers stacked on each other. Further reduction of gate signal lines saves wiring space, reduces the difficulty of manufacturing the pixel circuit, and achieves higher resolution.

[0215] In addition, in the design of FIG. 13, in the adjacent pixel columns, the same selection signal line is used to transmit the same selection signal, which is at least one of the first selection signal DA, the second selection signal DB, the third selection signal DC and the fourth selection signal DD, so as to further reduce the selection signal lines, save the wiring space, reduce the manufacturing difficulty of the pixel circuit, and achieve higher resolution.

[0216] FIG. 14 is a timing diagram of a driving method of the pixel circuit shown in FIG. 13 according to an embodiment of the present disclosure; and FIGS. 15A-15F are schematic diagrams of the circuit conduction state in each stage shown in FIG. 14. The timing of FIG. 14 is similar to that shown in FIG. 7, and the difference is that in FIG. 14, the first selection signal DA and the third selection signal DC are the same signal, and the second selection signal DB and the fourth selection signal DD are the same signal, and the display process and principle are the same as those shown in FIG. 7. Accordingly, the working processes of the circuit in the six stages shown in FIGS. 15A-15F are similar to the working principles of the circuit in the six stages shown in FIGS. 8A-8F. Since the first selection signal DA and the third selection signal DC are the same signal, in the first light emitting stage t1 shown in FIG. 15C, the first light emitting element D1 and the third light emitting element D3 emit light (for example, simultaneously), and in the second light emitting stage t2 shown in FIG. 15F, the second light emitting element D2 and the fourth light emitting element D4 emit light (for example, simultaneously).

[0217] Of course, according to the above-mentioned principle of controlling the working process of the pixel circuit, the timing can also be controlled so that in the first light emitting stage t1, the second light emitting element D2 and the fourth light emitting element D4 emit light (for example, simultaneously), and in the second light emitting stage t2, the first light emitting element D1 and the third light emitting element D3 emit light (for example, simultaneously).

[0218] FIG. 16 is a schematic block diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 16, at least one embodiment of the present disclosure further provides a display panel 1000, which includes any one of the pixel circuits 10 provided by the embodiments of the present disclosure, as shown in FIG. 16. The display panel 1000 can be, for example, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, or other types of display panels having display functions. The embodiments of the present disclosure do not limit this.

[0219] The structure, functions and technical effects of the display panel provided by the embodiments of the present disclosure can refer to the corresponding descriptions of the pixel circuit 10 provided by the embodiments of the present disclosure described above, which will not be repeated here.

[0220] For example, the display panel 1000 provided by at least one embodiment of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, and embodiments of the present disclosure are not limited thereto.

[0221] The following points also need to be explained:

[0222] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to general design.

[0223] (2) For the sake of clarity, the thickness of a layer or region is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure, that is, the drawings are not drawn according to the actual proportion.

[0224] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0225] The above only describes exemplary embodiments of the present disclosure, and is not intended to limit the protection scope of the present disclosure, and the protection scope of the present disclosure is determined according to the scope defined by the claims.

Claims

1. A pixel circuit, comprising: The first sub-pixel circuit includes a first driving sub-circuit, a first light-emitting element, and a second light-emitting element. The first driving sub-circuit is configured to control the magnitude of the driving current flowing through the first light-emitting element or the magnitude of the driving current flowing through the second light-emitting element. The second electrode of the first light-emitting element and the first electrode of the second light-emitting element are electrically connected. The first electrode of the first light-emitting element is configured to receive a first power supply voltage, and the second electrode of the second light-emitting element is configured to receive a second power supply voltage. The first light-emitting element and the second light-emitting element emit different colors from each other. A first gating circuit, connected in parallel with the first light-emitting element, is configured to determine, in response to a first gating signal applied to the driving terminal of the first gating sub-circuit, whether a first terminal and a second terminal of the first gating sub-circuit are connected via the first gating sub-circuit and whether the driving current flows through the first light-emitting element; and A second gating circuit, connected in parallel with the second light-emitting element, is configured to determine, in response to a second gating signal applied to the driving terminal of the second gating sub-circuit, whether the first and second terminals of the second gating sub-circuit are connected via the second gating sub-circuit and whether the driving current flows through the second light-emitting element.

2. The pixel circuit according to claim 1, wherein, The first terminal of the first gating sub-circuit is electrically connected to the first electrode of the first light-emitting element, and the second terminal of the first gating sub-circuit, the second electrode of the first light-emitting element, the first electrode of the second light-emitting element, and the first terminal of the second gating sub-circuit are electrically connected to the first node. The second terminal of the second gating sub-circuit is electrically connected to the second electrode of the second light-emitting element.

3. The pixel circuit according to claim 1 or 2, wherein, The first sub-pixel circuit further includes: A first gating control subcircuit is configured to apply a first gating signal to a driving terminal of the first gating subcircuit in response to a first gating control signal applied to a control terminal of the first gating control subcircuit, wherein the driving terminal of the first gating control subcircuit is electrically connected to the first gating control terminal to receive the first gating control signal, a first terminal of the first gating control subcircuit is connected to the first gating signal terminal to receive the first gating signal, and a second terminal of the first gating control subcircuit is electrically connected to the driving terminal of the first gating subcircuit; and The second gating control subcircuit is configured to apply the second gating signal to the driving terminal of the second gating subcircuit in response to a second gating control signal applied to the control terminal of the second gating control subcircuit. The driving terminal of the second gating control subcircuit is electrically connected to the second gating control terminal to receive the second gating control signal. The first terminal of the second gating control subcircuit is connected to the second gating signal terminal to receive the second gating signal. The second terminal of the second gating control subcircuit is electrically connected to the driving terminal of the second gating subcircuit.

4. The pixel circuit according to claim 3 further includes: A first gating storage subcircuit, wherein the first gating control subcircuit is configured to transmit the first gating signal to a first terminal of the first gating storage subcircuit in response to the first gating control signal, the first gating storage subcircuit is configured to store the first gating signal, the first terminal of the first gating storage subcircuit is electrically connected to the driving terminal of the first gating subcircuit and the second terminal of the first gating control subcircuit at a first gating node, and the second terminal of the first gating storage subcircuit is connected to a first power supply terminal to receive the first power supply voltage; The second gating storage sub-circuit is configured to transmit the second gating signal to a first terminal of the second gating storage sub-circuit in response to the second gating control signal. The second gating storage sub-circuit is configured to store the second gating signal. The first terminal of the second gating storage sub-circuit is electrically connected to the driving terminal of the second gating sub-circuit and the second terminal of the second gating control sub-circuit at a second gating node. The second terminal of the second gating storage sub-circuit is connected to the first power supply terminal to receive the first power supply voltage.

5. The pixel circuit according to claim 4, wherein, The first gating sub-circuit includes a first gating transistor, the gate of the first gating transistor serves as the driving terminal of the first gating sub-circuit, the first terminal of the first gating transistor is electrically connected to the first electrode of the first light-emitting element, and the second terminal of the first gating transistor is electrically connected to the second electrode of the first light-emitting element. The second gating sub-circuit includes a second gating transistor, the gate of the second gating transistor serves as the driving terminal of the second gating sub-circuit, the first terminal of the second gating transistor is electrically connected to the first electrode of the second light-emitting element, and the second terminal of the second gating transistor is electrically connected to the second electrode of the second light-emitting element.

6. The pixel circuit according to claim 5, wherein, The first gating control sub-circuit includes a first gating control transistor, the first gating control The gate of the transistor is electrically connected to the first gating control terminal to receive the first gating control signal, the first terminal of the first gating control transistor is connected to the first gating signal terminal to receive the first gating signal, and the second terminal of the first gating control transistor is electrically connected to the gate of the first gating transistor. The second gating control sub-circuit includes a second gating control transistor. The gate of the second gating control transistor is electrically connected to the second gating control terminal to receive the second gating control signal. The first terminal of the second gating control transistor is connected to the second gating signal terminal to receive the second gating signal. The second terminal of the second gating control transistor is electrically connected to the gate of the second gating transistor.

7. The pixel circuit according to claim 6, wherein, The first gating storage sub-circuit includes a first gating storage capacitor. The first electrode of the first gating storage capacitor is electrically connected to the gate of the first gating transistor and the second electrode of the first gating control transistor at the first gating node. The second electrode of the first gating storage capacitor is connected to the first power supply terminal to receive the first power supply voltage. The second gating storage sub-circuit includes a second gating storage capacitor. The first electrode of the second gating storage capacitor is electrically connected to the gate of the second gating transistor and the second electrode of the second gating control transistor at the second gating node. The second electrode of the second gating storage capacitor is connected to the first power supply terminal to receive the first power supply voltage.

8. The pixel circuit according to any one of claims 3-7, further comprising: The second sub-pixel circuit includes a second driving sub-circuit and a third light-emitting element, wherein the second driving sub-circuit is configured to control the magnitude of the driving current flowing through the third light-emitting element; The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors from each other.

9. The pixel circuit according to claim 8, wherein, Also includes: The first data writing sub-circuit is configured to write a first data signal to the control terminal of the first driving sub-circuit in response to a first data scan signal. The first driving sub-circuit is configured to control the magnitude of the driving current flowing through the first light-emitting element or the second light-emitting element according to the first data signal. as well as The second data writing sub-circuit is configured to write a second data signal to the control terminal of the second driving sub-circuit in response to a second data scan signal. The second driving sub-circuit is configured to... The second data signal controls the magnitude of the driving current flowing through the third light-emitting element.

10. The pixel circuit according to claim 9, wherein, The pixel circuit also includes: A first data storage sub-circuit, wherein the first data writing sub-circuit is electrically connected to a first terminal of the first data storage sub-circuit, and the first data storage sub-circuit is configured to transmit the first data signal to the first terminal of the first data storage sub-circuit in response to the first data scanning signal. The first driving sub-circuit includes a control terminal, a first terminal, and a second terminal. The control terminal of the first driving sub-circuit is electrically connected to the first terminal of the first data storage sub-circuit. The first terminal of the first driving sub-circuit is configured to receive the first power supply voltage. The second terminal of the first driving sub-circuit, the second terminal of the first data storage sub-circuit, the first electrode of the first light-emitting element, and the first terminal of the first gating sub-circuit are electrically connected to a second node. The second data storage sub-circuit is provided, wherein the second data writing sub-circuit is electrically connected to the first terminal of the second data storage sub-circuit and is configured to transmit the second data signal to the first terminal of the second data storage sub-circuit in response to the second data scanning signal. The second driving sub-circuit includes a control terminal, a first terminal, and a second terminal. The control terminal of the second driving sub-circuit is electrically connected to the first terminal of the second data storage sub-circuit. The first terminal of the second driving sub-circuit is configured to receive the first power supply voltage. The second terminal of the second driving sub-circuit, the second terminal of the second data storage sub-circuit, and the first electrode of the third light-emitting element are electrically connected to a third node.

11. The pixel circuit according to claim 10, wherein, The first driving sub-circuit includes a first driving transistor, which is configured to control the current used to drive the first light-emitting element to emit light under the control of the voltage of the gate of the first driving transistor. The first electrode of the first driving transistor is configured to receive the first power supply voltage, the second electrode of the first driving transistor is electrically connected to the first electrode of the first light-emitting element, and the second electrode of the second light-emitting element is configured to receive the second power supply voltage. The second driving sub-circuit includes a second driving transistor, which is configured to control the current used to drive the third light-emitting element to emit light under the control of the voltage of the gate of the second driving transistor. The first electrode of the second driving transistor is configured to receive the first power supply voltage, and the second electrode of the second driving transistor is electrically connected to the first electrode of the third light-emitting element. The second electrode of the third light-emitting element is configured to receive the second power supply voltage. The first data storage sub-circuit includes a first data storage capacitor. The first electrode of the first data storage capacitor is electrically connected to the gate of the first driving transistor. The second electrode of the first data storage capacitor is electrically connected to the second terminal of the first driving transistor, the first electrode of the first light-emitting element, and the first terminal of the first gating transistor are all electrically connected to the second node. The second data storage sub-circuit includes a second data storage capacitor. The first electrode of the second data storage capacitor is electrically connected to the gate of the second driving transistor. The second electrode of the second data storage capacitor, the second electrode of the first driving transistor, and the first electrode of the first light-emitting element are all electrically connected to the third node.

12. The pixel circuit according to claim 11, wherein, The first data writing sub-circuit includes a first data transistor, the first terminal of the first data transistor is electrically connected to the first terminal of the first data storage capacitor and the gate of the first driving transistor, the second terminal of the first data transistor is configured to receive a first data signal, and the first data transistor is configured to write the first data signal into the gate of the first driving transistor and the first data storage capacitor in response to a first data scan signal. The second data writing sub-circuit includes a second data transistor, the first terminal of the second data transistor being electrically connected to the first terminal of the second data storage capacitor and the gate of the second driving transistor, the second terminal of the second data transistor being configured to receive a second data signal, and the second data transistor being configured to write the second data signal into the gate of the second driving transistor and the second data storage capacitor in response to a second data scan signal.

13. The pixel circuit according to any one of claims 9-12, wherein, The first sub-pixel circuit further includes: A first sensing sub-circuit, wherein a first terminal of the first sensing sub-circuit is electrically connected to a first electrode of the first light-emitting element, a control terminal of the first sensing sub-circuit is configured to receive a first sensing scan signal, a second terminal of the first sensing sub-circuit is electrically connected to a first sensing signal line, the first sensing signal line is electrically connected to a first external detection circuit, and the first sensing sub-circuit is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the first sensing scan signal through the first external detection circuit to achieve compensation. The second sub-pixel circuit also includes: The second sensing sub-circuit, wherein a first terminal of the second sensing sub-circuit is electrically connected to a first electrode of the third light-emitting element, and a control terminal of the second sensing sub-circuit is configured to receive a second sensor signal. The second sensing sub-circuit is electrically connected to a second sensing signal line, which is electrically connected to a second external detection circuit. The second sensing sub-circuit is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second sensing scanning signal to achieve compensation.

14. The pixel circuit according to claim 13, wherein, The first sensing sub-circuit includes a first sensing transistor, the first electrode of the first sensing transistor is electrically connected to the first electrode of the first light-emitting element, the second electrode of the first sensing transistor is electrically connected to the first sensing signal line to connect to the first external detection circuit, the gate of the first sensing transistor is configured to receive the first sensing scan signal, and the first sensing transistor is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the first sensing scan signal through the first external detection circuit to achieve external compensation. The second sensing sub-circuit includes a second sensing transistor, the first electrode of which is electrically connected to the first electrode of the third light-emitting element, and the second electrode of which is electrically connected to the second sensing signal line to connect to the second external detection circuit. The gate of the second sensing transistor is configured to receive the second sensing scan signal, and the second sensing transistor is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second sensing scan signal to achieve external compensation by the second external detection circuit.

15. The pixel circuit according to claim 13 or 14, wherein, The pixel circuit further includes a second sub-pixel circuit, and the second sub-pixel circuit further includes: The system comprises a second driving sub-circuit, a third light-emitting element, and a fourth light-emitting element. The second driving sub-circuit is configured to control the magnitude of the driving current flowing through the third light-emitting element or the magnitude of the driving current flowing through the fourth light-emitting element. The second electrode of the third light-emitting element and the first electrode of the fourth light-emitting element are electrically connected. The first electrode of the third light-emitting element is configured to receive the first power supply voltage, and the second electrode of the fourth light-emitting element is configured to receive the second power supply voltage. The first, second, third, and fourth light-emitting elements emit different colors from each other. A third gating sub-circuit, connected in parallel with the third light-emitting element, is configured to determine whether a drive current flows through the third light-emitting element in response to a third gating signal applied to the drive terminal of the third gating sub-circuit; and A fourth gating sub-circuit, connected in parallel with the fourth light-emitting element, is configured to determine whether a drive current flows through the fourth light-emitting element in response to a fourth gating signal applied to the drive terminal of the fourth gating sub-circuit. The fourth light-emitting element.

16. The pixel circuit according to claim 15, wherein, The first terminal of the third gating sub-circuit is electrically connected to the first electrode of the third light-emitting element, and the second terminal of the third gating sub-circuit, the second electrode of the third light-emitting element, the first electrode of the fourth light-emitting element, and the first terminal of the fourth gating sub-circuit are electrically connected to the fourth node; The second terminal of the fourth gating sub-circuit is electrically connected to the second electrode of the fourth light-emitting element.

17. The pixel circuit according to claim 15 or 16, wherein, The first sub-pixel circuit further includes: A third gating control subcircuit is configured to apply a third gating signal to a driving terminal of the third gating subcircuit in response to a third gating control signal applied to a control terminal of the third gating control subcircuit, wherein the driving terminal of the third gating control subcircuit is electrically connected to the third gating control terminal to receive the third gating control signal, a first terminal of the third gating control subcircuit is connected to a third gating signal terminal to receive the third gating signal, and a second terminal of the third gating control subcircuit is electrically connected to the driving terminal of the third gating subcircuit; and A fourth gating control subcircuit is configured to apply a fourth gating signal to a driving terminal of the fourth gating subcircuit in response to a fourth gating control signal applied to a control terminal of the fourth gating control subcircuit, wherein the driving terminal of the fourth gating control subcircuit is electrically connected to the fourth gating control terminal to receive the fourth gating control signal, a first terminal of the fourth gating control subcircuit is connected to the fourth gating signal terminal to receive the fourth gating signal, and a second terminal of the fourth gating control subcircuit is electrically connected to the driving terminal of the fourth gating subcircuit.

18. The pixel circuit according to claim 17, further comprising: The third gating storage sub-circuit is configured to transmit the third gating signal to the first terminal of the third gating storage sub-circuit in response to the third gating control signal, wherein the first terminal of the third gating storage sub-circuit is electrically connected to the driving terminal of the third gating sub-circuit and the second terminal of the third gating control sub-circuit at the third gating node, and the second terminal of the third gating storage sub-circuit is connected to the first power supply terminal to receive the first power supply voltage; A fourth gating storage subcircuit is configured to transmit a fourth gating signal to a first terminal of the fourth gating storage subcircuit in response to the fourth gating control signal. The first terminal of the fourth gating storage subcircuit is electrically connected to the driving terminal of the fourth gating subcircuit and the second terminal of the fourth gating control subcircuit at the fourth gating node. The second terminal of the fourth gating storage subcircuit is connected to... The first power supply terminal is connected to receive the first power supply voltage.

19. The pixel circuit according to claim 18, wherein, The third gating sub-circuit includes a third gating transistor, the gate of which serves as the driving terminal of the third gating sub-circuit, the first electrode of which is electrically connected to the third electrode of the third light-emitting element, and the second electrode of which is electrically connected to the fourth electrode of the third light-emitting element. The fourth gating sub-circuit includes a fourth gating transistor. The gate of the fourth gating transistor serves as the driving terminal of the fourth gating sub-circuit. The first electrode of the fourth gating transistor is electrically connected to the third electrode of the fourth light-emitting element, and the second electrode of the fourth gating transistor is electrically connected to the second electrode of the fourth light-emitting element.

20. The pixel circuit according to claim 19, wherein, The third gating control sub-circuit includes a third gating control transistor. The gate of the third gating control transistor is electrically connected to the third gating control terminal to receive the third gating control signal. The first terminal of the third gating control transistor is connected to the third gating signal terminal to receive the first gating signal. The second terminal of the third gating control transistor is electrically connected to the gate of the third gating transistor. The fourth gating control sub-circuit includes a fourth gating control transistor. The gate of the fourth gating control transistor is electrically connected to the fourth gating control terminal to receive the fourth gating control signal. The first terminal of the fourth gating control transistor is connected to the fourth gating signal terminal to receive the fourth gating signal. The second terminal of the fourth gating control transistor is electrically connected to the gate of the fourth gating transistor.

21. The pixel circuit according to claim 19, wherein, The first data scanning signal is applied to the control terminal of the first data writing sub-circuit, and the second data scanning signal is applied to the control terminal of the second data writing sub-circuit; The control terminals of the first data writing sub-circuit, the second data writing sub-circuit, the first sensing sub-circuit, and the second sensing sub-circuit are electrically connected to the same sensing scan line, and the first data scan signal, the second data scan signal, the first sensing scan signal, and the second sensing scan signal are the same scan signal.

22. The pixel circuit according to claim 17, wherein, One of the first terminals of the first and second gating control subcircuits is electrically connected to the first terminals of the third and fourth gating control subcircuits via the same first gating signal line and the same first gating signal terminal. The other terminal of the first and second gating control subcircuits is electrically connected to the other terminal of the third and fourth gating control subcircuits via the same second gating signal line and the same second gating signal terminal. The gating control signals from the first gating signal terminal and the second gating signal terminal are different.

23. The pixel circuit according to any one of claims 15-22, wherein, In adjacent pixel columns, the same gating signal is transmitted using the same gating signal line, and the same gating signal is at least one of the first gating signal, the second gating signal, the third gating signal, and the fourth gating signal.

24. A driving method for a pixel circuit, wherein, The driving method is applicable to the pixel circuit according to any one of claims 1-23, wherein the display period of a frame image includes at least two time periods, and the driving method includes: The first light-emitting element and the second light-emitting element are controlled to emit light at different times by controlling the first gating signal applied to the driving terminal of the first gating sub-circuit and the second gating signal applied to the driving terminal of the second gating sub-circuit.

25. The driving method for the pixel circuit according to claim 24, wherein, The at least two time periods include a first time period and a second time period, wherein in the first time period, one of the first light-emitting element and the second light-emitting element emits light of a first color, and in the second time period, the other of the first light-emitting element and the second light-emitting element emits light of a second color; The first time period includes a first gating and data writing phase, and a first light emission phase following the first gating and data writing phase; The second time period includes a second gating and data writing phase, and a second light emission phase following the second gating and data writing phase; In the first gating and data writing stage and the second gating and data writing stage, both the first gating control signal and the second gating control signal are enabled signals. The first gating signal is written to the control terminal of the first gating sub-circuit through the first gating control sub-circuit, and the second gating signal is written to the control terminal of the second gating sub-circuit through the second gating control sub-circuit. In both the first gating and data writing phase and the second gating and data writing phase, the first gating signal and the second gating signal are mutually opposite signals, so that the first gating signal and the second gating signal are mutually opposite signals. One of the first selection sub-circuit and the second selection sub-circuit is turned on, and the other of the first selection sub-circuit and the second selection sub-circuit is turned off, so that during the first light-emitting stage and the second light-emitting stage, the light-emitting element connected in parallel with the turned-on sub-circuit does not emit light and the light-emitting element connected in parallel with the turned-off sub-circuit does not emit light.

26. The driving method for a pixel circuit according to claim 25, wherein, The pixel circuit includes a first data writing sub-circuit, which is configured to write a first data signal to the control terminal of the first driving sub-circuit in response to a first data scan signal. The first driving sub-circuit is configured to control the magnitude of the driving current flowing through the first light-emitting element or the second light-emitting element based on the first data signal. The driving method for the pixel circuit includes: During the first gating and data writing phase, the first data signal for controlling the grayscale of the first color is written. During the second gating and data writing phase, the second data signal used to control the grayscale of the second color is written.

27. The driving method for the pixel circuit according to claim 25 or 26, wherein, The first time period also includes a first reset phase that precedes the first strobe and data write phases; During the first reset phase, the first gating control signal is an enable signal to enable conduction between the first terminal and the second terminal of the first gating control sub-circuit. The first gating signal written to the control terminal of the first gating sub-circuit through the first gating control sub-circuit is an enable signal to enable conduction between the first terminal and the second terminal of the first gating sub-circuit via the first gating sub-circuit. The second gating control signal is an enable signal to enable conduction between the first and second terminals of the second gating control sub-circuit. The second gating signal, written to the control terminal of the second gating sub-circuit through the second gating control sub-circuit, is a disable signal to disable conduction between the first and second terminals of the second gating sub-circuit. Furthermore, the first reset signal is applied to the second electrode of the first light-emitting element via the first electrode of the first light-emitting element, the first terminal and the second terminal of the first gating sub-circuit, to reset the electrical signal of the second electrode of the first light-emitting element.

28. The driving method for the pixel circuit according to any one of claims 24-27, wherein, The pixel circuit includes a second sub-pixel circuit, which includes a second driving sub-circuit and a third light-emitting element. The second driving sub-circuit is configured to control the magnitude of the driving current flowing through the third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors from each other. The at least two time periods include a first time period and a second time period, wherein the first time period includes a first luminescence phase and the second time period includes a second luminescence phase; During the first light-emitting stage, the third light-emitting element emits light along with one of the first light-emitting element and the second light-emitting element; In the second light-emitting stage, the third light-emitting element emits light along with the other of the first and second light-emitting elements.

29. The driving method for the pixel circuit according to any one of claims 24-28, wherein, The second sub-pixel circuit further includes a second driving sub-circuit, a third light-emitting element and a fourth light-emitting element, a third gating sub-circuit and a fourth gating sub-circuit, wherein the second driving sub-circuit is configured to control the magnitude of the driving current flowing through the third light-emitting element or the magnitude of the driving current flowing through the fourth light-emitting element. The second electrode of the third light-emitting element and the first electrode of the fourth light-emitting element are electrically connected. The first electrode of the third light-emitting element is configured to receive the first power supply voltage, and the second electrode of the fourth light-emitting element is configured to receive the second power supply voltage. The first, second, third, and fourth light-emitting elements emit different colors. The third gating sub-circuit is connected in parallel with the third light-emitting element and is configured to determine whether a driving current flows through the third light-emitting element in response to a third gating signal applied to the driving terminal of the third gating sub-circuit. The fourth gating sub-circuit is connected in parallel with the fourth light-emitting element and is configured to determine whether a driving current flows through the fourth light-emitting element in response to a second gating signal applied to the driving terminal of the fourth gating sub-circuit. The at least two time periods include a first time period and a second time period, and the driving method includes: By controlling the first gating signal applied to the driving terminal of the first gating sub-circuit, the second gating signal applied to the driving terminal of the second gating sub-circuit, the third gating signal applied to the driving terminal of the third gating sub-circuit, and the fourth gating signal applied to the driving terminal of the fourth gating sub-circuit, the following can be achieved: During the first time period, one of the first light-emitting element and the second light-emitting element emits light along with one of the third light-emitting element and the fourth light-emitting element; During the second time period, the other of the first and second light-emitting elements is... The third light-emitting element and the other of the fourth light-emitting elements emit light.

30. The driving method for the pixel circuit according to claim 25 or 26, wherein, The first time period also includes a first reset phase that precedes the first strobe and data write phases; During the first reset phase, the first gating control signal is an enable signal to enable conduction between the first and second terminals of the first gating control sub-circuit. The first gating signal written to the control terminal of the first gating sub-circuit via the first gating control sub-circuit is a disable signal to disable conduction between the first and second terminals of the first gating sub-circuit. The second gating control signal is an enable signal that enables conduction between the first and second terminals of the second gating control sub-circuit. The second gating signal, written to the control terminal of the second gating sub-circuit through the second gating control sub-circuit, is an enable signal that enables conduction between the first and second terminals of the second gating sub-circuit via the second gating sub-circuit. Furthermore, the second power supply voltage is applied to the second electrode of the first light-emitting element via the second gating sub-circuit to reset the electrical signal of the second electrode of the first light-emitting element.

31. A display panel comprising the pixel circuitry of any one of claims 1-23.

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