Display panel

Abstract

A display panel. In at least one of a first stage of a write frame in which a data signal (Data) is stored in a gate of a driving transistor (T1) and a compensation transistor (T3) is turned off and a corresponding second stage in a hold frame, a first reset signal (Vi3) is transmitted to a source of the driving transistor (T1); in a third stage following the first stage and a fourth stage following the second stage, a light emitting element (EL) emits light; and between the first stage and the third stage, and / or between the second stage and the fourth stage, a first reset transistor (T8) is turned off to maintain the potential of the source of the driving transistor (T1) at the voltage of the first reset signal (Vi3).

Description

Display panel

[0001] This application claims priority to Chinese patent application No. 202410703856.9, filed on May 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology. Background Technology

[0003] Currently, low-frequency display technology is widely used to reduce the power consumption of display products.

[0004] Low-frequency display includes write frames and hold frames. Since the hold frame does not require writing data signals and needs to maintain the gate potential of the driving transistor without change, the characteristics of the driving transistor in this stage are significantly different from those in the write frame. This results in a significant difference in the brightness of the sub-pixel in the hold frame compared to the brightness in the write frame, causing screen flickering.

[0005] Therefore, existing low-frequency display technologies suffer from the aforementioned problems and urgently need improvement. Technical issues

[0006] In existing low-frequency display technologies, the brightness difference between the written frame and the held frame causes screen flickering. Technical solutions

[0007] This application provides a display panel having a first working mode operating at a first refresh rate and a second working mode operating at a second refresh rate, wherein the first refresh rate is greater than the second refresh rate;

[0008] When in the first working mode, the display panel has a first write frame; when in the second working mode, the display panel has a second write frame and a second hold frame. The second write frame includes a first stage and a third stage following the first stage. The second hold frame includes a second stage corresponding to the first stage and a fourth stage following the second stage and corresponding to the third stage.

[0009] Includes multiple pixel circuits, the pixel circuits including:

[0010] Light-emitting elements;

[0011] A driving transistor, connected to the light-emitting element, is used to generate a driving current based on the data signal in both the second write frame and the corresponding second hold frame to drive the light-emitting element to emit light.

[0012] A storage capacitor, electrically connected to the gate of the driving transistor, is used to store the data signal;

[0013] A compensation transistor is electrically connected between the gate and drain of the driving transistor;

[0014] A first reset transistor is electrically connected to the source of the driving transistor. In the first stage, the gate of the driving transistor stores the data signal and the compensation transistor is turned off. In at least one of the first stage and the corresponding second stage, the first reset transistor is turned on in response to a first gate pulse of the first gate signal to transmit the first reset signal to the source of the driving transistor.

[0015] The first switching transistor is electrically connected to the source of the driving transistor;

[0016] The second switching transistor is electrically connected to the drain of the driving transistor. In the third stage and the corresponding fourth stage, both the first switching transistor and the second switching transistor are turned on in response to the second gate pulse of the second gate signal to generate the driving current.

[0017] Wherein, at least one of the first stage and the third stage, and the corresponding second stage and the fourth stage, has a time interval, and the first reset transistor is used to turn off during the time interval to maintain the potential of the source of the driving transistor as the voltage of the first reset signal;

[0018] Wherein, the duration of the time interval is greater than or equal to 4H, 1H equals 1 / (f*m), f is the refresh rate of the display panel, m is the number of groups of the pixel circuit, and multiple pixel circuits in the same group are loaded with the same first gate signal and the same second gate signal.

[0019] The second write frame further includes a fifth stage preceding the first stage;

[0020] In the first and fifth phases, the first reset transistor is turned on in response to another first gate pulse of the first gate signal to transmit the first reset signal to the source of the driving transistor, wherein the voltage of the first reset signal in the first phase of the second write frame is different from the voltage in the third phase.

[0021] This application embodiment also provides another display panel having a first working mode operating at a first refresh rate and a second working mode operating at a second refresh rate, wherein the first refresh rate is greater than the second refresh rate;

[0022] When in the first working mode, the display panel has a first write frame; when in the second working mode, the display panel has a second write frame and a second hold frame. The second write frame includes a first stage and a third stage following the first stage. The second hold frame includes a second stage corresponding to the first stage and a fourth stage following the second stage and corresponding to the third stage.

[0023] Includes multiple pixel circuits, the pixel circuits including:

[0024] Light-emitting elements;

[0025] A driving transistor, connected to the light-emitting element, is used to generate a driving current based on the data signal in both the second write frame and the corresponding second hold frame to drive the light-emitting element to emit light.

[0026] A storage capacitor, electrically connected to the gate of the driving transistor, is used to store the data signal;

[0027] A compensation transistor is electrically connected between the gate and drain of the driving transistor;

[0028] A first reset transistor is electrically connected to the source of the driving transistor. In the first stage, the gate of the driving transistor stores the data signal and the compensation transistor is turned off. In at least one of the first stage and the corresponding second stage, the first reset transistor is turned on in response to a first gate pulse of the first gate signal to transmit the first reset signal to the source of the driving transistor.

[0029] The first switching transistor is electrically connected to the source of the driving transistor;

[0030] The second switching transistor is electrically connected to the drain of the driving transistor. In the third stage and the corresponding fourth stage, both the first switching transistor and the second switching transistor are turned on in response to the second gate pulse of the second gate signal to generate the driving current.

[0031] There is a time interval between at least one of the first stage and the third stage, and between the corresponding second stage and the fourth stage, wherein the first reset transistor is used to turn off during the time interval to maintain the potential of the source of the driving transistor as the voltage of the first reset signal.

[0032] This application embodiment also provides a display panel having a first working mode operating at a first refresh rate and a second working mode operating at a second refresh rate, wherein the first refresh rate is greater than the second refresh rate;

[0033] When in the first working mode, the display panel has a first write frame; when in the second working mode, the display panel has a second write frame and a second hold frame. The second write frame includes a first stage, a third stage after the first stage, and a fifth stage before the first stage. The second hold frame includes a second stage corresponding to the first stage and a fourth stage corresponding to the third stage after the second stage.

[0034] Includes multiple pixel circuits, the pixel circuits including:

[0035] Light-emitting elements;

[0036] A driving transistor, connected to the light-emitting element, is used to generate a driving current based on the data signal in both the second write frame and the corresponding second hold frame to drive the light-emitting element to emit light.

[0037] A storage capacitor, electrically connected to the gate of the driving transistor, is used to store the data signal;

[0038] A compensation transistor is electrically connected between the gate and drain of the driving transistor;

[0039] A first reset transistor is electrically connected to the source of the driving transistor. In the first stage, the gate of the driving transistor stores the data signal and the compensation transistor is turned off. In at least one of the first stage and the corresponding second stage, the first reset transistor is turned on in response to a first gate pulse of the first gate signal to transmit the first reset signal to the source of the driving transistor.

[0040] The first switching transistor is electrically connected to the source of the driving transistor;

[0041] The second switching transistor is electrically connected to the drain of the driving transistor. In the third stage and the corresponding fourth stage, both the first switching transistor and the second switching transistor are turned on in response to the second gate pulse of the second gate signal to generate the driving current.

[0042] The first gate signal further includes at least the first gate pulse located in the fifth stage, and the pulse width of the first gate pulse located in at least one of the first stage and the second stage is greater than the pulse width of the first gate pulse located in the fifth stage. Beneficial effects

[0043] This application provides a display panel in which, during at least one of the following stages—a first stage in the second write frame where the data signal is stored at the gate of the driving transistor and the compensation transistor is turned off, and a second stage in the corresponding second hold frame corresponding to the first stage—the first reset transistor is configured to be turned on in response to a first gate pulse of the first gate signal to transmit a first reset signal to the source of the driving transistor. Furthermore, in a third stage after the first stage in the second write frame and a fourth stage after the second stage in the corresponding second hold frame, both the first and second switching transistors are configured to be turned on in response to a first gate pulse of the first gate signal to transmit a first reset signal to the source of the driving transistor. The drive transistor is turned on by the second gate pulse of the second gate signal to generate the drive current, and there is a time interval between at least one of the first and third stages and between the second and fourth stages to turn off the first reset transistor to maintain the potential of the source of the drive transistor as the voltage of the first reset signal. This allows the voltage difference state between the gate and source of the drive transistor to be adjusted for at least one of the second write frame and the second hold frame for a longer duration, thereby improving the effect of adjusting the voltage difference state between the gate and source of the drive transistor in this stage. This effectively reduces the difference in light emission brightness of multiple light-emitting elements in the second hold frame and the second write frame, and improves the low-frequency flicker phenomenon. Attached Figure Description

[0044] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0045] Figure 1 is a schematic diagram of the pixel circuit provided in an embodiment of this application.

[0046] Figures 2 and 4 are two waveform diagrams of multiple signals provided in the embodiments of this application during the second write frame.

[0047] Figures 3 and 5 show two waveforms of multiple signals in the second holding frame provided in the embodiments of this application.

[0048] Figure 6 is a flowchart of the driving method for the display panel provided in an embodiment of this application. Embodiments of the present invention

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0050] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified; "electrical connection" indicates that the two are conductive, and is not limited to a direct or indirect connection.

[0051] In addition, it should be noted that the accompanying drawings only provide structures and steps that are closely related to this application, and omit some details that are not closely related to the application. The purpose is to simplify the drawings and make the application points clear at a glance, rather than indicating that the actual device is exactly the same as the drawings, and it is not intended to limit the actual device.

[0052] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the embodiments of this application without departing from the spirit and scope of this application, and such modifications or equivalent substitutions should all be covered within the scope of this application. Furthermore, each embodiment can be combined with each other, but will not be described in detail here.

[0053] This application provides a display panel, which may include, but is not limited to, the following embodiments and combinations thereof.

[0054] In some embodiments, the display panel has a first operating mode operating at a first refresh rate and a second operating mode operating at a second refresh rate, wherein the first refresh rate is greater than the second refresh rate; in the first operating mode, the display panel has a first write frame, and in the second operating mode, the display panel has a second write frame and a second hold frame, wherein the second write frame includes a first stage (stage 4) and a third stage (stage 5) following the first stage, and the second hold frame includes a second stage (stage 4') corresponding to the first stage and a fourth stage (stage 5') following the second stage and corresponding to the third stage; the display panel includes a plurality of pixel circuits, as shown in Figures 1 to 5, wherein the pixel circuit 100 includes: a light-emitting element EL; a driving transistor T1 connected to the light-emitting element EL, used to generate a driving current according to a data signal Data (potential may be greater than 0) in both the second write frame and the corresponding second hold frame to drive the light-emitting element EL to emit light; and a storage capacitor electrically connected to the gate of the driving transistor T1. The data signal Data is stored in the drive transistor T1. A compensation transistor T3 is electrically connected between the gate (electrically connected to node Q) and drain (electrically connected to node B) of the drive transistor T1. A first reset transistor T8 is electrically connected to the source (electrically connected to node A) of the drive transistor T1. In the first stage (stage 4), the gate of the drive transistor T1 stores the data signal Data and the compensation transistor T3 is turned off. In at least one of the first stage and the corresponding second stage (stage 4'), the first reset transistor T8 is turned on in response to the (second) first gate pulse p1 of the first gate signal Pscan2 to transmit the first reset signal Vi3 to the source of the drive transistor T1. A first switching transistor is also present. T5 is electrically connected to the source of the driving transistor T1; the second switching transistor T6 is electrically connected to the drain of the driving transistor T1. In the third stage (stage 5) and the corresponding fourth stage (stage 5'), both the first switching transistor T5 and the second switching transistor T6 are turned on in response to the second gate pulse p2 of the second gate signal EM to generate the driving current; wherein, at least one of the first stage and the third stage, and at least one of the corresponding second stage and the fourth stage, has a time interval (at least one of stage 4-1 and stage 4-1'), and the first reset transistor T8 is turned off during the time interval to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3.

[0055] The display panel can be, but is not limited to, an organic self-emissive display panel or an inorganic self-emissive direct-view display panel. The difference lies in whether the corresponding light-emitting element (EL) is an organic self-emissive device or an inorganic self-emissive device. Each light-emitting element (EL) is controlled to emit light by its respective pixel circuit and the signal it receives. Specifically, the multiple pixel circuits 100 in the display panel can be divided into multiple groups. Multiple pixel circuits 100 in the same group can be electrically connected to the same group of gate lines. Each group of gate lines can include, but is not limited to, a first gate line for transmitting the corresponding first gate signal Pscan2 and a second gate line for transmitting the corresponding second gate signal EM. The multiple gate signals transmitted by the multiple groups of gate lines can control the multiple groups of pixel circuits 100 to turn on sequentially. At the same time, when each pixel circuit 100 is turned on, its corresponding data signal Data can also be loaded to control the corresponding light-emitting element (EL) to emit light at the corresponding brightness.

[0056] Here, the refresh rate f represents the number of times the display panel can refresh the image in one second. Each refresh of the display panel can be understood as multiple groups of pixel circuits 100 being turned on in sequence, and each pixel circuit 100 can be loaded with the corresponding data signal Data for that frame. Therefore, 1 / f can be understood as the time required for the display panel to refresh the image once. If the display panel includes m groups of pixel circuits 100, then the average time for each group of pixel circuits 100 to be turned on is 1 / (f*m).

[0057] It should be noted that this example uses a first refresh rate that is greater than a second refresh rate. Therefore, the second working mode corresponding to the latter can be considered as the low-frequency working mode of the display panel. In this case, it must include a second hold frame after the second write frame. In contrast, in the high-frequency working mode, a first hold frame may or may not be set after the first write frame. This is not limited here.

[0058] For low-frequency display technology (using the second refresh rate in the second operating mode as an example), the frame used by the display panel to refresh the displayed image is called the second write frame. In the second write frame, multiple sets of pixel circuits 100 need to be sequentially activated, and a corresponding data signal Data is input to each pixel circuit 100 (refer to the above discussion). After the second write frame, at least one second hold frame can be provided. In the second hold frame, it is not necessary to sequentially activate multiple sets of pixel circuits 100 to input the corresponding data signal Data again. Instead, the gate of the driving transistor T1 in each pixel circuit 100 is maintained at the same potential as in the second write frame (related to the corresponding data signal Data), so as to generate the same driving current as in the second write frame to drive the light-emitting element EL to emit light of the same brightness. That is, the image presented by the display panel in the second write frame and the corresponding second hold frame is the same. Furthermore, the more second hold frames set after each second write frame, the lower the corresponding refresh rate, meaning the display panel needs to refresh the image again after such a large interval of second hold frames. Because the voltage difference between the gate and source of the driving transistor T1 in the pixel circuit 100 is significantly different in the second write frame and the second hold frame, the characteristics of the driving transistor T1 are also significantly different. This results in a significant difference in the brightness of multiple light-emitting elements EL in the second hold frame and the second write frame, causing screen flickering.

[0059] As shown in Figure 1, in the pixel circuit 100 of this embodiment, since the compensation transistor T3 is electrically connected between the gate and drain of the driving transistor T1, during the cutoff phase of the corresponding compensation transistor T3 in at least one of the second write frame and the corresponding second hold frame (each phase in the second write frame and the second hold frame is correspondingly set), it can be considered that the gate and drain of the driving transistor T1 are electrically disconnected at this time. At this time, the potential of the gate of the driving transistor T1 is maintained at the previous potential (related to the corresponding data signal Data) through the storage capacitor. At this time, the first reset transistor T8, which is electrically connected to the source of the driving transistor T1, is used to respond to the first gate signal. The first gate pulse p1 of signal Pscan2 turns on the transistor to transmit the first reset signal Vi3 to the source of the driving transistor T1. That is, during this stage, the potential of the source of the driving transistor T1 can be controlled by turning on the first reset transistor T8, so that the voltage difference between the gate and source of the driving transistor T1 can be adjusted in at least one of the second write frame and the corresponding second hold frame. After this (regardless of whether this frame is the second write frame or the second hold frame), the first switching transistor T5 and the second switching transistor T6 are turned on in response to the second gate pulse p2 of the second gate signal EM to generate a driving current to drive the light-emitting element EL to emit light.

[0060] To address the aforementioned technical issues, and in conjunction with Figures 1 to 3, this embodiment sets at least one of the first stage (stage 4) and the third stage (stage 5) in the second write frame, and the corresponding second stage (stage 4') and the fourth stage (stage 5') in the second hold frame, to have a time interval (i.e., setting at least one of stage 4-1 and stage 4-1'). The first reset transistor T8 is used to cut off during the time interval to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3. That is, the potential of the source of the driving transistor T1 in each pixel circuit 100 can remain close to the first reset signal Vi3 within the aforementioned added "time interval," thus allowing a longer adjustment period for the voltage difference between the gate and source of the driving transistor T1. This improves the effect of adjusting the voltage difference between the gate and source of the driving transistor T1 during this stage, effectively reducing the brightness difference between multiple light-emitting elements EL in the second hold frame and the second write frame, and improving the screen flickering phenomenon.

[0061] Furthermore, the duration of the time interval ti between the start time of the first gate pulse p1 and the start time of the corresponding second gate pulse p2 is greater than or equal to 4H, where 1H equals 1 / (f*m), f is the refresh rate of the display panel, m is the number of groups of the pixel circuit 100, and multiple pixel circuits 100 in the same group are loaded with the same first gate signal Pscan2 and the same second gate signal EM.

[0062] Understandably, the time interval ti between the start time of the first gate pulse p1 and the start time of the corresponding second gate pulse p2 is set to be greater than or equal to 4H (approximately the duration of the four sets of pixel circuits 100 being turned on). That is, the potential of the source of the driving transistor T1 in each set of pixel circuits 100 can approach the first reset signal Vi3 within a duration of 4H, so that the voltage difference state between the gate and source of the driving transistor T1 is adjusted for a longer period of time, thereby improving the effect of adjusting the voltage difference state between the gate and source of the driving transistor T1 in this stage, thereby effectively reducing the difference in light emission brightness of multiple light-emitting elements EL in the second holding frame and the second writing frame, and improving the screen flickering phenomenon.

[0063] In some embodiments, as shown in Figures 1 to 3, the pixel circuit 100 further includes: a data writing transistor T2, electrically connected to the source of the driving transistor T1 (electrically connected to node A), for being turned on in the second write frame in response to the fifth gate pulse p5 of the fifth gate signal Pscan1 to transmit the data signal Data to the source of the driving transistor T1; and a second reset transistor T4, electrically connected to the gate of the driving transistor T1 (electrically connected to node Q), for being turned on before the data writing transistor T2 is turned on in the second write frame. The compensation transistor T3 is turned on in response to the third gate pulse p3 of the third gate signal Nscan2 to transmit the second reset signal Vi_G to the gate of the driving transistor T1; the compensation transistor T3 is turned on in response to the fourth gate pulse p4 of the fourth gate signal Nscan1 when the data writing transistor T2 is turned on to transmit the data signal Data to the gate of the driving transistor T1, and is turned on when the second reset transistor T4 is turned on to transmit the second reset signal Vi_G to the drain (electrically connected to node B) and source of the driving transistor T1.

[0064] Specifically, in stage 2 of the second write frame in this embodiment, the second reset transistor T4 can first turn on in response to the third gate signal Nscan2 to transmit the second reset signal Vi_G to the gate of the driving transistor T1. Then, the compensation transistor T3 turns on in response to the fourth gate signal Nscan1 to transmit the second reset signal Vi_G sequentially to the drain and source of the driving transistor T1 via the gate of the driving transistor T1. Therefore, it is also called "Vi_G reset". In stage 3 of the second write frame (located after stage 2), the data write transistor T2 can turn on in response to the fifth gate signal Pscan1 to transmit the data signal Data to the source of the driving transistor T1. At the same time, the compensation transistor T3 also turns on in response to the fourth gate signal Nscan1 to transmit the data signal Data sequentially to the drain and gate of the driving transistor T1 via the source of the driving transistor T1. Therefore, it is also called "Data write".

[0065] It is understood that the compensation transistor T3 in this embodiment can be turned on at different stages to realize the electrical connection between the gate and drain of the driving transistor T1, thereby realizing the transmission of signals between the gate and drain of the driving transistor T1. Furthermore, when the driving transistor T1 is turned on, the interaction between the source and drain potentials of the driving transistor T1 can also be realized, thereby realizing the functions of resetting and writing data in the pixel circuit 100.

[0066] Furthermore, referring to Figures 1 to 3, the storage capacitor includes: a first storage capacitor Cst, electrically connected between the gate of the driving transistor T1 and the first voltage line for transmitting the first constant voltage signal VDD; and a second storage capacitor Cboost, electrically connected between the gate of the driving transistor T1 and the gate of the data writing transistor T2. Since one end of the second storage capacitor Cboost (electrically connected to the gate of the data writing transistor T2) is loaded with the fifth gate signal Pscan1, after stage 3 in the second write frame, the potential of the gate of the driving transistor T1 becomes close to the potential of the data signal Data. The end time of stage 3 in the second write frame is the rising edge of the fifth gate pulse p5 of the fifth gate signal Pscan1. The coupling effect of the second storage capacitor Cboost causes the potential of the gate of the driving transistor T1 to rise accordingly, thereby appropriately adjusting the range of the potential of the gate of the driving transistor T1 (so that the potential of the actual required data signal Data can be lower, thereby reducing power consumption). When the potential of the fifth gate signal Pscan1 is stable and the compensation transistor T3 is turned off, since the potential of one end of the first storage capacitor Cst (electrically connected to the first voltage line) is constant, the potential of the gate of the driving transistor T1 can be kept stable to store the data signal Data.

[0067] In some embodiments, as shown in Figures 1 to 3, the pixel circuit 100 further includes: a third reset transistor T7 electrically connected to the light-emitting element EL, configured to be turned on in response to the first gate pulse p1 of the first gate signal Pscan2 in each of the second write frame and the corresponding second hold frame to transmit the third reset signal Vi_Ano to the light-emitting element EL; the first switching transistor T5, the second switching transistor T6 and the driving transistor T1 are connected in series, the source of the first switching transistor T5 is electrically connected to a first voltage line for transmitting the first constant voltage signal VDD, and the drain of the second switching transistor T6 is electrically connected to the light-emitting element EL.

[0068] Specifically, the anode of the light-emitting element EL (electrically connected to node C) can be electrically connected to the drain of the driving transistor T1 and the drain of the second switching transistor T6, and the cathode of the light-emitting element EL (electrically connected to node B) can be grounded to have a second constant voltage signal VSS (potential close to ground potential, approximately 0). In stage 1 of the second write frame, the third reset transistor T7 can be turned on in response to the (first) first gate pulse p1 of the first gate signal Pscan2 to transmit the third reset signal Vi_Ano to the anode of the light-emitting element EL to reset it. Simultaneously, the first reset transistor T8 is also turned on to transmit the first reset signal Vi3 to the source of the driving transistor T1; hence, this is also referred to as "Vi3 writing." In stage 5 of the second write frame, the first switching transistor T5 and the second switching transistor T6 can be turned on in response to the second gate pulse p2 of the second gate signal EM, so that the first voltage line and ground are directly connected to generate a driving current to drive the light-emitting element EL to emit light.

[0069] This application also provides a method for driving a display panel, which can be including but not limited to the following embodiments and combinations thereof.

[0070] In some embodiments, as shown in FIG6, the driving method for the display panel described above may include, but is not limited to, the following steps.

[0071] S1, in at least one of the first stage in the second write frame where the data signal is stored at the gate of the driving transistor and the compensation transistor is turned off, and the second stage in the corresponding second hold frame corresponding to the first stage, the first reset transistor is turned on in response to the first gate pulse of the first gate signal to transmit the first reset signal to the source of the driving transistor.

[0072] As discussed above, in at least one of the first stage (where the compensation transistor T3 is turned off in the second write frame and the potential of the gate of the driving transistor T1 is maintained at the previous potential (related to the corresponding data signal Data) through the storage capacitor) and the second stage (corresponding to the second hold frame), the potential of the gate of the driving transistor T1 is maintained as related to the corresponding data signal Data. During this period, the first reset transistor T8 is turned on in response to the first gate pulse p1 of the first gate signal Pscan2 to transmit the first reset signal Vi3 to the source of the driving transistor T1, so that the voltage difference state between the gate and source of the driving transistor T1 can be adjusted in at least one of the second write frame and the corresponding second hold frame.

[0073] S2, in the third stage after the first stage in the second write frame, and in the fourth stage corresponding to the third stage after the second stage in the corresponding second hold frame, both the first switching transistor and the second switching transistor are turned on in response to the second gate pulse of the second gate signal to generate the drive current. At least one of the first stage and the third stage in the second write frame, and the second stage and the fourth stage in the corresponding second hold frame, has a time interval. The first reset transistor is turned off during the time interval to maintain the potential of the source of the drive transistor at the voltage of the first reset signal. The plurality of pixel circuits in the same group are electrically connected to the same first gate signal and the same second gate signal.

[0074] As discussed above, after the voltage difference between the gate and source of the driving transistor T1 is adjusted by S1, the first switching transistor T5 and the second switching transistor T6 are turned on in response to the second gate pulse p2 of the second gate signal EM, so as to generate a driving current to drive the light-emitting element EL to emit light.

[0075] By adding the aforementioned time interval (at least one of stage 4-1 and stage 4-1'), and simultaneously cutting off the first reset transistor T8 during this time interval to maintain the potential of the source of the driving transistor T1 as the voltage of the first reset signal Vi3, the voltage difference between the gate and source of the driving transistor T1 is adjusted for a longer period of time. This improves the effect of adjusting the voltage difference between the gate and source of the driving transistor T1 in this stage, thereby effectively reducing the difference in brightness of multiple light-emitting elements EL in the second hold frame and the second write frame, and improving the screen flickering phenomenon.

[0076] To better illustrate the display panel and its driving method in this application, this application further explains the working process of the aforementioned display panel.

[0077] The second write frame, which is the frame used by the display panel to refresh the display screen, requires the writing of data signals and the emission of light, as shown in Figures 4 and 2, and may include the following stages:

[0078] Phase 1 (Vi3 Writing): The first gate signal Pscan2 is a valid first gate pulse p1, which turns on both the third reset transistor T7 and the first reset transistor T8. The third reset signal Vi_Ano is transmitted to the anode (node ​​C) of the light-emitting element EL to reset it. The first reset signal Vi3 (voltage close to +7V) is transmitted to the source (node ​​A) of the driving transistor T1 to reset it. Since the previous phase was the light-emitting phase of the previous frame (second write frame or second hold frame), the potential of the gate (node ​​Q) of the driving transistor T1 is maintained at the beginning of Phase 1 of this second write frame as "the sum of the potential of the data signal Data (voltage between 0-5V) in the previous frame and the threshold voltage of the driving transistor T1 (less than the potential of the first reset signal Vi3)". Therefore, at this time, the gate-source voltage VQA of the driving transistor T1 is less than 0 and much less than the current threshold voltage of the driving transistor T1. Thus, the driving transistor T1 is turned on, and the fourth gate signal Nscan1 is an effective fourth gate pulse p4 to turn on the compensation transistor T3. Thus, the first reset signal Vi3 can also be transmitted sequentially from node A to node B and node Q to raise their potentials. When the potential of the gate-source voltage VQA of the driving transistor T1 rises to be equal to the current threshold voltage of the driving transistor T1, the driving transistor T1 is turned off. During this process, the gate-source voltage VQA of the driving transistor T1 changes from "(approximately 0-5V + the threshold voltage of the driving transistor T1 in the previous frame) - Vi3" to "the current threshold voltage of the driving transistor T1". The weighted average value of VQA in this stage can be denoted as OBS1.

[0079] Phase 2 (Vi_G Reset): The third gate signal Nscan2 is a valid third gate pulse p3, which turns on the second reset transistor T4. The second reset signal Vi_G (voltage close to -3.5V) is transmitted to the gate (node ​​Q) of the driving transistor T1 to reset it. Since the source (node ​​A) of the driving transistor T1 is loaded with the first reset signal Vi3 at the end of Phase 1, the gate-source voltage VQA of the driving transistor T1 at this time is (Vi_G-Vi3), which is much smaller than the current threshold voltage of the driving transistor T1. Therefore, the driving transistor T1 turns on. After the fourth gate signal Nscan1 is a valid fourth gate pulse p4, the compensation transistor T3 is turned on. Therefore, the second reset signal Vi_G can also be transmitted to node B and node A through node Q to pull down their potentials. When the potential of the gate-source voltage VQA of the driving transistor T1 rises to be equal to the current threshold voltage of the driving transistor T1, the driving transistor T1 is turned off. During this process, the gate-source voltage VQA of the driving transistor T1 changes from "Vi_G-Vi3" to "the current threshold voltage of the driving transistor T1". The weighted average value of VQA in this stage can be denoted as OBS2.

[0080] Phase 3 (Data Writing): The fifth gate signal Pscan1 is a valid fifth gate pulse p5 to turn on the data writing transistor T2. The data signal Data is transmitted to the source of the driving transistor T1. Since the gate (node ​​Q) of the driving transistor T1 is loaded with the second reset signal Vi_G at the end of Phase 2, the gate-source voltage VQA of the driving transistor T1 is (Vi_G-Data), which is much smaller than the current threshold voltage of the driving transistor T1. Therefore, the driving transistor T1 is turned on. The fourth gate signal Nscan1 is a valid fourth gate pulse p4 to turn on the compensation transistor T3. Therefore, the data signal Data can also be transmitted sequentially from node A to node B and node Q to raise their potentials. When the potential of the gate-source voltage VQA of the driving transistor T1 rises to be equal to the current threshold voltage of the driving transistor T1, the driving transistor T1 is turned off. During this process, the gate-source voltage VQA of the driving transistor T1 changes from "Vi_G-Data" to "the current threshold voltage of the driving transistor T1". The weighted average value of VQA in this phase can be denoted as OBS3.

[0081] Phase 4 (Vi3 Reset, New Phase): The first gate signal Pscan2 is a valid first gate pulse p1, which turns on both the third reset transistor T7 and the first reset transistor T8. The third reset signal Vi_Ano is transmitted to the anode (node ​​C) of the light-emitting element EL to reset it. The first reset signal Vi3 (voltage close to +7V) is transmitted to the source (node ​​A) of the driving transistor T1 to reset it. Since at the end of Phase 3, the gate (node ​​Q) of the driving transistor T1 is loaded with (the threshold voltage of the driving transistor T1 at that time + Data), the gate-source voltage VQA of the driving transistor T1 at this time is (the threshold voltage of the driving transistor T1 at that time + Data - Vi3), which is also less than the current threshold voltage of the driving transistor T1. Therefore, the driving transistor T1 is turned on, and the first reset signal Vi3 is also transmitted to node B via node A. During this process, the gate-source voltage VQA of the driving transistor T1 is always maintained as "the threshold voltage of the driving transistor T1 in Phase 3 + Data - Vi3". The weighted average value of VQA in this phase can be denoted as OBS4.

[0082] Phase 5 (Light Emission): The second gate signal EM is an effective second gate pulse p2, which turns on both the first switching transistor T5 and the second switching transistor T6. The first constant voltage signal VDD (voltage close to 4.6V) is transmitted to node A. Since at the end of phase 4, the gate (node ​​Q) of the driving transistor T1 is maintained at (threshold voltage of driving transistor T1 in phase 3 + Data), the gate-source voltage VQA of driving transistor T1 at this time is (threshold voltage of driving transistor T1 in phase 3 + Data - close to VDD), which is also less than the current threshold voltage of driving transistor T1. Therefore, driving transistor T1 is turned on, and a path is formed between the first voltage line and the second voltage line to generate driving current. The light-emitting element EL emits light. During this process, the gate-source voltage VQA of driving transistor T1 changes from "threshold voltage of driving transistor T1 in phase 3 + Data - Vi3" to "threshold voltage of driving transistor T1 in phase 3 + Data - close to VDD". The weighted average value of VQA in this phase can be denoted as OBS5.

[0083] The second holding frame, which is the frame used by the display panel to hold the previous display image, requires maintaining the gate potential of the driving transistor T1 and emitting light, as shown in Figures 5 and 3, and may include the following stages:

[0084] Phase 1' (Vi3 Reset): The first gate signal Pscan2 is a valid first gate pulse p1, which turns on both the third reset transistor T7 and the first reset transistor T8. The third reset signal Vi_Ano is transmitted to the anode (node ​​C) of the light-emitting element EL to reset it. The first reset signal Vi3 (voltage close to +7V) is transmitted to the source (node ​​A) of the driving transistor T1 to reset it. Since the potential of the gate (node ​​Q) of the driving transistor T1 in phase 5 is maintained at (the threshold voltage of the driving transistor T1 in phase 3 + Data), the gate-source voltage VQA of the driving transistor T1 at this time is (the threshold voltage of the driving transistor T1 in phase 3 + Data - Vi3), which is less than 0 and less than the current threshold voltage of the driving transistor T1. Therefore, the driving transistor T1 is turned on. The first reset signal Vi3 is transmitted from node A to node B. During this process, the gate-source voltage VQA of the driving transistor T1 is maintained at "(the threshold voltage of the driving transistor T1 in phase 3 + Data - Vi3)". The weighted average value of VQA in this phase can be denoted as OBS1'.

[0085] Stages 2' and 3': All gates are at their respective invalid potentials so that all transistors except the driving transistor T1 are turned off. Therefore, the gate-source voltage VQA of the driving transistor T1 is maintained at "(threshold voltage of the driving transistor T1 in stage 3 + Data - Vi3)" in both of these processes. The weighted average value of VQA in these two stages can be denoted as OBS2' and OBS3', respectively.

[0086] Phase 4' (Vi3 Reset, New Phase): The first gate signal Pscan2 is a valid first gate pulse p1 to turn on both the third reset transistor T7 and the first reset transistor T8. Similarly, in Phase 1', the third reset signal Vi_Ano is transmitted to the anode (node ​​C) of the light-emitting element EL to reset it, and the first reset signal Vi3 is transmitted to the source (node ​​A) of the driving transistor T1 to reset it. The driving transistor T1 is turned on, and during this process, the gate-source voltage VQA of the driving transistor T1 is still maintained as "the threshold voltage of the driving transistor T1 in Phase 3 + Data - Vi3". The weighted average value of VQA in this phase can be denoted as OBS4'.

[0087] Stage 5' (Light Emission): The second gate signal EM is an effective second gate pulse p2 to turn on both the first switching transistor T5 and the second switching transistor T6. Similarly, in stage 5, the first constant voltage signal VDD (voltage close to 4.6V) is transmitted to node A. Since at the end of stage 4', the gate (node ​​Q) of the driving transistor T1 is still maintained at (the threshold voltage of the driving transistor T1 in stage 3 + Data). Similarly, in stage 4', the driving transistor T1 is turned on to generate driving current, and the light-emitting element EL emits light. During this process, the gate-source voltage VQA of the driving transistor T1 is still maintained at "the threshold voltage of the driving transistor T1 in stage 3 + Data - Vi3". The weighted average value of VQA in this stage can be denoted as OBS5'.

[0088] Based on the above analysis, although stage 1' (Vi3 reset) reduces the difference between OBS1 and OBS1' by adjusting the potential of node A, the difference between OBS3 and OBS3' is significant. Furthermore, the weighted average value of VQA in other corresponding stages of the second write frame and the second hold frame also differs, resulting in a large difference between (OBS1+OBS2+OBS3+OBS5) and (OBS1'+OBS2'+OBS3'+OBS5'). If left unchecked, this will cause a significant difference in the characteristics of the driving transistor T1 between stage 5 (light emission) and stage 5' (light emission), leading to flickering.

[0089] Therefore, the following improvements are made in this application:

[0090] The differences between Figure 2 and Figure 4 also include:

[0091] Phase 4-1 (Vi3 Reset Hold, Another New Phase): The difference from Phase 4 above is that the first gate signal Pscan2 is an invalid potential so that the third reset transistor T7 and the first reset transistor T8 are both turned off, so that node A is left floating to maintain the voltage of the first reset signal Vi3 in Phase 4, and node C is left floating to maintain the voltage of the third reset signal Vi_Ano in Phase 4.

[0092] In this context, stage 4-1 refers to the stage in the second write frame where the first reset transistor T8, after being turned on in response to the first gate pulse p1 of the first gate signal Pscan2, is turned off to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3. As discussed above, in this stage, the potentials of nodes A, B, and Q continue from their respective potentials in stage 4. That is, the duration of OBS4 is further extended to prolong the duration of "adjusting the voltage difference between the gate and source of the driving transistor T1" in the second write frame, thereby increasing the adjustment amount (determined by the voltage difference between the gate and source of the driving transistor T1 and the corresponding duration), further reducing the brightness difference between the second hold frame and the second write frame, and further improving the low-frequency flickering phenomenon.

[0093] The differences between Figure 3 and Figure 5 also include:

[0094] Phase 4-1' (Vi3 Reset Hold, Another New Phase): The difference from Phase 4' above is that the first gate signal Pscan2 is an invalid potential so that the third reset transistor T7 and the first reset transistor T8 are both turned off, so that node A is left floating to maintain the voltage of the first reset signal Vi3 in Phase 4', and node C is left floating to maintain the voltage of the third reset signal Vi_Ano in Phase 4'.

[0095] Referring to the above discussion of stage 4-1, stage 4-1' is the stage in the second holding frame where the first reset transistor T8 is turned on in response to the first gate pulse p1 of the first gate signal Pscan2 and then turned off to maintain the potential of the source of the driving transistor T1 as the voltage of the first reset signal Vi3. Similarly, the potentials of nodes A, B, and Q in this stage continue from their respective potentials in stage 4', that is, the duration of the above-mentioned OBS4' is further extended to prolong the duration of "adjusting the voltage difference state between the gate and source of the driving transistor T1" to increase the adjustment amount (determined by the voltage difference state between the gate and source of the driving transistor T1 and the corresponding duration), further reducing the brightness difference between the second holding frame and the second write frame, and further improving the low-frequency flickering phenomenon.

[0096] Based on the above discussion of Figures 1, 2, and 3, in the first stage (stage 4) in the second write frame (corresponding to Figure 2) where the gate of the driving transistor T1 stores the data signal Data and the compensation transistor T3 is turned off, and in the corresponding second hold frame (corresponding to Figure 3) in the second stage (stage 4') corresponding to the first stage, the first reset transistor T8 is turned on in response to the first gate pulse p1 of the first gate signal Pscan2, and is also turned off to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3 (at least one of the corresponding stages 4-1 and 4-1').

[0097] Understandably, after at least one of stage 3 in the second write frame and stage 3' in the second hold frame, a corresponding stage (at least one of stage 4 corresponding to stage 3 and stage 4' corresponding to stage 3') is set. In this stage, the first reset transistor T8 is turned on to transmit the first reset signal Vi3 to the source of the driving transistor T1. By reasonably setting the time interval between the two, the voltage difference between the gate and source of the driving transistor T1 in at least one of the second write frame and the corresponding second hold frame can be adjusted. Further, if stage 4 exists in the second write frame, stage 4-1 is set between stage 4 and stage 5; if stage 4' exists in the second hold frame, stage 4-1' is set between stage 4' and stage 5'. In -1' (if stage 4' exists), the first switching transistor T5 and the second switching transistor T6 are still off, but the first reset transistor T8 is also set to be off, so that the source of the driving transistor T1 is left floating to maintain the potential as the voltage of the first reset signal Vi3. The duration for which the potential of the source of the driving transistor T1 is the voltage of the first reset signal Vi3 can be further increased, and the duration of "adjusting the voltage difference state of the gate and source of the driving transistor T1" in at least one of the second write frame and the corresponding second hold frame can be increased to improve the adjustment amount (determined by the voltage difference state of the gate and source of the driving transistor T1 and the corresponding duration) to compensate for the difference between (OBS1+OBS2+OBS3+OBS5) and (OBS1'+OBS2'+OBS3'+OBS5').

[0098] Furthermore, referring to Figures 1, 2, and 3, in the first stage (stage 4) of the second write frame (corresponding to Figure 2) where the gate of the driving transistor T1 stores the data signal Data and the compensation transistor T3 is turned off, and in the corresponding second hold frame (corresponding to Figure 3) in the second stage (stage 4') corresponding to the first stage, the first reset transistor T8 is used to turn on in response to the first gate pulse p1 of the first gate signal Pscan2, and is also used to turn off to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3.

[0099] Understandably, stage 4 and stage 4-1 are set in the second write frame, and stage 4' and stage 4-1' are set in the second hold frame, so that both the second write frame and the corresponding second hold frame have sufficient time to "adjust the voltage difference state between the gate and source of the driving transistor T1". That is, OBS4 and OBS4' can be large enough to compensate for the difference between (OBS1+OBS2+OBS3+OBS5) and (OBS1'+OBS2'+OBS3'+OBS5').

[0100] Based on the existence of the above-mentioned stages 4, 4-1, 4' and 4-1', wherein, in conjunction with Figures 1, 2 and 3, in the first stage (stage 4) in which the gate of the driving transistor T1 in the second write frame stores the data signal Data and the compensation transistor T3 is turned off, and in the corresponding second hold frame (corresponding to Figure 3) in the second stage (stage 4') corresponding to the first stage, the first reset transistor T8 is turned on for the same duration in response to the first gate pulse p1 of the first gate signal Pscan2, and / or is turned off for the same duration to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3.

[0101] Understandably, the durations of stages 4 and 4' are set to be the same, so that the charging time for node A is the same and the potential at the end of the two stages is the same. And / or, the durations of stages 4-1 and 4-1' are set to be the same, so that the potential for node A is maintained at the aforementioned potential for the same duration. Either of these two aspects can make OBS4 and OBS4' close. Furthermore, since "the time interval ti between the start time of the first gate pulse p1 and the start time of the corresponding second gate pulse p2 is greater than or equal to 4H", therefore... The aforementioned OBS4 and OBS4' can also be much larger than (OBS1+OBS2+OBS3+OBS5) and (OBS1'+OBS2'+OBS3'+OBS5'), thus the difference between (OBS1+OBS2+OBS3+OBS5) and (OBS1'+OBS2'+OBS3'+OBS5') can be ignored, so that (OBS1+OBS2+OBS3+OBS5+OBS4) and (OBS1'+OBS2'+OBS3'+OBS5'+OBS4') are close.

[0102] Based on the existence of the above-mentioned stages 4, 4-1, 4' and 4-1', wherein, in conjunction with Figures 1, 2 and 3, in the first stage (stage 4) in which the gate of the driving transistor T1 in the second write frame stores the data signal Data and the compensation transistor T3 is turned off, and in the corresponding second hold frame (corresponding to Figure 3) in the second stage (stage 4') corresponding to the first stage, the sum of the duration for which the first reset transistor T8 is turned on in response to the first gate pulse p1 of the first gate signal Pscan2 and the duration for which it is turned off to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3 is equal.

[0103] Understandably, since the charging characteristics of the driving transistor T1 are superior, the durations of both stage 4 and stage 4' are considered sufficient to charge the potential of node A to the voltage of the first reset signal Vi3. Therefore, it can be assumed that setting the sum of the durations of stage 4 and stage 4-1, and the sum of the durations of stage 4' and stage 4-1' to be the same will ensure that the potential of node A is close to the duration of the first reset signal Vi3, thus making OBS4 and OBS4' close. Of course, to further reduce the difference between OBS4 and OBS4', the durations of stage 4 and stage 4' can also be set to be the same, and the durations of stage 4-1 and stage 4-1' can also be set to be the same.

[0104] In some embodiments, as shown in Figures 1, 2, and 3, in at least one of the first stage (stage 4) in which the gate of the driving transistor T1 in the second write frame stores the data signal Data and the compensation transistor T3 is turned off, and the second stage (stage 4') in the corresponding second hold frame (corresponding to Figure 3) corresponding to the first stage, the duration for which the first reset transistor T8 is turned on in response to the first gate pulse p1 of the first gate signal Pscan2 is less than the duration for which it is turned off to maintain the potential of the source of the driving transistor T1 at the voltage of the first reset signal Vi3.

[0105] Understandably, since the charging characteristics of the driving transistor T1 are superior, the duration of stage 4 (if present) and stage 4' (if present) can be set to be sufficient to charge the potential of node A to the voltage of the first reset signal Vi3. At the same time, the duration of the subsequent stage 4-1 (if present) and stage 4-1' (if present) can be set to be longer. In this case, the supply of the first reset signal Vi3 can be stopped while maintaining the potential of node A at the voltage of the first reset signal Vi3. Therefore, it is possible to reduce the power consumption of the display panel and form a larger OBS4 (if present) and OBS4' (if present).

[0106] Based on the existence of stages 4 and 4' mentioned above, Table 1 shows the low-frequency flickering of stages 4-1 and 4-1' (taking the same duration as an example) under different durations, with the following definitions:

[0107] Among them, L DATA写入帧 L is the brightness of the display panel in the second write frame. DATA保持帧 The brightness of the display panel in the second hold frame is ΔL1(%). The larger the ΔL1(%), the more severe the low-frequency flicker. Referring to the relevant definitions above, 1H is based on stages 1 and 1' of the same duration (24H), stages 2 and 2' of the same duration (16H), stages 3 and 3' of the same duration (16H), and stages 4 and 4' of the same duration (16H). The difference is that the control group did not have stages 4-1 and 4-1' set, so the corresponding ΔL1(%) is larger. Among conditions 1, 2, and 3, the duration of stage 4-1 and stage 4-1' increases sequentially, and the corresponding ΔL1(%) decreases sequentially.

[0108] Table 1

[0109] Therefore, under the same conditions, the smaller the duration of stage 4-1 and stage 4-1', the less severe the low-frequency flicker phenomenon. In practical applications, the duration of stage 4-1 and stage 4-1' can be reasonably set according to the difference between (OBS1+OBS2+OBS3+OBS5) and (OBS1'+OBS2'+OBS3'+OBS5') (regardless of whether the two are the same).

[0110] In some embodiments, as shown in conjunction with Figures 1, 2 and 3, in the first stage (i.e., stage 4) of the second write frame and the corresponding second stage (i.e., stage 4') of the second hold frame, the first reset transistor T8 is turned on in response to the first gate pulse p1 of the first gate signal Pscan2, and the voltage of the first reset signal Vi3 in the first stage of the second write frame is different from the voltage of the first reset signal Vi3 in the second stage of the second hold frame.

[0111] Understandably, in this embodiment, the voltage of the first reset signal Vi3 in the first stage of the second write frame and the voltage of the second stage of the second hold frame are set to be different. The specific values ​​of the two stages can be set according to the difference between (OBS1+OBS2+OBS3+OBS5) and (OBS1'+OBS2'+OBS3'+OBS5'), and in conjunction with the two voltage values ​​and the duration of stage 4 and stage 4', respectively, so as to make (OBS1+OBS2+OBS3+OBS5+OBS4) and (OBS1'+OBS2'+OBS3'+OBS5'+OBS4') close.

[0112] In some embodiments, as shown in Figures 4 and 2, in the first stage (stage 4, i.e., Vi3 reset) of the second write frame and in the fifth stage (stage 1, i.e., Vi3 write) before the gate of the driving transistor T1 stores the data signal Data, the first reset transistor T8 is turned on in response to another (first) first gate pulse p1 of the first gate signal Pscan2 to transmit the first reset signal Vi3 to the source of the driving transistor T1, and the voltage of the first reset signal Vi3 in the first stage of the second write frame is different from the voltage in the third stage.

[0113] Understandably, since the first reset signal Vi3 serves different purposes in changing the source of the driving transistor T1 in stages 1 and 3, the former corresponds to stage 1' of the second holding frame, and the two stages form OBS1 and OBS1' respectively. Generally, the durations of the two stages are similar, and the voltage of the first reset signal Vi3 in the two stages is also similar. However, the latter is different between (OBS1+OBS2+OBS3+OBS5) of the second write frame and (OBS1'+OBS2'+OBS3'+OBS5') of the entire second holding frame. The voltage of the first reset signal Vi3 at this time can be reasonably set according to the degree of the above difference and taking into account the duration of stage 4 (therefore, it can be different from its voltage in stage 1).

[0114] It should be noted that this application only uses N-type transistors (threshold voltage greater than 0) for compensation transistor T3 and second reset transistor T4, and P-type transistors (threshold voltage greater than 0) for other transistors as an example. Of course, the above transistor types can be replaced, and the waveforms of the corresponding multiple gate signals also need to be adjusted accordingly to achieve the above multiple working stages. Of course, the transistors in the pixel circuit 100 can also be replaced with other types of transistors, such as triodes or MOSFETs, and the corresponding threshold voltages and corresponding gate signals should be matched and set.

[0115] It should be noted that the second hold frame mentioned in this application can be any second hold frame corresponding to the second write frame. In order to better improve the low-frequency screen flicker phenomenon, when setting the second hold frame as described above, the multiple second hold frames corresponding to the second write frame can be set in the same way so that the difference between the brightness of the second write frame and the brightness of each second hold frame is small.

[0116] In summary, in the embodiments of Figures 1 to 3 in this application, the second write frame further includes a sixth stage (stage 2) located between the fifth stage (stage 1) and the first stage (stage 4), and a seventh stage (stage 3) located between the sixth stage (stage 2) and the first stage (stage 4). The waveforms of the aforementioned plurality of gate signals may have the following characteristics:

[0117] The first gate signal includes the first gate pulse p1 in both the fifth stage (stage 1) and the first stage (stage 4);

[0118] The second gate signal in the third stage (stage 5) includes the second gate pulse p2;

[0119] The third gate signal in the sixth stage (stage 2) includes the third gate pulse p3;

[0120] The fourth gate signal includes the fourth gate pulse p4 in the fifth stage (stage 1), the sixth stage (stage 2) near the seventh stage, and the seventh stage (stage 3);

[0121] The fifth gate signal in the seventh stage (stage 3) includes the fifth gate pulse p5.

[0122] Meanwhile, based on the fact that the second holding frame also includes an eighth stage corresponding to the fifth stage, which is located before the second stage, the waveforms of the aforementioned plurality of gate signals can have the following characteristics:

[0123] The first gate signal includes the first gate pulse p1 in both the eighth stage (stage 1') and the second stage (stage 4');

[0124] The second gate signal in the fourth stage (stage 5') includes the second gate pulse p2.

[0125] In other embodiments, as shown in Figures 4 and 5, also based on the existence of the aforementioned stages 1 to 5 and stages 1' to 5', and based on the fact that the first gate signal Pscan2 further includes at least the first gate pulse p1 in the fifth stage (stage 1) before the first stage (stage 4) in the second write frame, the difference from Figures 2 and 3 is that, although the aforementioned time interval (at least one of stage 4-1 and stage 4-1') is added in Figures 4 and 5, the pulse width of the first gate pulse p1 located in at least one of the first stage (stage 4) and the second stage (stage 4') is set to be greater than the pulse width of the first gate pulse p1 located in the fifth stage (stage 1).

[0126] Understandably, different functions can be achieved by differentiating the pulse width of the first gate pulse p1 in different stages of the first gate signal Pscan2. For example, in the fifth stage (stage 1) of the second write frame, the pulse width of the first gate pulse p1 in the first gate signal Pscan2 can be set to be smaller. This only requires turning on both the third reset transistor T7 and the first reset transistor T8, and transmitting the third reset signal Vi_Ano to the anode (node ​​C) of the light-emitting element EL to reset it. However, in at least one of the first stage (stage 4) and the second stage (stage 4'), the pulse width of the first gate signal Pscan2... The pulse width of the first gate pulse p1 can be set to be relatively large. The first reset signal Vi3 (voltage close to +7V) is transmitted to the source (node ​​A) of the driving transistor T1 to reset it and is maintained at the voltage of the third reset signal Vi_Ano for a relatively long time. Similarly, the duration of the above-mentioned OBS4 can be further extended to prolong the duration of "adjusting the voltage difference state between the gate and source of the driving transistor T1" in the second write frame, thereby increasing the adjustment amount (determined by the voltage difference state between the gate and source of the driving transistor T1 and the corresponding duration), further reducing the brightness difference between the second hold frame and the second write frame, and further improving the low-frequency flicker phenomenon.

[0127] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a program instructing related hardware (e.g., a processor), and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware, such as by an integrated circuit to implement its corresponding function, or it can be implemented in the form of a software functional module, such as by a processor executing a program / instruction stored in memory to implement its corresponding function. This application is not limited to any particular combination of hardware and software.

[0128] The structure of the display panel provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, wherein, have a first working mode working at a first refresh rate and a second working mode working at a second refresh rate, the first refresh rate being greater than the second refresh rate; when in the first working mode, the display panel has a first write frame, and when in the second working mode, the display panel has a second write frame and a second holding frame, the second write frame including a first stage, a third stage after the first stage, and the second holding frame including a second stage corresponding to the first stage, a fourth stage corresponding to the third stage after the second stage; comprise a plurality of pixel circuits, the pixel circuit comprising: a light emitting element; a driving transistor connected to the light emitting element, for generating a driving current according to a data signal to drive the light emitting element to emit light in the second write frame and the corresponding second holding frame; a storage capacitor electrically connected to a gate of the driving transistor, for storing the data signal; a compensation transistor electrically connected between the gate and the drain of the driving transistor; a first reset transistor electrically connected to a source of the driving transistor, in the first stage, the gate of the driving transistor storing the data signal and the compensation transistor being turned off, in at least one of the first stage and the corresponding second stage, the first reset transistor is turned on in response to a first gate pulse of a first gate signal to transmit a first reset signal to the source of the driving transistor; a first switch transistor electrically connected to the source of the driving transistor; a second switch transistor electrically connected to the drain of the driving transistor, in the third stage and the corresponding fourth stage, the first switch transistor and the second switch transistor are both turned on in response to a second gate pulse of a second gate signal to generate the driving current; wherein at least one of the time interval between the first stage and the third stage and the corresponding second stage and the fourth stage has a time interval, and the first reset transistor is turned off in the time interval to maintain the potential of the source of the driving transistor as the voltage of the first reset signal; wherein the length of the time interval is greater than or equal to 4H, 1H is equal to 1 / (f*m), f is the refresh rate of the display panel, and m is the group number of the pixel circuit, and the pixel circuits in the same group are loaded with the same first gate signal and the same second gate signal; wherein the second write frame further comprises a fifth stage before the first stage; in the first stage and the fifth stage, the first reset transistor is turned on in response to another first gate pulse of the first gate signal to transmit the first reset signal to the source of the driving transistor, and the voltage of the first reset signal in the first stage of the second write frame is different from that in the third stage.

2. The display panel of claim 1, wherein, At least one of the first stage and the corresponding second stage, the first reset transistor is used to turn on for a time period in response to the first gate pulse of the first gate signal, and is used to turn off for a time period to maintain the potential of the source of the drive transistor as the voltage of the first reset signal.

3. The display panel of claim 1, wherein, At the first stage and the corresponding second stage, the first reset transistor is used to turn on in response to the first gate pulse of the first gate signal, and is used to turn off to maintain the potential of the source of the drive transistor as the first reset signal.

4. The display panel of claim 3, wherein, At the first stage and the corresponding second stage, at least one of the time period for which the first reset transistor is used to turn on in response to the first gate pulse of the first gate signal and the time period for which the first reset transistor is used to turn off to maintain the potential of the source of the drive transistor as the voltage of the first reset signal is the same.

5. The display panel of claim 3 or 4, wherein, At the first stage and the corresponding second stage, the sum of the time period for which the first reset transistor is used to turn on in response to the first gate pulse of the first gate signal and the time period for which the first reset transistor is used to turn off to maintain the potential of the source of the drive transistor as the voltage of the first reset signal is equal.

6. The display panel of any one of claims 1 to 5, wherein, The pixel circuit further comprises: a data write transistor electrically connected to the source of the drive transistor, used to turn on in the second write frame in response to a fifth gate pulse of a fifth gate signal to transmit the data signal to the source of the drive transistor; a second reset transistor electrically connected to the gate of the drive transistor, used to turn on in the second write frame in response to a third gate pulse of a third gate signal before the data write transistor turns on, to transmit a second reset signal to the gate of the drive transistor; The compensation transistor is used to turn on in response to a fourth gate pulse of a fourth gate signal when the data write transistor turns on, to transmit the data signal to the gate of the drive transistor, and to turn on when the second reset transistor turns on to transmit the second reset signal to the drain and source of the drive transistor.

7. The display panel of claim 6, wherein, The storage capacitor comprises: a first storage capacitor electrically connected between the gate of the drive transistor and a first voltage line used to transmit a first constant voltage signal; a second storage capacitor electrically connected between the gate of the drive transistor and the gate of the data write transistor.

8. A display panel, wherein, has a first working mode working at a first refresh rate and a second working mode working at a second refresh rate, the first refresh rate is greater than the second refresh rate; In the first working mode, the display panel has a first write frame, and in the second working mode, the display panel has a second write frame and a second holding frame, the second write frame includes a first stage, a third stage located after the first stage, and the second holding frame includes a second stage corresponding to the first stage, and a fourth stage corresponding to the third stage located after the second stage; comprises a plurality of pixel circuits, the pixel circuit comprises: a light emitting element; a driving transistor electrically connected with the light emitting element, for generating a driving current to drive the light emitting element to emit light according to the data signal in the second write frame and the corresponding second holding frame; a storage capacitor electrically connected to a gate of the driving transistor, for storing the data signal; a compensation transistor electrically connected between the gate and a drain of the driving transistor; a first reset transistor electrically connected to a source of the driving transistor, in the first stage, the gate of the driving transistor stores the data signal and the compensation transistor is turned off, in at least one of the first stage and the corresponding second stage, the first reset transistor is turned on in response to a first gate pulse of a first gate signal to transmit a first reset signal to the source of the driving transistor; a first switch transistor electrically connected to the source of the driving transistor; a second switch transistor electrically connected to the drain of the driving transistor, in the third stage and the corresponding fourth stage, the first switch transistor and the second switch transistor are both turned on in response to a second gate pulse of a second gate signal to generate the driving current; wherein at least one of a time interval between the first stage and the third stage and a time interval between the corresponding second stage and the fourth stage, the first reset transistor is turned off to maintain the potential of the source of the driving transistor as the voltage of the first reset signal.

9. The display panel of claim 8, wherein, The time interval is greater than or equal to 4H, 1H is equal to 1 / (f*m), f is the refresh rate of the display panel, and m is the number of groups of the pixel circuit, the pixel circuits in the same group are loaded with the same first gate signal and the same second gate signal.

10. The display panel of claim 9, wherein, In at least one of the first stage and the corresponding second stage, the first reset transistor is turned on in response to the first gate pulse of the first gate signal for a time period less than a time period for being turned off to maintain the potential of the source of the driving transistor as the voltage of the first reset signal.

11. The display panel of claim 9, wherein, In the first stage and the corresponding second stage, the first reset transistor is turned on in response to the first gate pulse of the first gate signal and is then turned off to maintain the potential of the source of the driving transistor as the first reset signal.

12. The display panel of claim 11, wherein, In the first stage and the corresponding second stage, at least one of the following conditions is met: the time period for which the first reset transistor is turned on in response to the first gate pulse of the first gate signal is the same, and the time period for which the first reset transistor is turned off to maintain the potential of the source of the driving transistor as the voltage of the first reset signal is the same.

13. The display panel of claim 11 or 12, wherein, In the first stage and the corresponding second stage, the sum of the time period for which the first reset transistor is turned on in response to the first gate pulse of the first gate signal and the time period for which the first reset transistor is turned off to maintain the potential of the source of the driving transistor as the voltage of the first reset signal is equal.

14. The display panel of claim 8, wherein, The second write frame further comprises a fifth stage before the first stage. In the first stage and the fifth stage, the first reset transistor is used for conducting in response to another first gate pulse of the first gate signal to transmit the first reset signal to the source of the driving transistor, and the voltage of the first reset signal in the first stage of the second write frame is different from the voltage in the third stage.

15. The display panel of any one of claims 8 to 14, wherein, The pixel circuit further comprises: a data write transistor electrically connected to the source of the driving transistor, used for conducting in the second write frame in response to a fifth gate pulse of a fifth gate signal to transmit the data signal to the source of the driving transistor; a second reset transistor electrically connected to the gate of the driving transistor, used for conducting in the second write frame before the data write transistor conducts in response to a third gate pulse of a third gate signal to transmit a second reset signal to the gate of the driving transistor; the compensation transistor is used for conducting in response to a fourth gate pulse of a fourth gate signal when the data write transistor conducts to transmit the data signal to the gate of the driving transistor, and conducting to transmit the second reset signal to the drain and the source of the driving transistor when the second reset transistor conducts.

16. The display panel of claim 15, wherein, The storage capacitor comprises: a first storage capacitor electrically connected between the gate of the driving transistor and a first voltage line used for transmitting a first constant voltage signal; a second storage capacitor electrically connected between the gate of the driving transistor and the gate of the data write transistor.

17. The display panel of claim 15, wherein, The pixel circuit further comprises: a third reset transistor electrically connected to the light emitting element, used for conducting in each of the second write frame and the corresponding second holding frame in response to the first gate pulse of the first gate signal to transmit a third reset signal to the light emitting element; the first switch transistor, the second switch transistor and the driving transistor are arranged in series, the source of the first switch transistor is electrically connected to a first voltage line used for transmitting a first constant voltage signal, and the drain of the second switch transistor is electrically connected to the light emitting element.

18. The display panel of claim 17, wherein, The second write frame further comprises a sixth stage between the fifth stage and the first stage, and a seventh stage between the sixth stage and the first stage; The first gate signal comprises the first gate pulse in the fifth stage and the first stage; The second gate signal comprises the second gate pulse in the third stage; The third gate signal comprises the third gate pulse in the sixth stage; The fourth gate signal comprises the fourth gate pulse in the fifth stage, a stage close to the seventh stage in the sixth stage and the seventh stage; The fifth gate signal comprises the fifth gate pulse in the seventh stage.

19. The display panel of claim 18, wherein, The second holding frame further comprises an eighth stage corresponding to the fifth stage before the second stage; The first gate signal comprises the first gate pulse in the eighth stage and the second stage; The second gate signal comprises the second gate pulse in the fourth stage.

20. A display panel, wherein, have a first operation mode operating at a first refresh rate and a second operation mode operating at a second refresh rate, the first refresh rate being greater than the second refresh rate; have a first write frame when in the first operation mode and have a second write frame and a second hold frame when in the second operation mode, the second write frame including a first stage, a third stage following the first stage, and a fifth stage preceding the first stage, the second hold frame including a second stage corresponding to the first stage, and a fourth stage following the second stage corresponding to the third stage; include a plurality of pixel circuits, the pixel circuit including: a light emitting element; a driving transistor connected to the light emitting element, for generating a driving current to drive the light emitting element to emit light in the second write frame and the corresponding second hold frame; generating the driving current according to a data signal to drive the light emitting element to emit light; a storage capacitor electrically connected to a gate of the driving transistor, for storing the data signal; a compensation transistor electrically connected between the gate and a drain of the driving transistor; a first reset transistor electrically connected to a source of the driving transistor, in the first stage in which the gate of the driving transistor stores the data signal and the compensation transistor is off, the first reset transistor is turned on in response to a first gate pulse of a first gate signal to transmit a first reset signal to the source of the driving transistor in at least one of the first stage and the corresponding second stage; a first switch transistor electrically connected to the source of the driving transistor; a second switch transistor electrically connected to the drain of the driving transistor, the first switch transistor and the second switch transistor are both turned on in response to a second gate pulse of a second gate signal to generate the driving current in the third stage and the corresponding fourth stage; wherein the first gate signal further includes the first gate pulse in the fifth stage, and a pulse width of the first gate pulse in at least one of the first stage and the second stage is greater than a pulse width of the first gate pulse in the fifth stage.

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