Inter-core communication method, electronic device, readable medium and computer program product

Abstract

Provided in the present disclosure is an inter-core communication method, which is applied to a multi-core processor. At least two processing cores among multiple processing cores are configured to share the same communication module. The communication module is configured with multiple interrupts, each processing core of the at least two processing cores corresponding to one interrupt of the multiple interrupts and serving as a receiver processing core of the interrupt. The communication module is configured with at least one channel. When a sender processing core for an interrupt sends target information to a receiver processing core for the interrupt, the sender processing core for the interrupt determines a target communication module; the sender processing core for the interrupt writes the target information into a target channel in the target communication module, so as to trigger a universal interrupt controller to which the target communication module belongs to send an interrupt message to the receiver processing core for the interrupt; and, on the basis of the interrupt message, the receiver processing core for the interrupt reads the target information from the target channel. Further disclosed in the present disclosure are an electronic device, a readable medium and a computer program product.

Description

Internuclear communication methods, electronic devices, readable media and computer program products

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese patent application CN 202410700256.7, filed on May 30, 2024, entitled "Multi-core Inter-core Communication Method, Electronic Device, Readable Medium and Computer Program Product", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of communication technology, and in particular to an inter-core communication method for a multi-core processor, an electronic device, a readable medium, and a computer program product. Background Technology

[0004] With the continuous improvement of advanced technologies and the increasing demands of practical applications, traditional embedded devices using single-core processors can no longer meet performance requirements. Currently, several multi-core processors have emerged, integrating high-performance microprocessors and real-time-critical microcontrollers. To achieve synchronous collaborative work among multiple cores, inter-core communication is necessary to enable collaborative processing.

[0005] The basic technical requirements for inter-core communication are twofold: real-time notification and information transmission. Currently, this is mostly achieved through a combination of software and hardware. The hardware provides a message interrupt mechanism to achieve real-time notification, while the software implements the communication protocol to standardize the message transmission pattern.

[0006] In terms of hardware implementation, the relevant technologies are mainly based on a point-to-point, unidirectional approach. This means that each pair of communicating processing cores requires two Mailbox hardware modules to achieve communication. For multi-core processors with a large number of processing cores, the number of Mailbox hardware modules increases exponentially with the number of cores, increasing the design complexity and cost of the chip. Furthermore, the number of communication channels between different processing cores varies significantly across different business scenarios, leading to substantial waste of hardware resources. Summary of the Invention

[0007] This disclosure provides a method for inter-core communication of a multi-core processor, an electronic device, a readable medium, and a computer program product.

[0008] This disclosure provides an inter-core communication method applied to a multi-core processor. The multi-core processor includes multiple processing cores, at least two of which are configured to share a common communication module. The communication module is configured with multiple interrupts, and each of the at least two processing cores corresponds to one of the multiple interrupts as the receiving processing core of the interrupt. The communication module is configured with at least one channel for communication between the at least two processing cores or for communication between the at least two processing cores and other cores among the multiple processing cores. The method includes: when an interrupt-sending processing core sends target information to the interrupt-receiving processing core, the interrupt-sending processing core determines a target communication module, wherein the target communication module is a communication module configured by the interrupt-receiving processing core; the interrupt-sending processing core writes the target information into a target channel in the target communication module to trigger a general interrupt controller to which the target communication module belongs to send an interrupt message to the interrupt-receiving processing core, wherein the target channel is one of the at least one channel; the interrupt-receiving processing core reads the target information from the target channel according to the interrupt message.

[0009] This disclosure also provides an electronic device, including a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the inter-core communication method according to this disclosure.

[0010] This disclosure also provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the inter-core communication method according to this disclosure.

[0011] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the inter-core communication method according to this disclosure. Attached Figure Description

[0012] In the accompanying drawings of the embodiments disclosed herein:

[0013] Figure 1 is a schematic diagram of the structure of a multi-core processor in the relevant technology;

[0014] Figure 2 is a schematic diagram of the structure of a multi-core processor provided in an embodiment of this disclosure;

[0015] Figure 3 is a flowchart illustrating the inter-core communication method for a multi-core processor provided in an embodiment of this disclosure;

[0016] Figure 4 is a schematic diagram of the zipc protocol provided in an embodiment of this disclosure;

[0017] Figure 5 is a schematic diagram of the process of transmitting target information using the target channel based on the zipc protocol according to an embodiment of this disclosure;

[0018] Figure 6 is a schematic diagram of transmitting target information using the target channel based on the zipc protocol according to an embodiment of this disclosure;

[0019] Figure 7 is a schematic block diagram of the electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0021] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0022] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0023] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0024] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0025] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0026] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so specified in this disclosure.

[0027] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0028] In some related technologies, inter-core communication in multi-core processors is based on a point-to-point unidirectional implementation. That is, each pair of communicating processing cores requires two Mailbox hardware modules to achieve communication. Figure 1 is a schematic diagram of the structure of a multi-core processor in related technologies. As shown in Figure 1, the multi-core system is integrated in a SOC (System on Chip), including processing cores Core1 to CoreN, Mailbox1 to MailboxN, NoC (Network-On-Chip), and GIC (Generic Interrupt Controller). Each processing core has an OS (Operating System), such as Linux, Baremetal, or RTOS. The Mailbox is a dedicated hardware peripheral for implementing inter-core communication. Each processing core is configured with one Generic Interrupt Controller (GIC) and one Mailbox. Processing cores Core1 to CoreN use the Mailbox for inter-core communication. During inter-core communication, interrupt messages are generated and sent to the Generic Interrupt Controller (GIC). NoC is the SOC system bus, used to connect various devices and responsible for transmitting data, address, and control information.

[0029] In fields such as smart cockpits and smart homes that use multi-core processors, the number of Mailbox hardware modules will increase exponentially with the number of processing cores. On the other hand, the number of communication channels between different processing cores varies significantly in different business scenarios. Therefore, the related technologies will result in a large waste of hardware resources, increase the design difficulty and cost of chips, and increase the cost of inter-core communication for multi-core processors.

[0030] To address the aforementioned technical problems, this disclosure provides a method for inter-core communication of a single Mailbox supporting multiple processing cores, applicable to a multi-core processor. At least two of the multiple processing cores are configured to share the same communication module. The communication module is configured with multiple interrupts, and each of the at least two processing cores corresponds to one of the multiple interrupts, serving as the receiving processing core of that interrupt.

[0031] In this embodiment of the disclosure, the Mailbox is used as an example to illustrate the communication module. As a hardware mechanism for process synchronization and data exchange between processors in a multi-core processor system, the Mailbox carries a small block of memory and does not occupy system memory. Through its registers, it can realize in-band data transmission or out-of-band data transmission.

[0032] The communication module is configured with at least one channel, which is used for communication between the at least two processing cores, or for communication between the at least two processing cores and other cores among a plurality of processing cores. In Mailbox channel allocation, the number of channels between the sending and receiving processing cores can be pre-determined according to business requirements. At least two processing cores are configured to share the same communication module, enabling one Mailbox hardware module to support communication between multiple pairs of processing cores, thereby reducing the number of Mailbox hardware modules in the SOC. By reducing the number of Mailbox hardware modules, the Mailbox initialization time can be reduced, and the cost of multi-core processors can be lowered, thus achieving efficient and low-cost inter-core communication for multi-core processors.

[0033] Figure 2 is a schematic diagram of the structure of a multi-core processor provided in an embodiment of this disclosure. The multi-core processor shown in Figure 2 includes six processing cores, namely Core1 to Core6. Core0, Core1, and Core2 are configured to share Mailbox0, Core3 and Core4 are configured to share Mailbox1, and Core5 and Core6 are configured to share Mailbox2. Mailbox0 belongs to the general interrupt controller GIC0, Mailbox1 belongs to the general interrupt controller GIC1, and Mailbox2 belongs to the general interrupt controller GIC2. Mailbox0 is configured with three interrupts, whose receiving processing cores are Core0, Core1, and Core2, respectively; Mailbox1 is configured with two interrupts, whose receiving processing cores are Core3 and Core4, respectively; and Mailbox2 is configured with two interrupts, whose receiving processing cores are Core5 and Core6, respectively. Mailbox0, Mailbox1, and Mailbox2 are each configured with at least one channel.

[0034] Figure 3 is a flowchart illustrating the inter-core communication method for a multi-core processor provided in an embodiment of this disclosure. As shown in Figure 3, the inter-core communication method includes the following steps S11 to S13.

[0035] In step S11, when the interrupted sender processing core sends target information to the interrupted receiver processing core, the interrupted sender processing core determines the target communication module, wherein the target communication module is the communication module configured by the interrupted receiver processing core.

[0036] Since multiple processing cores share a single communication module, in this step, the target communication module can be determined based on the correspondence between the receiving processing core and the communication module.

[0037] In step S12, the sending core of the interrupt writes the target information into the target channel in the target communication module to trigger the general interrupt controller to send an interrupt message to the receiving core of the interrupt, wherein the target channel is one of at least one channel.

[0038] The target channel is the channel configured between the sending and receiving processing cores of the interrupt, and is one of at least one channel configured in the communication module. In this embodiment, the channel is a register of the Mailbox. When the sending processing core of the interrupt transmits data to the receiving processing core, the sending processing core writes target information into the target channel of the interrupted Mailbox; the target information is the data to be transmitted. In this case, the General Interrupt Controller (GIC) to which the Mailbox belongs sends an interrupt message to the receiving processing core of the interrupt, thereby triggering an interrupt.

[0039] Step S13: The interrupt receiver processing core reads the target information from the target channel according to the interrupt message.

[0040] After receiving the interrupt message, the interrupt receiver core performs interrupt handling, that is, it accesses the target channel of the corresponding Mailbox and reads the target information from it.

[0041] The inter-core communication process of a multi-core processor according to an embodiment of this disclosure will be described in detail below with reference to Figure 2. As shown in Figure 2, if a sending core of an interrupt, such as Core3, Core4, Core5, or Core6, wants to transmit data with a receiving core of an interrupt, such as Core0, Core1, or Core2, the sending core writes the target information to the target channel of Mailbox0 through the general interrupt controller GIC0, thereby triggering an interrupt. The interrupt is then sent to the receiving core, i.e., Core0, Core1, or Core2, through the general interrupt controller GIC0. After receiving the interrupt message, the receiving core accesses the target channel of Mailbox0 to read the target information.

[0042] The inter-core communication method of this disclosure is applied to a multi-core processor. At least two of the multiple processing cores are configured to share the same communication module. The communication module is configured with multiple interrupts, and each of the at least two processing cores corresponds to one of the multiple interrupts, acting as the receiving processing core of that interrupt. The communication module is configured with at least one channel, which is used for communication between the at least two processing cores or for communication between the at least two processing cores and other cores among the multiple processing cores. When the sending processing core of an interrupt sends target information to the receiving processing core of an interrupt, the sending processing core of the interrupt determines the target communication module. The sending processing core of the interrupt writes the target information into the target channel in the target communication module to trigger the general interrupt controller to which the target communication module belongs to send an interrupt message to the receiving processing core of the interrupt. The receiving processing core of the interrupt reads the target information from the target channel according to the interrupt message. By supporting multiple processing cores with a single communication module and determining the inter-core communication channel based on communication requirements, the number of communication module hardware components can be reduced, hardware resource waste can be avoided, the cost of multi-core processors and inter-core communication between multi-core processors can be reduced, and the efficiency of inter-core communication of multi-core processors can be improved.

[0043] In some embodiments, after the receiving core of the interrupt reads the target information from the target channel according to the interrupt message (i.e., step S13), the inter-core communication method may further include: clearing the target information in the target channel. That is, after the interrupt processing is completed, the interrupt is cleared.

[0044] In related technologies, inter-core communication software for multi-core processors is implemented based on shared memory and inter-core interrupts. Shared memory technology primarily includes inter-core communication based on Remote Processor Messaging (RPMsg). RPMsg is a mechanism that provides inter-processor communication (IPC) functionality between the kernel driver of the host operating system (e.g., Linux) and a remote processor. Inter-core interrupts are implemented using Mailbox, which facilitates communication between multiple cores by transmitting control information. In the RPMsg+Mailbox approach, RPMsg manages shared memory through queues, writing specific queue IDs to the Mailbox register and generating inter-core interrupts. However, shared memory managed by queues has a data volume limitation, allowing only 512 bytes of data transfer at a time. When large data volumes are required for communication, this can negatively impact the efficiency of multi-core inter-core communication.

[0045] To address the aforementioned technical issues, this embodiment of the disclosure no longer utilizes RPMsg technology, but instead directly leverages Mailbox to achieve inter-core communication for multi-core processors. In other words, by directly writing target information into the target channel of the Mailbox, instead of managing shared memory through a queue, i.e., by no longer recording the ID of the management queue, the communication efficiency between the cores of the multi-core processor is improved.

[0046] In some embodiments, the target information includes first target information or second target information. The first target information includes at least information about shared memory in the multi-core processor, and the second target information does not include information about shared memory in the multi-core processor. The second target information is business data or preset indication information.

[0047] When the target information includes the first target information, the interrupted sending core and receiving core transmit the data to be transmitted via an "in-band + out-of-band" transmission method. In the context of this disclosure, the "in-band + out-of-band" transmission method refers to a data transmission method that utilizes a channel to transmit information from shared memory and retrieves the data to be transmitted from shared memory based on the shared memory information.

[0048] When the target information includes second target information, the interrupted sending core and receiving core transmit the data to be transmitted via "in-band" transmission. In the context of this disclosure, "in-band" transmission refers to a data transmission method that utilizes a channel to transmit the data to be transmitted without the involvement of shared memory. "In-band" transmission can be divided into two types: one is transmitting actual business data, i.e., the data to be transmitted is business data; the other is transmitting indication information, i.e., the data to be transmitted is preset indication information, such as notification messages, specific signals, etc.

[0049] In related technologies, there are two main transmission protocols for Mailbox: one is the doorbell protocol, which uses virtual channels and stipulates that a service can only use one virtual channel; the other is the data-transfer protocol, which uses physical channels and allows a service to use multiple physical channels. However, a service can only use one protocol, and once the channel and protocol used by a service are determined, that channel cannot be used for other services, reducing the utilization rate of the channel.

[0050] To address the aforementioned issues, this disclosure provides a novel Mailbox communication protocol, namely the zipc protocol. The zipc protocol employs a combination of physical and virtual channels, which improves channel utilization and enables conflict-free inter-core communication among multiple processing cores in multi-service scenarios.

[0051] In some embodiments, a channel may include n physical channels, where n is an integer greater than or equal to 2. The n physical channels include one designated channel and (n-1) transmission channels. One designated channel is divided into p virtual channels, where p is the number of services processed by the multi-core processor and p is an integer greater than or equal to 2. One service corresponds to one virtual channel.

[0052] The number of physical channels, n, can be determined based on the size of the target information. Specifically, the number of physical channels, n, can be calculated using the following formula:

[0053] The number of physical channels n-1 = the size of the target information / the capacity of the physical channels.

[0054] Figure 4 is a schematic diagram of the Zipc protocol provided in this embodiment. As shown in Figure 4, a multi-core processor can handle 32 services, i.e., p = 32. Correspondingly, a designated channel is divided into 32 virtual channels from 0 to 31, and each of the 32 virtual channels can support the aforementioned 32 services. The capacity of the (n-1) transmission channels is the same, and is also the same as the capacity of the designated channel. In this embodiment, the capacity of each physical channel is 32 bits.

[0055] Figure 5 is a schematic diagram of the process of transmitting target information using the target channel based on the zipc protocol according to an embodiment of the present disclosure. As shown in Figure 5, in some embodiments, when the target information includes first target information or service data, the interrupted sender processing core writes the target information into the target channel in the target communication module (i.e., step S12) including the following steps S121 to S123.

[0056] In step S121, it is determined whether all (n-1) transmission channels are empty. If all (n-1) transmission channels are empty, step S122 is executed. If at least one transmission channel is not empty, it is determined whether all (n-1) transmission channels are empty after waiting for a preset time. Step S122 is executed when all (n-1) transmission channels are empty.

[0057] In step S122, the interrupted sender processing core writes the target information into (n-1) transmission channels in the target communication module.

[0058] In some embodiments, different services time-division multiplex at least some (n-1) transmission channels.

[0059] In step S123, the target virtual channel in the specified channel is set as the target marker, wherein the target virtual channel is the virtual channel corresponding to the service to which the target information belongs.

[0060] After step S123 is completed, an interrupt is triggered.

[0061] If the transmission between the interrupted sending core and the receiving core is in an "in-band + out-of-band" mode, or an "in-band" mode, it indicates that data needs to be transmitted through transmission channels. Therefore, the target information of the current service is only written to each of the (n-1) transmission channels if there is no data to be transmitted in the current (i.e., all (n-1) transmission channels are empty). In other words, the data of the next service is transmitted only after the data of the previous service (i.e., the target information) has been transmitted, which ensures the accuracy of data transmission. In some embodiments, the (n-1) transmission channels can be polled to determine if all (n-1) transmission channels are empty. If at least one transmission channel is not empty, the system waits for a preset time and then checks if all (n-1) transmission channels are empty. When all (n-1) transmission channels are empty, the interrupted sending core writes the target information to the (n-1) transmission channels of the corresponding Mailbox. After writing the target information into (n-1) transmission channels of the target communication module, the bits of the virtual channel corresponding to the current service in the specified channel are set as the target flag. For example, setting it to 1 indicates that the in-band data of the current service has been transmitted and the current service is the service to which the target information belongs.

[0062] The ZipC protocol uses a combination of physical and virtual channels. A physical channel is divided into p virtual channels, supporting p inter-core communication services. If in-band data transmission exists, it is written into (n-1) physical transmission channels. All p services can use these physical transmission channels for in-band data transmission, thereby improving channel utilization. Therefore, the embodiments of this disclosure can enable processing cores to reuse the same transmission channels for transmitting different service data, further improving channel utilization.

[0063] In some embodiments, the first target information may include information about shared memory in various multi-core processors. When the target information includes the first target information, the interrupt sending processing core writing the target information into the target channel of the target communication module (i.e., step S12) includes: the interrupt sending processing core writing information about various types of shared memory in the multi-core processor into each of the (n-1) transmission channels in the target communication module, wherein information about each type of shared memory in the multi-core processor is written into one transmission channel. That is, during out-of-band transmission, information about different types of shared memory can be written into different transmission channels.

[0064] In some embodiments, the first target information may include: high-order address information of shared memory in a multi-core processor, low-order address information of shared memory in a multi-core processor, data length information of shared memory in a multi-core processor, and flag information.

[0065] Figure 6 is a schematic diagram of transmitting target information using the target channel based on the zipc protocol according to an embodiment of this disclosure. The process of transmitting target information through (n-1) transmission channels will be described in detail below with reference to Figure 6 and Figure 2.

[0066] Taking Mailbox0 in Figure 2 as an example, the channel allocation, interrupts, and the relationship between the sender processing core and receiver processing core of Mailbox0 are shown in Table 1:

[0067] Table 1

[0068] As shown in Table 1, Mailbox0 is configured with three interrupts, with Core0, Core 1, and Core 2 serving as the receiving cores. Taking Core 2 as an example, when Core 2 acts as the receiving core, there are multiple different sending cores: Core 0, Core 1, and Cores 3 through 6. Assume that inter-core communication requires the transmission of 128 bits of data within the band. This 128 bits includes: 64 bits of shared memory address information, where the high 32 bits are the high-order address of the shared memory (addr_high) and the low 32 bits are the low-order address (addr_low); 32 bits of the shared memory data length (len); and 32 bits of a flag. Each sending core (Core 0, Core 1, and Cores 3 through 6) needs to use five physical channels of Mailbox to communicate with Core 2, requiring a total of 30 physical channels. Different sending cores communicate with Core 2 using one interrupt, int_to_cpu2.

[0069] Taking the int_to_cpu2 interrupt with Core 0 as the sending core and Core 2 as the receiving core as the receiving core, the corresponding channels include five physical channels: chan10-chan14. Among them, chan10 is the designated channel, and chan11-chan14 are the transmission channels. As shown in Figure 6, the low-order address (addr_low) of the 32-bit shared memory in the 128-bit data is transmitted to chan11 of Mailbox0; the high-order address (addr_high) of the 32-bit shared memory in the 128-bit data is transmitted to chan12 of Mailbox0; the data length (len) of the 32-bit shared memory in the 128-bit data is transmitted to chan13 of Mailbox0; and the flag of the 32-bit data is transmitted to chan14 of Mailbox0.

[0070] If Core 0 and Core 2 have multiple service communication needs but only 5 channels, the zipc protocol is required. The zipc protocol divides the designated channel chan10 into 32 virtual channels, each corresponding to one of the 32 services, allowing up to 32 services to communicate between Core 0 and Core 2. In-band data transmission between different services between Core 0 and Core 2 can be time-divisionally written to the four transmission channels chan11-14. When a service requests a Mailbox channel, it is allocated a specific virtual channel. The interrupt mechanism is triggered by setting the virtual channel bit corresponding to that service to 1, thereby enabling inter-core communication.

[0071] In some embodiments, when the target information is a preset indication, the sending core and receiving core of the interruption transmit the indication information via an "in-band" transmission method. In this case, the target channel may include a designated channel, which is configured with p virtual channels, where p is the number of services processed by the multi-core processor and is an integer greater than or equal to 2. Each service corresponds to one virtual channel. That is, when the sending core and receiving core of the interruption transmit the indication information via an "in-band" transmission method, there is no need to use a transmission channel. Therefore, the channel may only include a designated channel and not a transmission channel. Accordingly, the sending core of the interruption writes the target information into the target channel in the target communication module (i.e., step S12) by sending the target information to the target communication module and setting the target virtual channel in the designated channel of the target channel as a target marker, wherein the target virtual channel is the virtual channel corresponding to the service to which the target information belongs. That is, the sending core of the interruption directly sends the target information to the target communication module and sets the bit position of the virtual channel corresponding to the current service in the designated channel as the target marker, for example, setting it to 1.

[0072] The inter-core communication method for multi-core processors provided in this disclosure allocates Mailbox channels. The number of channels between processing cores is pre-defined according to service requirements. All channels are allocated according to communication needs, and each channel designates a sending processing core and a receiving processing core. This allows a single Mailbox hardware module to support multiple processing cores, reducing the number of Mailbox hardware modules in the SoC and fully utilizing Mailbox channels, thus reducing chip cost and space. This disclosure also provides a novel Mailbox communication protocol that combines physical and virtual channels. A pair of processing cores can reuse physical channels to achieve in-band data transmission for different services, improving channel utilization. Furthermore, virtual channels are used to implement an interrupt mechanism for conflict-free inter-core communication.

[0073] This disclosure applies to scenarios where multiple processing cores of a multi-core processor work collaboratively, specifically relating to products such as smart cockpits and smart homes. Each processing core, having determined a communication channel, utilizes shared memory in conjunction with inter-core interrupts. Shared memory provides the channel for information exchange, while inter-core interrupts provide an event notification mechanism based on the channel configuration, thus achieving efficient inter-core communication.

[0074] This disclosure also provides an electronic device. FIG7 is a schematic block diagram of the electronic device provided in this disclosure. As shown in FIG7, the electronic device includes a memory 1 and a processor 2. The memory 1 stores a computer program that can be executed by the processor 2. When the computer program is executed by the processor 2, it implements any one of the inter-core communication methods according to the embodiments of this disclosure.

[0075] Processor 2 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); I / O interface (read-write interface) is connected between the processor and memory, enabling information exchange between the memory and the processor, including but not limited to a data bus (Bus).

[0076] This disclosure also provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements any one of the inter-core communication methods according to embodiments of this disclosure.

[0077] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements any one of the inter-core communication methods according to embodiments of this disclosure.

[0078] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0079] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0080] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0081] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A method for inter-core communication, applied to a multi-core processor, the multi-core processor comprising a plurality of processing cores, at least two of the plurality of processing cores being configured to share a same communication module, the communication module being configured with a plurality of interrupts, each of the at least two processing cores corresponding to one of the plurality of interrupts as a receiver processing core of the interrupt, the communication module being configured with at least one channel, the at least one channel being used for communication between the at least two processing cores or between the at least two processing cores and other cores of the plurality of processing cores, the method comprising: in a case where a sender processing core of an interrupt sends target information to a receiver processing core of the interrupt, the sender processing core of the interrupt determining a target communication module, wherein the target communication module is a communication module configured for the receiver processing core of the interrupt; the sender processing core of the interrupt writing the target information into a target channel in the target communication module to trigger a general interrupt controller to which the target communication module belongs to send an interrupt message to the receiver processing core of the interrupt, wherein the target channel is one of the at least one channel; and the receiver processing core of the interrupt reading the target information from the target channel according to the interrupt message. After the receiver processing core of the interrupt reads the target information from the target channel according to the interrupt message, the method further comprises: clearing the target information in the target channel. The target information comprises first target information or second target information, the first target information comprising at least information of shared memory in the multi-core processor, the second target information not comprising information of shared memory in the multi-core processor, and the second target information comprising service data or preset indication information. The target information comprises the first target information or the service data, the at least one channel comprising n physical channels, n being an integer greater than or equal to 2, the n physical channels comprising one designated channel and (n-1) transmission channels, the one designated channel being divided into p virtual channels, p being a number of services processed by the multi-core processor and p being an integer greater than or equal to 2, each service corresponding to one virtual channel, 2. The method of claim 1, wherein, The sender processing core of the interrupt writing the target information into the target channel in the target communication module comprises: in a case where the (n-1) transmission channels are all empty, the sender processing core of the interrupt writing the target information into the (n-1) transmission channels in the target communication module; and setting a target virtual channel in the one designated channel as a target marker, wherein the target virtual channel is a virtual channel corresponding to a service to which the target information belongs. The sender processing core of the interrupt writing the target information into the target channel in the target communication module further comprises:

3. The method of claim 1, wherein, ​ 4. The method of claim 3, wherein, ​ ​ ​ ​ 5. The method according to claim 4, wherein, ​ In a case that at least one of the transmission channels is not empty, it is judged whether the (n-1) transmission channels are all empty after waiting for a preset time length, and until the (n-1) transmission channels are all empty, the sender processing core of the interrupt writes the target information into the (n-1) transmission channels in the target communication module.

6. The method of claim 4 or 5, wherein, The target information includes the first target information, the first target information includes information of a plurality of types of shared memories in the multi-core processor, and the sender processing core of the interrupt writes the target information into a target channel in the target communication module, including: The sender processing core of the interrupt writes information of a plurality of types of shared memories in the multi-core processor into the (n-1) transmission channels in the target communication module, wherein information of each type of shared memory in the multi-core processor is written into one transmission channel.

7. The method of claim 6, wherein, The first target information includes high-bit address information of a shared memory in the multi-core processor, low-bit address information of the shared memory in the multi-core processor, data length information of the shared memory in the multi-core processor, and flag information.

8. The method of claim 4, wherein, Different services time-division multiplex at least part of the (n-1) transmission channels.

9. The method of claim 3, wherein, The target information includes the preset indication information, the target channel includes one designated channel, the one designated channel is a physical channel, the one designated channel is divided into p virtual channels, p is the number of services processed by the multi-core processor, and p is an integer greater than or equal to 2, each service corresponds to one virtual channel, The sender processing core of the interrupt writes the target information into a target channel in the target communication module, including: The sender processing core of the interrupt sends the target information to the target communication module, and sets a target virtual channel in the one designated channel as a target mark, wherein the target virtual channel is a virtual channel corresponding to a service to which the target information belongs.

10. The method of any one of claims 1 to 9, wherein, The communication module is a Mailbox module. 11.An electronic device, comprising a memory and a processor, The memory stores a computer program executable by the processor, and the computer program is executed by the processor to implement the inter-core communication method according to any one of claims 1 to 10. 12.A computer readable medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the inter-core communication method according to any one of claims 1 to 10. 13.A computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the inter-core communication method according to any one of claims 1 to 10.

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