Pixel circuit, pixel driving method, and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a pixel driving method, and a display apparatus. The pixel comprises a light-emitting element, a drive circuit, a display control circuit, a control data writing circuit, a first energy storage circuit and a set circuit, wherein the drive circuit generates a drive current under the control of a display data voltage; the display control circuit controls the connection or disconnection between a second end of the drive circuit and a second voltage end under the control of the potential of a first control node; the control data writing circuit controls the connection or disconnection between a control data line and the first control node under the control of a control voltage; and the set circuit controls the connection or disconnection between a third voltage end and the first control node under the control of a scanning signal. The embodiments of the present disclosure avoid the problems of luminance instability during light emission and a shift in chromaticity coordinates brought about by an unstable current value in a current region, ameliorate the phenomenon of unstable low-grayscale display, and ameliorate the problems of heat being emitted and the power consumption being high in pure pulse-amplitude-modulation drive control.

Description

Pixel circuit, pixel driving method and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410668834.3, filed on May 27, 2024 in China, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a pixel driving method and a display device. BACKGROUND

[0004] The related pixel circuit has the problems of unstable light-emitting brightness and color coordinate deviation caused by unstable current value in a low current region, and the related pixel circuit is unstable in low gray scale display and has large heat generation and power consumption in pure PAM (pulse amplitude modulation) driving control. SUMMARY

[0005] The main purpose of the present disclosure is to provide a pixel circuit, a pixel driving method and a display device, which solve the problems of unstable light-emitting brightness and color coordinate deviation caused by unstable current value in a low current region of the related pixel circuit, and solve the problems of instability in low gray scale display and large heat generation and power consumption in pure PAM (pulse amplitude modulation) driving control of the related pixel circuit.

[0006] In one aspect, the embodiments of the present disclosure provide a pixel circuit, comprising a light-emitting element, a driving circuit, a display control circuit, a control data writing circuit, a first energy storage circuit and a setting circuit;

[0007] A first pole of the light-emitting element is electrically connected with a first voltage terminal;

[0008] A control terminal of the driving circuit is electrically connected with a display data line, a first terminal of the driving circuit is electrically connected with a second pole of the light-emitting element, a second terminal of the driving circuit is electrically connected with a first terminal of the display control circuit, and the driving circuit is used for generating a driving current for driving the light-emitting element under the control of a display data voltage provided by the display data line;

[0009] A control terminal of the display control circuit is electrically connected with a first control node, a second terminal of the display control circuit is electrically connected with a second voltage terminal, and the display control circuit is used for controlling the second terminal of the driving circuit and the second voltage terminal to be connected or disconnected under the control of a potential of the first control node;

[0010] The control data writing circuit is electrically connected with the control voltage line, the control data line and the first control node respectively, and is configured to control the control data line to be connected or disconnected with the first control node under the control of the control voltage provided by the control voltage line.

[0011] The first energy storage circuit is electrically connected with the first control node, and is configured to maintain the potential of the first control node.

[0012] The setting circuit is electrically connected with the scan line, the third voltage terminal and the first control node respectively, and is configured to control the third voltage terminal to be connected or disconnected with the first control node under the control of the scan signal provided by the scan line.

[0013] Optionally, the control data writing circuit comprises a first data writing circuit, a switch control circuit and a second energy storage circuit.

[0014] The first data writing circuit is electrically connected with the scan line, the control voltage line and the second control node respectively, and is configured to control the control voltage line to be connected or disconnected with the second control node under the control of the scan signal.

[0015] The switch control circuit is electrically connected with the second control node, the control data line and the first control node respectively, and is configured to control the control data line to be connected or disconnected with the first control node under the control of the potential of the second control node.

[0016] The second energy storage circuit is electrically connected with the second control node, and is configured to maintain the potential of the second control node.

[0017] Optionally, the pixel circuit further comprises a second data writing circuit and a third energy storage circuit.

[0018] The second data writing circuit is electrically connected with the scan line, the display data line and the control end of the driving circuit respectively, and is configured to control the display data line to be connected or disconnected with the control end of the driving circuit under the control of the scan signal.

[0019] The third energy storage circuit is electrically connected with the control end of the driving circuit, and is configured to maintain the potential of the control end of the driving circuit.

[0020] Optionally, the pixel circuit further comprises a second data writing circuit, a compensation control circuit and a third energy storage circuit.

[0021] The second data writing circuit is electrically connected with the scanning line, the display data line and the second end of the driving circuit respectively, and is configured to control the display data line and the second end of the driving circuit to be in communication or disconnected under the control of the scanning signal provided by the scanning line.

[0022] The compensation control circuit is electrically connected with the scanning line, the control end of the driving circuit and the first end of the driving circuit respectively, and is configured to control the control end of the driving circuit and the first end of the driving circuit to be in communication or disconnected under the control of the scanning signal.

[0023] The third energy storage circuit is electrically connected with the control end of the driving circuit, and is configured to maintain the potential of the control end of the driving circuit.

[0024] Optionally, the pixel circuit further comprises a reset circuit.

[0025] The reset circuit is electrically connected with the reset control line, the fourth voltage end and the control end of the driving circuit respectively, and is configured to control the fourth voltage end and the control end of the driving circuit to be in communication or disconnected under the control of the reset control signal provided by the reset control line.

[0026] Optionally, the pixel circuit further comprises a first light-emitting control circuit.

[0027] The first light-emitting control circuit is electrically connected with the light-emitting control line, the second pole of the light-emitting element and the first end of the driving circuit respectively, and is configured to control the second pole of the light-emitting element and the first end of the driving circuit to be in communication or disconnected under the control of the light-emitting control signal provided by the light-emitting control line.

[0028] Optionally, the pixel circuit further comprises a second light-emitting control circuit.

[0029] The second light-emitting control circuit is electrically connected with the light-emitting control line, the second end of the driving circuit and the first end of the display control circuit respectively, and is configured to control the second end of the driving circuit and the first end of the display control circuit to be in communication or disconnected under the control of the light-emitting control signal.

[0030] Optionally, the driving circuit comprises a driving transistor, the set circuit comprises a first transistor, the display control circuit comprises a second transistor, the control data writing circuit comprises a third transistor, and the first energy storage circuit comprises a first capacitor.

[0031] The gate of the driving transistor is electrically connected with the display data line, the first pole of the driving transistor is electrically connected with the second pole of the light emitting element, and the second pole of the driving transistor is electrically connected with the first pole of the second transistor;

[0032] The gate of the first transistor is electrically connected with the scan line, the first pole of the first transistor is electrically connected with the third voltage terminal, and the second pole of the first transistor is electrically connected with the first control node;

[0033] The gate of the second transistor is electrically connected with the first control node, and the second pole of the second transistor is electrically connected with the second voltage terminal;

[0034] The gate of the third transistor is electrically connected with the control voltage line, the first pole of the third transistor is electrically connected with the control data line, and the second pole of the third transistor is electrically connected with the first control node;

[0035] The first end of the first capacitor is electrically connected with the first control node, and the second end of the first capacitor is electrically connected with a direct current voltage terminal.

[0036] Optionally, the first data writing circuit comprises a fourth transistor, the switch control circuit comprises a fifth transistor, and the second energy storage circuit comprises a second capacitor;

[0037] The gate of the fourth transistor is electrically connected with the scan line, the first pole of the fourth transistor is electrically connected with the control voltage line, and the second pole of the fourth transistor is electrically connected with the second control node;

[0038] The gate of the fifth transistor is electrically connected with the second control node, the first pole of the fifth transistor is electrically connected with the control data line, and the second pole of the fifth transistor is electrically connected with the first control node;

[0039] The first end of the second capacitor is electrically connected with the second control node, and the second end of the second capacitor is electrically connected with a direct current voltage terminal.

[0040] Optionally, the second data writing circuit comprises a sixth transistor, and the third energy storage circuit comprises a third capacitor;

[0041] The gate of the sixth transistor is electrically connected with the scan line, the first pole of the sixth transistor is electrically connected with the display data line, and the second pole of the sixth transistor is electrically connected with the control terminal of the driving circuit;

[0042] The first end of the third capacitor is electrically connected with the control terminal of the driving circuit, and the second end of the third capacitor is electrically connected with a direct current voltage terminal.

[0043] Optionally, the compensation control circuit comprises a seventh transistor, the second data writing circuit comprises an eighth transistor, and the third energy storage circuit comprises a third capacitor.

[0044] The gate of the seventh transistor is electrically connected with the scan line, the first pole of the seventh transistor is electrically connected with the control end of the driving circuit, and the second pole of the seventh transistor is electrically connected with the first end of the driving circuit.

[0045] The gate of the eighth transistor is electrically connected with the scan line, the first pole of the eighth transistor is electrically connected with the display data line, and the second pole of the eighth transistor is electrically connected with the second end of the driving circuit.

[0046] The first end of the third capacitor is electrically connected with the control end of the driving circuit, and the second end of the third capacitor is electrically connected with the direct current voltage end.

[0047] Optionally, the reset circuit comprises a ninth transistor.

[0048] The gate of the ninth transistor is electrically connected with the reset control line, the first pole of the ninth transistor is electrically connected with the fourth voltage end, and the second pole of the ninth transistor is electrically connected with the control end of the driving circuit.

[0049] Optionally, the first light emitting control circuit comprises a tenth transistor.

[0050] The gate of the tenth transistor is electrically connected with the light emitting control line, the first pole of the tenth transistor is electrically connected with the second pole of the light emitting element, and the second pole of the tenth transistor is electrically connected with the first end of the driving circuit.

[0051] Optionally, the second light emitting control circuit comprises an eleventh transistor.

[0052] The gate of the eleventh transistor is electrically connected with the light emitting control line, the first pole of the eleventh transistor is electrically connected with the second end of the driving circuit, and the second pole of the eleventh transistor is electrically connected with the first end of the display control circuit.

[0053] In a second aspect, the embodiments of the present disclosure provide a pixel driving method applied to the pixel circuit described above; a display period comprises a reset time period; the pixel driving method comprises:

[0054] In the reset time period, the reset circuit controls the communication between the third voltage end and the first control node under the control of the scan signal, and the display control circuit controls the communication between the second end of the driving circuit and the second voltage end under the control of the potential of the first control node.

[0055] In the display period, the driving circuit generates a driving current for driving the light emitting element under control of a display data voltage; the control data write-in circuit controls the first control node to be connected with or disconnected from the control data line under control of a control voltage; and the display control circuit controls the second end of the driving circuit to be disconnected from the second voltage end under control of the potential of the first control node when the control data write-in circuit controls the first control node to be connected with the control data line.

[0056] Optionally, the display period comprises N display stages; N is an integer greater than 1.

[0057] The pixel driving method comprises:

[0058] In the nth display period, the control data line provides an nth control data voltage; n is a positive integer less than or equal to N.

[0059] The duration of the mth display period is less than the duration of the m+1th display period; m is a positive integer less than N.

[0060] In a third aspect, the embodiments of the present disclosure provide a display device comprising the pixel circuit.

[0061] Optionally, the display device provided by at least one embodiment of the present disclosure further comprises a plurality of control data lines and a plurality of data voltage providing circuits.

[0062] The data voltage providing circuit is electrically connected with the control data line and configured to provide a control data voltage for the control data line.

[0063] Optionally, the data voltage providing circuit comprises N data providing units; N is an integer greater than 1; and m is a positive integer less than N.

[0064] The mth data providing unit comprises an mth reset unit, an mth control unit, an mth providing unit and an mth energy storage unit.

[0065] The mth reset unit is electrically connected with an initial control line, a fifth voltage end and an mth node, and configured to connect or disconnect the fifth voltage end and the mth node under control of an initial control signal provided by the initial control line.

[0066] The mth control unit is electrically connected with the mth node, an mth control end, an m+1th control end, a sixth voltage end and a seventh voltage end, and configured to control the mth node to be connected with or disconnected from the sixth voltage end under control of an mth control signal provided by the mth control end, and control the mth node to be connected with or disconnected from the seventh voltage end under control of an m+1th control signal provided by the m+1th control end.

[0067] The mth providing unit is electrically connected with the mth node, the mth data voltage terminal and the control data line, and is configured to control the mth data voltage terminal to be in communication or disconnected with the control data line under the control of the potential of the mth node;

[0068] The mth energy storage unit is electrically connected with the mth node, and is configured to maintain the potential of the mth node.

[0069] The Nth data providing unit comprises an Nth reset unit, an Nth control unit, an Nth providing unit and an Nth energy storage unit.

[0070] The Nth reset unit is electrically connected with an initial control line, an eighth voltage terminal and an Nth node, and is configured to control the eighth voltage terminal to be in communication or disconnected with the Nth node under the control of an initial control signal provided by the initial control line.

[0071] The Nth control unit is electrically connected with the Nth node, an Nth control terminal, a first control terminal, a sixth voltage terminal and a seventh voltage terminal, and is configured to control the Nth node to be in communication or disconnected with the sixth voltage terminal under the control of an Nth control signal provided by the Nth control terminal, and control the Nth node to be in communication or disconnected with the seventh voltage terminal under the control of a first control signal provided by the first control terminal.

[0072] The Nth providing unit is electrically connected with the Nth node, an Nth data voltage terminal and the control data line, and is configured to control the Nth data voltage terminal to be in communication or disconnected with the control data line under the control of the potential of the Nth node.

[0073] The Nth energy storage unit is electrically connected with the Nth node, and is configured to maintain the potential of the Nth node.

[0074] Optionally, the mth reset unit comprises an mth reset transistor, the mth control unit comprises an mth first control transistor and an mth second control transistor, the mth providing unit comprises an mth providing transistor, and the mth energy storage unit comprises an mth storage capacitor.

[0075] The gate of the mth reset transistor is electrically connected with the initial control line, the first pole of the mth reset transistor is electrically connected with the fifth voltage terminal, and the second pole of the mth reset transistor is electrically connected with the mth node.

[0076] The gate of the mth first control transistor is electrically connected with the mth control terminal, the first pole of the mth first control transistor is electrically connected with the sixth voltage terminal, and the second pole of the mth first control transistor is electrically connected with the mth node.

[0077] The gate of the mth second control transistor is electrically connected with the m+1th control end, the first electrode of the mth second control transistor is electrically connected with the mth node, and the second electrode of the mth second control transistor is electrically connected with the seventh voltage end;

[0078] The gate of the mth providing transistor is electrically connected with the mth node, the first electrode of the mth providing transistor is electrically connected with the mth data voltage end, and the second electrode of the mth providing transistor is electrically connected with the control data line.

[0079] The first end of the mth storage capacitor is electrically connected with the mth node, and the second end of the mth storage capacitor is electrically connected with a direct current voltage end.

[0080] Optionally, the Nth reset unit comprises an Nth reset transistor, the Nth control unit comprises an Nth first control transistor and an Nth second control transistor, the Nth providing unit comprises an Nth providing transistor, and the Nth energy storage unit comprises an Nth storage capacitor.

[0081] The gate of the Nth reset transistor is electrically connected with the initial control line, the first electrode of the Nth reset transistor is electrically connected with the eighth voltage end, and the second electrode of the Nth reset transistor is electrically connected with the Nth node.

[0082] The gate of the Nth first control transistor is electrically connected with the Nth control end, the first electrode of the Nth first control transistor is electrically connected with the sixth voltage end, and the second electrode of the Nth first control transistor is electrically connected with the Nth node.

[0083] The gate of the Nth second control transistor is electrically connected with the N+1th control end, the first electrode of the Nth second control transistor is electrically connected with the Nth node, and the second electrode of the Nth second control transistor is electrically connected with the seventh voltage end.

[0084] The gate of the Nth providing transistor is electrically connected with the Nth node, the first electrode of the Nth providing transistor is electrically connected with the Nth data voltage end, and the second electrode of the Nth providing transistor is electrically connected with the control data line.

[0085] The first end of the Nth storage capacitor is electrically connected with the Nth node, and the second end of the Nth storage capacitor is electrically connected with a direct current voltage end.

[0086] The display data voltage provided by the display data line can be used to control the driving circuit to perform PWM (pulse amplitude modulation) control, and the display data voltage provided by the display data line can be used to control the data writing circuit, the first energy storage circuit, the setting circuit and the display control circuit to perform PWM (pulse width modulation) control. The PWM driving can cut multiple gray scale spaces, the number of gray scales in each gray scale interval can be adjusted arbitrarily, the display data voltage provided by the display data line DTM can be adjusted in each gray scale space, in the same Data Range (data voltage range), the number of gray scales is reduced, and the light emitting element can work in a high current area, avoiding the problem of unstable light emitting brightness and color coordinate deviation caused by unstable current value in a low current area, improving the unstable phenomenon of low gray scale display, and improving the problem of heat generation and large power consumption of pure PAM driving control. BRIEF DESCRIPTION OF DRAWINGS

[0087] FIG. 1 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] FIG. 2 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] FIG. 3 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] FIG. 4 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0091] FIG. 5 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0092] FIG. 6 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0093] FIG. 7 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0094] FIG. 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0095] FIG. 9A is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8;

[0096] FIG. 9B is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8;

[0097] FIG. 9C is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8;

[0098] FIG. 9D is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8;

[0099] FIG. 9E is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8;

[0100] FIG. 10 is a circuit diagram of a pixel circuit, in accordance with at least one embodiment of the present disclosure;

[0101] FIG. 11A is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 10;

[0102] FIG. 11B is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 10;

[0103] FIG. 11C is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 10;

[0104] FIG. 11D is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 10;

[0105] FIG. 11E is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 10;

[0106] FIG. 12 is a circuit diagram of a pixel circuit, in accordance with at least one embodiment of the present disclosure;

[0107] FIG. 13A is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 12;

[0108] FIG. 13B is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 12;

[0109] FIG. 13C is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 12;

[0110] FIG. 13D is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 12;

[0111] FIG. 13E is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 12;

[0112] FIG. 14 is a circuit diagram of a pixel circuit, in accordance with at least one embodiment of the present disclosure;

[0113] FIG. 15A is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0114] FIG. 15B is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0115] FIG. 15C is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0116] FIG. 15D is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0117] FIG. 15E is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 14;

[0118] FIG. 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0119] FIG. 17A is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 16;

[0120] FIG. 17B is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 16;

[0121] FIG. 17C is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 16;

[0122] FIG. 17D is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 16;

[0123] FIG. 17E is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 16;

[0124] FIG. 18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0125] FIG. 19A is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 18;

[0126] FIG. 19B is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 18;

[0127] FIG. 19C is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 18;

[0128] FIG. 19D is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 18;

[0129] FIG. 19E is a timing diagram of operation of at least one embodiment of the pixel circuit of FIG. 18;

[0130] FIG. 20 is a schematic diagram of a connection relationship between a data voltage providing circuit and a control data line included in a display device according to at least one embodiment of the present disclosure;

[0131] FIG. 21 is a structural diagram of at least one embodiment of a data voltage providing circuit;

[0132] FIG. 22 is a circuit diagram of at least one embodiment of a data voltage providing circuit;

[0133] FIG. 23 is a timing diagram of operation of at least one embodiment of the data voltage providing circuit of FIG. 22;

[0134] FIG. 24 is a circuit diagram of at least one embodiment of a data voltage providing circuit;

[0135] FIG. 25 is a timing diagram of operation of at least one embodiment of the data voltage providing circuit of FIG. 24. DETAILED DESCRIPTION

[0136] The technical solutions in the embodiments of the present disclosure will be clearly and completely described in combination with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0137] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0138] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0139] As shown in FIG. 1, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a driving circuit 10, a display control circuit 11, a control data writing circuit 12, a first energy storage circuit 13 and a setting circuit 14.

[0140] The first pole of the light emitting element E1 is electrically connected with a first voltage terminal V1.

[0141] The control terminal of the driving circuit 10 is electrically connected with a display data line DTM, the first end of the driving circuit 10 is electrically connected with the second pole of the light emitting element E1, the second end of the driving circuit 10 is electrically connected with the first end of the display control circuit 11, and the driving circuit 10 is used to generate a driving current for driving the light emitting element E1 under the control of a display data voltage provided by the display data line DTM.

[0142] The control terminal of the display control circuit 11 is electrically connected with a first control node PW, and the second end of the display control circuit 11 is electrically connected with a second voltage terminal V2. The display control circuit 11 is used to control the communication or disconnection between the second end of the driving circuit 10 and the second voltage terminal V2 under the control of the potential of the first control node PW.

[0143] The control data writing circuit 12 is electrically connected with a control voltage line DTM1, a control data line SLM and the first control node PW respectively, and is used to control the communication or disconnection between the control data line SLM and the first control node PW under the control of a control voltage provided by the control voltage line DTM1.

[0144] The first energy storage circuit 13 is electrically connected with the first control node PW, and is used for maintaining the potential of the first control node PW.

[0145] The setting circuit 14 is electrically connected with the scan line GTM, the third voltage terminal V3 and the first control node PW respectively, and is used for controlling the communication or disconnection between the third voltage terminal V3 and the first control node PW under the control of the scan signal provided by the scan line GTM.

[0146] The pixel circuit in at least one embodiment of the present disclosure can control the driving circuit 10 to perform PWM (pulse amplitude modulation) control through the display data voltage provided by the display data line DTM, and can control the control data writing circuit 12, the first energy storage circuit 13, the setting circuit 14 and the display control circuit 11 to perform PWM (pulse width modulation) control, the PWM driving can cut multiple gray scale spaces, the number of gray scales contained in each gray scale interval can be adjusted arbitrarily, the display data voltage provided by the display data line DTM can adjust the voltage in each gray scale space, in the same Data Range (data voltage range), the number of gray scales is reduced, and the light emitting element can work in a high current area, avoiding the problems of unstable light emitting brightness and color coordinate deviation caused by unstable current value in a low current area, improving the phenomenon of unstable low gray scale display, and improving the problems of heat generation and large power consumption caused by pure PAM driving control.

[0147] When at least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure works, the display period includes a reset time period;

[0148] In the reset time period, the setting circuit 14 controls the communication between the third voltage terminal V3 and the first control node PW under the control of the scan signal, the display control circuit 11 controls the communication between the second end of the driving circuit 10 and the second voltage terminal V2 under the control of the potential of the first control node NC1, and the driving circuit 10 drives the light emitting element E1 to emit light.

[0149] In the display period, the driving circuit 10 generates a driving current for driving the light emitting element E1 under the control of the display data voltage, the control data writing circuit 12 controls the communication or disconnection between the first control node PW and the control data line SLM under the control of the control voltage, and when the control data writing circuit 12 controls the communication between the first control node PW and the control data line SLM, the display control circuit controls the disconnection between the second end of the driving circuit 10 and the second voltage terminal V2 under the control of the potential of the first control node PW.

[0150] Optionally, the second voltage terminal can be a low voltage terminal or a power supply voltage terminal, and the third voltage terminal can be a high voltage terminal or a low voltage terminal.

[0151] In at least one embodiment of the present disclosure, the control data writing circuit comprises a first data writing circuit, a switch control circuit and a second energy storage circuit;

[0152] The first data writing circuit is electrically connected with the scan line, the control voltage line and the second control node respectively, and is configured to control the control voltage line and the second control node to be connected or disconnected under the control of the scan signal.

[0153] The switch control circuit is electrically connected with the second control node, the control data line and the first control node respectively, and is configured to control the control data line and the first control node to be connected or disconnected under the control of the potential of the second control node.

[0154] The second energy storage circuit is electrically connected with the second control node, and is configured to maintain the potential of the second control node.

[0155] In a specific implementation, the control data writing circuit can comprise a first data writing circuit, a switch control circuit and a second energy storage circuit; the first data writing circuit writes the control voltage provided by the control voltage line to the second control node under the control of the scan signal; the switch control circuit controls the control data line and the first control node to be connected or disconnected under the control of the potential of the second control node; and the second energy storage circuit maintains the potential of the second control node.

[0156] Optionally, the first voltage terminal can be a power supply voltage terminal or a low voltage terminal.

[0157] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the control data writing circuit comprises a first data writing circuit 21, a switch control circuit 22 and a second energy storage circuit 20.

[0158] The first data writing circuit 21 is electrically connected with the scan line GTM, the control voltage line DTM1 and the second control node NC2 respectively, and is configured to control the control voltage line DTM1 and the second control node NC2 to be connected or disconnected under the control of the scan signal.

[0159] The switch control circuit 22 is electrically connected with the second control node NC2, the control data line SLM and the first control node PW respectively, and is configured to control the control data line SLM and the first control node PW to be connected or disconnected under the control of the potential of the second control node NC2.

[0160] The second energy storage circuit 20 is electrically connected with the second control node NC2, and is configured to maintain the potential of the second control node NC2.

[0161] The pixel circuit in at least one embodiment of the present disclosure further comprises a second data writing circuit and a third energy storage circuit;

[0162] The second data writing circuit is electrically connected with the scanning line, the display data line and the control end of the driving circuit respectively, and is used for controlling the display data line and the control end of the driving circuit to be connected or disconnected under the control of the scanning signal.

[0163] The third energy storage circuit is electrically connected with the control end of the driving circuit, and is used for maintaining the potential of the control end of the driving circuit.

[0164] In specific implementation, the pixel circuit can further comprise a second data writing circuit and a third energy storage circuit. The second data writing circuit writes the display data voltage provided by the display data line to the control end of the driving circuit under the control of the scanning signal. The third energy storage circuit maintains the potential of the control end of the driving circuit.

[0165] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit in at least one embodiment of the present disclosure further comprises a second data writing circuit 31 and a third energy storage circuit 32.

[0166] The second data writing circuit 31 is electrically connected with the scanning line GTM, the display data line DTM and the control end of the driving circuit 10 respectively, and is used for controlling the display data line DTM and the control end of the driving circuit 10 to be connected or disconnected under the control of the scanning signal.

[0167] The third energy storage circuit 32 is electrically connected with the control end of the driving circuit 10, and is used for maintaining the potential of the control end of the driving circuit 10.

[0168] The pixel circuit in at least one embodiment of the present disclosure further comprises a second data writing circuit, a compensation control circuit and a third energy storage circuit.

[0169] The second data writing circuit is electrically connected with the scanning line, the display data line and the second end of the driving circuit respectively, and is used for controlling the display data line and the second end of the driving circuit to be connected or disconnected under the control of the scanning signal provided by the scanning line.

[0170] The compensation control circuit is electrically connected with the scanning line, the control end of the driving circuit and the first end of the driving circuit respectively, and is used for controlling the control end of the driving circuit and the first end of the driving circuit to be connected or disconnected under the control of the scanning signal.

[0171] The third energy storage circuit is electrically connected with the control end of the driving circuit, and is used for maintaining the potential of the control end of the driving circuit.

[0172] In specific implementation, the pixel circuit can further include a second data writing circuit, a compensation control circuit and a third energy storage circuit; the second data writing circuit controls the display data voltage provided by the display data line to be written to the second end of the driving circuit under the control of the scanning signal; the compensation control circuit controls the communication or disconnection between the control end of the driving circuit and the first end of the driving circuit under the control of the scanning signal; and the third energy storage circuit maintains the potential of the control end of the driving circuit.

[0173] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit according to at least one embodiment of the present disclosure further includes a second data writing circuit 31, a compensation control circuit 33 and a third energy storage circuit 32.

[0174] The second data writing circuit 31 is electrically connected with the scanning line GTM, the display data line DTM and the second end of the driving circuit 10 respectively, and is configured to control the communication or disconnection between the display data line DTM and the second end of the driving circuit 10 under the control of the scanning signal provided by the scanning line GTM.

[0175] The compensation control circuit 33 is electrically connected with the scanning line GTM, the control end of the driving circuit 10 and the first end of the driving circuit 10 respectively, and is configured to control the communication or disconnection between the control end of the driving circuit 10 and the first end of the driving circuit 10 under the control of the scanning signal.

[0176] The third energy storage circuit 32 is electrically connected with the control end of the driving circuit 10, and is configured to maintain the potential of the control end of the driving circuit 10.

[0177] The pixel circuit according to at least one embodiment of the present disclosure further includes a reset circuit.

[0178] The reset circuit is electrically connected with a reset control line, a fourth voltage end and the control end of the driving circuit respectively, and is configured to control the communication or disconnection between the fourth voltage end and the control end of the driving circuit under the control of a reset control signal provided by the reset control line.

[0179] In specific implementation, the pixel circuit can further include a reset circuit, which writes the fourth voltage signal provided by the fourth voltage end to the control end of the driving circuit under the control of a reset control signal.

[0180] Optionally, the fourth voltage end can be a high voltage end or a low voltage end.

[0181] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit according to at least one embodiment of the present disclosure further comprises a reset circuit 51.

[0182] The reset circuit 51 is electrically connected with a reset control line RSTM, a fourth voltage terminal V4 and a control terminal of the driving circuit 10, respectively, for controlling the communication or disconnection between the fourth voltage terminal V4 and the control terminal of the driving circuit 10 under the control of a reset control signal provided by the reset control line RSTM.

[0183] The pixel circuit according to at least one embodiment of the present disclosure further comprises a first light-emitting control circuit.

[0184] The first light-emitting control circuit is electrically connected with a light-emitting control line, a second electrode of the light-emitting element and a first terminal of the driving circuit, respectively, for controlling the communication or disconnection between the second electrode of the light-emitting element and the first terminal of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control line.

[0185] In specific implementation, the pixel circuit can further comprise a first light-emitting control circuit, which controls the communication or disconnection between the second electrode of the light-emitting element and the first terminal of the driving circuit under the control of the light-emitting control signal.

[0186] As shown in FIG. 6, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit according to at least one embodiment of the present disclosure further comprises a first light-emitting control circuit 61.

[0187] The first light-emitting control circuit 61 is electrically connected with a light-emitting control line EM, a second electrode of the light-emitting element E1 and a first terminal of the driving circuit 10, respectively, for controlling the communication or disconnection between the second electrode of the light-emitting element E1 and the first terminal of the driving circuit 10 under the control of a light-emitting control signal provided by the light-emitting control line EM.

[0188] The pixel circuit according to at least one embodiment of the present disclosure further comprises a second light-emitting control circuit.

[0189] The second light-emitting control circuit is electrically connected with the light-emitting control line, a second terminal of the driving circuit and a first terminal of the display control circuit, respectively, for controlling the communication or disconnection between the second terminal of the driving circuit and the first terminal of the display control circuit under the control of the light-emitting control signal.

[0190] In specific implementation, the pixel circuit can further comprise a second light-emitting control circuit, which controls the communication or disconnection between the second terminal of the driving circuit and the first terminal of the display control circuit under the control of the light-emitting control signal.

[0191] As shown in FIG. 7, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5, the pixel circuit according to at least one embodiment of the present disclosure further comprises a first light-emitting control circuit 61 and a second light-emitting control circuit 62.

[0192] The first light-emitting control circuit 61 is electrically connected with the light-emitting control line EM, the second electrode of the light-emitting element E1 and the first end of the driving circuit 10 respectively, and is configured to control the communication or disconnection between the second electrode of the light-emitting element E1 and the first end of the driving circuit 10 under the control of the light-emitting control signal provided by the light-emitting control line EM.

[0193] The second light-emitting control circuit 62 is electrically connected with the light-emitting control line EM, the second end of the driving circuit 10 and the first end of the display control circuit 11 respectively, and is configured to control the communication or disconnection between the second end of the driving circuit 10 and the first end of the display control circuit 11 under the control of the light-emitting control signal.

[0194] Optionally, the driving circuit comprises a driving transistor, the setting circuit comprises a first transistor, the display control circuit comprises a second transistor, and the control data writing circuit comprises a third transistor; the first energy storage circuit comprises a first capacitor.

[0195] The gate of the driving transistor is electrically connected with the display data line, the first electrode of the driving transistor is electrically connected with the second electrode of the light-emitting element, and the second electrode of the driving transistor is electrically connected with the first electrode of the second transistor.

[0196] The gate of the first transistor is electrically connected with the scanning line, the first electrode of the first transistor is electrically connected with the third voltage terminal, and the second electrode of the first transistor is electrically connected with the first control node.

[0197] The gate of the second transistor is electrically connected with the first control node, and the second electrode of the second transistor is electrically connected with the second voltage terminal.

[0198] The gate of the third transistor is electrically connected with the control voltage line, the first electrode of the third transistor is electrically connected with the control data line, and the second electrode of the third transistor is electrically connected with the first control node.

[0199] The first end of the first capacitor is electrically connected with the first control node, and the second end of the first capacitor is electrically connected with a direct current voltage terminal.

[0200] Optionally, the first data writing circuit comprises a fourth transistor, the switch control circuit comprises a fifth transistor, and the second energy storage circuit comprises a second capacitor.

[0201] The gate of the fourth transistor is electrically connected with the scan line, the first electrode of the fourth transistor is electrically connected with the control voltage line, and the second electrode of the fourth transistor is electrically connected with the second control node;

[0202] The gate of the fifth transistor is electrically connected with the second control node, the first electrode of the fifth transistor is electrically connected with the control data line, and the second electrode of the fifth transistor is electrically connected with the first control node;

[0203] The first end of the second capacitor is electrically connected with the second control node, and the second end of the second capacitor is electrically connected with a direct current voltage end.

[0204] Optionally, the second data writing circuit comprises a sixth transistor, and the third energy storage circuit comprises a third capacitor;

[0205] The gate of the sixth transistor is electrically connected with the scan line, the first electrode of the sixth transistor is electrically connected with the display data line, and the second electrode of the sixth transistor is electrically connected with the control end of the driving circuit;

[0206] The first end of the third capacitor is electrically connected with the control end of the driving circuit, and the second end of the third capacitor is electrically connected with the direct current voltage end.

[0207] Optionally, the compensation control circuit comprises a seventh transistor, the second data writing circuit comprises an eighth transistor, and the third energy storage circuit comprises a third capacitor;

[0208] The gate of the seventh transistor is electrically connected with the scan line, the first electrode of the seventh transistor is electrically connected with the control end of the driving circuit, and the second electrode of the seventh transistor is electrically connected with the first end of the driving circuit;

[0209] The gate of the eighth transistor is electrically connected with the scan line, the first electrode of the eighth transistor is electrically connected with the display data line, and the second electrode of the eighth transistor is electrically connected with the second end of the driving circuit;

[0210] The first end of the third capacitor is electrically connected with the control end of the driving circuit, and the second end of the third capacitor is electrically connected with the direct current voltage end.

[0211] Optionally, the reset circuit comprises a ninth transistor;

[0212] The gate of the ninth transistor is electrically connected with the reset control line, the first electrode of the ninth transistor is electrically connected with the fourth voltage end, and the second electrode of the ninth transistor is electrically connected with the control end of the driving circuit.

[0213] Optionally, the first light-emitting control circuit comprises a tenth transistor;

[0214] The gate of the tenth transistor is electrically connected with the light-emitting control line, the first pole of the tenth transistor is electrically connected with the second pole of the light-emitting element, and the second pole of the tenth transistor is electrically connected with the first end of the driving circuit.

[0215] Optionally, the second light-emitting control circuit comprises an eleventh transistor.

[0216] The gate of the eleventh transistor is electrically connected with the light-emitting control line, the first pole of the eleventh transistor is electrically connected with the second end of the driving circuit, and the second pole of the eleventh transistor is electrically connected with the first end of the display control circuit.

[0217] Optionally, the direct current voltage end can be a high voltage end, but is not limited thereto.

[0218] As shown in FIG. 8, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the driving circuit comprises a driving transistor M0, the setting circuit comprises a first transistor M1, the display control circuit comprises a second transistor M2, and the control data writing circuit comprises a third transistor M3; the first energy storage circuit comprises a first capacitor C1; and the light-emitting element is an organic light-emitting diode O1.

[0219] The anode of the organic light-emitting diode O1 is electrically connected with the power voltage end ELVDD.

[0220] The gate of the driving transistor M0 is electrically connected with the display data line DTM, the drain of the driving transistor M0 is electrically connected with the cathode of the organic light-emitting diode O1, and the source of the driving transistor M0 is electrically connected with the drain of the second transistor T2.

[0221] The gate of the first transistor M1 is electrically connected with the scanning line GTM, the drain of the first transistor M1 is electrically connected with the high voltage end VDD, and the source of the first transistor M1 is electrically connected with the first control node PW.

[0222] The gate of the second transistor M2 is electrically connected with the first control node PW, and the source of the second transistor M2 is electrically connected with the low voltage end ELVSS.

[0223] The gate of the third transistor M3 is electrically connected with the control voltage line DTM1, the drain of the third transistor M3 is electrically connected with the control data line SLM, and the source of the third transistor M3 is electrically connected with the first control node PW.

[0224] The first end of the first capacitor C1 is electrically connected with the first control node PW, and the second end of the first capacitor C1 is electrically connected with the high voltage end VDD.

[0225] In at least one embodiment of the pixel circuit shown in FIG. 8, all the transistors are n-type transistors, but not limited thereto.

[0226] As shown in FIG. 9A, at least one embodiment of the pixel circuit shown in FIG. 8 in operation, a frame time F1 includes a reset period SR; the display period includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5 arranged in sequence;

[0227] The first display stage S1 lasts for 38μs, the sum of the time duration of the first display stage S1 and the time duration of the second display stage S2 is 174μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2 and the time duration of the third display stage S3 is 797μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2, the time duration of the third display stage S3 and the time duration of the fourth display stage S4 is 3597μs, and the frame time F1 lasts for 16.7ms;

[0228] The first gray scale interval includes the first display stage S1, the second gray scale interval includes the first display stage S1 and the second display stage S2, the third gray scale interval includes the first display stage S1, the second display stage S2 and the third display stage S3, the fourth gray scale interval includes the first display stage S1, the second display stage S2, the third display stage S3 and the fourth display stage S4, and the fifth gray scale interval includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5;

[0229] The frame time is 16.7ms, 5 gray scale intervals are set, in the first gray scale interval, the SLM provides a -8V voltage signal; in the second gray scale interval, the SLM provides a -11V voltage signal; in the third gray scale interval, the SLM provides a -14V voltage signal; in the fourth gray scale interval, the SLM provides a -17V voltage signal; and in the fifth gray scale interval, the SLM provides a -20V voltage signal;

[0230] The first display stage lasts for 38μs, corresponding to 1 gray scale-16 gray scale; the second display stage lasts for 136μs, corresponding to 17 gray scale-32 gray scale; the third display stage lasts for 623μs, corresponding to 33 gray scale-64 gray scale; the fourth gray scale interval lasts for 2800μs, corresponding to 65 gray scale-127 gray scale; and the fifth gray scale interval lasts for 13103μs, corresponding to 128-256 gray scale;

[0231] The number of display stages included in one frame time F1 determines the number of gray scale intervals, and the time duration of each display stage determines the corresponding number of gray scales;

[0232] In the reset time period SR, the GTM provides a high voltage signal, M1 is turned on, PW is connected with VDD, M2 is turned on, the source of M0 is connected with ELVSS, and M0 drives O1 to emit light; the DTM provides a display data voltage, the voltage value of the display data voltage determines the current value of the driving current generated by M0, and by adjusting the voltage value of the display data voltage, the high and low gray scales in the corresponding gray scale interval are adjusted;

[0233] In one frame time F1, the DTM1 provides a -9.5V voltage signal;

[0234] In the first display stage S1, the SLM provides a -8V voltage signal, and M3 is turned off; M2 is turned on, M0 drives O1 to emit light, and the light emitting time of O1 is 38μs; by controlling the display data voltage provided by the DTM, 1 gray scale-16 gray scale adjustment can be realized;

[0235] In the second display stage S2, the SLM provides a -11V voltage signal, M3 is turned on, PW is connected with the SLM, M2 is turned off, and O1 does not emit light;

[0236] In the third display stage S3, the SLM provides a -14V voltage signal, M3 is turned on, PW is connected with the SLM, M2 is turned off, and O1 does not emit light;

[0237] In the fourth display stage S4, the SLM provides a -17V voltage signal, M3 is turned on, PW is connected with the SLM, M2 is turned off, and O1 does not emit light;

[0238] In the fifth display stage S5, the SLM provides a -20V voltage signal, M3 is turned on, PW is connected with the SLM, M2 is turned off, and O1 does not emit light.

[0239] As shown in FIG. 9B, at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure works as follows: one frame time F1 includes a reset time period SR; and the display period includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5 arranged in sequence;

[0240] The first display stage S1 lasts for 38 μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597 μs, and the duration of one frame F1 is 16.7 ms;

[0241] In the reset period SR, the GTM provides a high voltage signal, the M1 is turned on, the PW is connected with the VDD, the M2 is turned on, the source of the M0 is connected with the ELVSS, and the M0 drives the O1 to emit light; the DTM provides a display data voltage, the voltage value of the display data voltage determines the current value of the driving current generated by the M0, and the voltage value of the display data voltage is adjusted to adjust the gray scale level in the corresponding gray scale interval;

[0242] In one frame F1, the DTM1 provides a -12.5 V voltage signal.

[0243] In the first display stage S1, the SLM provides a -8 V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0244] In the second display stage S2, the SLM provides a -11 V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0245] In the third display stage S3, the SLM provides a -14 V voltage signal, the M3 is turned on, the PW is connected with the SLM, the M2 is turned off, and the O1 does not emit light.

[0246] In the fourth display stage S4, the SLM provides a -17 V voltage signal, the M3 is turned on, the PW is connected with the SLM, the M2 is turned off, and the O1 does not emit light.

[0247] In the fifth display stage S5, the SLM provides a -20 V voltage signal, the M3 is turned on, the PW is connected with the SLM, the M2 is turned off, and the O1 does not emit light.

[0248] The light emitting time of the O1 is 174 μs, the current value of the driving current of the O1 is adjusted by controlling the display data voltage provided by the DTM, and 17 gray scale-32 gray scale display is realized.

[0249] As shown in FIG. 9C, at least one embodiment of the pixel circuit shown in FIG. 8 works as follows: one frame F1 includes a reset period SR; the display period includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5 arranged in sequence.

[0250] The first display stage S1 lasts for 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the duration of one frame F1 is 16.7ms;

[0251] In the reset period SR, the GTM provides a high voltage signal, the M1 is turned on, the PW is connected with the VDD, the M2 is turned on, the source of the M0 is connected with the ELVSS, and the M0 drives the O1 to emit light; the DTM provides a display data voltage, the voltage value of the display data voltage determines the current value of the driving current generated by the M0, and the voltage value of the display data voltage is adjusted to adjust the gray scale level in the corresponding gray scale interval.

[0252] In one frame F1, the DTM1 provides a -15.5V voltage signal.

[0253] In the first display stage S1, the SLM provides a -8V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0254] In the second display stage S2, the SLM provides a -11V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0255] In the third display stage S3, the SLM provides a -14V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0256] In the fourth display stage S4, the SLM provides a -17V voltage signal, the M3 is turned on, the PW is connected with the SLM, the M2 is turned off, and the O1 does not emit light.

[0257] In the fifth display stage S5, the SLM provides a -20V voltage signal, the M3 is turned on, the PW is connected with the SLM, the M2 is turned off, and the O1 does not emit light.

[0258] The light emitting time of the O1 is 797μs, the current value of the driving current of the O1 can be adjusted by controlling the display data voltage provided by the DTM, and 33 gray scale-64 gray scale display is realized.

[0259] As shown in FIG. 9D, at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure works as follows: a frame time F1 includes a reset time period SR; the display period includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5 arranged in sequence;

[0260] The first display stage S1 lasts for 38μs, the sum of the time duration of the first display stage S1 and the time duration of the second display stage S2 is 174μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2 and the time duration of the third display stage S3 is 797μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2, the time duration of the third display stage S3 and the time duration of the fourth display stage S4 is 3597μs, and the frame time F1 lasts for 16.7ms;

[0261] During the reset time period SR, the GTM provides a high voltage signal, M1 is turned on, PW is connected with VDD, M2 is turned on, the source of M0 is connected with ELVSS, and M0 drives O1 to emit light; the DTM provides a display data voltage, the voltage value of the display data voltage determines the current value of the driving current generated by M0, and the voltage value of the display data voltage is adjusted to adjust the gray level in the corresponding gray scale interval;

[0262] During the frame time F1, the DTM1 provides a -18.5V voltage signal;

[0263] During the first display stage S1, the SLM provides a -8V voltage signal, and M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0264] During the second display stage S2, the SLM provides a -11V voltage signal, and M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0265] During the third display stage S3, the SLM provides a -14V voltage signal, and M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0266] During the fourth display stage S4, the SLM provides a -17V voltage signal, and M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0267] During the fifth display stage S5, the SLM provides a -20V voltage signal, M3 is turned on, PW is connected with the SLM, M2 is turned off, and O1 does not emit light;

[0268] The light emitting time of O1 is 3597μs, the current value of the driving current of O1 is adjusted by controlling the display data voltage provided by the DTM, and 65 gray scale-127 gray scale display is realized.

[0269] As shown in FIG. 9E, at least one embodiment of the pixel circuit shown in FIG. 8 works as follows: a frame time F1 includes a reset time period SR; the display period includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5 arranged in sequence.

[0270] The first display stage S1 lasts for 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the frame time F1 lasts for 16.7ms.

[0271] In the reset time period SR, the GTM provides a high voltage signal, the M1 is turned on, the PW is connected with the VDD, the M2 is turned on, the source of the M0 is connected with the ELVSS, and the M0 drives the O1 to emit light; the DTM provides a display data voltage, the voltage value of the display data voltage determines the current value of the driving current generated by the M0, and the voltage value of the display data voltage is adjusted to adjust the gray scale level in the corresponding gray scale interval.

[0272] In the frame time F1, the DTM1 provides a -21.5V voltage signal.

[0273] In the first display stage S1, the SLM provides a -8V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0274] In the second display stage S2, the SLM provides a -11V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0275] In the third display stage S3, the SLM provides a -14V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0276] In the fourth display stage S4, the SLM provides a -17V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0277] In the fifth display stage S5, the SLM provides a -20V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light.

[0278] The light emitting time of the O1 is 16.7ms, the current value of the driving current of the O1 is adjusted by controlling the display data voltage provided by the DTM, and 128 gray scale-256 gray scale display is realized.

[0279] In at least one embodiment of the present disclosure, the number of gray scale intervals is taken as 5 for example; in specific implementation, the number of gray scale intervals can be an integer greater than 1; for example, the number of gray scale intervals can be greater than or equal to 2 and less than or equal to 4, or the number of gray scale intervals can be greater than or equal to 6. When the number of gray scale intervals decreases, the number of required driving signals decreases, and the circuit structure is simplified.

[0280] As shown in FIG. 10, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the driving circuit includes a driving transistor M0, the setting circuit includes a first transistor M1, the display control circuit includes a second transistor M2, the control data writing circuit includes a third transistor M3; the first energy storage circuit includes a first capacitor C1; the light emitting element is an organic light emitting diode O1; the first light emitting control circuit includes a tenth transistor M10;

[0281] The anode of O1 is electrically connected with a power supply voltage terminal ELVDD;

[0282] The gate of the tenth transistor M10 is electrically connected with the light emitting control line EM, the drain of the tenth transistor M10 is electrically connected with the cathode of O1, and the source of the tenth transistor M10 is electrically connected with the drain of the driving transistor M0;

[0283] The source of the driving transistor M0 is electrically connected with the drain of the second transistor M2;

[0284] The gate of the first transistor M1 is electrically connected with the scanning line GTM, the drain of the first transistor M1 is electrically connected with a high voltage terminal VDD, and the source of the first transistor M1 is electrically connected with the first control node PW;

[0285] The gate of the second transistor M2 is electrically connected with the first control node PW, and the source of the second transistor M2 is electrically connected with a low voltage terminal ELVSS;

[0286] The drain of the third transistor M3 is electrically connected with the control data line SLM, and the source of the third transistor M3 is electrically connected with the first control node PW;

[0287] The first end of the first capacitor C1 is electrically connected with the first control node PW, and the second end of the first capacitor C1 is electrically connected with the high voltage terminal VDD;

[0288] The first data writing circuit includes a fourth transistor M4, the switch control circuit includes a fifth transistor M5, and the second energy storage circuit includes a second capacitor C2;

[0289] The gate of the fourth transistor M4 is electrically connected with the scan line GTM, the drain of the fourth transistor M4 is electrically connected with the control voltage line DTM1, and the source of the fourth transistor M4 is electrically connected with the second control node NC2;

[0290] The gate of the fifth transistor M5 is electrically connected with the second control node NC2, the drain of the fifth transistor M5 is electrically connected with the control data line SLM, and the source of the fifth transistor M5 is electrically connected with the first control node PW;

[0291] The first end of the second capacitor C2 is electrically connected with the second control node NC2, and the second end of the second capacitor C2 is electrically connected with the high voltage end VDD;

[0292] The second data write circuit comprises a sixth transistor M6, and the third energy storage circuit comprises a third capacitor C3;

[0293] The gate of the sixth transistor M6 is electrically connected with the scan line GTM, the drain of the sixth transistor M6 is electrically connected with the display data line DTM, and the source of the sixth transistor M6 is electrically connected with the gate of the driving transistor M0;

[0294] The first end of the third capacitor C3 is electrically connected with the gate of M0, and the second end of the third capacitor C3 is electrically connected with the high voltage end VDD.

[0295] In at least one embodiment of the pixel circuit shown in FIG. 10, all the transistors are n-type transistors.

[0296] As shown in FIG. 11A, in at least one embodiment of the pixel circuit shown in FIG. 10, during operation, one frame time comprises a light-emitting preparation time period SZ arranged in sequence, and the light-emitting preparation time period SZ comprises a reset time period SR; one frame time comprises a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0297] During the light-emitting preparation time period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0298] During the reset time period SR, GTM provides a high voltage signal, M1 is turned on, and PW is connected with VDD; M4 is turned on, DTM1 provides a -9.5V voltage signal to NC2, SLM provides a -8V voltage signal, and M3 is turned off; M6 is turned on, and DTM provides a display data voltage to the gate of M0;

[0299] During the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, EM provides a high voltage signal, and M10 is turned on.

[0300] The first display stage S1 lasts for 38 μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597 μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4 and the duration of the fifth display stage S5 is 16.7 ms;

[0301] In one frame time, the DTM1 provides a -9.5 V voltage signal;

[0302] In the first display stage S1, the SLM provides a -8 V voltage signal, M3 is turned off, M2 is turned on, M0 drives O1 to emit light, and the light emitting time of O1 is 38 μs; by controlling the display data voltage provided by the DTM, 1 gray scale-16 gray scale adjustment can be realized;

[0303] In the second display stage S2, the SLM provides a -11 V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0304] In the third display stage S3, the SLM provides a -14 V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0305] In the fourth display stage S4, the SLM provides a -17 V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0306] In the fifth display stage S5, the SLM provides a -20 V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light.

[0307] As shown in FIG. 11B, at least one embodiment of the pixel circuit shown in FIG. 10 works as follows: one frame time includes a light emitting preparation time period SZ arranged in sequence, and the light emitting preparation time period SZ includes a reset time period SR; one frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0308] In the light emitting preparation time period SZ, the EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0309] In the reset period SR, the GTM provides a high voltage signal, the M1 is turned on, the PW is communicated with the VDD; the M4 is opened, the DTM1 provides a -12.5V voltage signal to the NC2, the SLM provides a -8V voltage signal, the M3 is turned off; the M6 is opened, the DTM provides a display data voltage to the gate of the M0;

[0310] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, the EM provides a high voltage signal, the M10 is opened;

[0311] The time duration of the first display stage S1 is 38μs, the sum of the time duration of the first display stage S1 and the time duration of the second display stage S2 is 174μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2 and the time duration of the third display stage S3 is 797μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2, the time duration of the third display stage S3 and the time duration of the fourth display stage S4 is 3597μs, and the sum of the time duration of the first display stage S1, the time duration of the second display stage S2, the time duration of the third display stage S3, the time duration of the fourth display stage S4 and the time duration of the fifth display stage S5 is 16.7ms;

[0312] In a frame time, the DTM1 provides a -12.5V voltage signal;

[0313] In the first display stage S1, the SLM provides a -8V voltage signal, the M3 is turned off; the M2 is turned on, the M0 drives the O1 to emit light;

[0314] In the second display stage S2, the SLM provides a -11V voltage signal, the M3 is turned off; the M2 is turned on, the M0 drives the O1 to emit light; the light emitting time of the O1 is 174μs, and 17 gray scale-32 gray scale adjustment can be realized by controlling the display data voltage provided by the DTM;

[0315] In the third display stage S3, the SLM provides a -14V voltage signal, the M3 is turned on, the PW is communicated with the SLM, the M2 is turned off, and the O1 does not emit light;

[0316] In the fourth display stage S4, the SLM provides a -17V voltage signal, the M3 is turned on, the PW is communicated with the SLM, the M2 is turned off, and the O1 does not emit light;

[0317] In the fifth display stage S5, the SLM provides a -20V voltage signal, the M3 is turned on, the PW is communicated with the SLM, the M2 is turned off, and the O1 does not emit light.

[0318] As shown in FIG. 11C, at least one embodiment of the pixel circuit shown in FIG. 10, when working, a frame time includes a light-emitting preparation time period SZ which is arranged in sequence and includes a reset time period SR; the frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0319] In the light-emitting preparation time period SZ, the EM provides a low voltage signal, the M10 is turned off, and the O1 does not emit light;

[0320] In the reset time period SR, the GTM provides a high voltage signal, the M1 is turned on, and the PW is connected with the VDD; the M4 is turned on, the DTM1 provides a -15.5V voltage signal to the NC2, the SLM provides a -8V voltage signal, and the M3 is turned off; the M6 is turned on, and the DTM provides a display data voltage to the gate of the M0;

[0321] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, the EM provides a high voltage signal, and the M10 is turned on;

[0322] The duration of the first display stage S1 is 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4 and the duration of the fifth display stage S5 is 16.7ms;

[0323] In a frame time, the DTM1 provides a -15.5V voltage signal;

[0324] In the first display stage S1, the SLM provides a -8V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light;

[0325] In the second display stage S2, the SLM provides a -11V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light;

[0326] In the third display stage S3, the SLM provides a -14V voltage signal, and the M3 is turned off; the M2 is turned on, and the M0 drives the O1 to emit light; the light-emitting time of the O1 is 797μs, and 33 gray scale-64 gray scale adjustment can be realized by controlling the display data voltage provided by the DTM;

[0327] In the fourth display stage S4, the SLM provides a -17V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0328] In the fifth display stage S5, the SLM provides a -20V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light.

[0329] As shown in FIG. 11D, at least one embodiment of the pixel circuit shown in FIG. 10 works as follows. A frame time includes a light-emitting preparation time period SZ, which includes a reset time period SR, arranged in sequence; a frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4, and a fifth display stage S5;

[0330] In the light-emitting preparation time period SZ, the EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0331] In the reset time period SR, the GTM provides a high voltage signal, M1 is turned on, and PW is in communication with VDD; M4 is turned on, DTM1 provides a -18.5V voltage signal to NC2, the SLM provides a -8V voltage signal, and M3 is turned off; M6 is turned on, and DTM provides a display data voltage to the gate of M0;

[0332] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, the EM provides a high voltage signal, and M10 is turned on;

[0333] The first display stage S1 lasts for 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, and the duration of the fourth display stage S4 is 3597μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4, and the duration of the fifth display stage S5 is 16.7ms;

[0334] In a frame time, DTM1 provides a -18.5V voltage signal;

[0335] In the first display stage S1, the SLM provides a -8V voltage signal, and M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0336] In the second display stage S2, the SLM provides -11V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0337] In the third display stage S3, the SLM provides -14V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0338] In the fourth display stage S4, the SLM provides -17V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light; the light emitting time of O1 is 3597μs, by controlling the display data voltage provided by the DTM, 65 gray scale-127 gray scale adjustment can be realized;

[0339] In the fifth display stage S5, the SLM provides -20V voltage signal, M3 is on, PW is communicated with the SLM, M2 is off, O1 does not emit light.

[0340] As shown in FIG. 11E, at least one embodiment of the pixel circuit shown in FIG. 10 works as follows: a frame time includes a light emitting preparation time period SZ which includes a reset time period SR, the frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0341] In the light emitting preparation time period SZ, the EM provides low voltage signal, M10 is off, O1 does not emit light;

[0342] In the reset time period SR, the GTM provides high voltage signal, M1 is on, PW is communicated with VDD; M4 is on, DTM1 provides -21.5V voltage signal to NC2, the SLM provides -8V voltage signal, M3 is off; M6 is on, the DTM provides display data voltage to the gate of M0;

[0343] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, the EM provides high voltage signal, M10 is on;

[0344] The first display stage S1 lasts for 38 μs, the sum of the time duration of the first display stage S1 and the time duration of the second display stage S2 is 174 μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2 and the time duration of the third display stage S3 is 797 μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2, the time duration of the third display stage S3 and the time duration of the fourth display stage S4 is 3597 μs, and the sum of the time duration of the first display stage S1, the time duration of the second display stage S2, the time duration of the third display stage S3, the time duration of the fourth display stage S4 and the time duration of the fifth display stage S5 is 16.7 ms;

[0345] The DTM1 provides a -21.5 V voltage signal in one frame time;

[0346] In the first display stage S1, the SLM provides a -8 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0347] In the second display stage S2, the SLM provides a -11 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0348] In the third display stage S3, the SLM provides a -14 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0349] In the fourth display stage S4, the SLM provides a -17 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0350] In the fifth display stage S5, the SLM provides a -20 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light; the light emitting time of O1 is 16.7 ms, and 128 gray scale-256 gray scale adjustment can be realized by controlling the display data voltage provided by the DTM.

[0351] As shown in FIG. 12, on the basis of at least one embodiment of the pixel circuit shown in FIG. 7, the driving circuit comprises a driving transistor M0, the setting circuit comprises a first transistor M1, the display control circuit comprises a second transistor M2, the first energy storage circuit comprises a first capacitor C1, the light emitting element is an organic light emitting diode O1, and the first light emitting control circuit comprises a tenth transistor M10.

[0352] The anode of O1 is electrically connected with a power voltage terminal ELVDD;

[0353] The gate of the tenth transistor M10 is electrically connected with the light-emitting control line EM, the drain of the tenth transistor M10 is electrically connected with the cathode of O1, and the source of the tenth transistor M10 is electrically connected with the drain of the driving transistor M0.

[0354] The gate of the first transistor M1 is electrically connected with the scan line GTM, the drain of the first transistor M1 is electrically connected with the high voltage end VDD, and the source of the first transistor M1 is electrically connected with the first control node PW;

[0355] The gate of the second transistor M2 is electrically connected with the first control node PW, and the source of the second transistor M2 is electrically connected with the low voltage end ELVSS.

[0356] The gate of M3 is electrically connected with the second control node NC2, the drain of the third transistor M3 is electrically connected with the control data line SLM, and the source of the third transistor M3 is electrically connected with the first control node PW.

[0357] The first end of the first capacitor C1 is electrically connected with the first control node PW, and the second end of the first capacitor C1 is electrically connected with the high voltage end VDD.

[0358] The first data writing circuit comprises a fourth transistor M4, the switch control circuit comprises a fifth transistor M5, and the second energy storage circuit comprises a second capacitor C2.

[0359] The gate of the fourth transistor M4 is electrically connected with the scan line GTM, the drain of the fourth transistor M4 is electrically connected with the control voltage line DTM1, and the source of the fourth transistor M4 is electrically connected with the second control node NC2.

[0360] The gate of the fifth transistor M5 is electrically connected with the second control node NC2, the drain of the fifth transistor M5 is electrically connected with the control data line SLM, and the source of the fifth transistor M5 is electrically connected with the first control node PW.

[0361] The first end of the second capacitor C2 is electrically connected with the second control node NC2, and the second end of the second capacitor C2 is electrically connected with the high voltage end VDD.

[0362] The compensation control circuit comprises a seventh transistor M7, the second data writing circuit comprises an eighth transistor M8, and the third energy storage circuit comprises a third capacitor C3.

[0363] The gate of the seventh transistor M7 is electrically connected with the scan line GTM, the drain of the seventh transistor M7 is electrically connected with the gate of the driving transistor M0, and the source of the seventh transistor M7 is electrically connected with the drain of M0.

[0364] The gate of the eighth transistor M8 is electrically connected with the scan line GTM, the drain of the eighth transistor M8 is electrically connected with the display data line DTM, and the source of the eighth transistor M8 is electrically connected with the source of the driving transistor M0;

[0365] The first end of the third capacitor C3 is electrically connected with the gate of the driving transistor M0, and the second end of the third capacitor C3 is electrically connected with the high voltage end VDD;

[0366] The reset circuit comprises a ninth transistor M9;

[0367] The gate of the ninth transistor M9 is electrically connected with the reset control line RSTM, the drain of the ninth transistor M9 is electrically connected with the high voltage end VDD, and the source of the ninth transistor M9 is electrically connected with the gate of M0;

[0368] The second light-emitting control circuit comprises an eleventh transistor M11;

[0369] The gate of the eleventh transistor M11 is electrically connected with the light-emitting control line EM, the drain of the eleventh transistor M11 is electrically connected with the source of M0, and the source of the eleventh transistor M11 is electrically connected with the drain of M2.

[0370] Optionally, the fourth voltage end can be a high voltage end.

[0371] In at least one embodiment of the pixel circuit shown in FIG. 12, all the transistors are n-type transistors.

[0372] As shown in FIG. 13A, in at least one embodiment of the pixel circuit shown in FIG. 12, when working, one frame time comprises a light-emitting preparation time period SZ arranged in sequence, the light-emitting preparation time period SZ comprises an initialization time period SC and a reset time period SR arranged in sequence; one frame time comprises a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0373] In the light-emitting preparation time period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0374] In the initialization time period SC, RSTM provides a high voltage signal, M9 is turned on, and VDD is connected with the gate of M0;

[0375] In the reset period SR, the GTM provides a high voltage signal, M1 is turned on, VDD is connected with the gate of M2; M4 is turned on, DTM1 provides a -9.5V voltage signal to NC2, SLM provides a -8V voltage signal, M3 is turned off; M7 is turned on, M6 is turned on, DTM provides a display data voltage Vdata to the source of M0, for example, Vdata is equal to 0.8V, the threshold voltage of M0 is 0.5V;

[0376] At the beginning of the reset period SR, M0 is turned on, the potential of the gate of M0 is changed until the potential of the gate of M0 becomes Vdata+Vth, M0 is turned off to perform threshold voltage compensation; the potential of the gate of M0 is 1.3V; the driving current is determined by Vdata, and the gray scale space is determined by the control voltage provided by DTM1;

[0377] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, RSTM provides a low voltage signal, and EM provides a high voltage signal, M10 is turned on;

[0378] The duration of the first display stage S1 is 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4 and the duration of the fifth display stage S5 is 16.7ms;

[0379] In a frame time, DTM1 provides a -9.5V voltage signal;

[0380] In the first display stage S1, SLM provides a -8V voltage signal, and M3 is turned off; M2 is turned on, M0 drives O1 to emit light, and the light emitting time of O1 is 38μs; by controlling the display data voltage provided by DTM, 1 gray scale-16 gray scale adjustment can be realized;

[0381] In the second display stage S2, SLM provides a -11V voltage signal, M3 is turned on, PW is connected with SLM, M2 is turned off, and O1 does not emit light;

[0382] In the third display stage S3, SLM provides a -14V voltage signal, M3 is turned on, PW is connected with SLM, M2 is turned off, and O1 does not emit light;

[0383] In the fourth display stage S4, the SLM provides a -17V voltage signal, M3 is turned on, the PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0384] In the fifth display stage S5, the SLM provides a -20V voltage signal, M3 is turned on, the PW is in communication with the SLM, M2 is turned off, and O1 does not emit light.

[0385] As shown in FIG. 13B, at least one embodiment of the pixel circuit shown in FIG. 12 works as follows. A frame time includes a light-emitting preparation time period SZ arranged in sequence, which includes an initialization time period SC and a reset time period SR arranged in sequence; a frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4, and a fifth display stage S5;

[0386] In the light-emitting preparation time period SZ, the EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0387] In the initialization time period SC, the RSTM provides a high voltage signal, M9 is turned on, and VDD is in communication with the gate of M0;

[0388] In the reset time period SR, the GTM provides a high voltage signal, M1 is turned on, and VDD is in communication with the gate of M2; M4 is turned on, DTM1 provides a -9.5V voltage signal to NC2, the SLM provides a -8V voltage signal, and M3 is turned off; M7 is turned on, M6 is turned on, DTM provides a display data voltage Vdata to the source of M0, for example, Vdata is equal to 0.8V, and the threshold voltage of M0 is 0.5V;

[0389] At the beginning of the reset time period SR, M0 is turned on, the potential of the gate of M0 is changed until the potential of the gate of M0 becomes Vdata+Vth, and M0 is turned off to perform threshold voltage compensation; the potential of the gate of M0 is 1.3V; the driving current is determined by Vdata, and the gray scale space is determined by the control voltage provided by DTM1;

[0390] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, the RSTM provides a low voltage signal, the EM provides a high voltage signal, and M10 is turned on;

[0391] The first display stage S1 lasts for 38 μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597 μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4 and the duration of the fifth display stage S5 is 16.7 ms;

[0392] In one frame time, the DTM1 provides a -12.5 V voltage signal;

[0393] In the first display stage S1, the SLM provides a -8 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0394] In the second display stage S2, the SLM provides a -11 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light; the light emitting time of O1 is 174 μs, and 17 gray scale-32 gray scale adjustment can be realized by controlling the display data voltage provided by the DTM;

[0395] In the third display stage S3, the SLM provides a -14 V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0396] In the fourth display stage S4, the SLM provides a -17 V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0397] In the fifth display stage S5, the SLM provides a -20 V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light.

[0398] As shown in FIG. 13C, at least one embodiment of the pixel circuit shown in FIG. 12 works as follows: one frame time includes a light emitting preparation time period SZ arranged in sequence, the light emitting preparation time period SZ includes an initialization time period SC and a reset time period SR arranged in sequence; one frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0399] In the light emitting preparation time period SZ, the EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0400] In the initialization period SC, the RSTM provides a high voltage signal, M9 is turned on, VDD is connected to the gate of M0;

[0401] In the reset period SR, the GTM provides a high voltage signal, M1 is turned on, VDD is connected to the gate of M2; M4 is turned on, DTM1 provides a -9.5V voltage signal to NC2, SLM provides a -8V voltage signal, M3 is turned off; M7 is turned on, M6 is turned on, DTM provides a display data voltage Vdata to the source of M0, for example, Vdata equals to 0.8V, the threshold voltage of M0 is 0.5V;

[0402] At the beginning of the reset period SR, M0 is turned on, the potential of the gate of M0 is changed until the potential of the gate of M0 becomes Vdata+Vth, M0 is turned off to perform threshold voltage compensation; the potential of the gate of M0 is 1.3V; the driving current is determined by Vdata, and the gray scale space is determined by the control voltage provided by DTM1;

[0403] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, the RSTM provides a low voltage signal, and the EM provides a high voltage signal, M10 is turned on;

[0404] The duration of the first display stage S1 is 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4 and the duration of the fifth display stage S5 is 16.7ms;

[0405] In one frame time, DTM1 provides a -15.5V voltage signal;

[0406] In the first display stage S1, SLM provides a -8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0407] In the second display stage S2, SLM provides a -11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0408] In the third display stage S3, the SLM provides a -14V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light; the light emitting time of O1 is 797μs, and 33 gray scale-64 gray scale adjustment can be realized by controlling the display data voltage provided by the DTM;

[0409] In the fourth display stage S4, the SLM provides a -17V voltage signal, M3 is on, the PW is in communication with the SLM, M2 is off, and O1 does not emit light.

[0410] In the fifth display stage S5, the SLM provides a -20V voltage signal, M3 is on, the PW is in communication with the SLM, M2 is off, and O1 does not emit light.

[0411] As shown in FIG. 13D, at least one embodiment of the pixel circuit shown in FIG. 12 works as follows: a frame time includes a light emitting preparation time period SZ arranged in sequence, the light emitting preparation time period SZ includes an initialization time period SC and a reset time period SR arranged in sequence; a frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0412] In the light emitting preparation time period SZ, the EM provides a low voltage signal, M10 is off, and O1 does not emit light.

[0413] In the initialization time period SC, the RSTM provides a high voltage signal, M9 is on, and VDD is in communication with the gate of M0.

[0414] In the reset time period SR, the GTM provides a high voltage signal, M1 is on, and VDD is in communication with the gate of M2; M4 is on, DTM1 provides a -9.5V voltage signal to NC2, the SLM provides a -8V voltage signal, and M3 is off; M7 is on, M6 is on, the DTM provides a display data voltage Vdata to the source of M0, for example, Vdata is equal to 0.8V, and the threshold voltage of M0 is 0.5V.

[0415] At the beginning of the reset time period SR, M0 is on, the potential of the gate of M0 is changed until the potential of the gate of M0 becomes Vdata+Vth, and M0 is off to perform threshold voltage compensation; the potential of the gate of M0 is 1.3V; the driving current is determined by Vdata, and the gray scale space is determined by the control voltage provided by DTM1.

[0416] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, the RSTM provides a low voltage signal, and the EM provides a high voltage signal, and M10 is on.

[0417] The first display stage S1 lasts for 38 μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797 μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597 μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4 and the duration of the fifth display stage S5 is 16.7 ms;

[0418] In one frame time, the DTM1 provides a -18.5 V voltage signal;

[0419] In the first display stage S1, the SLM provides a -8 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0420] In the second display stage S2, the SLM provides a -11 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0421] In the third display stage S3, the SLM provides a -14 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light;

[0422] In the fourth display stage S4, the SLM provides a -17 V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light; the light emitting time of O1 is 3597 μs, and 65 gray scale-127 gray scale adjustment can be realized by controlling the display data voltage provided by the DTM;

[0423] In the fifth display stage S5, the SLM provides a -20 V voltage signal, M3 is turned on, the PW is in communication with the SLM, M2 is turned off, and O1 does not emit light.

[0424] As shown in FIG. 13E, at least one embodiment of the pixel circuit shown in FIG. 12 works as follows: one frame time includes a light emitting preparation time period SZ arranged in sequence, the light emitting preparation time period SZ includes an initialization time period SC and a reset time period SR arranged in sequence; one frame time includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5;

[0425] In the light emitting preparation time period SZ, the EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0426] In the initialization time period SC, the RSTM provides a high voltage signal, M9 is turned on, and VDD is in communication with the gate of M0;

[0427] In the reset period SR, the GTM provides a high voltage signal, M1 is on, VDD is connected with the gate of M2; M4 is on, DTM1 provides a -9.5V voltage signal to NC2, SLM provides a -8V voltage signal, M3 is off; M7 is on, M6 is on, DTM provides a display data voltage Vdata to the source of M0, for example, Vdata is equal to 0.8V, the threshold voltage of M0 is 0.5V;

[0428] At the beginning of the reset period SR, M0 is on, the potential of the gate of M0 is changed until the potential of the gate of M0 becomes Vdata+Vth, M0 is off to perform threshold voltage compensation; the potential of the gate of M0 is 1.3V; the driving current is determined by Vdata, and the gray scale space is determined by the control voltage provided by DTM1;

[0429] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, the RSTM provides a low voltage signal, and the EM provides a high voltage signal, M10 is on;

[0430] The duration of the first display stage S1 is 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4 and the duration of the fifth display stage S5 is 16.7ms;

[0431] In one frame time, DTM1 provides a -21.5V voltage signal;

[0432] In the first display stage S1, SLM provides a -8V voltage signal, and M3 is off; M2 is on, and M0 drives O1 to emit light;

[0433] In the second display stage S2, SLM provides a -11V voltage signal, and M3 is off; M2 is on, and M0 drives O1 to emit light;

[0434] In the third display stage S3, SLM provides a -14V voltage signal, and M3 is off; M2 is on, and M0 drives O1 to emit light;

[0435] In the fourth display stage S4, SLM provides a -17V voltage signal, and M3 is off; M2 is on, and M0 drives O1 to emit light;

[0436] In the fifth display stage S5, the SLM provides a -20V voltage signal, M3 is turned off; M2 is turned on, M0 drives O1 to emit light; the light emitting time of O1 is 16.7ms, and 128 gray scale-256 gray scale adjustment can be realized by controlling the display data voltage provided by the DTM.

[0437] As shown in FIG. 14, based on at least one embodiment of the pixel circuit shown in FIG. 1, the driving circuit includes a driving transistor M0, the setting circuit includes a first transistor M1, the display control circuit includes a second transistor M2, and the control data writing circuit includes a third transistor M3; the first energy storage circuit includes a first capacitor C1; and the light emitting element is an organic light emitting diode O1.

[0438] The cathode of O1 is electrically connected with a low voltage end ELVSS.

[0439] The gate of the driving transistor M0 is electrically connected with the display data line, the drain of the driving transistor M0 is electrically connected with the anode of the organic light emitting diode O1, and the source of the driving transistor M0 is electrically connected with the drain of the second transistor T2.

[0440] The gate of the first transistor M1 is electrically connected with the scanning line GTM, the drain of the first transistor M1 is electrically connected with a high voltage end VDD, and the source of the first transistor M1 is electrically connected with the first control node PW.

[0441] The gate of the second transistor M2 is electrically connected with the first control node PW, and the source of the second transistor M2 is electrically connected with a power voltage end ELVDD.

[0442] The gate of the third transistor M3 is electrically connected with the control voltage line DTM1, the drain of the third transistor M3 is electrically connected with the control data line SLM, and the source of the third transistor M3 is electrically connected with the first control node PW.

[0443] The first end of the first capacitor C1 is electrically connected with the first control node PW, and the second end of the first capacitor C1 is electrically connected with a low voltage end VSS.

[0444] In at least one embodiment of the pixel circuit shown in FIG. 14, all the transistors are p-type transistors, but the present disclosure is not limited thereto.

[0445] As shown in FIG. 15A, when at least one embodiment of the pixel circuit shown in FIG. 14 is in operation, one frame time F1 includes a reset time period SR; the display period includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5 arranged in sequence;

[0446] The first display stage S1 lasts for 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the duration of one frame F1 is 16.7ms;

[0447] The first gray scale interval includes the first display stage S1, the second gray scale interval includes the first display stage S1 and the second display stage S2, the third gray scale interval includes the first display stage S1, the second display stage S2 and the third display stage S3, the fourth gray scale interval includes the first display stage S1, the second display stage S2, the third display stage S3 and the fourth display stage S4, and the fifth gray scale interval includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5;

[0448] One frame is 16.7ms, 5 gray scale intervals are set, in the first gray scale interval, the SLM provides a -8V voltage signal; in the second gray scale interval, the SLM provides a -11V voltage signal; in the third gray scale interval, the SLM provides a -14V voltage signal; in the fourth gray scale interval, the SLM provides a -17V voltage signal; and in the fifth gray scale interval, the SLM provides a -20V voltage signal;

[0449] The first display stage lasts for 38μs, corresponding to 1 gray scale-16 gray scale; the second display stage lasts for 136μs, corresponding to 17 gray scale-32 gray scale; the third display stage lasts for 623μs, corresponding to 33 gray scale-64 gray scale; the fourth gray scale interval lasts for 2800μs, corresponding to 65 gray scale-127 gray scale; and the fifth gray scale interval lasts for 13103μs, corresponding to 128-256 gray scale;

[0450] The number of display stages included in one frame F1 determines the number of gray scale intervals, and the duration of each display stage determines the corresponding number of gray scales;

[0451] In the reset time period SR, the GTM provides a high voltage signal, the M1 is turned on, the PW is connected with the VDD, the M2 is turned on, the source of the M0 is connected with the ELVSS, and the M0 drives the O1 to emit light; the DTM provides a display data voltage, the voltage value of the display driving voltage determines the current value of the driving current generated by the M0, and the voltage value of the display data voltage is adjusted to adjust the high and low gray scales in the corresponding gray scale interval;

[0452] In a frame time F1, the DTM1 provides a 9.5V voltage signal;

[0453] In the first display stage S1, the SLM provides an 8V voltage signal, the M3 is off, the M2 is on, the M0 drives the O1 to emit light, and the light emitting time of the O1 is 38μs; by controlling the display data voltage provided by the DTM, 1 gray scale-16 gray scale adjustment can be realized;

[0454] In the second display stage S2, the SLM provides an 11V voltage signal, the M3 is on, the PW is in communication with the SLM, the M2 is off, and the O1 does not emit light;

[0455] In the third display stage S3, the SLM provides a 14V voltage signal, the M3 is on, the PW is in communication with the SLM, the M2 is off, and the O1 does not emit light;

[0456] In the fourth display stage S4, the SLM provides a 17V voltage signal, the M3 is on, the PW is in communication with the SLM, the M2 is off, and the O1 does not emit light;

[0457] In the fifth display stage S5, the SLM provides a 20V voltage signal, the M3 is on, the PW is in communication with the SLM, the M2 is off, and the O1 does not emit light.

[0458] As shown in FIG. 15B, at least one embodiment of the pixel circuit shown in FIG. 14 of the present disclosure works as follows: a frame time F1 includes a reset time period SR; the display period includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5 arranged in sequence;

[0459] The time duration of the first display stage S1 is 38μs, the sum of the time duration of the first display stage S1 and the time duration of the second display stage S2 is 174μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2 and the time duration of the third display stage S3 is 797μs, the sum of the time duration of the first display stage S1, the time duration of the second display stage S2, the time duration of the third display stage S3 and the time duration of the fourth display stage S4 is 3597μs, and the time duration of the frame time F1 is 16.7ms;

[0460] In the reset time period SR, the GTM provides a high voltage signal, the M1 is on, the PW is in communication with the VDD, the M2 is on, the source of the M0 is in communication with the ELVSS, the M0 drives the O1 to emit light; the DTM provides a display data voltage, the voltage value of the display driving voltage determines the current value of the driving current generated by the M0, and by adjusting the voltage value of the display data voltage, the gray scale level in the corresponding gray scale interval is adjusted;

[0461] In a frame time F1, the DTM1 provides a 12.5V voltage signal;

[0462] In the first display stage S1, the SLM provides an 8V voltage signal, the M3 is off; the M2 is on, and the M0 drives the O1 to emit light;

[0463] In the second display stage S2, the SLM provides an 11V voltage signal, the M3 is off; the M2 is on, and the M0 drives the O1 to emit light;

[0464] In the third display stage S3, the SLM provides a 14V voltage signal, the M3 is on, the PW is in communication with the SLM, the M2 is off, and the O1 does not emit light;

[0465] In the fourth display stage S4, the SLM provides a 17V voltage signal, the M3 is on, the PW is in communication with the SLM, the M2 is off, and the O1 does not emit light;

[0466] In the fifth display stage S5, the SLM provides a 20V voltage signal, the M3 is on, the PW is in communication with the SLM, the M2 is off, and the O1 does not emit light;

[0467] The light-emitting time of the O1 is 174μs, and by controlling the display data voltage provided by the DTM, the current value of the driving current of the O1 can be adjusted to realize 17 gray scale-32 gray scale display.

[0468] As shown in FIG. 15C, at least one embodiment of the pixel circuit shown in FIG. 14 works in a frame time F1 including a reset period SR; the display period includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5 arranged in sequence;

[0469] The duration of the first display stage S1 is 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the duration of the frame time F1 is 16.7ms;

[0470] In the reset period SR, the GTM provides a high voltage signal, the M1 is on, the PW is in communication with the VDD, the M2 is on, the source of the M0 is in communication with the ELVSS, the M0 drives the O1 to emit light; the DTM provides a display data voltage, the voltage value of the display driving voltage determines the current value of the driving current generated by the M0, and by adjusting the voltage value of the display data voltage, the gray scale level in the corresponding gray scale interval is adjusted;

[0471] In a frame time F1, DTM1 provides a 15.5V voltage signal;

[0472] In the first display stage S1, SLM provides an 8V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0473] In the second display stage S2, SLM provides an 11V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0474] In the third display stage S3, SLM provides a 14V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0475] In the fourth display stage S4, SLM provides a 17V voltage signal, M3 is on, PW is connected with SLM, M2 is off, O1 does not emit light;

[0476] In the fifth display stage S5, SLM provides a 20V voltage signal, M3 is on, PW is connected with SLM, M2 is off, O1 does not emit light;

[0477] The light-emitting time of O1 is 797μs, by controlling the display data voltage provided by DTM, the current value of the driving current of O1 can be adjusted, and 33 gray scale-64 gray scale display is realized.

[0478] As shown in FIG. 15D, at least one embodiment of the pixel circuit shown in FIG. 14 works in a frame time F1 which includes a reset time period SR; the display period includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5 arranged in sequence;

[0479] The duration of the first display stage S1 is 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the duration of the frame time F1 is 16.7ms;

[0480] In the reset time period SR, GTM provides a high voltage signal, M1 is on, PW is connected with VDD, M2 is on, the source of M0 is connected with ELVSS, M0 drives O1 to emit light; DTM provides a display data voltage, the voltage value of the display driving voltage determines the current value of the driving current generated by M0, by adjusting the voltage value of the display data voltage, the gray scale high and low in the corresponding gray scale interval is adjusted;

[0481] In a frame time F1, DTM1 provides a 18.5V voltage signal;

[0482] In the first display stage S1, SLM provides an 8V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0483] In the second display stage S2, SLM provides an 11V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0484] In the third display stage S3, SLM provides an 14V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0485] In the fourth display stage S4, SLM provides an 17V voltage signal, M3 is off; M2 is on, M0 drives O1 to emit light;

[0486] In the fifth display stage S5, SLM provides an 20V voltage signal, M3 is on, PW is connected with SLM, M2 is off, O1 does not emit light;

[0487] The light emitting time of O1 is 3597μs, by controlling the display data voltage provided by DTM, the current value of the driving current of O1 can be adjusted, and 65 gray scale-127 gray scale display is realized.

[0488] As shown in FIG. 15E, at least one embodiment of the pixel circuit shown in FIG. 14 works in a frame time F1, which includes a reset time period SR; the display period includes the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5 arranged in sequence;

[0489] The duration of the first display stage S1 is 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2 and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3 and the duration of the fourth display stage S4 is 3597μs, and the duration of the frame time F1 is 16.7ms;

[0490] In the reset time period SR, GTM provides a high voltage signal, M1 is on, PW is connected with VDD, M2 is on, the source of M0 is connected with ELVSS, M0 drives O1 to emit light; DTM provides a display data voltage, the voltage value of the display driving voltage determines the current value of the driving current generated by M0, by adjusting the voltage value of the display data voltage, the gray scale high and low in the corresponding gray scale interval is adjusted;

[0491] In a frame time F1, the DTM1 provides a 21.5V voltage signal;

[0492] In a first display stage S1, the SLM provides an 8V voltage signal, the M3 is off; the M2 is on, and the M0 drives the O1 to emit light;

[0493] In a second display stage S2, the SLM provides an 11V voltage signal, the M3 is off; the M2 is on, and the M0 drives the O1 to emit light;

[0494] In a third display stage S3, the SLM provides a 14V voltage signal, the M3 is off; the M2 is on, and the M0 drives the O1 to emit light;

[0495] In a fourth display stage S4, the SLM provides a 17V voltage signal, the M3 is off; the M2 is on, and the M0 drives the O1 to emit light;

[0496] In a fifth display stage S5, the SLM provides a 20V voltage signal, the M3 is off; the M2 is on, and the M0 drives the O1 to emit light;

[0497] The light emitting time of the O1 is 16.7ms, by controlling the display data voltage provided by the DTM, the current value of the driving current of the O1 can be adjusted, and 128 gray scale-256 gray scale display is realized.

[0498] As shown in Figure 16, on the basis of at least one embodiment of the pixel circuit shown in Figure 6, the driving circuit includes a driving transistor M0, the setting circuit includes a first transistor M1, the display control circuit includes a second transistor M2, the control data writing circuit includes a third transistor M3; the first energy storage circuit includes a first capacitor C1; the light emitting element is an organic light emitting diode O1; the first light emitting control circuit includes a tenth transistor M10;

[0499] The cathode of the O1 is electrically connected with a low voltage end ELVSS;

[0500] The gate of the tenth transistor M10 is electrically connected with the light emitting control line EM, the drain of the tenth transistor M10 is electrically connected with the anode of the O1, and the source of the tenth transistor M10 is electrically connected with the drain of the driving transistor M0;

[0501] The source of the driving transistor M0 is electrically connected with the drain of the second transistor M2;

[0502] The gate of the first transistor M1 is electrically connected with the scanning line GTM, the drain of the first transistor M1 is electrically connected with a low level VSS, and the source of the first transistor M1 is electrically connected with the first control node PW;

[0503] The gate of the second transistor M2 is electrically connected with the first control node PW, and the source of the second transistor M2 is electrically connected with the power voltage terminal ELVDD;

[0504] The drain of the third transistor M3 is electrically connected with the control data line SLM, and the source of the third transistor M3 is electrically connected with the first control node PW;

[0505] The first end of the first capacitor C1 is electrically connected with the first control node PW, and the second end of the first capacitor C1 is electrically connected with the high voltage terminal VDD;

[0506] The first data write circuit comprises a fourth transistor M4, the switch control circuit comprises a fifth transistor M5, and the second energy storage circuit comprises a second capacitor C2;

[0507] The gate of the fourth transistor M4 is electrically connected with the scan line GTM, the drain of the fourth transistor M4 is electrically connected with the control voltage line DTM1, and the source of the fourth transistor M4 is electrically connected with the second control node NC2;

[0508] The gate of the fifth transistor M5 is electrically connected with the second control node NC2, the drain of the fifth transistor M5 is electrically connected with the control data line SLM, and the source of the fifth transistor M5 is electrically connected with the first control node PW;

[0509] The first end of the second capacitor C2 is electrically connected with the second control node NC2, and the second end of the second capacitor C2 is electrically connected with the high voltage terminal VDD;

[0510] The second data write circuit comprises a sixth transistor M6, and the third energy storage circuit comprises a third capacitor C3;

[0511] The gate of the sixth transistor M6 is electrically connected with the scan line GTM, the drain of the sixth transistor M6 is electrically connected with the display data line DTM, and the source of the sixth transistor M6 is electrically connected with the gate of the driving transistor M0;

[0512] The first end of the third capacitor C3 is electrically connected with the gate of M0, and the second end of the third capacitor C3 is electrically connected with the high voltage terminal VDD.

[0513] In at least one embodiment of the pixel circuit shown in FIG. 16, all the transistors are p-type transistors.

[0514] As shown in Figure 17A, when at least one embodiment of the pixel circuit shown in Figure 16 is working, a frame time F1 includes a sequentially set light emission preparation time period SZ, the light emission preparation time period SZ includes a reset time period SR; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0515] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0516] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and PW is connected to VDD; M4 is turned on, DTM1 provides a 9.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M6 is turned on, and DTM provides the display data voltage to the gate of M0.

[0517] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, EM provides a high voltage signal and M10 is turned on;

[0518] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0519] Within one frame time F1, DTM1 provides a 9.5V voltage signal;

[0520] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light. The light emission time of O1 is 38μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 1 to 16 grayscale levels can be achieved.

[0521] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0522] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0523] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light;

[0524] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is in communication with the SLM, M2 is turned off, and O1 does not emit light.

[0525] As shown in FIG. 17B, at least one embodiment of the pixel circuit shown in FIG. 16 works as follows. A frame time F1 includes a light-emitting preparation time period SZ, which includes a reset time period SR, arranged in sequence; the frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4, and a fifth display stage S5;

[0526] In the light-emitting preparation time period SZ, the EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0527] In the reset time period SR, the GTM provides a high voltage signal, M1 is turned on, and PW is in communication with VDD; M4 is turned on, DTM1 provides a 12.5V voltage signal to NC2, the SLM provides an 8V voltage signal, and M3 is turned off; M6 is turned on, and DTM provides a display data voltage to the gate of M0;

[0528] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, the EM provides a high voltage signal, and M10 is turned on;

[0529] The first display stage S1 lasts for 38μs, the sum of the duration of the first display stage S1 and the duration of the second display stage S2 is 174μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, and the duration of the third display stage S3 is 797μs, the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, and the duration of the fourth display stage S4 is 3597μs, and the sum of the duration of the first display stage S1, the duration of the second display stage S2, the duration of the third display stage S3, the duration of the fourth display stage S4, and the duration of the fifth display stage S5 is 16.7ms;

[0530] In the frame time F1, DTM1 provides a 12.5V voltage signal;

[0531] In the first display stage S1, the SLM provides an 8V voltage signal, and M3 is turned off; M2 is turned on, and M0 drives O1 to emit light;

[0532] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 174μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 17 to 32 can be achieved.

[0533] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0534] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0535] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0536] As shown in Figure 11C, when at least one embodiment of the pixel circuit shown in Figure 10 is working, a frame time F1 includes a sequentially set light emission preparation time period SZ, the light emission preparation time period SZ includes a reset time period SR; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0537] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0538] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and PW is connected to VDD; M4 is turned on, DTM1 provides a 15.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M6 is turned on, and DTM provides the display data voltage to the gate of M0.

[0539] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, EM provides a high voltage signal and M10 is turned on;

[0540] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0541] Within one frame time F1, DTM1 provides a 15.5V voltage signal;

[0542] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0543] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0544] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 797μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 33 to 64 can be achieved.

[0545] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0546] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0547] As shown in Figure 17D, when at least one embodiment of the pixel circuit shown in Figure 16 is working, a frame time F1 includes a sequentially set light emission preparation time period SZ, the light emission preparation time period SZ includes a reset time period SR; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0548] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0549] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and PW is connected to VDD; M4 is turned on, DTM1 provides an 18.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M6 is turned on, and DTM provides the display data voltage to the gate of M0.

[0550] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, EM provides a high voltage signal and M10 is turned on;

[0551] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0552] Within one frame time F1, DTM1 provides an 18.5V voltage signal;

[0553] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0554] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0555] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0556] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 3597μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 65 to 127 can be achieved.

[0557] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0558] As shown in Figure 17E, when at least one embodiment of the pixel circuit shown in Figure 16 is working, a frame time F1 includes a sequentially set light emission preparation time period SZ, the light emission preparation time period SZ includes a reset time period SR; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0559] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0560] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and PW is connected to VDD; M4 is turned on, DTM1 provides a 21.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M6 is turned on, and DTM provides the display data voltage to the gate of M0.

[0561] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4 and the fifth display stage S5, EM provides a high voltage signal and M10 is turned on;

[0562] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0563] Within one frame time F1, DTM1 provides a 21.5V voltage signal;

[0564] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0565] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0566] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0567] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0568] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 16.7ms. By controlling the display data voltage provided by the DTM, the grayscale adjustment from 128 to 256 can be achieved.

[0569] As shown in Figure 18, based on at least one embodiment of the pixel circuit shown in Figure 7, the driving circuit includes a driving transistor M0, the setting circuit includes a first transistor M1, the display control circuit includes a second transistor M2, and the control data writing circuit includes a third transistor M3; the first energy storage circuit includes a first capacitor C1; the light-emitting element is an organic light-emitting diode O1; and the first light-emitting control circuit includes a tenth transistor M10.

[0570] The cathode of O1 is electrically connected to the low-voltage terminal ELVSS;

[0571] The gate of the tenth transistor M10 is electrically connected to the light-emitting control line EM, the drain of the tenth transistor M10 is electrically connected to the anode of O1, and the source of the tenth transistor M10 is electrically connected to the drain of the driving transistor M0.

[0572] The gate of the first transistor M1 is electrically connected to the scan line GTM, the drain of the first transistor M1 is electrically connected to the low-level terminal VSS, and the source of the first transistor M1 is electrically connected to the first control node PW.

[0573] The gate of the second transistor M2 is electrically connected to the first control node PW, and the source of the second transistor M2 is electrically connected to the power supply voltage terminal ELVDD.

[0574] The drain of the third transistor M3 is electrically connected to the control data line SLM, and the source of the third transistor M3 is electrically connected to the first control node PW.

[0575] The first terminal of the first capacitor C1 is electrically connected to the first control node PW, and the second terminal of the first capacitor C1 is electrically connected to the high voltage terminal VDD.

[0576] The first data writing circuit includes a fourth transistor M4, the switch control circuit includes a fifth transistor M5, and the second energy storage circuit includes a second capacitor C2.

[0577] The gate of the fourth transistor M4 is electrically connected to the scan line GTM, the drain of the fourth transistor M4 is electrically connected to the control voltage line DTM1, and the source of the fourth transistor M4 is electrically connected to the second control node NC2.

[0578] The gate of the fifth transistor M5 is electrically connected to the second control node NC2, the drain of the fifth transistor M5 is electrically connected to the control data line SLM, and the source of the fifth transistor M5 is electrically connected to the first control node PW.

[0579] The first terminal of the second capacitor C2 is electrically connected to the second control node NC2, and the second terminal of the second capacitor C2 is electrically connected to the high voltage terminal VDD.

[0580] The compensation control circuit includes a seventh transistor M7, the second data writing circuit includes an eighth transistor M8, and the third energy storage circuit includes a third capacitor C3.

[0581] The gate of the seventh transistor M7 is electrically connected to the scan line GTM, the drain of the seventh transistor M7 is electrically connected to the gate of the driving transistor M0, and the source of the seventh transistor M7 is electrically connected to the drain of M0.

[0582] The gate of the eighth transistor M8 is electrically connected to the scan line GTM, the drain of the eighth transistor M8 is electrically connected to the display data line DTM, and the source of the eighth transistor M8 is electrically connected to the source of the driving transistor M0.

[0583] The first terminal of the third capacitor C3 is electrically connected to the gate of the driving transistor M0, and the second terminal of the third capacitor C3 is electrically connected to the high voltage terminal VDD.

[0584] The reset circuit includes a ninth transistor M9;

[0585] The gate of the ninth transistor M9 is electrically connected to the reset control line RSTM, the drain of the ninth transistor M9 is electrically connected to the low-level terminal VSS, and the source of the ninth transistor M9 is electrically connected to the gate of M0.

[0586] The second light-emitting control circuit includes an eleventh transistor M11;

[0587] The gate of the eleventh transistor M11 is electrically connected to the light-emitting control line EM, the drain of the eleventh transistor M11 is electrically connected to the source of M0, and the source of the eleventh transistor M11 is electrically connected to the drain of M2.

[0588] Optionally, the fourth voltage terminal can be a high voltage terminal.

[0589] In at least one embodiment of the pixel circuit shown in Figure 18, all transistors are n-type transistors.

[0590] As shown in Figure 19A, when at least one embodiment of the pixel circuit shown in Figure 18 is working, a frame time F1 includes a light-emitting preparation time period SZ set sequentially, the light-emitting preparation time period SZ includes an initialization time period SC and a reset time period SR set sequentially; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0591] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0592] During the initialization period SC, RSTM provides a high voltage signal, M9 is turned on, and the gates of VDD and M0 are connected;

[0593] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and the gates of VDD and M2 are connected; M4 is turned on, DTM1 provides a 9.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M7 is turned on, M6 is turned on, DTM provides the display data voltage Vdata to the source of M0, for example, Vdata equals 0.8V, and the threshold voltage of M0 is 0.5V;

[0594] At the start of the reset period SR, M0 is turned on, changing the potential of M0's gate until the gate potential of M0 becomes Vdata+Vth, at which point M0 is turned off to perform threshold voltage compensation; the potential of M0's gate is 1.3V; the drive current is determined by Vdata, and the grayscale space is determined by the control voltage provided by DTM1.

[0595] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, RSTM provides a low voltage signal, EM provides a high voltage signal, and M10 is turned on.

[0596] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0597] Within one frame time F1, DTM1 provides a 9.5V voltage signal;

[0598] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off, M2 is turned on, and M0 drives O1 to emit light. The light emission time of O1 is 38μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 1 to 16 grayscale levels can be achieved.

[0599] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0600] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0601] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0602] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0603] As shown in Figure 19B, when at least one embodiment of the pixel circuit shown in Figure 18 is working, a frame time F1 includes a light-emitting preparation time period SZ set sequentially, the light-emitting preparation time period SZ includes an initialization time period SC and a reset time period SR set sequentially; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0604] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0605] During the initialization period SC, RSTM provides a high voltage signal, M9 is turned on, and the gates of VDD and M0 are connected;

[0606] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and the gates of VDD and M2 are connected; M4 is turned on, DTM1 provides a 9.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M7 is turned on, M6 is turned on, DTM provides the display data voltage Vdata to the source of M0, for example, Vdata equals 0.8V, and the threshold voltage of M0 is 0.5V;

[0607] At the start of the reset period SR, M0 is turned on, changing the potential of M0's gate until the gate potential of M0 becomes Vdata+Vth, at which point M0 is turned off to perform threshold voltage compensation; the potential of M0's gate is 1.3V; the drive current is determined by Vdata, and the grayscale space is determined by the control voltage provided by DTM1.

[0608] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, RSTM provides a low voltage signal, EM provides a high voltage signal, and M10 is turned on.

[0609] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0610] Within one frame time F1, DTM1 provides a 12.5V voltage signal;

[0611] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0612] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 174μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 17 to 32 can be achieved.

[0613] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0614] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0615] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0616] As shown in Figure 19C, when at least one embodiment of the pixel circuit shown in Figure 18 is working, a frame time F1 includes a light-emitting preparation time period SZ set sequentially, the light-emitting preparation time period SZ includes an initialization time period SC and a reset time period SR set sequentially; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0617] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0618] During the initialization period SC, RSTM provides a high voltage signal, M9 is turned on, and the gates of VDD and M0 are connected;

[0619] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and the gates of VDD and M2 are connected; M4 is turned on, DTM1 provides a 9.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M7 is turned on, M6 is turned on, DTM provides the display data voltage Vdata to the source of M0, for example, Vdata equals 0.8V, and the threshold voltage of M0 is 0.5V;

[0620] At the start of the reset period SR, M0 is turned on, changing the potential of M0's gate until the gate potential of M0 becomes Vdata+Vth, at which point M0 is turned off to perform threshold voltage compensation; the potential of M0's gate is 1.3V; the drive current is determined by Vdata, and the grayscale space is determined by the control voltage provided by DTM1.

[0621] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, RSTM provides a low voltage signal, EM provides a high voltage signal, and M10 is turned on.

[0622] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0623] Within one frame time F1, DTM1 provides a 15.5V voltage signal;

[0624] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0625] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0626] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 797μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 33 to 64 can be achieved.

[0627] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0628] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0629] As shown in Figure 19D, when at least one embodiment of the pixel circuit shown in Figure 18 is working, a frame time F1 includes a light-emitting preparation time period SZ set sequentially, the light-emitting preparation time period SZ includes an initialization time period SC and a reset time period SR set sequentially; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0630] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0631] During the initialization period SC, RSTM provides a high voltage signal, M9 is turned on, and the gates of VDD and M0 are connected;

[0632] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and the gates of VDD and M2 are connected; M4 is turned on, DTM1 provides a 9.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M7 is turned on, M6 is turned on, DTM provides the display data voltage Vdata to the source of M0, for example, Vdata equals 0.8V, and the threshold voltage of M0 is 0.5V;

[0633] At the start of the reset period SR, M0 is turned on, changing the potential of M0's gate until the gate potential of M0 becomes Vdata+Vth, at which point M0 is turned off to perform threshold voltage compensation; the potential of M0's gate is 1.3V; the drive current is determined by Vdata, and the grayscale space is determined by the control voltage provided by DTM1.

[0634] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, RSTM provides a low voltage signal, EM provides a high voltage signal, and M10 is turned on.

[0635] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0636] Within one frame time F1, DTM1 provides an 18.5V voltage signal;

[0637] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0638] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0639] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0640] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 3597μs. By controlling the display data voltage provided by the DTM, grayscale adjustment from 65 to 127 can be achieved.

[0641] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned on, PW is connected to the SLM, M2 is turned off, and O1 does not emit light.

[0642] As shown in Figure 19E, when at least one embodiment of the pixel circuit shown in Figure 18 is working, a frame time F1 includes a light-emitting preparation time period SZ set sequentially, the light-emitting preparation time period SZ includes an initialization time period SC and a reset time period SR set sequentially; a frame time F1 includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4 and a fifth display stage S5.

[0643] During the light emission preparation period SZ, EM provides a low voltage signal, M10 is turned off, and O1 does not emit light;

[0644] During the initialization period SC, RSTM provides a high voltage signal, M9 is turned on, and the gates of VDD and M0 are connected;

[0645] During the reset period SR, GTM provides a high voltage signal, M1 is turned on, and the gates of VDD and M2 are connected; M4 is turned on, DTM1 provides a 9.5V voltage signal to NC2, SLM provides an 8V voltage signal, and M3 is turned off; M7 is turned on, M6 is turned on, DTM provides the display data voltage Vdata to the source of M0, for example, Vdata equals 0.8V, and the threshold voltage of M0 is 0.5V;

[0646] At the start of the reset period SR, M0 is turned on, changing the potential of M0's gate until the gate potential of M0 becomes Vdata+Vth, at which point M0 is turned off to perform threshold voltage compensation; the potential of M0's gate is 1.3V; the drive current is determined by Vdata, and the grayscale space is determined by the control voltage provided by DTM1.

[0647] In the first display stage S1, the second display stage S2, the third display stage S3, the fourth display stage S4, and the fifth display stage S5, RSTM provides a low voltage signal, EM provides a high voltage signal, and M10 is turned on.

[0648] The duration of the first display phase S1 is 38 μs. The sum of the durations of the first display phase S1 and the second display phase S2 is 174 μs. The sum of the durations of the first display phase S1, the second display phase S2, and the third display phase S3 is 797 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, and the fourth display phase S4 is 3597 μs. The sum of the durations of the first display phase S1, the second display phase S2, the third display phase S3, the fourth display phase S4, and the fifth display phase S5 is 16.7 ms.

[0649] Within one frame time F1, DTM1 provides a 21.5V voltage signal;

[0650] In the first display stage S1, the SLM provides an 8V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0651] In the second display stage S2, the SLM provides an 11V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0652] In the third display stage S3, the SLM provides a 14V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0653] In the fourth display stage S4, the SLM provides a 17V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light.

[0654] In the fifth display stage S5, the SLM provides a 20V voltage signal, M3 is turned off; M2 is turned on, and M0 drives O1 to emit light; the light emission time of O1 is 16.7ms. By controlling the display data voltage provided by the DTM, the grayscale adjustment from 128 to 256 can be achieved.

[0655] The pixel driving method described in this embodiment is applied to the pixel circuit described above; the display period includes a reset time period; the pixel driving method includes:

[0656] During the reset period, the set circuit, under the control of the scan signal, controls the connection between the third voltage terminal and the first control node, and the display control circuit, under the control of the potential of the first control node, controls the connection between the second terminal of the drive circuit and the second voltage terminal.

[0657] During the display cycle, the driving circuit generates a driving current for the light-emitting element under the control of the display data voltage; the control data writing circuit controls the connection or disconnection between the first control node and the control data line under the control of the control voltage; when the control data writing circuit controls the connection between the first control node and the control data line, the display control circuit controls the disconnection between the second terminal of the driving circuit and the second voltage terminal under the control of the potential of the first control node.

[0658] In at least one embodiment of this disclosure, the display cycle includes N display stages; N is an integer greater than 1.

[0659] The pixel driving method includes:

[0660] During the nth display cycle, the control data line provides the nth control data voltage; n is a positive integer less than or equal to N;

[0661] The duration of the m-th display cycle is less than the duration of the (m+1)-th display cycle; m is a positive integer less than N.

[0662] The display device described in this disclosure includes the pixel circuit described above.

[0663] The display device described in at least one embodiment of this disclosure further includes multiple rows of control data lines and multiple data voltage supply circuits;

[0664] The data voltage supply circuit is electrically connected to the control data line and is used to provide control data voltage to the control data line.

[0665] As shown in Figure 20, the line labeled SLM is the control data line, and the line labeled 200 is the data voltage supply circuit. The data voltage supply circuit 200 is electrically connected to the control data line SLM and is used to provide control data voltage to the control data line SLM.

[0666] In at least one embodiment of this disclosure, the data voltage providing circuit includes N data providing units; N is an integer greater than 1; m is a positive integer less than N;

[0667] The m-th data providing unit includes the m-th reset unit, the m-th control unit, the m-th providing unit, and the m-th energy storage unit;

[0668] The m-th reset unit is electrically connected to the initial control line, the fifth voltage terminal, and the m-th node, respectively, and is used to connect or disconnect the fifth voltage terminal and the m-th node under the control of the initial control signal provided by the initial control line.

[0669] The m-th control unit is electrically connected to the m-th node, the m-th control terminal, the m+1-th control terminal, the sixth voltage terminal, and the seventh voltage terminal, respectively. It is used to control the connection or disconnection between the m-th node and the sixth voltage terminal under the control of the m-th control signal provided by the m-th control terminal, and to control the connection or disconnection between the m-th node and the seventh voltage terminal under the control of the m+1-th control signal provided by the m+1-th control terminal.

[0670] The m-th providing unit is electrically connected to the m-th node, the m-th data voltage terminal, and the control data line, respectively, and is used to control the connection or disconnection between the m-th data voltage terminal and the control data line under the control of the potential of the m-th node;

[0671] The m-th energy storage unit is electrically connected to the m-th node and is used to maintain the potential of the m-th node;

[0672] The Nth data providing unit includes the Nth reset unit, the Nth control unit, the Nth providing unit, and the Nth energy storage unit;

[0673] The Nth reset unit is electrically connected to the initial control line, the eighth voltage terminal and the Nth node respectively, and is used to connect or disconnect the eighth voltage terminal and the Nth node under the control of the initial control signal provided by the initial control line.

[0674] The Nth control unit is electrically connected to the Nth node, the Nth control terminal, the first control terminal, the sixth voltage terminal, and the seventh voltage terminal, respectively, and is used to control the connection or disconnection between the Nth node and the sixth voltage terminal under the control of the Nth control signal provided by the Nth control terminal, and to control the connection or disconnection between the Nth node and the seventh voltage terminal under the control of the first control signal provided by the first control terminal.

[0675] The Nth providing unit is electrically connected to the Nth node, the Nth data voltage terminal and the control data line respectively, and is used to control the connection or disconnection between the Nth data voltage terminal and the control data line under the control of the potential of the Nth node;

[0676] The Nth energy storage unit is electrically connected to the Nth node and is used to maintain the potential of the Nth node.

[0677] In at least one embodiment of this disclosure, N equals 5 as an example.

[0678] As shown in Figure 21, the data voltage providing circuit includes a first data providing unit, a second data providing unit, a third data providing unit, a fourth data providing unit, and a fifth data providing unit;

[0679] The first data providing unit includes a first reset unit 111, a first control unit 112, a first providing unit 113, and a first energy storage unit 114;

[0680] The first reset unit 111 is electrically connected to the initial control line RST, the fifth voltage terminal V5 and the first node Q1 respectively, and is used to connect or disconnect the fifth voltage terminal V5 and the first node Q1 under the control of the initial control signal provided by the initial control line RST.

[0681] The first control unit 112 is electrically connected to the first node Q1, the first control terminal G1, the second control terminal G2, the sixth voltage terminal V6, and the seventh voltage terminal V7, respectively. It is used to control the connection or disconnection between the first node Q1 and the sixth voltage terminal V6 under the control of the first control signal provided by the first control terminal G1, and to control the connection or disconnection between the first node Q1 and the seventh voltage terminal V7 under the control of the second control signal provided by the second control terminal G2.

[0682] The first providing unit 113 is electrically connected to the first node Q1, the first data voltage terminal D1 and the control data line SLM respectively, and is used to control the connection or disconnection between the first data voltage terminal D1 and the control data line SLM under the control of the potential of the first node Q1.

[0683] The first energy storage unit 114 is electrically connected to the first node Q1 and is used to maintain the potential of the first node Q1;

[0684] The second data providing unit includes a second reset unit 121, a second control unit 122, a second providing unit 123, and a second energy storage unit 124;

[0685] The second reset unit 121 is electrically connected to the initial control line RST, the fifth voltage terminal V5, and the second node Q2, respectively, and is used to connect or disconnect the fifth voltage terminal V5 and the second node Q2 under the control of the initial control signal provided by the initial control line RST.

[0686] The second control unit 122 is electrically connected to the second node Q2, the second control terminal G2, the third control terminal G3, the sixth voltage terminal V6, and the seventh voltage terminal V7, respectively. It is used to control the connection or disconnection between the second node Q2 and the sixth voltage terminal V6 under the control of the second control signal provided by the second control terminal G2, and to control the connection or disconnection between the second node Q2 and the seventh voltage terminal V7 under the control of the third control signal provided by the third control terminal G3.

[0687] The second providing unit 123 is electrically connected to the second node Q2, the second data voltage terminal D2 and the control data line SLM respectively, and is used to control the connection or disconnection between the second data voltage terminal D2 and the control data line SLM under the control of the potential of the second node Q2;

[0688] The second energy storage unit 124 is electrically connected to the second node Q2 to maintain the potential of the second node Q2;

[0689] The third data providing unit includes a third reset unit 131, a third control unit 132, a third providing unit 133, and a third energy storage unit 134;

[0690] The third reset unit 131 is electrically connected to the initial control line RST, the fifth voltage terminal V5 and the third node Q3 respectively, and is used to connect or disconnect the fifth voltage terminal V5 and the third node Q3 under the control of the initial control signal provided by the initial control line RST.

[0691] The third control unit 132 is electrically connected to the third node Q3, the third control terminal G3, the fourth control terminal G4, the fifth voltage terminal V5, and the sixth voltage terminal V6, respectively. It is used to control the connection or disconnection between the third node Q3 and the sixth voltage terminal V6 under the control of the third control signal provided by the third control terminal G3, and to control the connection or disconnection between the third node Q3 and the seventh voltage terminal V7 under the control of the fourth control signal provided by the fourth control terminal G4.

[0692] The third providing unit 133 is electrically connected to the third node Q3, the third data voltage terminal D3 and the control data line SLM respectively, and is used to control the connection or disconnection between the third data voltage terminal D3 and the control data line SLM under the control of the potential of the third node Q3.

[0693] The third energy storage unit 134 is electrically connected to the third node Q3 and is used to maintain the potential of the third node Q3;

[0694] The fourth data providing unit includes a fourth reset unit 141, a fourth control unit 142, a fourth providing unit 143, and a fourth energy storage unit 144;

[0695] The fourth reset unit 141 is electrically connected to the initial control line RST, the fifth voltage terminal V5 and the fourth node Q4 respectively, and is used to connect or disconnect the fifth voltage terminal V5 and the fourth node Q4 under the control of the initial control signal provided by the initial control line RST.

[0696] The fourth control unit 142 is electrically connected to the fourth node Q4, the fourth control terminal G4, the fifth control terminal G5, the sixth voltage terminal V6, and the seventh voltage terminal V7, respectively. It is used to control the connection or disconnection between the fourth node Q4 and the sixth voltage terminal V6 under the control of the fourth control signal provided by the fourth control terminal G4, and to control the connection or disconnection between the fourth node Q4 and the seventh voltage terminal V7 under the control of the fifth control signal provided by the fifth control terminal G5.

[0697] The fourth providing unit 143 is electrically connected to the fourth node Q4, the fourth data voltage terminal D4 and the control data line SLM respectively, and is used to control the connection or disconnection between the fourth data voltage terminal D4 and the control data line SLM under the control of the potential of the fourth node Q4.

[0698] The fourth energy storage unit 144 is electrically connected to the fourth node Q4 and is used to maintain the potential of the fourth node Q4;

[0699] The fifth data providing unit includes a fifth reset unit 151, a fifth control unit 152, a fifth providing unit 153, and a fifth energy storage unit 154;

[0700] The fifth reset unit 151 is electrically connected to the initial control line RST, the eighth voltage terminal V8 and the fifth node Q5 respectively, and is used to connect or disconnect the eighth voltage terminal V8 and the fifth node Q5 under the control of the initial control signal provided by the initial control line RST.

[0701] The fifth control unit 152 is electrically connected to the fifth node Q5, the fifth control terminal G5, the first control terminal G1, the sixth voltage terminal V6, and the seventh voltage terminal V7, respectively. It is used to control the connection or disconnection between the fifth node Q5 and the sixth voltage terminal V6 under the control of the fifth control signal provided by the fifth control terminal G5, and to control the connection or disconnection between the fifth node Q5 and the seventh voltage terminal V7 under the control of the first control signal provided by the first control terminal G1.

[0702] The fifth providing unit 153 is electrically connected to the fifth node Q5, the fifth data voltage terminal D5 and the control data line SLM respectively, and is used to control the connection or disconnection between the fifth data voltage terminal D5 and the control data line SLM under the control of the potential of the fifth node Q5.

[0703] The fifth energy storage unit 154 is electrically connected to the fifth node Q5 and is used to maintain the potential of the fifth node Q5.

[0704] Optionally, the m-th reset unit includes the m-th reset transistor, the m-th control unit includes the m-th first control transistor and the m-th second control transistor, the m-th providing unit includes the m-th providing transistor, and the m-th energy storage unit includes the m-th storage capacitor;

[0705] The gate of the m-th reset transistor is electrically connected to the initial control line, the first terminal of the m-th reset transistor is electrically connected to the fifth voltage terminal, and the second terminal of the m-th reset transistor is electrically connected to the m-th node.

[0706] The gate of the m-th first control transistor is electrically connected to the m-th control terminal, the first electrode of the m-th first control transistor is electrically connected to the sixth voltage terminal, and the second electrode of the m-th first control transistor is electrically connected to the m-th node.

[0707] The gate of the m-th second control transistor is electrically connected to the (m+1)-th control terminal, the first terminal of the m-th second control transistor is electrically connected to the m-th node, and the second terminal of the m-th second control transistor is electrically connected to the seventh voltage terminal.

[0708] The gate of the m-th transistor is electrically connected to the m-th node, the first terminal of the m-th transistor is electrically connected to the m-th data voltage terminal, and the second terminal of the m-th transistor is electrically connected to the control data line.

[0709] The first end of the m-th storage capacitor is electrically connected to the m-th node, and the second end of the m-th storage capacitor is electrically connected to the DC voltage terminal.

[0710] Optionally, the Nth reset unit includes an Nth reset transistor, the Nth control unit includes an Nth first control transistor and an Nth second control transistor, the Nth providing unit includes an Nth providing transistor, and the Nth energy storage unit includes an Nth storage capacitor;

[0711] The gate of the Nth reset transistor is electrically connected to the initial control line, the first terminal of the Nth reset transistor is electrically connected to the eighth voltage terminal, and the second terminal of the Nth reset transistor is electrically connected to the Nth node.

[0712] The gate of the Nth first control transistor is electrically connected to the Nth control terminal, the first electrode of the Nth first control transistor is electrically connected to the sixth voltage terminal, and the second electrode of the Nth first control transistor is electrically connected to the Nth node.

[0713] The gate of the Nth second control transistor is electrically connected to the N+1th control terminal, the first terminal of the Nth second control transistor is electrically connected to the Nth node, and the second terminal of the Nth second control transistor is electrically connected to the seventh voltage terminal.

[0714] The gate of the Nth transistor is electrically connected to the Nth node, the first terminal of the Nth transistor is electrically connected to the Nth data voltage terminal, and the second terminal of the Nth transistor is electrically connected to the control data line.

[0715] The first end of the Nth storage capacitor is electrically connected to the Nth node, and the second end of the Nth storage capacitor is electrically connected to the DC voltage terminal.

[0716] As shown in Figure 22, based on at least one embodiment of the data voltage supply circuit shown in Figure 21,

[0717] The first reset unit includes a first reset transistor TR1; the first control unit includes a first first control transistor TC11 and a first second control transistor TC12; the first supply unit includes a first supply transistor TP1; and the first energy storage unit includes a first storage capacitor Cst1.

[0718] The gate of the first reset transistor TR1 is electrically connected to the initial control line RST, the drain of the first reset transistor TR1 is electrically connected to the low voltage signal terminal VSSN, and the source of the first reset transistor TR1 is electrically connected to the first node Q1.

[0719] The gate of the first control transistor TC11 is electrically connected to the first control terminal G1, the drain of the first control transistor TC11 is electrically connected to the high voltage terminal VDD, and the source of the first control transistor TC11 is electrically connected to the first node Q1.

[0720] The gate of the first second control transistor TC12 is electrically connected to the second control terminal G2, the drain of the first second control transistor TC12 is electrically connected to the first node Q1, and the source of the first second control transistor TC12 is electrically connected to the low voltage signal terminal VSSN.

[0721] The gate of the first providing transistor TP1 is electrically connected to the first node Q1, the drain of the first providing transistor TP1 is electrically connected to the first data voltage terminal D1, and the source of the first providing transistor TP1 is electrically connected to the control data line SLM.

[0722] The first terminal of Cst1 is electrically connected to the first node Q1, and the second terminal of Cst1 is electrically connected to the high voltage terminal VDD.

[0723] The second reset unit includes a second reset transistor TR2; the second control unit includes a second first control transistor TC21 and a second second control transistor TC22; the second supply unit includes a second supply transistor TP2; and the second energy storage unit includes a second storage capacitor Cst2.

[0724] The gate of the second reset transistor TR2 is electrically connected to the initial control line RST, the drain of the second reset transistor TR2 is electrically connected to the low voltage signal terminal VSSN, and the source of the second reset transistor TR2 is electrically connected to the second node Q2.

[0725] The gate of the second first control transistor TC21 is electrically connected to the second control terminal G2, the drain of the second first control transistor TC21 is electrically connected to the high voltage terminal VDD, and the source of the second first control transistor TC21 is electrically connected to the second node Q2.

[0726] The gate of the second control transistor TC22 is electrically connected to the third control terminal G3, the drain of the second control transistor TC22 is electrically connected to the second node Q2, and the source of the second control transistor TC22 is electrically connected to the low voltage signal terminal VSSN.

[0727] The gate of the second providing transistor TP2 is electrically connected to the second node Q2, the drain of the second providing transistor TP2 is electrically connected to the second data voltage terminal D2, and the source of the second providing transistor TP2 is electrically connected to the control data line SLM.

[0728] The first terminal of Cst2 is electrically connected to the second node Q2, and the second terminal of Cst2 is electrically connected to the high voltage terminal VDD.

[0729] The third reset unit includes a third reset transistor TR3; the third control unit includes a third first control transistor TC31 and a third second control transistor TC32; the third supply unit includes a second supply transistor TP3; and the third energy storage unit includes a third storage capacitor Cst3.

[0730] The gate of the third reset transistor TR3 is electrically connected to the initial control line RST, the drain of the third reset transistor TR3 is electrically connected to the low voltage signal terminal VSSN, and the source of the third reset transistor TR3 is electrically connected to the third node Q3.

[0731] The gate of the third first control transistor TC31 is electrically connected to the third control terminal G3, the drain of the third first control transistor TC31 is electrically connected to the high voltage terminal VDD, and the source of the third first control transistor TC31 is electrically connected to the third node Q3.

[0732] The gate of the third second control transistor TC32 is electrically connected to the fourth control terminal G4, the drain of the third second control transistor TC32 is electrically connected to the third node Q3, and the source of the third second control transistor TC32 is electrically connected to the low voltage signal terminal VSSN.

[0733] The gate of the third providing transistor TP3 is electrically connected to the third node Q3, the drain of the third providing transistor TP3 is electrically connected to the third data voltage terminal D3, and the source of the third providing transistor TP3 is electrically connected to the control data line SLM.

[0734] The first terminal of Cst3 is electrically connected to the third node Q3, and the second terminal of Cst3 is electrically connected to the high voltage terminal VDD.

[0735] The fourth reset unit includes a fourth reset transistor TR4; the fourth control unit includes a fourth first control transistor TC41 and a fourth second control transistor TC42; the fourth supply unit includes a fourth supply transistor TP4; and the fourth energy storage circuit includes a fourth storage capacitor Cst4.

[0736] The gate of the fourth reset transistor TR4 is electrically connected to the initial control line RST, the drain of the fourth reset transistor TR4 is electrically connected to the low voltage signal terminal VSSN, and the source of the fourth reset transistor TR4 is electrically connected to the fourth node Q4.

[0737] The gate of the fourth first control transistor TC41 is electrically connected to the fourth control terminal G4, the drain of the fourth first control transistor TC41 is electrically connected to the high voltage terminal VDD, and the source of the fourth first control transistor TC41 is electrically connected to the fourth node Q4.

[0738] The gate of the fourth second control transistor TC42 is electrically connected to the fifth control terminal G5, the drain of the fourth second control transistor TC42 is electrically connected to the fourth node Q4, and the source of the fourth second control transistor TC42 is electrically connected to the low voltage signal terminal VSSN.

[0739] The gate of the fourth providing transistor TP4 is electrically connected to the fourth node Q4, the drain of the fourth providing transistor TP4 is electrically connected to the fourth data voltage terminal D4, and the source of the fourth providing transistor TP4 is electrically connected to the control data line SLM.

[0740] The first terminal of Cst4 is electrically connected to the fourth node Q4, and the second terminal of Cst4 is electrically connected to the high voltage terminal VDD.

[0741] The fifth reset unit includes a fifth reset transistor TR5; the fifth control unit includes a fifth first control transistor TC51 and a fifth second control transistor TC52; the fifth supply unit includes a fifth supply transistor TP5; and the fifth energy storage circuit includes a fifth storage capacitor Cst5.

[0742] The gate of the fifth reset transistor TR5 is electrically connected to the initial control line RST, the drain of the fifth reset transistor TR5 is electrically connected to the high voltage terminal VDD, and the source of the fifth reset transistor TR5 is electrically connected to the fifth node Q5.

[0743] The gate of the fifth first control transistor TC51 is electrically connected to the fifth control terminal G5, the drain of the fifth first control transistor TC51 is electrically connected to the high voltage terminal VDD, and the source of the fifth first control transistor TC51 is electrically connected to the fifth node Q5.

[0744] The gate of the fifth second control transistor TC52 is electrically connected to the first control terminal G1, the drain of the fifth second control transistor TC52 is electrically connected to the fifth node Q5, and the source of the fifth second control transistor TC52 is electrically connected to the first low voltage signal terminal VSSN.

[0745] The gate of the fifth transistor TP5 is electrically connected to the fifth node Q5, the drain of the fifth transistor TP5 is electrically connected to the fifth data voltage terminal D5, and the source of the fifth transistor TP5 is electrically connected to the control data line SLM.

[0746] The first terminal of Cst5 is electrically connected to the fifth node Q5, and the second terminal of Cst5 is electrically connected to the high voltage terminal VDD.

[0747] In at least one embodiment of the driving circuit shown in Figure 22, all transistors are n-type transistors.

[0748] In at least one embodiment of this disclosure, the fifth voltage terminal can be a low voltage signal terminal, the sixth voltage terminal can be a high voltage terminal, the seventh voltage terminal can be a low voltage signal terminal, and the eighth voltage terminal can be a high voltage terminal.

[0749] Figure 23 is a timing diagram of at least one embodiment of the data voltage supply circuit shown in Figure 22.

[0750] When at least one embodiment of the data voltage supply circuit shown in Figure 22 is in operation, the supply period includes a reset phase, a first time period t1, a second time period t2, a third time period t3, a fourth time period t4, and a fifth time period t5, which are set sequentially.

[0751] During the reset phase, RST provides a high voltage signal, TR1, TR2, TR3, TR4 and TR5 are turned on, VSSN is connected to Q1, VSSN is connected to Q2, VSSN is connected to Q3, VSSN is connected to Q4 and VSSN is connected to Q5.

[0752] As shown in Figure 23

[0753] At the start of the first time period t1, G1 provides a high voltage signal, TC11 is turned on, and VDD is connected to Q1;

[0754] During the first time period, Cst1 maintains the potential of Q1; SLM and D1 are connected, with D1 providing a -8V voltage signal and SLM providing a -8V voltage signal; G2 provides a low voltage signal, and TC12 is turned off; Cst5 maintains the potential of Q5.

[0755] At the start of the second time period t2, G2 provides a high voltage signal, TC21 is turned on, connecting VDD and Q2; TC12 is turned on, connecting Q1 and VSSN.

[0756] During the second time period t2, Cst2 maintains the potential of Q2; SLM and D2 are connected, with D2 providing a -11V voltage signal and SLM providing a -11V voltage signal; Cst1 maintains the potential of Q1;

[0757] At the start of the third time period t3, G3 provides a high voltage signal, TC31 turns on, and VDD is connected to Q3; TC22 turns on, and Q2 is connected to VSSN.

[0758] During the third time interval t3, Cst3 maintains the potential of Q3; SLM and D3 are connected, with D3 providing a -14V voltage signal and SLM providing a -14V voltage signal; Cst2 maintains the potential of Q2;

[0759] At the start of the fourth time period t4, G4 provides a high voltage signal, TC41 turns on, and VDD is connected to Q4; TC32 turns on, and Q3 is connected to VSSN.

[0760] During the fourth time interval t4, Cst4 maintains the potential of Q4; SLM and D4 are connected, with D4 providing a -17V voltage signal and SLM providing a -17V voltage signal; Cst3 maintains the potential of Q3;

[0761] At the start of the fifth time period t5, G5 provides a high voltage signal, TC51 turns on, connecting VDD and Q5; TC42 turns on, connecting Q4 and VSSN.

[0762] During the fifth time interval t5, Cst5 maintains the potential of Q5; SLM and D5 are connected, with D5 providing a -20V voltage signal and SLM providing a -20V voltage signal; Cst4 maintains the potential of Q4.

[0763] As shown in Figure 24, based on at least one embodiment of the data voltage supply circuit shown in Figure 21,

[0764] The first reset unit includes a first reset transistor TR1; the first control unit includes a first first control transistor TC11 and a first second control transistor TC12; the first supply unit includes a first supply transistor TP1; and the first energy storage unit includes a first storage capacitor Cst1.

[0765] The gate of the first reset transistor TR1 is electrically connected to the initial control line RST, the drain of the first reset transistor TR1 is electrically connected to the first high voltage signal terminal VDDN, and the source of the first reset transistor TR1 is electrically connected to the first node Q1.

[0766] The gate of the first control transistor TC11 is electrically connected to the first control terminal G1, the drain of the first control transistor TC11 is electrically connected to the low-level terminal VSS, and the source of the first control transistor TC11 is electrically connected to the first node Q1.

[0767] The gate of the first second control transistor TC12 is electrically connected to the second control terminal G2, the drain of the first second control transistor TC12 is electrically connected to the first node Q1, and the source of the first second control transistor TC12 is electrically connected to the second high voltage signal terminal VDDP.

[0768] The gate of the first providing transistor TP1 is electrically connected to the first node Q1, the drain of the first providing transistor TP1 is electrically connected to the first data voltage terminal D1, and the source of the first providing transistor TP1 is electrically connected to the control data line SLM.

[0769] The first terminal of Cst1 is electrically connected to the first node Q1, and the second terminal of Cst1 is electrically connected to the high voltage terminal VDD.

[0770] The second reset unit includes a second reset transistor TR2; the second control unit includes a second first control transistor TC21 and a second second control transistor TC22; the second supply unit includes a second supply transistor TP2; and the second energy storage unit includes a second storage capacitor Cst2.

[0771] The gate of the second reset transistor TR2 is electrically connected to the initial control line RST, the drain of the second reset transistor TR2 is electrically connected to the first high voltage signal terminal VDDN, and the source of the second reset transistor TR2 is electrically connected to the second node Q2.

[0772] The gate of the second first control transistor TC21 is electrically connected to the second control terminal G2, the drain of the second first control transistor TC21 is electrically connected to the low-level terminal VSS, and the source of the second first control transistor TC21 is electrically connected to the second node Q2.

[0773] The gate of the second control transistor TC22 is electrically connected to the third control terminal G3, the drain of the second control transistor TC22 is electrically connected to the second node Q2, and the source of the second control transistor TC22 is electrically connected to the second high voltage signal terminal VDDP.

[0774] The gate of the second providing transistor TP2 is electrically connected to the second node Q2, the drain of the second providing transistor TP2 is electrically connected to the second data voltage terminal D2, and the source of the second providing transistor TP2 is electrically connected to the control data line SLM.

[0775] The first terminal of Cst2 is electrically connected to the second node Q2, and the second terminal of Cst2 is electrically connected to the high voltage terminal VDD.

[0776] The third reset unit includes a third reset transistor TR3; the third control unit includes a third first control transistor TC31 and a third second control transistor TC32; the third supply unit includes a second supply transistor TP3; and the third energy storage unit includes a third storage capacitor Cst3.

[0777] The gate of the third reset transistor TR3 is electrically connected to the initial control line RST, the drain of the third reset transistor TR3 is electrically connected to the first high voltage signal terminal VDDN, and the source of the third reset transistor TR3 is electrically connected to the third node Q3.

[0778] The gate of the third first control transistor TC31 is electrically connected to the third control terminal G3, the drain of the third first control transistor TC31 is electrically connected to the low-level terminal VSS, and the source of the third first control transistor TC31 is electrically connected to the third node Q3.

[0779] The gate of the third second control transistor TC32 is electrically connected to the fourth control terminal G4, the drain of the third second control transistor TC32 is electrically connected to the third node Q3, and the source of the third second control transistor TC32 is electrically connected to the second high voltage signal terminal VDDP.

[0780] The gate of the third providing transistor TP3 is electrically connected to the third node Q3, the drain of the third providing transistor TP3 is electrically connected to the third data voltage terminal D3, and the source of the third providing transistor TP3 is electrically connected to the control data line SLM.

[0781] The first terminal of Cst3 is electrically connected to the third node Q3, and the second terminal of Cst3 is electrically connected to the high voltage terminal VDD.

[0782] The fourth reset unit includes a fourth reset transistor TR4; the fourth control unit includes a fourth first control transistor TC41 and a fourth second control transistor TC42; the fourth supply unit includes a fourth supply transistor TP4; and the fourth energy storage unit includes a fourth storage capacitor Cst4.

[0783] The gate of the fourth reset transistor TR4 is electrically connected to the initial control line RST, the drain of the fourth reset transistor TR4 is electrically connected to the first high voltage signal terminal VDDN, and the source of the fourth reset transistor TR4 is electrically connected to the fourth node Q4.

[0784] The gate of the fourth first control transistor TC41 is electrically connected to the fourth control terminal G4, the drain of the fourth first control transistor TC41 is electrically connected to the low-level terminal VSS, and the source of the fourth first control transistor TC41 is electrically connected to the fourth node Q4.

[0785] The gate of the fourth second control transistor TC42 is electrically connected to the fifth control terminal G5, the drain of the fourth second control transistor TC42 is electrically connected to the fourth node Q4, and the source of the fourth second control transistor TC42 is electrically connected to the second high voltage signal terminal VDDP.

[0786] The gate of the fourth providing transistor TP4 is electrically connected to the fourth node Q4, the drain of the fourth providing transistor TP4 is electrically connected to the fourth data voltage terminal D4, and the source of the fourth providing transistor TP4 is electrically connected to the control data line SLM.

[0787] The first terminal of Cst4 is electrically connected to the fourth node Q4, and the second terminal of Cst2 is electrically connected to the high voltage terminal VDD.

[0788] The fifth reset unit includes a fifth reset transistor TR5; the fifth control unit includes a fifth first control transistor TC51 and a fifth second control transistor TC52; the fifth supply unit includes a fifth supply transistor TP5; and the fifth energy storage unit includes a fifth storage capacitor Cst5.

[0789] The gate of the fifth reset transistor TR5 is electrically connected to the initial control line RST, the drain of the fifth reset transistor TR5 is electrically connected to the low-level terminal VSS, and the source of the fifth reset transistor TR5 is electrically connected to the fifth node Q5.

[0790] The gate of the fifth first control transistor TC51 is electrically connected to the fifth control terminal G5, the drain of the fifth first control transistor TC51 is electrically connected to the low-level terminal VSS, and the source of the fifth first control transistor TC51 is electrically connected to the fifth node Q5.

[0791] The gate of the fifth second control transistor TC52 is electrically connected to the first control terminal G1, the drain of the fifth second control transistor TC52 is electrically connected to the fifth node Q5, and the source of the fifth second control transistor TC52 is electrically connected to the second high voltage signal terminal VDDP.

[0792] The gate of the fifth transistor TP5 is electrically connected to the fifth node Q5, the drain of the fifth transistor TP5 is electrically connected to the fifth data voltage terminal D5, and the source of the fifth transistor TP5 is electrically connected to the control data line SLM.

[0793] The first terminal of Cst5 is electrically connected to the fifth node Q5, and the second terminal of Cst2 is electrically connected to the high voltage terminal VDD.

[0794] In at least one embodiment of the data voltage supply circuit shown in Figure 24, all transistors are p-type transistors.

[0795] In at least one embodiment of this disclosure, the fifth voltage terminal may be a first high voltage signal terminal, the sixth voltage terminal may be a low level terminal, the seventh voltage terminal may be a second high voltage signal terminal, and the eighth voltage terminal may be a low level terminal.

[0796] Figure 25 is a timing diagram of at least one embodiment of the data voltage supply circuit shown in Figure 24.

[0797] At least one embodiment of the data voltage supply circuit shown in Figure 24 provides a period including a reset phase, a first time period t1, a second time period t2, a third time period t3, a fourth time period t4, and a fifth time period t5 when in operation;

[0798] During the reset phase, RST provides a low voltage signal, TR1, TR2, TR3, TR4 and TR5 are turned on, VDDN is connected to Q1, VDDN is connected to Q2, VDDN is connected to Q3, VDDN is connected to Q4 and VDDN is connected to Q5.

[0799] As shown in Figure 25

[0800] At the start of the first time period t1, G1 provides a low voltage signal, TC11 is turned on, and VSS and Q1 are connected;

[0801] During the first time interval t1, Cst1 maintains the potential of Q1; SLM and D1 are connected, D1 provides an 8V voltage signal, and SLM provides an 8V voltage signal; G2 provides a high voltage signal, and TC12 is turned off; Cst5 maintains the potential of Q5.

[0802] At the start of the second time period t2, G2 provides a low voltage signal, TC21 turns on, connecting VSS and Q2; TC12 turns on, connecting Q1 and VDDP.

[0803] During the second time period t2, Cst2 maintains the potential of Q2; SLM and D2 are connected, with D2 providing an 11V voltage signal and SLM providing an 11V voltage signal; Cst1 maintains the potential of Q1.

[0804] At the start of the third time period t3, G3 provides a low voltage signal, TC31 turns on, and VSS is connected to Q3; TC22 turns on, and Q2 is connected to VDDP.

[0805] During the third time period t3, Cst3 maintains the potential of Q3; SLM and D3 are connected, with D3 providing a 14V voltage signal and SLM providing a 14V voltage signal; Cst2 maintains the potential of Q2;

[0806] At the start of the fourth time period t4, G4 provides a low voltage signal, TC41 turns on, and VSS is connected to Q4; TC32 turns on, and Q3 is connected to VDDP.

[0807] During the fourth time interval t4, Cst4 maintains the potential of Q4; SLM and D4 are connected, with D4 providing a 17V voltage signal and SLM providing a 17V voltage signal; Cst3 maintains the potential of Q3.

[0808] At the start of the fifth time period t5, G5 provides a low voltage signal, TC51 turns on, connecting VSS and Q5; TC42 turns on, connecting Q4 and VDDP.

[0809] During the fifth time interval t5, Cst5 maintains the potential of Q5; SLM and D5 are connected, with D5 providing a 20V voltage signal and SLM providing a 20V voltage signal; Cst4 maintains the potential of Q4.

[0810] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a light emitting element, a driving circuit, a display control circuit, a control data writing circuit, a first energy storage circuit and a setting circuit; a first electrode of the light emitting element is electrically connected with a first voltage terminal; a control terminal of the driving circuit is electrically connected with a display data line, a first terminal of the driving circuit is electrically connected with a second electrode of the light emitting element, a second terminal of the driving circuit is electrically connected with a first terminal of the display control circuit, the driving circuit is configured to generate a driving current for driving the light emitting element under the control of a display data voltage provided by the display data line; a control terminal of the display control circuit is electrically connected with a first control node, a second terminal of the display control circuit is electrically connected with a second voltage terminal, the display control circuit is configured to control the second terminal of the driving circuit and the second voltage terminal to be connected or disconnected under the control of a potential of the first control node; the control data writing circuit is electrically connected with a control voltage line, a control data line and the first control node respectively, and is configured to control the control data line and the first control node to be connected or disconnected under the control of a control voltage provided by the control voltage line; the first energy storage circuit is electrically connected with the first control node, and is configured to maintain the potential of the first control node; the setting circuit is electrically connected with a scanning line, a third voltage terminal and the first control node respectively, and is configured to control the third voltage terminal and the first control node to be connected or disconnected under the control of a scanning signal provided by the scanning line.

2. The pixel circuit of claim 1, wherein, the control data writing circuit comprises a first data writing circuit, a switch control circuit and a second energy storage circuit; the first data writing circuit is electrically connected with the scanning line, a control voltage line and a second control node respectively, and is configured to control the control voltage line and the second control node to be connected or disconnected under the control of the scanning signal; the switch control circuit is electrically connected with the second control node, the control data line and the first control node respectively, and is configured to control the control data line and the first control node to be connected or disconnected under the control of a potential of the second control node; the second energy storage circuit is electrically connected with the second control node, and is configured to maintain the potential of the second control node.

3. The pixel circuit of claim 2, wherein, further comprising a second data writing circuit and a third energy storage circuit; the second data writing circuit is electrically connected with the scanning line, a display data line and a control terminal of the driving circuit respectively, and is configured to control the display data line and the control terminal of the driving circuit to be connected or disconnected under the control of the scanning signal; the third energy storage circuit is electrically connected with the control terminal of the driving circuit, and is configured to maintain the potential of the control terminal of the driving circuit.

4. The pixel circuit of claim 2, wherein, further comprising a second data writing circuit, a compensation control circuit and a third energy storage circuit; the second data writing circuit is electrically connected with a scanning line, a display data line and a second terminal of the driving circuit respectively, and is configured to control the display data line and the second terminal of the driving circuit to be connected or disconnected under the control of a scanning signal provided by the scanning line. The compensation control circuit is electrically connected with the scan line, the control end of the driving circuit and the first end of the driving circuit respectively, and is used for controlling the communication or disconnection between the control end of the driving circuit and the first end of the driving circuit under the control of the scan signal. The third energy storage circuit is electrically connected with the control end of the driving circuit, and is used for maintaining the potential of the control end of the driving circuit.

5. The pixel circuit of claim 4, wherein, A reset circuit is further included; The reset circuit is electrically connected with the reset control line, the fourth voltage end and the control end of the driving circuit respectively, and is used for controlling the communication or disconnection between the fourth voltage end and the control end of the driving circuit under the control of the reset control signal provided by the reset control line.

6. The pixel circuit of any one of claims 2 to 5, wherein, A first light-emitting control circuit is further included; The first light-emitting control circuit is electrically connected with the light-emitting control line, the second electrode of the light-emitting element and the first end of the driving circuit respectively, and is used for controlling the communication or disconnection between the second electrode of the light-emitting element and the first end of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line.

7. The pixel circuit of claim 6, wherein, A second light-emitting control circuit is further included; The second light-emitting control circuit is electrically connected with the light-emitting control line, the second end of the driving circuit and the first end of the display control circuit respectively, and is used for controlling the communication or disconnection between the second end of the driving circuit and the first end of the display control circuit under the control of the light-emitting control signal.

8. The pixel circuit of claim 1, wherein, The driving circuit includes a driving transistor, the setting circuit includes a first transistor, the display control circuit includes a second transistor, the control data writing circuit includes a third transistor, and the first energy storage circuit includes a first capacitor; The gate of the driving transistor is electrically connected with the display data line, the first electrode of the driving transistor is electrically connected with the second electrode of the light-emitting element, and the second electrode of the driving transistor is electrically connected with the first electrode of the second transistor; The gate of the first transistor is electrically connected with the scan line, the first electrode of the first transistor is electrically connected with the third voltage end, and the second electrode of the first transistor is electrically connected with the first control node; The gate of the second transistor is electrically connected with the first control node, and the second electrode of the second transistor is electrically connected with the second voltage end; The gate of the third transistor is electrically connected with the control voltage line, the first electrode of the third transistor is electrically connected with the control data line, and the second electrode of the third transistor is electrically connected with the first control node; The first end of the first capacitor is electrically connected with the first control node, and the second end of the first capacitor is electrically connected with a direct-current voltage end.

9. The pixel circuit of claim 2, wherein, The first data writing circuit includes a fourth transistor, the switch control circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor; The gate of the fourth transistor is electrically connected with the scan line, the first electrode of the fourth transistor is electrically connected with the control voltage line, and the second electrode of the fourth transistor is electrically connected with the second control node. A gate of the fifth transistor is electrically connected with the second control node, a first pole of the fifth transistor is electrically connected with the control data line, and a second pole of the fifth transistor is electrically connected with the first control node. A first end of the second capacitor is electrically connected with the second control node, and a second end of the second capacitor is electrically connected with a direct current voltage end.

10. The pixel circuit of claim 3, wherein, The second data writing circuit comprises a sixth transistor, and the third energy storage circuit comprises a third capacitor. A gate of the sixth transistor is electrically connected with the scanning line, a first pole of the sixth transistor is electrically connected with the display data line, and a second pole of the sixth transistor is electrically connected with the control end of the driving circuit. A first end of the third capacitor is electrically connected with the control end of the driving circuit, and a second end of the third capacitor is electrically connected with the direct current voltage end.

11. The pixel circuit as claimed in claim 4, wherein, The compensation control circuit comprises a seventh transistor, the second data writing circuit comprises an eighth transistor, and the third energy storage circuit comprises a third capacitor. A gate of the seventh transistor is electrically connected with the scanning line, a first pole of the seventh transistor is electrically connected with the control end of the driving circuit, and a second pole of the seventh transistor is electrically connected with the first end of the driving circuit. A gate of the eighth transistor is electrically connected with the scanning line, a first pole of the eighth transistor is electrically connected with the display data line, and a second pole of the eighth transistor is electrically connected with the second end of the driving circuit. A first end of the third capacitor is electrically connected with the control end of the driving circuit, and a second end of the third capacitor is electrically connected with the direct current voltage end.

12. The pixel circuit of claim 5, wherein, The reset circuit comprises a ninth transistor. A gate of the ninth transistor is electrically connected with the reset control line, a first pole of the ninth transistor is electrically connected with the fourth voltage end, and a second pole of the ninth transistor is electrically connected with the control end of the driving circuit.

13. The pixel circuit of claim 6, wherein, The first light emitting control circuit comprises a tenth transistor. A gate of the tenth transistor is electrically connected with the light emitting control line, a first pole of the tenth transistor is electrically connected with the second pole of the light emitting element, and a second pole of the tenth transistor is electrically connected with the first end of the driving circuit.

14. The pixel circuit of claim 7, wherein, The second light emitting control circuit comprises an eleventh transistor. A gate of the eleventh transistor is electrically connected with the light emitting control line, a first pole of the eleventh transistor is electrically connected with the second end of the driving circuit, and a second pole of the eleventh transistor is electrically connected with the first end of the display control circuit.

15. A pixel driving method applied to the pixel circuit in any one of claims 1 to 14, wherein a display period comprises a reset time period, and the pixel driving method comprises: In the reset time period, the setting circuit controls the communication between the third voltage end and the first control node under the control of the scanning signal, and the display control circuit controls the communication between the second end of the driving circuit and the second voltage end under the control of the potential of the first control node. In the display period, the driving circuit generates a driving current for driving the light emitting element under the control of the display data voltage; the control data writing circuit controls the first control node to be connected with or disconnected from the control data line under the control of the control voltage; when the control data writing circuit controls the first control node to be connected with the control data line, the display control circuit controls the second end of the driving circuit to be disconnected from the second voltage end under the control of the potential of the first control node.

16. The pixel driving method of claim 15, wherein, The display period includes N display stages; N is an integer greater than 1; The pixel driving method includes: In the nth display period, the control data line provides an nth control data voltage; n is a positive integer less than or equal to N; The duration of the mth display period is less than the duration of the m+1th display period; m is a positive integer less than N.

17. A display device comprising the pixel circuit according to any one of claims 1 to 14.

18. The display device of claim 17, wherein, Further comprising a plurality of control data lines and a plurality of data voltage providing circuits; The data voltage providing circuit is electrically connected with the control data line and configured to provide a control data voltage for the control data line.

19. The display device of claim 18, wherein, The data voltage providing circuit includes N data providing units; N is an integer greater than 1; m is a positive integer less than N; The mth data providing unit includes an mth reset unit, an mth control unit, an mth providing unit and an mth energy storage unit; The mth reset unit is electrically connected with an initial control line, a fifth voltage end and an mth node respectively, and configured to be connected or disconnected between the fifth voltage end and the mth node under the control of an initial control signal provided by the initial control line; The mth control unit is electrically connected with the mth node, an mth control end, an m+1th control end, a sixth voltage end and a seventh voltage end respectively, and configured to control the mth node to be connected or disconnected with the sixth voltage end under the control of an mth control signal provided by the mth control end, and control the mth node to be connected or disconnected with the seventh voltage end under the control of an m+1th control signal provided by the m+1th control end; The mth providing unit is electrically connected with the mth node, an mth data voltage end and the control data line respectively, and configured to control the mth data voltage end to be connected or disconnected with the control data line under the control of the potential of the mth node; The mth energy storage unit is electrically connected with the mth node, and configured to maintain the potential of the mth node; The Nth data providing unit includes an Nth reset unit, an Nth control unit, an Nth providing unit and an Nth energy storage unit; The Nth reset unit is electrically connected with an initial control line, an eighth voltage end and an Nth node respectively, and configured to be connected or disconnected between the eighth voltage end and the Nth node under the control of an initial control signal provided by the initial control line; The Nth control unit is electrically connected with the Nth node, the Nth control terminal, the first control terminal, the sixth voltage terminal and the seventh voltage terminal, and is configured to control the Nth node to be connected or disconnected with the sixth voltage terminal under the control of an Nth control signal provided by the Nth control terminal, and control the Nth node to be connected or disconnected with the seventh voltage terminal under the control of a first control signal provided by the first control terminal. The Nth providing unit is electrically connected with the Nth node, the Nth data voltage terminal and the control data line, and is configured to control the Nth data voltage terminal to be connected or disconnected with the control data line under the control of the potential of the Nth node. The Nth energy storage unit is electrically connected with the Nth node, and is configured to maintain the potential of the Nth node.

20. The display device of claim 19, wherein, The mth reset unit comprises an mth reset transistor, the mth control unit comprises an mth first control transistor and an mth second control transistor, and the mth providing unit comprises an mth providing transistor. The mth energy storage unit comprises an mth storage capacitor. The gate of the mth reset transistor is electrically connected with the initial control line, the first pole of the mth reset transistor is electrically connected with the fifth voltage terminal, and the second pole of the mth reset transistor is electrically connected with the mth node. The gate of the mth first control transistor is electrically connected with the mth control terminal, the first pole of the mth first control transistor is electrically connected with the sixth voltage terminal, and the second pole of the mth first control transistor is electrically connected with the mth node. The gate of the mth second control transistor is electrically connected with the m+1th control terminal, the first pole of the mth second control transistor is electrically connected with the mth node, and the second pole of the mth second control transistor is electrically connected with the seventh voltage terminal. The gate of the mth providing transistor is electrically connected with the mth node, the first pole of the mth providing transistor is electrically connected with the mth data voltage terminal, and the second pole of the mth providing transistor is electrically connected with the control data line. The first end of the mth storage capacitor is electrically connected with the mth node, and the second end of the mth storage capacitor is electrically connected with a direct current voltage terminal.

21. The display device of claim 19, wherein, The Nth reset unit comprises an Nth reset transistor, the Nth control unit comprises an Nth first control transistor and an Nth second control transistor, and the Nth providing unit comprises an Nth providing transistor. The Nth energy storage unit comprises an Nth storage capacitor. The gate of the Nth reset transistor is electrically connected with the initial control line, the first pole of the Nth reset transistor is electrically connected with the eighth voltage terminal, and the second pole of the Nth reset transistor is electrically connected with the Nth node. The gate of the Nth first control transistor is electrically connected with the Nth control terminal, the first pole of the Nth first control transistor is electrically connected with the sixth voltage terminal, and the second pole of the Nth first control transistor is electrically connected with the Nth node. The gate of the Nth second control transistor is electrically connected with the N+1th control end, the first pole of the Nth second control transistor is electrically connected with the Nth node, and the second pole of the Nth second control transistor is electrically connected with the seventh voltage end; The gate of the Nth providing transistor is electrically connected with the Nth node, the first pole of the Nth providing transistor is electrically connected with the Nth data voltage end, and the second pole of the Nth providing transistor is electrically connected with the control data line; The first end of the Nth storage capacitor is electrically connected with the Nth node, and the second end of the Nth storage capacitor is electrically connected with a direct current voltage end.

Images